JP2017228932A - Switched capacitor circuit and AD conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switched capacitor circuit capable of improving a performance of an offset-free.SOLUTION: A capacitor 21 is connected to a place between a noninverted input terminal of an operational amplifier and a voltage V1. A switch S1 is parallely connected with the capacitor 21. A switch S2 selectively switches the voltage V1 connected to a contact point a and a voltage of the inverted input terminal connected to a contact point b by through a capacitor 22 by being connected to the noninverted input terminal. An output terminal is connected to the inverted input terminal through a switch S3 and a parallel circuit of the capacitor 12. A switch S4 selectively switches a voltage V3 connected to the contact point a and a voltage V2 connected to the contact point b through a capacitor 11, and connected to the inverted input terminal. A control circuit 20A turns on switching elements S1 and S3 in a sampling period and switches switching elements S2 and S4 to the contact point b, and thereby the voltage V2 is sampled and the switches S2 and S4 are switched to the contact point a by turning off the switches S1 and S3 in a holding period.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a switched capacitor circuit and an analog / digital conversion apparatus using the switched capacitor circuit. Hereinafter, analog / digital conversion is referred to as AD conversion, and digital / analog conversion is referred to as DA conversion.

  For example, a non-volatile memory such as a flash memory uses a large number of differential amplifiers as follows. Non-volatile memories using FN (Fowler-Nordheim) tunneling use many voltages in the chip, such as 20 V, 10 V, 7 V, 4 V, power supply voltage VDD, reference voltage Vref, and the like. These voltages are generated by, for example, a bandgap reference voltage generation circuit (BGR circuit) and a charge pump circuit for program (write), erase and read operations, and control of these voltages is basically a differential amplifier. Alternatively, it is performed by an operational amplifier and a reference voltage source. Therefore, the operational performance of differential amplifiers and operational amplifiers is very important.

  FIG. 1A is a circuit diagram showing a configuration example of a differential amplifier DA1 according to the prior art, and FIG. 1B is a graph showing an offset in an operation characteristic example of the differential amplifier DA1 of FIG. 1A. FIG. 1C is a circuit diagram showing a configuration example of the buffer circuit of the voltage follower using the operational amplifier OP1 according to the related art.

  In the differential amplifier DA1 of FIG. 1A, as is well known, offset is an important problem as follows. The differential amplifier DA1 has an offset voltage between the non-inverting input terminal and the inverting input terminal, and the offset voltage Voffset in FIG. 1B shifts the operating point as shown in the following equation.

Vin = Vref + Voffset (1)

  Here, Vin is an input voltage, and Vref is a reference voltage.

  In addition, the output voltage Vref_buf of the voltage follower buffer circuit using the operational amplifier OP1 in FIG. 1C varies according to the offset voltage Voffset as follows.

Vref_buf = Vref + Voffset (2)

  If the offset voltage Voffset is 36 mV (when the variance is 3σ) and the reference voltage Vref is 1.2 V, the operating point voltage Vtrip or the output voltage Vref_buf is shifted by about 3% from the target voltage. This 3% is also applied to the high voltage (HV) and intermediate voltage (MV) generated in the charge pump circuit or regulator circuit, and these voltages are greatly shifted. For example, when the program voltage Vpgm is 20V, the program voltage Vpgm becomes 20.6V, and the increase of the output voltage may reach approximately 1V. This has a great influence which cannot be ignored with respect to the shift of the program threshold voltage Vth of the flash memory, for example.

  FIG. 2 is a circuit diagram showing a configuration example of a switched capacitor circuit according to a conventional example.

  Switched capacitor circuits are very popular circuits in the field of AD converters or DA converters. In FIG. 2, the switched capacitor circuit is configured to include an operational amplifier OP1, switches Sa and Sb, capacitors 11 and 12, and a control circuit 20. Here, the non-inverting input terminal of the operational amplifier OP1 is grounded, for example, and a parallel circuit of the switch Sb and the capacitor 12 having the capacitance value Cb is connected between the inverting input terminal and the output terminal of the operational amplifier OP1. The reference voltage Vref is connected to the inverting input terminal of the operational amplifier OP1 through the capacitor 11 having the capacitance value Ca through the contact a of the switch Sa, and the contact b of the switch Sa is connected through the capacitor 11 having the capacitance value Ca. Is connected to the input voltage Vin. The control circuit 20 uses the control signal φ to control switching of the switch Sa and on / off of the switch Sb.

  In the switched capacitor circuit of FIG. 2, the voltage Vm at the inverting input terminal is held to be the voltage Vp at the non-inverting input terminal by the feedback loop of the operational amplifier OP1.

  The relationship between charge and voltage in the sampling period and hold period of the switched capacitor circuit configured as described above is as follows. Note that the sampling period and the hold period are alternately repeated at the same time, for example.

(1) Sampling period:
The switch Sa is switched to the contact b, and the switch Sb is turned on and short-circuited. At this time, the charge Qm_s at the inverting input terminal and the voltage Vm_s at the inverting input terminal are expressed by the following equations.

Qm_s = Ca (Vm_s−Vin) + Cb (Vm_s−Vout_s) (3)
Vm_s = Vp + Voffset = Vout_s (4)

  Here, Vp is the voltage at the non-inverting input terminal, and Vout_s is the output voltage Vout during the sampling period.

(2) Hold period:
The switch Sa is switched to the contact a, and the switch Sb is turned off and opened. At this time, the charge Qm_h at the inverting input terminal and the voltage Vm_h at the inverting input terminal are expressed by the following equations.

Qm_h
= Ca (Vm_h-Vref) + Cb (Vm_h-Vout_h)
= Qm_s (5)
Vm_h = Vp + Voffset = Vm_s (6)

  From the above relationship, the output voltage Vout_h in the hold period is expressed by the following equation.

Vout_h = (Ca / Cb) × (Vin−Vref) + Vp + Voffset
(7)

JP 2001-0607047 A JP 2003-078365 A JP 2006-197142 A JP 2007-104531 A JP 2008-125046 A US Patent Application Publication No. 2007/0132629

  Although the differential amplifier OP1 configured as described above operates as a non-inverting amplifier, there is a problem that the offset voltage Voffset appears in the output voltage Vout after all.

  In order to solve this problem, for example, Patent Documents 1 to 6 disclose various switched capacitor circuits in which the offset is canceled (hereinafter referred to as offset free). However, the prior art has a problem in that the configuration of the offset-free switched capacitor circuit is complicated, and the offset-free performance is restricted by specific conditions.

  An object of the present invention is to provide a switched capacitor circuit that can solve the above-described problems, has a simpler circuit configuration than the prior art, and can improve offset-free performance, and an AD converter using the switched capacitor circuit. It is in.

The switched capacitor circuit according to the first invention is:
An operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal;
First to fourth capacitors;
The first and third switch elements that are short-circuited or opened by being turned on or off, respectively, and the second and fourth switches that selectively switch the common terminal to either the first contact or the second contact. Switch elements of
A switched capacitor circuit comprising a control circuit for controlling the first to fourth switch elements,
The first capacitor is connected between the non-inverting input terminal and a predetermined first voltage;
The first switch element is connected in parallel with the first capacitor,
The second switch element selectively transmits the first voltage connected to the first contact and the voltage of the inverting input terminal connected to the second contact through the second capacitor. Switch to non-inverting input terminal,
The output terminal is connected to the inverting input terminal through a parallel circuit of the third switch element and the fourth capacitor,
The fourth switch element selectively inputs the third voltage connected to the first contact and the second voltage connected to the second contact through the third capacitor. Connect to the terminal and switch,
The control circuit is
In the sampling period, the first and third switch elements are turned on and short-circuited, and the second and fourth switch elements are switched to the second contact point, thereby referring to the first voltage and the second switch element. Sampling the voltage of
In the hold period, the first and third switch elements are turned off and opened, the second and fourth switch elements are switched to the first contact points, and the third voltage is referred to, and the output By holding the output voltage from the terminal,
A differential voltage between the second voltage and the third voltage is amplified and output as the output voltage.

  In the switched capacitor circuit, the divided value obtained by dividing the capacitance value of the first capacitor by the capacitance value of the second capacitor is obtained by dividing the capacitance value of the third capacitor by the capacitance value of the fourth capacitor. The division value is set to be substantially equal to the calculated division value.

  In the switched capacitor circuit, the capacitance value of the first capacitor is substantially equal to the capacitance value of the third capacitor, and the capacitance value of the second capacitor is equal to the capacitance value of the fourth capacitor. It is characterized by being set to be substantially equal.

Furthermore, in the switched capacitor circuit,
The first voltage and the third voltage are set to a predetermined reference voltage,
The second voltage is an input voltage.

  Here, in the switched capacitor circuit, the reference voltage is set to a ground voltage.

  Still further, in the switched capacitor circuit, the first voltage is set to a ground voltage.

Furthermore, in the switched capacitor circuit,
A series input circuit of the fourth switch element and the third capacitor is:
A plurality of series input circuits of a fifth switch element corresponding to the fourth switch element and a fifth capacitor corresponding to the third capacitor, and connecting the plurality of series input circuits in parallel;
The differential voltage between the second voltage and the third voltage for each of the series input circuits is amplified and added, and output as the output voltage.

The AD converter according to the second invention is
The switched capacitor circuit;
Conversion means for converting the output voltage from the operational amplifier into digital data;
Storage means for temporarily storing digital data from the conversion means;
DA conversion means for converting the digital data of the output voltage from the storage means into an analog input voltage and outputting as the third voltage for each of the serial input circuits,
A successive approximation AD conversion process is performed by inputting an input voltage as the second voltage and sequentially comparing the input voltage with the switched capacitor circuit.

  Therefore, according to the switched capacitor circuit of the present invention, it is possible to provide a switched capacitor circuit that has a simpler circuit configuration than that of the prior art and that can improve offset-free performance, and an AD converter using the switched capacitor circuit. .

It is a circuit diagram which shows the structural example of differential amplifier DA1 which concerns on a prior art. It is a graph which shows the offset in the example of an operation characteristic of differential amplifier DA1 of FIG. 1A. It is a circuit diagram which shows the structural example of the buffer circuit of a voltage follower using operational amplifier OP1 which concerns on a prior art. It is a circuit diagram which shows the structural example of the switched capacitor circuit which concerns on a prior art example. It is a circuit diagram which shows the structural example of the switched capacitor circuit which concerns on Embodiment 1 of this invention. FIG. 4 is a circuit diagram illustrating an operation during a sampling period of the switched capacitor circuit of FIG. 3. FIG. 4 is a circuit diagram illustrating an operation during a hold period of the switched capacitor circuit of FIG. 3. It is a circuit diagram which shows the structural example of the switched capacitor circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the structural example of the successive approximation type AD converter which concerns on Embodiment 3 of this invention. It is a flowchart which shows the successive approximation type AD conversion process performed by the AD conversion apparatus of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
FIG. 3 is a circuit diagram showing a configuration example of the switched capacitor circuit according to the first embodiment of the present invention. In FIG. 3, the switched capacitor circuit according to the first embodiment includes an operational amplifier OP11, switches S1 to S4, capacitors 11, 12, 21, and 22 and a control circuit 20A.

  Here, the switches S1, S3 are turned on or off to short-circuit or open both terminals. The switches S2 and S4 are switched by selectively connecting the common terminal to either the contact point a or the contact point b.

  The non-inverting input terminal of the operational amplifier OP11 is connected to the voltage V1 through the capacitor 21 having the capacitance value Cap and to the voltage V1 through the switch S1. The non-inverting input terminal of the operational amplifier OP11 is connected to the voltage V1 through the capacitor 22 having the capacitance value Cbp and the common terminal of the switch S2 and the contact a, and is also connected to the common terminal of the capacitor 22 having the capacitance value Cbp and the switch S2. And an inverting input terminal of the operational amplifier OP11 through the contact b. A parallel circuit of a switch S3 and a capacitor 12 having a capacitance value Cbn is connected between the inverting input terminal and the output terminal of the operational amplifier OP11. The voltage V3 is connected to the inverting input terminal of the operational amplifier OP11 via the capacitor 11 having the capacitance value Can via the common terminal of the switch S4 and the contact a, and the switch S4 via the capacitor 11 having the capacitance value Can. The voltage V2 is connected through the common terminal and the contact b. Here, the switch S4 and the capacitor 11 constitute a series input circuit.

  The control circuit 20A uses the control signal φ to control switching of the switches S2 and S4 and on / off of the switches S1 and S3, and generates and outputs a voltage V1 having a predetermined value. As will be described in detail later, the control circuit 20A generates and outputs a predetermined voltage V2 or V3 when the voltage V2 or V3 is a set value. The same applies to the second and third embodiments.

  4A is a circuit diagram illustrating an operation during a sampling period of the switched capacitor circuit of FIG. 3, and FIG. 4B is a circuit diagram illustrating an operation during a hold period of the switched capacitor circuit of FIG. Hereinafter, the operation of the switched capacitor circuit of FIG. 3 and the offset-free condition will be described with reference to FIGS. 4A and 4B. Note that the sampling period and the hold period are alternately repeated at the same time, for example.

(1) Sampling period:
In the sampling period, the switch S1 is turned on and short-circuited, the switch S2 is switched to the contact b, the switch S3 is turned on and short-circuited, and the switch S4 is switched to the contact b. At this time, the charge Qp_s of the non-inverting input terminal of the operational amplifier OP11 and its voltage Vp_s, and the charge Qm_s of the inverting input terminal and its voltage Vm_s are expressed by the following equations.

Qp_s = Cap (Vp_s−V1) + Cbp (Vp_s−Vm_s) (8)
Vp_s = V1 (9)
Qm_s = Can (Vm_s−V2) + Cbn (Vm_s−Vout_s) (10)
Vm_s = Vp_s + Voffset = Vout_s (11)

  Therefore, the following equation is obtained from the relationship of the above equations.

Qp_s = −Cbp × Voffset (12)
Qm_s = Can (V1 + Voffset−V2) (13)
Vm_s = V1 + Voffset (14)

(2) Hold period:
In the hold period, the switch S1 is turned off and opened, the switch S2 is switched to the contact a, the switch S3 is turned off and opened, and the switch S4 is switched to the contact a. At this time, the charge Qp_h of the non-inverting input terminal of the operational amplifier OP11 and its voltage Vp_h, the charge Qm_h of the inverting input terminal and its voltage Vm_h are expressed by the following equations.

Qp_h = Cap (Vp_h−V1) + Cbp (Vp_h−V1) (15)
Qm_h = Can (Vm_h−V3) + Cbn (Vm_h−Vout_h) (16)
Vm_h = Vp_h + Voffset (17)

  In the hold period, the following equation is established because there is no path through which each charge of the non-inverting input terminal and the inverting input terminal flows.

Qp_h = Qp_s (18)
Qm_h = Qm_s (19)

  From the above formula, the following formula is obtained.

Vp_h = V1-Cbp / (Cap + Cbp) × Voffset (20)
Vm_h = V1 + Cap / (Cap + Cbp) × Voffset (21)

In formula (22), Cap × Cbn = Can × Cbp (23)
That is,
Cap / Cbp = Can / Cbn (24)
If the above is referred to as condition A, the following equation is obtained.

Vout_h = V1 + (Can / Cbn) × (V2−V3) (25)

Further, in formula (22), Cap = Can (26)
Cbp = Cbn (27)
If the above is referred to as condition B, the following equation is obtained similarly.

Vout_h = V1 + (Can / Cbn) × (V2−V3) (28)

  To summarize the above considerations, in the condition A or condition B, the output voltage Vout_s is expressed by the following equation in the sampling period.

Vout_s = V1 + Voffset (29)

  In the hold period, the output voltage Vout_h is expressed by the following equation.

Vout_h = V1 + (Ca / Cb) × (V2−V3) (30)

  Here, Ca = Cap = Can and Cb = Cbp = Cbn (in the case of condition B).

  Therefore, the switched capacitor circuit of FIG. 3 is offset-free, and the differential voltage between the input voltages V2 and V3 can be amplified or attenuated by the voltage amplification factor (Ca / Cb) and output. Note that the equation of condition A or condition B may be an equation of substantially equal relation.

  As described above, according to the switched capacitor circuit of FIG. 3, the two capacitors 21 and 22 with respect to the non-inverting input terminal of the differential amplifier OP11 are compared with the switched capacitor circuit of FIG. And a switch capacitor circuit that has a simpler circuit configuration than that of the prior art, can improve the offset-free performance, and maintains the amplification function and the level shift function by further adding two switches S1 and S2. Can be provided.

Here, even if the capacitance values Cap and Cbp of the added capacitors 21 and 22 have an error (Cap ≠ Can, Cbp ≠ Cbn), the output offset voltage becomes smaller than that in the conventional technique as shown below. . For example, the error δ is | Cap−Can | / (Cap + Can) = δ (31)
The error voltage Verror due to the offset in the output voltage Vout is obtained from the equation (22) under the approximate condition of δ ² << 1.

Verror≈2 × δ × Voffset (32)

  For example, by setting V1 = V3 = 0V, a simple amplifier circuit of output voltage Vout = (Ca / Cb) × V2 can be configured by the switched capacitor circuit according to the present embodiment. Here, it is possible to operate as a DA converter by setting V2 = VDD. Note that the voltage V1 = V3 is not limited to V1 = V3 = 0V, and may be set to a predetermined reference voltage.

  For example, by setting V1 = 0V, the switched capacitor circuit according to the present embodiment can configure a differential amplifier circuit of output voltage Vout = (Ca / Cb) × (V2−V3).

Embodiment 2. FIG.
FIG. 5 is a circuit diagram showing a configuration example of a switched capacitor circuit according to Embodiment 2 of the present invention. The switched capacitor circuit according to the second embodiment in FIG. 5 differs from the switched capacitor circuit according to the first embodiment in FIG. 3 in the following points.
(1) Instead of the series input circuit of the switch S4 and the capacitor 11, a series input circuit of the switch S4a and the capacitor 11-1, a series input circuit of the switch S4b and the capacitor 11-2,..., And the switch S4N and the capacitor 11-N The parallel input circuit is provided.
(2) Instead of the control circuit 20A, a control circuit 20B that generates and outputs control signals φ, φ1 to φN and a voltage V1 is provided.
Hereinafter, the difference will be described in detail.

  In FIG. 5, capacitors 11-1 to 11-N have capacitance values Ca1 to CaN, respectively, and capacitor 12 has a capacitance value Cb. Capacitor 21 has a capacitance value Cat = Ca1 + Ca2 +... + CaN, and capacitor 22 has a capacitance value Cb.

  The inverting input terminal of the operational amplifier OP11 is connected to the voltage V3a via the contact point a of the capacitor 11-1 and the switch S4a, and is connected to the voltage V2a via the contact point b of the capacitor 11-1 and the switch S4a. Further, the inverting input terminal of the operational amplifier OP11 is connected to the voltage V3b via the contact point a of the capacitor 11-2 and the switch S4b, and is connected to the voltage V2b via the contact point b of the capacitor 11-2 and the switch S4b. Similarly, the inverting input terminal of the operational amplifier OP11 is connected to the voltage V3N via the contact a of the capacitor 11-N and the switch S4N, and to the voltage V2N via the contact b of the capacitor 11-N and the switch S4N. Connected.

  Control circuit 20B generates control signal φ for controlling switches S1 to S3 and also generates control signals φ1 to φN for controlling switching of switches S4a to S4N, respectively. Here, the switches S1 to S3 are controlled in the same manner as in the first embodiment, and the switches S4a to S4N are switched to the contact b in the sampling period and switched to the contact a in the hold period.

  The output voltage Vout in the hold period of the switched capacitor circuit configured as described above is expressed by the following equation.

Vout
= V1 + Ca1 / Cb × (V2a−V3a)
+ Ca2 / Cb × (V2b−V3b)
...
+ CaN / Cb × (V2N−V3N) (33)

  Therefore, the switched capacitor circuit according to the second embodiment can configure an amplifier circuit that adds and amplifies a plurality of N input voltage differences (V2a−V3a), (V2b−V3b),..., (V2N−V3N). .

  Here, by setting V3a = V3b =... = V3N and V2a = V2b =... = V2N, a voltage generation circuit that can be adjusted with a predetermined step voltage such as 0.1 V step can be configured.

Embodiment 3. FIG.
FIG. 6 is a circuit diagram showing a configuration example of a successive approximation AD converter according to Embodiment 3 of the present invention. The AD converter according to the third embodiment of FIG. 6 is particularly configured by using a switched capacitor circuit (N = 4) according to the third embodiment of FIG. It is a feature. The successive approximation AD converter includes a switched capacitor circuit (N = 4) according to Embodiment 3 of FIG. 5, an inverter 30, a 4-bit register 31, a DA converter 32, and a control circuit 20C. Configured. Hereinafter, differences from the third embodiment will be described in detail.

  In FIG. 6, an input voltage Vin is input as a voltage V2 to the contacts b of the switches S4a to S4d. The output voltage Vout from the operational amplifier OP11 is input to the 4-bit register 31 and stored as binary digital data via the inverter 30. The 4-bit register 31 constitutes temporary storage means, and outputs 4-bit digital data Dout relating to the stored output voltage to an external circuit and also to the DA converter 32. The DA converter 32 performs digital / analog conversion of the input digital data Dout to the voltage V3 and outputs it to the contacts a of the switches S4a to S4d.

  The control circuit 20C controls the switches S1 to S3 in the same manner as in the second embodiment, and generates and outputs a predetermined voltage V1 (a ground voltage in the present embodiment). The control circuit 20C generates control signals φ1 to φ4 and outputs them to the switches S4a to S4d, respectively, and controls the switching as shown in FIG. Here, in particular, the control circuit 20C first switches the switches S4a to S4d to b in the sampling period in each cycle of processing, and then sequentially switches the switches S4a to S4d from the contact b to the contact a in the hold period. Control. Further, the control circuit 20C outputs the control signal φ to the 4-bit register 31 as a synchronous clock.

  In this configuration example, the capacitance value Cat of the capacitor 21 is expressed by the following equation.

Cat = Ca1 + Ca2 + Ca3 + Ca4 (34)

  Further, the relationship between the capacitance values of the capacitors 11-1 to 11-N, 12, and 22 is set, for example, as in the following equation.

Ca1 / Cb = 3
Ca2 / Cb = 3
Ca3 / Cb = 6
Ca4 / Cb = 12 (35)

  FIG. 7 is a flowchart showing the successive approximation type AD conversion process executed by the AD conversion apparatus of FIG. 6, and the process of FIG. 7 shows the process of one sample cycle of AD conversion. Hereinafter, the successive approximation AD conversion process will be described with reference to FIG.

  In the AD conversion process of FIG. 7, for example, it is assumed that the input voltage Vin = 0 to 1V, the power supply voltage VDD = 3V, and the threshold voltage Vth = 1.5V of the inverter 30, and the number of generated bits of the voltage V3 is small. The initial voltage V3 is set to 0V instead of 0.5V. This is because if the initial voltage V3 is set to 0.5V, it is necessary to set 1.5V as the voltage V1.

  The 4-bit digital data after AD conversion is composed of the first to fourth bits, where the first bit is MSB (Most Significant Bit) and the fourth bit is LSB (Least Significant Bit). To do.

  In step S1 of FIG. 7, first, in the sampling mode, the switches S1 and S3 are turned on to short-circuit, and the switch S2 is switched to the contact b. Further, the switches S4a to S4d are switched to the contact point b, and the input voltage Vin is sampled. Next, in step S2, in the hold mode, the switches S1 and S3 are turned off and opened, the switch S2 is switched to the contact a, and the input voltage Vin is held.

  Further, in step S3, when the voltage V3 is set to 0V (ground voltage) and the switch S4a is switched to the contact point a, a voltage value of 3 × (Vin−V3) is output to the output voltage Vout. Next, in step S4, it is determined by the inverter 30 whether or not the output voltage Vout ≧ 1.5V. The control circuit 20C proceeds to step S5 when YES, and proceeds to step S6 when NO. In step S5, 1 is set in the MSB of the 4-bit register 31, the voltage value of V3 + 0.5V is set to the voltage V3, and the process proceeds to step S7. On the other hand, in step S6, 0 is set in the MSB, the voltage value of V3 + 0V is set to the voltage V3, and the process proceeds to step S7.

  Next, in step S7, the switch S4b is switched to the contact a, and a voltage value of 6 × (Vin−V3) is output to the output voltage Vout. In step S8, it is determined whether or not the output voltage Vout ≧ 1.5V. If YES, the process proceeds to step S9. If NO, the process proceeds to step S10. In step S9, 1 is set in the second bit, the calculated value of V3 + 0.25V is set to voltage V3, and the process proceeds to step S11. On the other hand, in step S10, 0 is set in the second bit, the voltage value of V3 + 0V is set to voltage V3, and the process proceeds to step S11.

  Next, in S11, the switch S4c is switched to the contact point a, a voltage value of 12 × (Vin−V3) is output to the output voltage Vout, and the process proceeds to Step S12. In step S12, it is determined whether or not the output voltage Vout ≧ 1.5V. If YES, the process proceeds to step S13. If NO, the process proceeds to step S14. In step S13, 1 is set in the third bit, the voltage value of V3 + 0.125V is set to voltage V3, and the process proceeds to step S15. On the other hand, in step S14, 0 is set in the third bit, the voltage value of V3 + 0V is set to voltage V3, and the process proceeds to step S15.

  Next, in step S15, the switch S4d is switched to the contact point a, a voltage value of 24 × (Vin−V3) is output to the output voltage Vout, and the process proceeds to step S16. In step S16, it is determined whether or not the output voltage Vout ≧ 1.5V. If YES, the process proceeds to step S17. If NO, the process proceeds to step S18. In step S17, 1 is set in LSB, and the process returns to step S1 to execute the process of the next cycle. On the other hand, in step S18, 0 is set in LSB, and the process returns to step S1 to execute the process of the next cycle.

  In the AD conversion process of FIG. 7, for example, when the input voltage Vin = 0.7V, the output voltage Vout = 2.1V is set in step S3, YES is set in step S4, and 1 is set in the MSB in step S5. V3 = 0.5V. Next, in step S7, the output voltage Vout = 1.2V, NO in step S8, 0 is set in the second bit in step S10, and the voltage V3 = 0.5V. Next, in step S11, the output voltage Vout = 2.4V, YES in step S12, 1 is set in the third bit in step S13, and the voltage V3 = 0.625V. Next, in step S12, the output voltage Vout becomes 1.8V, YES in step S16, and 1 is set in LSB. That is, 4-bit output voltage digital data “1011” is obtained.

  As described above, according to the present embodiment, the AD conversion apparatus is configured by using the switched capacitor circuit using the multi-input operational amplifier, so that the AD conversion can be performed with a simple circuit configuration as compared with the prior art. The device can be configured.

  In the fourth embodiment, a 4-bit successive approximation AD converter is configured. However, the present invention is not limited to this, and similarly, a 1-bit or multiple-bit successive approximation AD converter is configured. May be.

  In the above embodiments, a switched capacitor circuit and an AD converter using the same are disclosed. However, these circuits and devices can be used for a semiconductor device or a semiconductor memory device, for example.

  As described above in detail, according to the switched capacitor circuit according to the present invention, the circuit configuration is simpler than that of the prior art, and the switched capacitor circuit capable of improving the offset-free performance and the AD using the same A conversion device can be provided.

11, 12, 21, 22, 11-1 to 11-4, 11-1 to 11-N ... capacitors,
20, 20A, 20B, 20C ... control circuit,
30 ... Inverter,
31 ... 4-bit register,
32 ... DA converter,
DA1 ... differential amplifier,
OP1, OP11 ... operational amplifiers,
S1 to S4, S4a to S4d, S4a to S4N, switches.

Claims (8)

An operational amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal;
First to fourth capacitors;
The first and third switch elements that are short-circuited or opened by being turned on or off, respectively, and the second and fourth switches that selectively switch the common terminal to either the first contact or the second contact. Switch elements of
A switched capacitor circuit comprising a control circuit for controlling the first to fourth switch elements,
The first capacitor is connected between the non-inverting input terminal and a predetermined first voltage;
The first switch element is connected in parallel with the first capacitor,
The second switch element selectively transmits the first voltage connected to the first contact and the voltage of the inverting input terminal connected to the second contact through the second capacitor. Switch to non-inverting input terminal,
The output terminal is connected to the inverting input terminal through a parallel circuit of the third switch element and the fourth capacitor,
The fourth switch element selectively inputs the third voltage connected to the first contact and the second voltage connected to the second contact through the third capacitor. Connect to the terminal and switch,
The control circuit is
In the sampling period, the first and third switch elements are turned on and short-circuited, and the second and fourth switch elements are switched to the second contact point, thereby referring to the first voltage and the second switch element. Sampling the voltage of
In the hold period, the first and third switch elements are turned off and opened, the second and fourth switch elements are switched to the first contact points, and the third voltage is referred to, and the output By holding the output voltage from the terminal,
A switched capacitor circuit, wherein a differential voltage between the second voltage and the third voltage is amplified and output as the output voltage.   The division value obtained by dividing the capacitance value of the first capacitor by the capacitance value of the second capacitor is substantially equal to the division value obtained by dividing the capacitance value of the third capacitor by the capacitance value of the fourth capacitor. 2. The switched capacitor circuit according to claim 1, wherein the switched capacitor circuits are set to be equal.   The capacitance value of the first capacitor is set to be substantially equal to the capacitance value of the third capacitor, and the capacitance value of the second capacitor is set to be substantially equal to the capacitance value of the fourth capacitor. The switched capacitor circuit according to claim 1. The first voltage and the third voltage are set to a predetermined reference voltage,
The switched capacitor circuit according to claim 1, wherein the second voltage is an input voltage.   5. The switched capacitor circuit according to claim 4, wherein the reference voltage is set to a ground voltage.   The switched capacitor circuit according to claim 1, wherein the first voltage is set to a ground voltage. A series input circuit of the fourth switch element and the third capacitor is:
A plurality of series input circuits of a fifth switch element corresponding to the fourth switch element and a fifth capacitor corresponding to the third capacitor, and connecting the plurality of series input circuits in parallel;
4. The difference voltage between the second voltage and the third voltage for each of the series input circuits is amplified and added to output as the output voltage. The switched capacitor circuit according to one. A switched capacitor circuit according to claim 7,
Conversion means for converting the output voltage from the operational amplifier into digital data;
Storage means for temporarily storing digital data from the conversion means;
DA conversion means for converting the digital data of the output voltage from the storage means into an analog input voltage and outputting as the third voltage for each of the serial input circuits,
An AD converter that performs a successive approximation type AD conversion process by inputting an input voltage as the second voltage and sequentially comparing the input voltage with the switched capacitor circuit.

Images