JP2017212367A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of being miniaturized while suppressing reduction in electrostatic capacitance, and to provide the semiconductor device.SOLUTION: A method of manufacturing a semiconductor device includes the following steps of: forming a first insulating film 102 on a substrate, and then, providing a plurality of openings on the first insulating film 102, and forming a metal layer on the first insulating film 102 while filling the plurality of openings; etching the metal layer to remove the metal layer on the first insulating film 102, and forming recessed parts B1 on an upper surface of the metal layer that fills each of the plurality of openings; and forming on the first insulating film 102 a lower layer electrode 110, a second insulating film 112, and an upper layer electrode 114 in this order to form an MIM capacitor C.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  An MIM (Metal Insulator Metal) capacitor is known as a capacitor element in a semiconductor device. An MIM capacitor is a capacitor having a metal-insulator-metal laminated structure. As a conventional method for manufacturing an MIM capacitor, for example, a method disclosed in Patent Document 1 is known.

  In the manufacturing method of the MIM capacitor disclosed in Patent Document 1, an insulating material is deposited on the lower electrode film at a film forming temperature within a range of 430 ° C. or higher and 500 ° C. or lower, which is higher than a normal capacitor insulating film forming temperature. And forming a dielectric film (capacitor film) having a plurality of fine gaps with the upper surface of the lower electrode film and having an upper surface with irregularities along with the gap, and forming a lower portion on the dielectric film. The same conductive material as that of the electrode film is deposited to form an upper electrode film.

  In Patent Document 1, according to the MIM capacitor of the manufacturing method as described above, the dielectric film having a substantially larger surface area than the flat dielectric film is formed by forming the upper surface of the dielectric film in an uneven shape. Since a film can be formed, the capacitance can be increased compared to a conventional MIM capacitor of the same size.

JP 2010-205763 A

  By the way, modern semiconductor devices are increasingly miniaturized, and miniaturization is required for individual circuit elements integrated in the semiconductor device. The MIM capacitor is no exception, and it is necessary to greatly reduce the element area. However, it is meaningless if the capacitance of the MIM capacitor is reduced by downsizing.

  In the MIM capacitor, in order to reduce the element area without lowering the capacitance, it is necessary to increase the capacitance per unit area. As a method for increasing the capacitance per unit area, for example, reducing the thickness of the insulating film can be mentioned. However, when the thickness of the insulating film is reduced, there arises a new problem that the breakdown voltage is lowered.

  In that regard, the MIM capacitor according to Patent Document 1 is devised so that the capacitance per unit area increases. However, in the MIM capacitor according to Patent Document 1, the distance between the lower electrode film and the upper electrode film is increased at the portion where the gap between the lower electrode film and the dielectric film is provided, and the capacitance is reduced. There is a problem that it ends up. In addition, since the dielectric constant differs between the dielectric film and the gap region, there is a problem that the capacitance is likely to vary.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that can be reduced in size while suppressing a decrease in capacitance.

  In the method for manufacturing a semiconductor device according to the present invention, after forming a first insulating film on a substrate, a plurality of openings are provided in the first insulating film, and the first insulating film is filled while filling the plurality of openings. Forming a metal layer on the film; etching the metal layer to remove the metal layer on the first insulating film; and forming a recess on an upper surface of the metal layer filling each of the plurality of openings. And a step of forming a MIM capacitor by forming a lower electrode, a second insulating film, and an upper electrode in this order on the first insulating film.

  On the other hand, a semiconductor device according to the present invention is provided on a wiring formed on a substrate, a first insulating film formed on the substrate and covering the wiring, and the first insulating film on the wiring. A plurality of apertures filled with metal and having recesses on the upper surface of the metal, and formed in this order on the first insulating film, each corresponding to the plurality of apertures. And a MIM capacitor including a lower layer electrode having a recess at a position, a second insulating film, and an upper layer electrode.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the manufacturing method and semiconductor device of a semiconductor device which can be reduced in size, suppressing the fall of an electrostatic capacitance.

It is a longitudinal cross-sectional view which shows an example of schematic structure of the semiconductor device which concerns on embodiment. It is a top view which shows an example of the via plug array of the semiconductor device which concerns on embodiment. It is a part of longitudinal cross-sectional view which shows an example of the manufacturing process of the semiconductor device which concerns on embodiment. It is a part of longitudinal cross-sectional view which shows an example of the manufacturing process of the semiconductor device which concerns on embodiment. It is a part of longitudinal cross-sectional view which shows an example of the manufacturing process of the semiconductor device which concerns on embodiment. It is a longitudinal cross-sectional view which shows the structure of the semiconductor device which concerns on a comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  With reference to FIG. 1 to FIG. 5, a method of manufacturing a semiconductor device including an MIM capacitor and a semiconductor device according to the present embodiment will be described. Before that, for understanding of the semiconductor device according to the present embodiment. Next, a semiconductor device 20 according to a comparative example including the MIM capacitor CAP according to the comparative example will be described with reference to FIG.

  As shown in FIG. 6, the semiconductor device 20 includes a lower layer electrode 200, an insulating film 202, an upper layer electrode 204, via plugs 208 and 209, wirings 210 and 212, and an insulating film 206.

  The MIM capacitor CAP according to the comparative example is formed using the lower layer electrode 200 and the upper layer electrode 204 as both electrodes (electrode pairs) and the insulating film 202 as a capacitor film. The lower layer electrode 200 is, for example, a multilayer metal film formed by sandwiching an Al (aluminum) based alloy film between refractory metals such as Ti (titanium) and TiN (titanium nitride) or a laminated film thereof. To Ti / TiN / Al / TiN. As the insulating film 202, a SiON film (silicon oxynitride film) is used as an example, and as the upper electrode 204, a TiN film is used as an example.

  The upper layer electrode 204 is connected to the wiring 210 by a via plug 208 provided in the insulating film 206, and the lower layer electrode 200 is connected to the wiring 212 by a via plug 209 provided in the insulating film 206. The MIM capacitor CAP is connected to other circuit elements and the like of the semiconductor device 20 by wirings 210 and 212.

  In the MIM capacitor CAP according to the comparative example configured as described above, since the insulating film 202 as the capacitor film is formed flat, the capacitance of the MIM capacitor CAP is the size of the insulating film 202 in plan view. Determined by.

  Next, a semiconductor device 10 including the MIM capacitor C according to the present embodiment will be described with reference to FIGS. 1 shows a schematic configuration of a semiconductor device 10 including an MIM capacitor C according to the present embodiment, FIG. 2 shows a via plug array in the semiconductor device 10, and FIGS. 3 to 5 show a semiconductor according to the present embodiment. The main process in the manufacturing method of the apparatus 10 is shown schematically.

  In the semiconductor device 10 according to the present embodiment, other elements such as an active element such as a transistor and a passive element such as a resistor may be formed along with the MIM capacitor. Only the peripheral part of the MIM capacitor is shown in the figure. In addition, a certain layer is formed on “another layer” or “on a substrate” in the present embodiment is not limited to the case where a certain layer is formed on another layer or directly on the substrate. The case where it forms through three layers is included.

  As shown in FIG. 1, the semiconductor device 10 includes a lower layer wiring 100, a via plug array 150, an insulating film 102, an MIM capacitor C, via plugs 118 and 119, an interlayer film 116, an insulating film 124, and upper layer wirings 120 and 122. It is configured. The semiconductor device 10 according to the present embodiment includes a substrate and a circuit element (an active element such as a transistor, a passive element such as a resistor) layer formed on the substrate, and the lower layer wiring 100 includes the circuit element layer. Although formed above, the substrate and the circuit element layer are not shown in FIG.

  The lower layer wiring 100 is a part of a wiring layer that connects each circuit element in the semiconductor device 10. In this embodiment, a via plug array 150 is formed on the lower layer wiring 100. In addition, the periphery of the lower layer wiring 100 and the via plug array 150 is covered with an insulating film 102.

  The via plug array 150 is a part in which via plugs 104 in which openings (via holes) provided in the insulating film 102 are filled with metal are arranged in an array. Each via plug 104 constituting the via plug array 150 has a recess B1 in the upper part thereof. The position of the recess B1 corresponds to the recess B2 of the insulating film 112 of the MIM capacitor C. As will be described later, the recess B1 of the via plug 104 is provided to form the recess B2 in the insulating film 112 in the manufacturing process of the semiconductor device 10.

  The MIM capacitor C according to the present embodiment includes a lower layer electrode 110 that is an electrode pair of the MIM capacitor C, an upper layer electrode 114, and an insulating film 112 as a capacitor film, and is disposed above the via plug array 150. ing. The upper part of the MIM capacitor C is covered with an interlayer film 116.

  As described above, the recess B2 is provided in the insulating film 112 of the MIM capacitor C, and the surface area of the insulating film 112 is smaller than that of the MIM capacitor CAP according to the comparative example having the same element area. It has been expanded. Thus, the MIM capacitor C according to the present embodiment can increase the capacitance as compared with the MIM capacitor CAP according to the comparative example.

  The upper layer wirings 120 and 122 are part of a wiring layer that connects each circuit element in the semiconductor device 10, and the MIM capacitor C is connected to the other circuit elements of the semiconductor device 10 through the upper layer wirings 120 and 122. ing. In other words, the upper layer wiring 120 is connected to the upper layer electrode 114 which is one electrode of the MIM capacitor C via the via plug 118, and the upper layer wiring 122 is connected to the lower layer electrode 110 which is the other electrode of the MIM capacitor C with the via plug 119. Connected through. The upper wirings 120 and 122 are covered with an insulating film 124 formed on the interlayer film 116.

  Next, the via plug array 150 according to the present embodiment will be described in more detail with reference to FIG. FIG. 2A is a plan view of the via plug array 150 according to the present embodiment. As shown in FIG. 2A, the via plug array 150 has a substantially square shape, and a plurality of via plug arrays 150 (6 × 7 = 42 in this embodiment) arranged in an array with a constant mutual interval. The via plug 104 is configured. The via plug array 150 is formed so as to be located inside the insulating film 112 in plan view.

  As shown in FIG. 1, each via plug 104 has a recess B <b> 1 on the upper surface, thereby causing the insulating film 112 to have a recess B <b> 2, thereby increasing the surface area of the insulating film 112. In the MIM capacitor C according to the present embodiment, the via plugs 104 having the recesses B1 are arranged in an array so that the insulating film 112 also has the recesses B2 arranged in an array at positions corresponding to the recesses B1. It is expressed and the capacitance is further increased.

  In the present embodiment, an example in which the cross-sectional shape (the shape in plan view) of each via plug 104 of the via plug array 150 is substantially square has been described. However, the present invention is not limited to this, and other shapes such as a circular shape and an elliptical shape are available. It is good also as a form made into this shape. FIG. 2B shows a form in which the cross-sectional shape of the via plug 104 is a substantially regular hexagonal shape. As described above, by using the via plug 104a having a substantially regular hexagonal cross-sectional shape, it is possible to obtain the via plug array 150a in which the via plugs 104a are arranged closest.

  Next, a method for manufacturing the semiconductor device 10 including the MIM capacitor C according to the present embodiment will be described with reference to FIGS.

First, a circuit element (an active element such as a transistor, a passive element such as a resistor) is formed on a substrate (not shown), an insulating film is formed on the circuit element, and then a via contact for wiring is formed.
Next, after forming a metal film to be a wiring layer on the insulating film, the metal film is processed by photolithography and etching, and the lower layer wiring 100 connected to the via contact is formed on an insulating film 112 described later. Form in the corresponding position. Thereafter, an insulating film 102 is formed on the lower layer wiring 100.

  Next, using photolithography and dry etching, a plurality of vias V1 corresponding to a via plug array 150 described later is formed in the insulating film 102 on the lower wiring 100, and then the insulating film 102 including the inside of the via V1. An adhesion layer is formed on the top of the substrate. The adhesion layer is a base layer that increases the adhesion degree of a W (tungsten) layer to be formed next. As an example, a Ti film and a TiN film are formed using a CVD (Chemical Vapor Deposition) method or the like. Thereafter, as shown in FIG. 3A, a metal layer 130 for burying the via V1 is formed by using a CVD method or the like. The metal layer 130 is formed using W, for example.

  Next, as shown in FIG. 3B, the entire surface is etched by dry etching (W etch back) to form a plurality of via plugs 104. At this time, the cross section of each of the plurality of via plugs 104 is, for example, a substantially square of 1 μm × 1 μm, and the interval between adjacent via plugs 104 is, for example, 1 μm. During the main etching, a recess is formed to form a recess B1 in the via plug 104. The recess is generated, for example, by setting the W etch back time longer than usual. By this step, the via plug array 150 (or via plug array 150a) is formed on the lower layer wiring 100.

  Next, as shown in FIG. 4A, a lower layer electrode 110 made of a multilayer metal film having a laminated film of a refractory metal of Ti and TiN, an Al alloy film, and a TiN film is formed by sputtering or the like. Form. For example, the film structure of the lower layer electrode 110 is Ti / TiN / Al / TiN from the lower layer.

  Thereafter, an insulating film 112 is formed by a CVD method or the like. The insulating film 112 is formed using, for example, a SiON film. Thereafter, the upper electrode 114 is formed by sputtering or the like. The upper layer electrode 114 is formed by a TiN film, for example. The lower layer electrode 110 and the upper layer electrode 114 constitute an electrode pair of the MIM capacitor C according to the present embodiment, and the insulating film 112 constitutes a capacitor film of the MIM capacitor C according to the present embodiment.

  Here, as shown in FIG. 4A, the presence of the recess B1 in the via plug array 150 also forms a recess in the lower layer electrode 110, the insulating film 112, and the upper layer electrode 114. By forming the recess B2 in the insulating film 112, the surface area of the insulating film 112 increases compared to the surface area of the insulating film 202 (see FIG. 6) of the MIM capacitor CAP according to the comparative example having an equivalent element area. As a result, the MIM capacitor C according to the present embodiment is configured so that the capacitance can be increased as compared with the MIM capacitor CAP according to the comparative example.

  As shown in FIG. 4B, the insulating film 112 and the upper layer electrode 114 are processed using photolithography and dry etching, and are formed into a desired MIM capacitor C shape.

  Next, as shown in FIG. 5A, an interlayer film 116 is formed by a CVD method or the like.

  Next, after forming the via V2 corresponding to the via plugs 118 and 119 in the interlayer film 116, a multilayer metal film is formed on the interlayer film 116 while burying the via V2. Next, the multilayer metal film is processed using photolithography and etching to form upper layer wirings 120 and 122. Next, as shown in FIG. 5B, an insulating film 124 is formed on the upper wirings 120 and 122, and the semiconductor device 10 according to the present embodiment is manufactured.

  As described above in detail, according to the MIM capacitor C in the semiconductor device 10 according to the present embodiment, the surface area of the MIM capacitor can be increased without reducing the breakdown voltage by increasing the surface area without reducing the thickness of the insulating film. The capacity per hit can be increased. For example, if 16 square via plugs 104 of 1 μm × 1 μm are arranged in a region corresponding to a square MIM capacitor C (capacitor film) of 9 μm × 9 μm and the depth of the recess is 1 μm, the surface area is 1.7. Can be doubled. This increases the capacity per unit area by about 1.7 times.

In the above-described embodiment, an example in which the SiON film is used as the capacitor film of the MIM capacitor has been described. However, the present invention is not limited to this, and other insulating films such as a SiN film (silicon nitride film), Ta ₂ O, or the like. _Five films (tantalum oxide films) or the like may be used.

  In the above embodiment, the via plug array in which the via plugs are arranged in an array shape has been described as an example. However, the present invention is not limited to this. For example, the via plugs are arranged in a checkered pattern or randomly arranged. It is good also as a form.

  In the above embodiment, the upper layer wirings 120 and 122 are formed on the MIM capacitor C via the via plugs 118 and 119 and connected to other circuit elements of the semiconductor device 10 by way of example. It is not limited to this. For example, the lower electrode 110 and the upper electrode 114 may be extended to form a wiring and connected to other circuit elements.

10, 20 Semiconductor device 100 Lower layer wiring 102 Insulating film 104 Via plug 110 Lower layer electrode 112 Insulating film 114 Upper layer electrode 116 Interlayer film 118, 119 Via plug 120, 122 Upper layer wiring 124 Insulating film 130 Metal layer 150, 150a Via plug array 200 Lower layer electrode 202 Insulating film 204 Upper layer electrode 206 Insulating film 208, 209 Via plug 210, 212 Wiring B1, B2 Recess C, CAP MIM capacitor V1, V2 Via

Claims (9)

Forming a plurality of holes in the first insulating film after forming the first insulating film on the substrate, and forming a metal layer on the first insulating film while filling the plurality of openings;
Etching the metal layer to remove the metal layer on the first insulating film and forming a recess on the upper surface of the metal layer filling each of the plurality of openings;
Forming a MIM capacitor by forming a lower electrode, a second insulating film, and an upper electrode in this order on the first insulating film;
A method of manufacturing a semiconductor device including: The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of openings are a plurality of openings arranged in an array in the region of the second insulating film in a plan view. The method for manufacturing a semiconductor device according to claim 1, wherein a cross-sectional shape of the plurality of apertures is any one of a rectangle, a circle, and a hexagon. Further comprising forming a first wiring on the substrate;
The step of forming the metal layer includes providing the plurality of apertures reaching the first wiring in the first insulating film after forming the first insulating film on the first wiring, The method for manufacturing a semiconductor device according to claim 1, wherein a metal layer is formed on the first insulating film while filling the openings. Forming a circuit element layer including a circuit element on the substrate;
The semiconductor device according to claim 4, wherein the step of forming the first wiring on the substrate is a step of forming the first wiring on the circuit element layer as a part of the wiring connecting the circuit elements. Manufacturing method. Etching and removing a part of the second insulating film and a part of the upper layer electrode to expose a part of the lower electrode;
Forming an interlayer film on the entire surface;
Forming a first via contact connected to the upper layer electrode and a second via contact connected to the exposed lower layer electrode in the interlayer film;
A third insulating film is formed on the interlayer film, a second wiring connected to the first via contact on the third insulating film, and a third connected to the second via contact The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a wiring of the semiconductor device. Wiring formed on the substrate;
A first insulating film formed on the substrate and covering the wiring;
A plurality of openings provided in the first insulating film on the wiring and filled with metal inside and having recesses on the upper surface of the metal;
An MIM capacitor that is formed in this order on the first insulating film and includes a lower electrode having a recess at a position corresponding to each of the plurality of openings, a second insulating film, and an upper electrode;
A semiconductor device including: The semiconductor device according to claim 7, wherein the plurality of openings are a plurality of openings arranged in an array inside the region of the second insulating film in a plan view.
A circuit element layer including a circuit element formed on the substrate;
The semiconductor device according to claim 7, wherein the wiring is a part of wiring that is formed on the circuit element layer and connects the circuit elements.

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