JP2017208654A - Packet processing apparatus and packet processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid voltage drop due to sudden change of load occurring in a packet processing unit when receiving packets intensively, while suppressing power consumption, or to avoid occurrence of packet loss due to impact of voltage drop, or the like.SOLUTION: A packet processing apparatus includes an input packet detector 203 for receiving input of a packet from an input port, and detecting the timing at which input of a packet is received, a delay inserting unit 202 for delaying the packet by a prescribed time from the detection timing, a load packet generating unit 204 for generating a dummy packet (load packet) in the prescribed time, and a load packet multiplexing unit 205 for multiplexing the generated dummy packet and the above-mentioned packet. The packet processing apparatus further includes an interface unit 101 performing packet processing of a multiplex packet and sending to a next state packet processing unit, i.e., an ingres unit 102.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a packet processing device and a packet processing method.

  In recent years, with the increase in the speed and the high density integration of transmission devices, the power consumption of field-programmable gate arrays (FPGAs) that realize the main functions of the devices is increasing. In the packet processing apparatus, a packet processing unit that receives a packet and temporarily stores the received packet in a memory may receive a packet from a plurality of routes at the same time, thereby temporarily increasing a load. In such a state, when a sudden load change occurs and the voltage falls below the guaranteed operating voltage, a packet error occurs and the packet is discarded.

  As a prior art, for such a problem, firstly, there is a technique for stabilizing a load variation due to the presence or absence of a packet by operating a dummy circuit during a period in which no packet is input (for example, Patent Document 1 below). reference.). Secondly, there is a technique for increasing the frequency of the power supply to follow the supply of power in order to suppress fluctuations in the output voltage triggered by reception of the packet (see, for example, Patent Document 2 below). ).

JP 2008-72164 A International Publication No. 2009/078104

  However, in the first prior art, current consumption due to dummy data is always generated even during a packet non-input period, and current that does not need to be consumed is consumed during a packet non-input period. Therefore, the conflicting demands for low power consumption and stable load fluctuation cannot be satisfied. Further, in the second prior art, although power consumption is suppressed, there is a problem that control of power supply voltage control is complicated.

  In one aspect, an object of the present invention is to avoid packet loss caused by the influence of voltage drop due to sudden load change caused by concentrated reception of packets while suppressing power consumption.

  According to one aspect of the present invention, an input port receives a packet input, detects a timing at which the packet input is received, delays the packet by a predetermined time from the detected timing, generates a dummy packet at the predetermined time, A packet processing device and a packet processing method are proposed in which a multiplexed packet obtained by multiplexing a generated dummy packet and a packet is sent to a packet processing unit in the next stage.

  Advantageous Effects of Invention According to one aspect of the present invention, it is possible to avoid a packet loss that occurs due to an influence of a voltage drop due to a sudden load change caused by concentrated reception of packets while suppressing power consumption.

FIG. 1 is an explanatory diagram of an example of a hardware configuration of the packet processing device according to the first embodiment. FIG. 2 is an explanatory diagram of an example of a functional configuration of the packet processing device according to the first embodiment. FIG. 3A is a flowchart illustrating a processing procedure of the input packet detection unit. FIG. 3B is a time chart showing the relationship between the load packet generation / multiplex control signal and the input packet. FIG. 4 is a time chart showing the relationship between load packet multiplexing timing and input packets. FIG. 5 is an explanatory diagram showing an example of the structure of the main signal packet and the load packet. FIG. 6 is an explanatory diagram of another example of the hardware configuration of the packet processing device according to the second embodiment. FIG. 7A is an explanatory diagram of an example of the contents of a packet format in the packet processing device according to the second embodiment. FIG. 7B is an explanatory diagram of the contents of the definition of each field of the packet format in the packet processing apparatus according to the second embodiment. FIG. 8A is an explanatory diagram of an example of a functional configuration of the interface unit of the packet processing device according to the second embodiment and the contents of the packet. FIG. 8B is a flowchart of an example of a processing procedure of the interface unit of the packet processing device according to the second embodiment. FIG. 9A is an explanatory diagram of an example of a functional configuration of the ingress unit of the packet processing device according to the second embodiment and the contents of the packet. FIG. 9B is a flowchart illustrating an example of a processing procedure of the ingress unit of the packet processing device according to the second embodiment. FIG. 10A is an explanatory diagram of an example of a functional configuration of the egress unit of the packet processing device according to the second embodiment and the contents of the packet. FIG. 10B is a flowchart illustrating an example of a processing procedure of the egress unit of the packet processing device according to the second embodiment. FIG. 11A is an explanatory diagram of another example of the functional configuration of the interface unit of the packet processing device according to the second embodiment and the contents of the packet. FIG. 11B is a flowchart illustrating another example of the processing procedure of the interface unit of the packet processing apparatus according to the second embodiment. FIG. 12 is an explanatory diagram of another example of the hardware configuration of the packet processing device according to the third embodiment. FIG. 13 is an explanatory diagram of another example of the contents of the packet format in the packet processing device according to the third embodiment.

  Exemplary embodiments of a packet processing apparatus and a packet processing method according to the present invention are explained in detail below with reference to the accompanying drawings.

(Embodiment 1)

  FIG. 1 is an explanatory diagram of an example of a hardware configuration of the packet processing device according to the first embodiment. FIG. 1 shows a configuration example of an Ethernet (registered trademark) -based packet processing device 100 configured with an FPGA (Field-Programmable Gate Array), which is a specific example of the packet processing device.

  1, the packet processing apparatus 100 includes an interface unit (FPGA # 1) 101, an ingress unit (FPGA # 2) 102, and an egress unit (FPGA # 3) 103. The interface unit (FPGA # 1) 101 performs packet transmission / reception with external interface ports (port # 1 to port #n). The ingress unit (FPGA # 2) 102 performs packet processing in the input direction (Ingress) from the external interface port to the packet processing apparatus 100. The egress unit (FPGA # 3) 103 performs packet processing in the output direction (Egress) from the packet processing apparatus 100 to the external interface port.

  A user packet (input packet) input from the external interface port is received by the interface unit (FPGA # 1) 101. The interface unit (FPGA # 1) 101 checks the frame normality of the input packet, and transfers only packets without error to the ingress unit (FPGA # 2) 102 at the subsequent stage.

  The ingress unit (FPGA # 2) 102 performs input bandwidth control and destination resolution using the external memory 112 or the like based on the header information of the packet, and includes an egress unit (FPGA) in the subsequent stage including information on the destination resolution. # 3) Transfer to 103.

  The egress unit (FPGA # 3) 103 performs output bandwidth control and packet duplication processing to a plurality of destinations using the external memory 113 or the like according to the header information of the received packet, and the interface unit (FPGA) in the subsequent stage. # 1) Transfer to 101. The interface unit (FPGA # 1) 101 outputs the received packet to an appropriate external interface port.

  The packet processing apparatus 100 includes a CPU 150 that performs monitoring control of each device in the packet processing apparatus 100, and power supply units 121, 122, and 123 that supply necessary power to each device.

(Functional configuration of packet processing device)
FIG. 2 is an explanatory diagram illustrating an example of a functional configuration of the packet processing device according to the first embodiment, and corresponds to an example of a hardware configuration of the packet processing device illustrated in FIG. 1. In FIG. 2, a first-stage interface unit (FPGA # 1) 101 to which a packet is input includes a packet input multiplexing unit 201, a delay insertion unit 202, an input packet detection unit 203, a load packet generation unit 204, and a load packet. A multiplexing unit 205 and a packet processing unit 206 are provided.

  The input packet checks the normality of the packet in the packet input multiplexing unit 201, discards the error packet, multiplexes the normal packet and transmits it to the subsequent stage, and the packet processing unit 206 transmits the next ingress unit ( FPGA # 2) 102.

  In addition to the packet input multiplexing unit 201, the interface unit (FPGA # 1) 101 that performs processing on the input side of the packet processing device according to the first exemplary embodiment illustrated in FIG. Similarly to the first interface unit (FPGA # 1) 601 of the packet processing apparatus according to the second embodiment, an input packet inspection unit and a header & FCS adding unit may be provided.

  Then, new processing units (a delay insertion unit 202, an input packet detection unit 203, a load packet generation unit 204, and a load packet multiplexing unit 205) are arranged between the packet input multiplexing unit 201 and the packet processing unit 206.

  The delay insertion unit 202 accumulates the main signal packet for a certain period of time, and transmits the input packet to the load packet multiplexing unit 205 after accumulating for a certain period of time. This fixed time, that is, the delay time, may be a time until voltage stabilization in a sudden load change. This fixed time can be set freely. The delay insertion unit 202 realizes its function by, for example, a memory that accumulates input packets (not shown).

  When the packet input multiplexing unit 201 detects an input of a normal input packet with no error, the input packet detection unit 203 generates load packet multiplexing timing (that is, load packet generation timing and multiplexing timing) for the input packet. The load packet generation unit 204 and the load packet multiplexing unit 205 are notified of instructions regarding the load packet multiplexing timing. Details of processing in the input packet detection unit 203 will be described later with reference to FIGS. 3A and 3B.

  The load packet generation unit 204 generates a load packet at a timing instructed by the input packet detection unit 203 and transmits the generated load packet to the load packet multiplexing unit 205. This load packet has identification information for distinguishing it from the input packet in the header so that the load packet termination unit 209 (to be described later) can identify the load packet.

  The load packet multiplexing unit 205 multiplexes the main signal packet transmitted from the delay insertion unit 202 and the load packet transmitted from the load packet generation unit 204 according to the instruction notified from the input packet detection unit 203, The multiplexed main signal packet and load packet are transmitted to the packet processing unit 206. As described above, the packet processing unit 206 transfers the multiplexed main signal packet and load packet to the ingress unit (FPGA # 2) 102 at the next stage.

  The ingress unit (FPGA # 2) 102 is a packet that performs an interface function with the external memory 112 such as a table search process and an input bandwidth control process for resolving the transfer destination of the main signal packet, and a packet buffer for the process. A processing unit 207 is provided.

  In addition, in the ingress unit (FPGA # 2) 102 of the packet processing device according to the first exemplary embodiment illustrated in FIG. 2, in addition to the packet processing unit 207, the packet processing according to the second exemplary embodiment illustrated in FIG. Similarly to the ingress unit (FPGA # 2) 602 of the apparatus, an input packet inspection unit, a packet multiplexing unit, and a packet identification unit may be provided.

  The next-stage egress unit (FPGA # 3) 103 includes a packet processing unit 208 that uses the external memory 113 to perform packet duplication processing and output bandwidth control processing for multicast and broadcast.

  In the egress unit (FPGA # 3) 103 of the packet processing apparatus according to the first exemplary embodiment illustrated in FIG. 2, in addition to the packet processing unit 208, the packet processing according to the second exemplary embodiment illustrated in FIG. Similar to the egress unit (FPGA # 3) 603 of the apparatus, an input packet inspection unit and a packet distribution unit may be provided.

  In addition, the last interface unit (FPGA # 1) 101 that outputs a packet arranges a load packet termination unit 209 that performs termination processing of a load packet before performing original packet processing. The load packet termination unit 209 terminates the load packet generated in order to create a sudden load change situation, and executes discard processing. The main signal packet is handed over to the subsequent packet output separation unit 210 and transmitted from an appropriate port.

  In addition to the load packet termination unit 209, the interface unit (FPGA # 1) 101 that performs processing on the output side of the packet processing device according to the first exemplary embodiment illustrated in FIG. Similarly to the second interface unit (FPGA # 4) 604 of the packet processing apparatus according to the second embodiment, an input packet inspection unit, a packet processing unit, and a packet output separation unit may be provided.

(Processing procedure of input packet detector)
Next, the processing procedure of the input packet detection unit 203 will be described. FIG. 3A is a flowchart illustrating a processing procedure of the input packet detection unit. FIG. 3B is a time chart showing the relationship between the load packet generation / multiplex control signal and the input packet.

  In the flowchart of FIG. 3A, first, the input packet detection unit 203 determines whether or not a normal input packet has been detected (step S301). Here, after waiting for a normal input packet to be detected (step S301: No), if a normal input packet is detected (step S301: Yes), a timer for a predetermined time is started (step S302). . With the start of the timer, the load packet generation / multiplex control signal is turned ON at that timing (step S303).

  Then, it is determined whether or not the timer has expired (step S304). Here, after waiting for the timer to expire (step S304: No), when the timer expires (step S304: Yes), at that timing, the load packet generation / multiplex control signal is turned OFF (step S305), The process returns to step S301 to wait for the next input packet.

  In this way, the timing from when the load packet generation / multiplex control signal is turned on until it is turned off is the load packet multiplex timing. The load packet generation / multiplexing control signal is used as a load packet generation start timing in the subsequent load packet generation unit 204, and is used as a load packet multiplexing timing in the load packet multiplexing unit 205. Therefore, upon receiving a notification that the load packet generation / multiplex control signal is ON (step S303) from the input packet detection unit 203, the load packet generation unit 204 starts generation of the load packet. When receiving the notification of turning off the load packet generation / multiplex control signal (step S305), the generation of the load packet is stopped.

  In FIG. 3B, each of the rectangles (reference symbols A to E) in the input packet represents a normal input packet, and when the first input packet (packet A) of consecutive normal packets is detected, The load packet generation / multiplex control signal is turned ON (step S303), and the load packet generation / multiplex control signal is turned OFF (step S305) after a lapse of a certain time regardless of the presence or absence of successive input packets thereafter. After that, when a new normal packet (packet E) is detected, the load packet generation / multiplex control signal is turned ON again (step S303), and a certain period of time regardless of the presence or absence of subsequent input packets. It shows that the load packet generation / multiplex control signal is turned off (step S305) after elapse.

  FIG. 4 is a time chart showing the relationship between load packet multiplexing timing and input packets. In the time chart of FIG. 4, input packets of various lengths exist continuously / discontinuously. A load packet multiplexing timing pulse is output at the time when a leading packet of consecutive input packets is detected, and each input packet is delayed by the timing of the pulse. Further, the load packet is multiplexed at the delayed location.

  Since the ingress unit (FPGA # 2) 102 has a memory interface outside the FPGA such as a table search for solving the transfer destination of the main signal packet and a packet buffer for input bandwidth control processing, the interface unit (FPGA # 2) 1) Current consumption is larger than 101. Further, the egress unit (FPGA # 3) 103 at the next stage uses the same interface as the ingress unit (FPGA # 2) 102 because an external memory is used for multicast and broadcast packet replication processing and output bandwidth control. Current consumption is larger than that of the unit (FPGA # 1) 101. As a result, a voltage drop occurs at the beginning of successive packets.

  As shown in FIG. 4, the load packet multiplexing timing corresponds to the voltage drop occurrence timing. Therefore, since the main signal packet is adjusted so as not to exist at the load packet multiplexing timing, that is, when the voltage drop occurs, the main signal packet does not cause a packet loss due to a voltage drop. Therefore, in the packet processing device according to the present embodiment, it is not necessary to adjust the power supply so as not to cause a voltage drop.

(Example of main signal packet / load packet structure)
Next, an example of the structure of the main signal packet and the load packet will be described. FIG. 5 is an explanatory diagram showing an example of the structure of the main signal packet and the load packet. In FIG. 5, a main signal packet 501 generally includes a header 511, a payload 512, and an FCS (Frame Check Sequence) 513.

  On the other hand, the load packet 502 includes a header 521, a payload 522, and an FCS 523, similarly to the main signal packet 501. The load packet 502 is provided with load packet identification information 525 indicating that it is a load packet in the header 521, and the corresponding packet is identified and discarded by the load packet termination unit 209 at the subsequent stage. Further, the payload 522 of the load packet 502 is configured to be able to select All “0”, All “1,” “0/1 alternating or random” as the payload pattern, and the payload length (size) is fixed length and variable. A length (for example, 64 bytes to 9600 bytes) can be selected.

  Since the voltage drop amount is proportional to the current fluctuation amount per unit time, it is possible to mitigate the voltage drop by creating a more gradual load fluctuation state than the sudden load change at the time of main signal packet input. For this purpose, the payload length should be as large as possible (for example, 9600 bytes).

  On the other hand, the payload length may be as small as possible (for example, 64 bytes), and as many load packets as possible may be generated during the load packet multiplexing timing. If the voltage falls below the operation guarantee voltage due to the influence of a voltage drop due to load fluctuation, packet loss occurs. The packet loss is a load packet corresponding to the voltage drop occurrence timing.

  However, once the packet is lost, the load packet is discarded in the next block. Considering this point, by increasing the number of load packets, there is a high possibility that the load packets remain without being discarded until the final block. Therefore, it may be advantageous to make the payload length as small as possible in that the influence (the degree to which no load is applied) at the time of discarding a single packet is reduced.

  Therefore, the length of the payload should be selected in consideration of the configuration and scale of the packet processing apparatus, the contents of the power supply to be used, and the like.

  As described above, the packet processing apparatus according to the present embodiment temporarily stores the main signal after detecting the arrival of the main signal packet in order to avoid the influence of current and voltage fluctuation due to sudden load change. A sudden load change state due to a load packet different from the main signal packet is generated, and the main signal packet is processed after voltage fluctuation due to the sudden load change is stabilized.

  As described above, according to the packet processing apparatus according to the first embodiment, the interface unit (FPGA # 1) 101 on the input processing side accepts input of a packet from the input port, and the input packet detection unit 203 The timing at which the input is received is detected, the delay insertion unit 202 delays the packet by a predetermined time from the detected timing, the load packet generation unit 204 generates a dummy packet at the predetermined time, and the load packet multiplexing unit 205 , The generated dummy packet and the packet are multiplexed, and the multiplexed packet is sent to the ingress unit (FPGA # 2) 102 which is the packet processing unit in the next stage. Packet loss can be avoided.

  In addition, it is not necessary to add a component such as a capacitor for suppressing sudden load change by an FPGA external circuit, and it is possible to reduce the size and cost by reducing the number of components.

  In order to avoid the loss of the main signal packet, the current is not always consumed when no packet is input. Therefore, power consumption can be suppressed.

  Also, according to the packet processing apparatus of the first embodiment, the output processing interface unit 101 connected to the output port that is the output target is the egress unit (FPGA # 3), which is the preceding packet processing unit. ) Accepts the input of the multiplexed packet from 103, and the load packet termination unit 209 identifies the packet and the dummy packet from the multiplexed packet, and discards the identified dummy packet. Since the identified packet is output to the output port, the load packet is not erroneously output from the output port.

  Further, according to the packet processing apparatus according to the first embodiment, the dummy packet 502 includes the load packet identification information 525 that can be recognized as a dummy packet in the header 521 of the dummy packet. Identification becomes easy.

  As described above, in the packet processing apparatus that has a plurality of input ports and a plurality of output ports, processes a packet received by the input port, and transmits the packet from the output port, the input processing interface unit receives by the input port. The received packet is input, the timing when the packet is input is detected, the packet is delayed by a predetermined time from the detected timing, and a dummy packet can be generated at the predetermined time.

  Further, the packet processing unit receives the generated dummy packet and the packet from the input processing interface unit, and can temporarily store the input dummy packet and the packet in the memory.

  The output processing interface unit receives the dummy packet and the packet from the packet processing unit, identifies the input dummy packet and the packet, discards the identified dummy packet, and outputs the identified packet Can be output to the port.

(Embodiment 2)
FIG. 6 is an explanatory diagram of an example of a hardware configuration of the packet processing device according to the second embodiment. FIG. 6 also shows a configuration example of an Ethernet-based packet processing device 600 configured with an FPGA, which is a specific example of the packet processing device, as in FIG.

  In FIG. 6, the packet processing device 600 is similar to the packet processing device 100 shown in FIG. 1 in that the first interface unit (FPGA # 1) 601, the ingress unit (FPGA # 2) 602, and the egress unit (FPGA #). 3) 603. Further, unlike the packet processing apparatus 100 shown in FIG. 1, the packet processing apparatus 600 includes a second interface unit (FPGA # 4) 604 that is another interface unit.

  The first interface unit (FPGA # 1) 601 performs packet transmission / reception with external interface ports (port # 1 to port #n). The second interface unit (FPGA # 4) 604 performs packet transmission / reception with the external interface port (port # n + 1 to port # n + n).

  The ingress unit (FPGA # 2) 602 performs packet processing in the input direction (Ingress) from the external interface port to the packet processing apparatus 100. That is, the ingress unit (FPGA # 2) 602 receives input packets from both the first interface unit (FPGA # 1) 601 and the second interface unit (FPGA # 4) 604. The egress unit (FPGA # 3) 603 performs packet processing in the output direction (Egress) from the packet processing apparatus 100 to the external interface port.

  A user packet (input packet) input from the external interface port is received by the first interface unit (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604, and the frame normality is checked. The data is transferred to the ingress portion (FPGA # 2) 602 at the subsequent stage. The ingress unit (FPGA # 2) 602 performs input bandwidth control and destination resolution using the external memory 612 or the like based on the header information of the packet, and includes the egress unit (FPGA) in the subsequent stage including the information on the destination resolution. # 3) Transfer to 603.

  The egress unit (FPGA # 3) 603 performs output bandwidth control and packet duplication processing to a plurality of destinations using the external memory 613 or the like according to the header information of the received packet, and the first interface unit in the subsequent stage The data is transferred to (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604 and transmitted from an appropriate external interface port. Further, the packet processing apparatus 600 is similar to the packet processing apparatus 100 shown in FIG. 1, the CPU 650 that performs monitoring control of each device in the packet processing apparatus 600, and the power supply unit 621 that supplies necessary power to each device. , 622, 623, 624 and the like.

(Packet format contents)
Next, the contents of the packet format will be described. FIG. 7A is an explanatory diagram showing an example of the contents of the packet format in the apparatus. FIG. 7B is an explanatory diagram showing the definition contents of each field of the packet format in the apparatus.

  In FIG. 7A, 700 indicates a packet format of a user packet (main signal packet) input from the external interface port, and 710 indicates a packet format of the in-device packet.

  The packet format 700 of the user packet (input packet) includes a “Payload” field 701 and a “FCS-U” field 702. As shown in FIG. 7B, the “Payload” field 701 stores the payload that is the data body of the input packet. The “Payload” field 701 also stores a DA (Destination Address) related to the destination MAC address of the input packet and an SA (Source Address) related to the source MAC address. The FCS-U field 702 stores an FCS for checking the normality of the input packet.

  In contrast, the packet format 710 of the in-device packet includes a “Packet Type” field 711, a “Forwarding Type” field 712, a “Src port” field 713, and a “Dest port” field 714. , “Reserved” field 715, “Payload” field 716, “FCS-U” field 718, main signal packet part, “FCS-H” field 719, and Consists of

  As shown in FIG. 7B, the “Packet Type” field 711 stores a packet type, that is, a code for identifying whether the packet is a main signal packet or a load packet. If “Packet Type” is “00b”, the packet is a main signal packet. If “Packet Type” is “10b”, the packet is a load packet. Here, “b” indicates that it is expressed in binary (binary number). Hereinafter, “b” in the code indicates that it is expressed in binary (binary number).

  The “Forwarding Type” field 712 stores a code for identifying the type of communication, that is, whether the packet is unicast, multicast, or broadcast. If “Forwarding Type” is “00b”, it is unicast, if “01b”, it is multicast, and if “10b”, it is broadcast.

  The “Src port” field 713 stores a source port indicating the port number of the input packet. If “Src port” is “000b”, it is “port1”, and if “001b” is “port2”,. . . If “111b”, it is “port8”. Further, the “Dest port” field 714 stores a destination port indicating a port number of an output destination of the input packet.

  Similarly to “Src port”, “Dest port” is “port1” if “000b”, “port2” if “001b”,. . . If “111b”, it is “port8”. In the “Reserved” field 715, a code indicating a reserved area (for example, “000000b” or the like) is stored.

The “Payload” field 716 and the “FCS-U” field 717 include:
The “Payload” field 701 and the “FCS-U” field 702 of the packet format 700 of the input packet are stored as they are. The “FCS-H” field 718 checks the frame normality for the area from the “Packet Type” field 711 to the “FCS-U” field 717 at the head of the header.

  As described above, the input packet (packet format 700) received by the packet processing device 100 is communicated in the packet processing device 100 by the in-device packet format 710 to which the header part and the FCS are added. . Then, by adding the definition of “Packet Type” for the load packet, the main signal packet and the load packet can be identified.

(Functional configuration and processing procedure in input side processing of first and second interface units)
Next, the functional configuration of the first interface unit (FPGA # 1) 601 and the second interface unit (FPGA # 4) 604 and the first interface unit (FPGA # 1) 601 of the packet processing apparatus according to the second embodiment, The input side processing in the second interface unit (FPGA # 4) 604 will be described. FIG. 8A is an explanatory diagram illustrating an example of the functional configuration of the interface unit of the packet processing device according to the second embodiment and the contents of the packet, and FIG. 8B illustrates the interface unit of the packet processing device according to the second embodiment. It is a flowchart which shows an example of a process sequence.

  In FIG. 8A, a first interface unit (FPGA # 1) 601 is connected to an input / output port (port # 1 to port #n), an input packet inspection unit 801, a packet multiplexing unit 802, a header & FCS adding unit 803, a delay An insertion unit 804, an input packet detection unit 805, a load packet generation unit 806, a load packet multiplexing unit 807, and a packet processing unit 808 are provided. Also, the second interface unit (FPGA # 4) 604 has the same components as the first interface unit (FPGA # 1) 601 (input packet inspection unit, packet multiplexing unit, header & FCS adding unit, delay insertion unit, input packet) A detection unit, a load packet generation unit, a load packet multiplexing unit, and a packet processing unit).

  An input packet 820 input from an input port (any of port # 1 to port #n) is checked for normality of a frame by the input packet inspection unit 801, and is discarded if an error occurs. An error-free packet is multiplexed with packets from a plurality of input ports in the subsequent packet multiplexing unit 802. After that, the header & FCS assigning unit 803 calculates FCS (FCS-H) to check the normality of the header part used in the apparatus and the frame in the area including Payload and FCS-U from the head of the header. To grant. In this way, the main signal packet 830 is generated.

  The main signal packet 830 sets “Packet Type” in the header portion to “PT = 00b” so that it can be identified as the main signal packet. Also, “Forwarding Type” in the header part is once transferred to the subsequent block (ingress part (FPGA # 2) 602) as “FT = 00b”. Further, “Src port” is “Src port = 000b” in the main signal packet 830 to indicate that it is input from the port # 1. Since the output destination port is assigned again in the subsequent block, the input port number is used here, and “Dest port = 000b”.

  Thereafter, when the input packet detection unit 805 detects the input of the packet, the main signal packet 830 is given a delay of a certain time by the delay insertion unit 804 and is sent to the load packet multiplexing unit 807. At this time, since the load packet insertion opportunity is obtained, the load packet generation unit 806 generates a load packet 840.

  In order to identify the load packet 840 as a load packet, “Packet Type” in the header portion is set to “PT = 10b”. In order to prevent copying in the egress part (FPGA # 3) 603, the “Forwarding Type” in the header part is always set to “FT = 00b” so that the unicast is always set. Also, “Src port” is set to “Src port = 000b” and “Dest port = 000b”. Since a load packet is a packet that is eventually discarded, neither the input port number nor the output destination port number is important. Not only the above code but also any code that does not cause an error is stored. That's fine.

  After the load packet generation unit 806 generates the load packet 840 in this way, the load packet 840 is transmitted to the load packet multiplexing unit 807, and the load packet 840 is transmitted while the main signal packet 830 is delayed. It is transmitted to the subsequent block (ingress part (FPGA # 2) 602). Note that the packet processing unit 808 performs packet processing that is originally performed (for example, processing such as statistical counting).

  A processing procedure in the first interface unit (FPGA # 1) 601 is shown in FIG. 8B. First, it is determined whether or not a packet is input from the input port (step S861). Here, it waits for the packet to be input (step S861: No), and if it is input (step S861: Yes), it is determined whether the input packet is an error packet (step S862). .

  If the input packet is an error packet in step S862 (step S862: Yes), the packet is discarded (step S863), and the process returns to step S861. On the other hand, if the input packet is not an error packet in step S862 (step S862: No), the packet is multiplexed with a packet input from another port (step S864), and the header and FCS are added to the packet. (Step S865).

  Thereafter, a delay is inserted into the multiplexed packet (main signal packet) to which the header and FCS are added (step S866), and further, a load packet is generated (step S867). Multiplex (step S868). The multiplexed packet is subjected to predetermined packet processing (step S869), then transferred to the ingress unit (FPGA # 2) 602 (step S870), and the process returns to step S861.

  The first interface unit (FPGA # 1) 601 performs processing on the input packet in such a procedure, and then passes the data to the ingress unit (FPGA # 2) 602. The second interface unit (FPGA # 2) 602 also executes processing in the same procedure as the first interface unit (FPGA # 1) 601.

(Functional configuration and processing procedure of ingress part)
Next, a functional configuration of the ingress unit (FPGA # 2) 602 of the packet processing apparatus according to the second embodiment and processing in the ingress unit (FPGA # 2) 602 will be described. FIG. 9A is an explanatory diagram illustrating an example of a functional configuration of the ingress unit and the contents of the packet, and FIG. 9B is a flowchart illustrating an example of a processing procedure of the ingress unit of the packet processing device according to the second exemplary embodiment.

  9A, the ingress unit (FPGA # 2) 602 includes an input packet inspection unit 901, a packet multiplexing unit 902, a packet identification unit 903, a destination determination unit 904, and a packet processing unit 905.

  A packet in which a main signal packet and a load packet input from the first interface unit (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604 are multiplexed is received by the input packet inspection unit 901 for each frame. Normality is checked, and in case of an error, the packet is discarded. The packet having no error is multiplexed with the packet from the first interface unit (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604 in the subsequent packet multiplexing unit 902 and transferred to the packet identification unit 903. . The multiplexed packet transferred to the packet identification unit 903 is identified by the packet identification unit 903 as a main signal packet and a load packet.

  The packet identification unit 903 refers to the field of “Packet Type” in the header of each packet, and if “PT = 00b”, it is a main signal packet 930, and if “PT = 10b”, it is a load packet 940. Identify.

  The main signal packet 930 with “PT = 00b” is transferred to the destination resolution unit 904 and resolves the destination information using an external memory in which the destination information is stored. For example, when the transfer destination of the main signal packet is “port # 2”, as shown in the main signal packet 930, the “Forwarding Type” field of the header is set to “FT = 00b (uni)” indicating unicast. In addition, the “Dest port” field is rewritten to “Dest port = 001b” indicating the port # 2, respectively, and then transferred to the packet processing unit 905 in the subsequent stage.

  On the other hand, since the load packet 940 with “PT = 10b” already stores destination information in the first interface unit (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604, the destination resolution is performed. Therefore, the destination resolution unit 904 is skipped and transferred to the subsequent packet processing unit 905. The packet processing unit 905 at the subsequent stage performs packet processing (for example, input bandwidth control) that is originally performed.

  The processing procedure in the ingress unit (FPGA # 2) 602 is shown in FIG. 9B. First, it is determined whether a packet is input from the first interface unit (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604 (step S961). Here, waiting for a packet to be input (step S961: No), and if it is input (step S961: Yes), it is determined whether the input packet is an error packet (step S962). .

  If the input packet is an error packet in step S962 (step S962: Yes), the packet is discarded (step S963), and the process returns to step S961. On the other hand, if the input packet is not an error packet in step S961 (step S962: No), the packet is multiplexed with a packet input from another interface unit (step S964).

  Then, it is determined whether each multiplexed packet is a main signal packet or a load packet (step S965). Here, when it is a main signal packet (step S965: Yes), the destination solution processing described above is performed (step S966), and the process proceeds to step S967. On the other hand, if it is not the main signal packet, that is, if it is a load packet (step S965: No), the process proceeds to step S967 without doing anything.

  After that, predetermined packet processing is performed on the multiplexed packet (step S967), and then the packet is transferred to the egress part (FPGA # 3) 603 (step S968), and the process returns to step S961.

  In the ingress part (FPGA # 2) 602, after performing various processes including the destination resolution process for the multiplexed packet in such a procedure, the data is transferred to the egress part (FPGA # 3) 603.

(Functional configuration and processing procedure of egress section)
Next, a functional configuration of the egress unit (FPGA # 3) 603 of the packet processing apparatus according to the second embodiment and processing in the egress unit (FPGA # 3) 603 will be described. FIG. 10A is an explanatory diagram illustrating an example of the functional configuration of the egress unit of the packet processing device according to the second embodiment and the contents of the packet, and FIG. 10B illustrates the egress unit of the packet processing device according to the second embodiment. It is a flowchart which shows an example of a process sequence.

  10A, an egress unit (FPGA # 3) 603 includes an input packet inspection unit 1001, a packet processing unit 1002, and a packet distribution unit 1003.

  The packet input from the ingress unit (FPGA # 2) 602 is checked for normality of the frame for each packet by the input packet inspection unit 1001, and in the case of an error, the packet is discarded. For packets having no error, the packet processing unit 1002 at the subsequent stage performs packet processing (for example, output bandwidth control) that is originally performed.

  Reference numeral 1030 denotes a main signal packet subjected to packet processing in the packet processing unit 1002, and reference numeral 1040 denotes a load packet subjected to packet processing in the packet processing unit 1002. In either case, the packet is transferred to the packet distribution unit 1003 in the subsequent stage.

  The packet distribution unit 1003 determines the distribution destination based on the code in the “Dest port” field in the header of each packet. The field of “Dest port” of the main signal packet 1030 is “Dest port = 001b”, and “001b” indicates the port # 2, so the first interface unit (FPGA) connected to the port # 2 # 1) Transfer to 601.

  Further, since the “Dest port” field of the load packet 1040 is “Dest port = 000b” and “000b” indicates the port # 1, the first interface unit connected to the port # 1 ( FPGA # 1) Transfer to 601. However, as described above, in the load packet, the number of the output port is not important, and the code in the “Dest port” field may be distributed to any interface unit including a load packet terminal unit described later.

  The processing procedure in the egress section (FPGA # 3) 603 is shown in FIG. 10B. First, it is determined from the ingress unit (FPGA # 2) 602 whether or not a packet has been input (step S1061). Here, it waits for the packet to be input (step S1061: No), and when it is input (step S1061: Yes), it is determined whether the input packet is an error packet (step S1062). .

  In step S1062, if the input packet is an error packet (step S1062: Yes), the packet is discarded (step S1063), and the process returns to step S1061. On the other hand, in step S1061, when the input packet is not an error packet (step S1062: No), predetermined packet processing is performed on the packet (step S1064).

  Then, after predetermined packet processing is performed, it is determined whether the transfer destination of the packet is the first interface unit (FPGA # 1) 601 or the second interface unit (FPGA # 4) 604 (step). S1065). If the transfer destination is the first interface unit (FPGA # 1) 601 (step S1065: Yes), the transfer is transferred to the first interface unit (FPGA # 1) 601 (step S1066), and then to step S1061. Return.

  On the other hand, when the transfer destination is not the first interface unit (FPGA # 1) 601, that is, when it is the second interface unit (FPGA # 4) 604 (step S1065: No), the second interface unit (FPGA # 4). It transfers to 604 (step S1067), and returns to step S1061 after that.

  The egress unit (FPGA # 3) 603 performs packet processing on the multiplexed packet in such a procedure, and then passes the data to the output processing interface unit connected to the output port.

(Functional configuration and processing procedure in output side processing of first and second interface units)
Next, the functional configuration of the first interface unit (FPGA # 1) 601 and the second interface unit (FPGA # 4) 604 and the first interface unit (FPGA # 1) 601 of the packet processing apparatus according to the second embodiment, The output side processing in the second interface unit (FPGA # 4) 604 will be described. FIG. 11A is an explanatory diagram illustrating another example of the functional configuration of the interface unit and the contents of the packet, and FIG. 11B illustrates another example of the processing procedure of the interface unit of the packet processing device according to the second exemplary embodiment. It is a flowchart.

  In FIG. 11A, a first interface unit (FPGA # 1) 601 is connected to an input / output port (port # 1 to port #n), and an input packet inspection unit 1101, a load packet termination unit 1102, a packet processing unit 1103, a packet An output separation unit 1104. Also, the second interface unit (FPGA # 4) 604 has the same components (input packet inspection unit, load packet termination unit, packet processing unit, packet output separation unit) as the first interface unit (FPGA # 1) 601. I have.

  The packet input from the egress part (FPGA # 3) 603 is checked for normality of the frame for each packet by the input packet inspection part 1101, and in the case of an error, the packet is discarded. A packet having no error is transferred to the load packet termination unit 1102 at the subsequent stage.

  The load packet termination unit 903 refers to the “Packet Type” field in the header of each packet, and discards all the packets of “PT = 10b” (load packet 1140). The packet of “PT = 00b” (main signal packet 1130) is transferred to the packet processing unit 1103 at the subsequent stage. Therefore, only the main signal packet 1130 is transferred from the load packet termination unit 903 to the packet processing unit 1103.

  The packet processing unit 1103 performs packet processing (for example, statistical count) that is originally performed, and then transfers the packet to the packet output separation unit 1104 at the final stage. The packet output separation unit 1104 deletes the in-device header and FCS-H. As a result, the state is returned to the state of the output packet 1150, that is, the state of the input packet 820 shown in FIG. 8A. Then, the output packet 1150 is output to the port # 2 based on “Dest port = 001b” in the “Dest port” field.

  The procedure of the output side processing in the first interface unit (FPGA # 1) 601 is shown in FIG. 11B. First, it is determined from the egress part (FPGA # 3) 603 whether or not a packet has been input (step S1161). Here, after waiting for the packet to be input (step S1161: No), if it is input (step S1161: Yes), it is determined whether or not the input packet is an error packet (step S1162). .

  In step S1162, if the input packet is an error packet (step S1162: Yes), the packet is discarded (step S1163), and the process returns to step S1161. On the other hand, if the input packet is not an error packet in step S1161 (step S1162: No), it is next determined whether the packet is a load packet (step S1164). If the packet is a load packet (step S1164: YES), the load packet is discarded (step S1165), and the process returns to step S1161.

  On the other hand, when the packet is not a load packet, that is, a main signal packet (step S1164: No), predetermined packet processing is performed on the main signal packet (step S1166). Further, the in-device header and FCS-H are deleted (step S1167), and the packet from which the in-device header and FCS-H are deleted (that is, the packet in the state when it is input) is output to a predetermined output port. (Step S1168), and then the process returns to step S1161.

  The first interface unit (FPGA # 1) 601 can perform output side processing in such a procedure.

  As described above, according to the packet processing apparatus according to the second embodiment, as in the first embodiment, it is possible to suppress a sudden change in load during main signal packet processing and to avoid loss of the main signal packet. Become.

  Also, according to the packet processing apparatus according to the second exemplary embodiment, the ingress unit (FPGA # 2) 102, which is a packet processing unit, receives an input of a multiplexed packet from the interface unit (FPGA # 1) 101, and receives a packet identification unit 903. Thus, a packet and a dummy packet are identified from the multiplex packet, and a specific packet process (for example, a destination resolution process) is performed only on the identified packet by the destination resolution unit 904, and a special packet process is performed. After this is done, the multiplex packet is sent to the output processing interface connected to the output port that is the output target, so the destination is not given to the load signal. Will not be output.

(Embodiment 3)
FIG. 12 is a diagram illustrating another example of the hardware configuration of the packet processing device according to the third embodiment. FIG. 12 also shows a configuration example of an Ethernet-based packet processing device 600 configured with an FPGA, which is a specific example of the packet processing device, similarly to FIGS. 1 and 6. FIG. 13 is an explanatory diagram of an example of the contents of the packet format in the packet processing apparatus according to the third embodiment.

  The packet processing apparatus according to the second embodiment shown in FIG. 6 is a so-called 1RU (Rack Unit) type apparatus completed in one card, whereas the packet according to the third embodiment shown in FIG. The processing device is a shelf type device that transmits packets across a plurality of cards.

  In FIG. 12, the packet processing apparatus includes a first card 1200 and a second card 1250. The configuration in each card is the same as that of the packet processing apparatus 100 according to the second embodiment shown in FIG.

  Further, the first card 1200 and the second card 1250 are the same as the packet processing apparatus 100 shown in FIG. 1 and the packet processing apparatus 600 shown in FIG. 6, respectively, of each device in the first card 1200 and the second card 1250. A CPU unit (not shown) that performs monitoring control and a power source unit (not shown) that supplies necessary power to each device may be provided.

  As shown in FIG. 12, it has 16 ports configured to straddle two cards 1200, 1250. Specifically, the first interface unit (FPGA # 1) 1201 of the first card 1200 is port # 1 to port # 4, and the second interface unit (FPGA # 4) 1204 of the first card 1200 is port # 5 to port # 5. # 8, the first interface unit (FPGA # 1) 1251 of the second card 1250 is port # 9 to port # 12, and the second interface unit (FPGA # 4) 1254 of the second card 1250 is port # 13 to port # 16. Have each.

  Further, the ingress portion (FRGA # 2) 1202 of the first card 1200 is not only sent to the egress portion (FRGA # 3) 1203 of the first card 1200 but also to the egress portion (FRGA # 3) 1253 of the second card 1250. The packet is transferred. Similarly, the ingress part (FRGA # 2) 1252 of the second card 1250 not only applies to the egress part (FRGA # 3) 1253 of the second card 1250 but also to the egress part (FRGA # 3) 1203 of the first card 1200. The packet is transferred.

  In order to realize such extension, in FIG. 13, the ports in the “Src port” field and the “Dest port” field of the header portion of the in-device packet format of the main signal packet are extended to 1-16. Let Specifically, “0000b” (“port1”) to “1111b” (port16) are assigned to both “Src port” and “Dest port”.

  Accordingly, the ingress portion (FRGA # 2) 1202 of the first card 1200 and the ingress portion (FRGA # 2) 1252 of the second card 1250 are “Dest port = 0000b” to “Dest port = 1111b” in the “Dest port” field. ], The packet is transferred to the egress part (FRGA # 3) 1203 of the first card 1200. If “Dest port = 1000b” to “Dest port = 1111b”, the packet is sent to the egress part of the second card 1250. Transfer to (FRGA # 3) 1253.

The “Src port” field 713 stores a source port indicating the port number of the input packet. If “Src port” is “0000b”, it is “port1”, if “0001b”, it is “port2”. . . If it is “0111b”, it is “port8”. Further, the “Dest port” field 714 stores a destination port indicating a port number of an output destination of the input packet.

  Similarly to “Src port”, “Dest port” is “port1” if “0000b”, “port2” if “0001b”,. . . If it is “0111b”, it is “port8”. In the “Reserved” field 715, a code indicating a reserved area (for example, “000000b” or the like) is stored.

  As described above, according to the packet processing apparatus according to the third embodiment, as in the first and second embodiments, it is possible to suppress a sudden load change during main signal packet processing and to avoid loss of the main signal packet. It becomes possible.

  The packet processing apparatus according to the third embodiment includes a plurality of cards as a unit having an input processing interface unit, a packet processing unit, and an output processing interface unit, and the card packet processing unit ( Multiple packets are transmitted and received between the ingress units 1202 and 1252 and the egress units 1203 and 1253), so that the packet processing device is expanded, the device itself becomes larger, and the amount of packets to be processed can be increased. Is possible.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) In a packet processing apparatus that has a plurality of input ports and a plurality of output ports, processes a packet received by the input port, and transmits the packet from the output port.
Input process in which the packet received by the input port is input, the timing at which the packet is input is detected, the packet is delayed by a predetermined time from the detected timing, and a dummy packet is generated at the predetermined time Interface section,
A packet processing unit that receives the generated dummy packet and the packet from the input processing interface unit and temporarily stores the input dummy packet and the packet in a memory;
A packet processing apparatus comprising:

(Appendix 2) The dummy packet and the packet are input from the packet processing unit, the input dummy packet and the packet are identified, the identified dummy packet is discarded, and the identified packet 2. The packet processing device according to claim 1, further comprising an output processing interface unit that outputs a message to the output port.

(Supplementary Note 3) The packet processing unit
The packet processing apparatus according to appendix 1 or 2, wherein the input dummy packet and the packet are identified, and specific packet processing is performed only on the identified packet.

(Supplementary Note 4) The packet processing device according to any one of Supplementary Notes 1 to 3, wherein the dummy packet includes identification information that can be recognized as a dummy packet in a header of the dummy packet. .

(Supplementary Note 5) The packet processing unit includes a first packet processing unit and a second packet processing unit,
The first packet processing unit includes:
Identify the input dummy packet and the packet,
Perform packet processing on destination resolution only for the identified packet,
After performing the packet processing, send the dummy packet and the packet to a second packet processing unit,
The second packet processing unit
Packet processing is performed on the dummy packet and the packet input from the first packet processing unit,
The packet processing device according to any one of appendices 1 to 3, wherein after the packet processing is performed, the dummy packet and the packet are sent to the output processing interface unit to be output. .

(Supplementary Note 6) A plurality of units including the input processing interface unit, the packet processing unit, and the output processing interface unit are provided.
The packet processing device according to any one of appendices 2 to 5, wherein the dummy packet and the packet are transmitted and received between the packet processing units of each unit.

(Supplementary note 7) The packet processing device according to any one of supplementary notes 2 to 6, wherein the input processing interface unit performs processing of the output processing interface unit.

(Supplementary note 8) A plurality of output processing interface units are provided,
The packet processing device according to any one of appendices 2 to 7, wherein the packet processing unit sends the dummy packet and the packet to any one of the plurality of output processing interface units.

(Supplementary Note 9) A plurality of the input processing interface units are provided,
The packet processing device according to any one of appendices 1 to 8, wherein the packet processing unit receives the dummy packet and the packet from any one of the plurality of input processing interface units. .

(Additional remark 10) In the packet processing method which has a plurality of input ports and a plurality of output ports, processes a packet received by the input port, and transmits from the output port,
The packet received by the input port is input, the timing at which the packet is input is detected, the packet is delayed by a predetermined time from the detected timing, and a dummy packet is generated at the predetermined time,
A packet processing method, wherein the generated dummy packet and the packet are input, and the input dummy packet and the packet are temporarily stored in a memory.

(Supplementary Note 11) The dummy packet and the packet temporarily stored in the memory are input, the input dummy packet and the packet are identified, the identified dummy packet is discarded, and the identified 11. The packet processing method according to appendix 10, wherein the packet is output to the output port.

(Supplementary Note 12) The generated dummy packet and the packet are input, the input dummy packet and the packet are identified, and specific packet processing is performed only on the identified packet The packet processing method according to appendix 11, characterized by:

(Supplementary note 13) The dummy packet includes identification information that can be recognized as a dummy packet in the header of the dummy packet.
The packet processing method according to any one of appendices 10 to 12, wherein the dummy packet and the packet are identified based on the identification information.

100, 600 Packet processing device 101, 601, 1201, 1251 Interface unit (FPGA # 1)
102, 602, 1202, 1252 Ingress part (FPGA # 2)
103, 603, 1203, 1253 Egress section (FPGA # 3)
112, 113 Memory 121, 122, 123, 621, 622, 623, 624 Power supply unit 150, 650 CPU
201 packet input multiplexing unit 202, 804 delay insertion unit 203, 805 input packet detection unit 204, 806 load packet generation unit 205, 807 load packet multiplexing unit 206, 207, 208, 808, 905, 1002, 1103 packet processing unit 209, 1102 Load packet termination unit 210 Packet output separation unit 604, 1204, 1254 Second interface unit (FPGA # 4)
801, 901, 1001, 1101 Input packet inspection unit 802, 902 Packet multiplexing unit 803 Header & FCS grant unit 903 Packet identification unit 904 Destination resolution unit 1003 Packet distribution unit 1104 Packet output separation unit 1200 First card 1250 Second card

Claims (12)

In a packet processing device having a plurality of input ports and a plurality of output ports, processing a packet received by the input port, and transmitting from the output port,
Input process in which the packet received by the input port is input, the timing at which the packet is input is detected, the packet is delayed by a predetermined time from the detected timing, and a dummy packet is generated at the predetermined time Interface section,
A packet processing unit that receives the generated dummy packet and the packet from the input processing interface unit and temporarily stores the input dummy packet and the packet in a memory;
A packet processing apparatus comprising: The dummy packet and the packet are inputted from the packet processing unit, the inputted dummy packet and the packet are identified, the identified dummy packet is discarded, and the identified packet is sent to the output port The packet processing apparatus according to claim 1, further comprising an output processing interface unit configured to output to the network. The packet processing unit
The packet processing apparatus according to claim 1 or 2, wherein the inputted dummy packet and the packet are identified, and specific packet processing is performed only on the identified packet.   The packet processing apparatus according to claim 1, wherein the dummy packet includes identification information that can be recognized as a dummy packet in a header of the dummy packet. The packet processing unit includes a first packet processing unit and a second packet processing unit,
The first packet processing unit includes:
Identify the input dummy packet and the packet,
Perform packet processing on destination resolution only for the identified packet,
After performing the packet processing, send the dummy packet and the packet to a second packet processing unit,
The second packet processing unit
Packet processing is performed on the dummy packet and the packet input from the first packet processing unit,
The packet processing according to any one of claims 1 to 3, wherein after the packet processing is performed, the dummy packet and the packet are sent to the output processing interface unit to be output. apparatus. A plurality of units including the input processing interface unit, the packet processing unit, and the output processing interface unit;
The packet processing apparatus according to claim 2, wherein the dummy packet and the packet are transmitted and received between the packet processing units of each unit. A plurality of output processing interface units;
The packet processing apparatus according to claim 2, wherein the packet processing unit sends the dummy packet and the packet to any one of the plurality of output processing interface units. A plurality of input processing interface units are provided,
8. The packet processing according to claim 1, wherein the packet processing unit receives the dummy packet and the packet from any one of the plurality of input processing interface units. apparatus. In a packet processing method having a plurality of input ports and a plurality of output ports, processing a packet received by the input port, and transmitting from the output port,
The packet received by the input port is input, the timing at which the packet is input is detected, the packet is delayed by a predetermined time from the detected timing, and a dummy packet is generated at the predetermined time,
A packet processing method, wherein the generated dummy packet and the packet are input, and the input dummy packet and the packet are temporarily stored in a memory.   The dummy packet and the packet temporarily stored in the memory are input, the input dummy packet and the packet are identified, the identified dummy packet is discarded, and the identified packet is The packet processing method according to claim 9, wherein the packet is output to the output port.   The generated dummy packet and the packet are input, the input dummy packet and the packet are identified, and specific packet processing is performed only on the identified packet. The packet processing method according to claim 10. The dummy packet includes identification information that can be recognized as a dummy packet in the header of the dummy packet,
The packet processing method according to claim 9, wherein the dummy packet and the packet are identified based on the identification information.

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