JP2017192261A - Synchronous rectification circuit for wireless power receiver, control circuit therefor, control method, wireless power receiver and power reception control circuit, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an overvoltage protective function for a synchronous rectification circuit, the function differing from that in the conventional one.SOLUTION: A zero current detection circuit 202 detects a zero-cross point of current on the basis of a voltage across an AC1 terminal and AC2 terminal to which a full-bridge circuit 102 is connected. A control logic 204, depending on a detection signal ZC_DET from the zero current detection circuit 202, generates four control signals SG1 to SG4 for instructing ON/OFF of four transistors M1 to M4 constituting the full-bridge circuit 102. An overvoltage detection comparator 210, when a voltage Vof a rectification line 106 of the full-bridge circuit 102 exceeds an overvoltage threshold voltage V, asserts an overvoltage detection signal S. A timing control section 206, in response to assertion of the overvoltage detection signal S, makes switching timing of at least one of the four transistors M1 to M4 be different from timing instructed by the control signals SG1 to SG4.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a synchronous rectifier circuit of a wireless power receiving apparatus.

FIG. 1 is a block diagram of a wireless power supply system 900. The wireless power supply system 900 includes a wireless power transmission device 902 and a wireless power reception device 910. The wireless power transmitting apparatus 902 transmits the power signal S1 from the transmission coil 904. Wireless power receiving device 910 receives power signal S <b> 1 at receiving coil 912. Full bridge circuit 914 rectifies the current _{I AC} flowing through the receiver coil 912. Controller 918, a full bridge circuit 914, switching control in synchronism with the current _{I AC} waveform.

The current rectified by the full bridge circuit 914 is smoothed by the smoothing capacitor 916. The voltage V _RECT generated in the smoothing capacitor 916 is made constant by a regulator (eg, LDO) 920. A full bridge circuit 914, a controller 918, a regulator 920, and the like are integrated in a power reception control IC (Integrated Circuit) 930.

The power transmission device 902 and the power reception device 910 can communicate with each other, and a feedback loop is formed so as to keep the rectified voltage V _RECT at a target value (DP: Desired Point). However, when the coupling degree of the transmission coil 904 and the reception coil 912 changes at a speed exceeding the feedback response speed or the load of the regulator 920 fluctuates rapidly, the rectified voltage V _RECT jumps. When the rectified voltage V _RECT becomes an overvoltage, the withstand voltage of the transistors that form the full bridge circuit 914 and the regulator 920 may be exceeded.

A comparator 932 is provided to detect an overvoltage of the rectified voltage V _RECT . When V _RECT > V _{OVP and an} overvoltage state is detected, the switches SW91 and SW92 are turned on. As a result, the capacitors C91 and C92 are connected in parallel to the reception antenna 934, the resonance frequency of the reception antenna 934 changes, and the reception power decreases. As a result, an increase in the rectified voltage V _RECT is suppressed and overvoltage protection is applied.

US Pat. No. 8,278,889

  In the overvoltage protection shown in FIG. 1, external capacitors C91 and C92 are required to change the resonance frequency, which increases the cost and increases the mounting area. In particular, in the wireless power receiving apparatus, in addition to the capacitors C91 and C92, capacitors C93 and C94 for setting the resonance frequency, a modulation capacitor (not shown), and the like are externally attached, so that the number of capacitors can be reduced. It is meaningful if possible.

In this overvoltage protection, since the resonance frequency of the receiving antenna 934 is changed, a delay occurs until the protection is applied, and it may take time until the rectified voltage V _RECT decreases.

  The present invention has been made in view of such a problem, and one of the exemplary purposes of an aspect thereof is to provide a synchronous rectifier circuit having an overvoltage protection function different from the conventional one.

  One embodiment of the present invention relates to a control circuit that forms a synchronous rectifier circuit together with a full bridge circuit. The control circuit compares at least one of the voltages of the first AC input and the second AC input to which the full bridge circuit is connected with a threshold voltage, and generates at least one detection signal indicating the comparison result. And the control logic for generating four control signals for instructing on and off of the four transistors constituting the full bridge circuit according to at least one detection signal, and the voltage of the rectifier line of the full bridge circuit is overvoltage. An overvoltage detection comparator that asserts an overvoltage detection signal when a threshold voltage is exceeded, and a timing control that makes the switching timing of at least one of the four transistors different from the timing indicated by the control signal in response to the assertion of the overvoltage detection signal A section.

  According to this aspect, in the overvoltage state, the rectifier circuit can be protected from the overvoltage state by shifting the switching timing from the optimum point indicated by the control signal, thereby shifting the phase of the current waveform with respect to the voltage waveform, and controlling the power factor. Moreover, an overvoltage state can be suppressed.

  The timing control unit may change the switching timing of at least two transistors on the low side in response to the assertion of the overvoltage detection signal. The timing control unit may change the switching timing of the four transistors in response to the assertion of the overvoltage detection signal.

  The timing control unit may include a delay circuit that delays at least one of the four control signals in response to the assertion of the overvoltage detection signal.

  The delay amount of the delay circuit may depend on the set value of the register. By making it possible to adjust the delay amount from the outside, it is possible to realize overvoltage protection optimal for the system.

  The amount of delay when the overvoltage detection signal is asserted may depend on the slope of the voltage of the rectification line. By increasing the delay amount as the voltage gradient increases, adaptive overvoltage protection can be realized.

  The amount of delay when the overvoltage detection signal is asserted may depend on the voltage level of the rectification line. Adaptive overvoltage protection can be realized by increasing the delay amount as the voltage level increases.

  The control circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to a synchronous rectifier circuit. The synchronous rectifier circuit may include a full bridge circuit and any of the control circuits described above that control the full bridge circuit.

  The synchronous rectifier circuit may be used for a wireless power receiving apparatus and rectify the current of the receiving coil.

  Another aspect of the present invention relates to a power reception control circuit used in a wireless power receiving apparatus. The power reception control circuit includes any one of the above-described control circuits that controls the full bridge circuit connected to the reception coil, a regulator that stabilizes the rectified voltage generated by the full bridge circuit, and data to be transmitted to the wireless power transmission apparatus. And a modulator that modulates data and superimposes it on the receiving coil.

  Another aspect of the present invention relates to a wireless power receiving apparatus. The wireless power receiving apparatus stabilizes a rectified voltage generated in a receiving coil, a full bridge circuit connected to the receiving coil, a smoothing capacitor connected to the full bridge circuit, a control circuit for controlling the full bridge circuit, and the smoothing capacitor. And a regulator to perform.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes a wireless power receiving device.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the synchronous rectifier circuit can be protected from an overvoltage state.

It is a block diagram of a wireless power feeding system. It is a circuit diagram of a synchronous rectifier circuit including a control circuit according to an embodiment. FIG. 3 is an operation waveform diagram when the synchronous rectifier circuit of FIG. 2 is normal. It is an operation | movement waveform diagram in an overvoltage state. It is a block diagram of a wireless power receiving apparatus provided with the synchronous rectification circuit of FIG. It is a figure which shows an electronic device provided with a wireless power receiving apparatus.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  FIG. 2 is a circuit diagram of the synchronous rectifier circuit 100 including the control circuit 200 according to the embodiment. The synchronous rectifier circuit 100 includes a full bridge circuit 102 and a control circuit 200. The control circuit 200 is an integrated circuit (IC) integrated on a single semiconductor substrate together with the full bridge circuit 102. In a high power application, the power transistor constituting the full bridge circuit 102 may be constituted by a discrete element.

  The synchronous rectifier circuit 100 has an AC1 terminal (first AC input), an AC2 terminal (second AC input), a RECT terminal, and a GND terminal. A power source, a coil, and an antenna that generate an AC signal are connected to the AC1 terminal and the AC2 terminal. A smoothing capacitor 104 is connected to the RECT terminal, and the GND terminal is grounded. The full bridge circuit 102 is connected to the rectification line 106 and the RECT terminal, and is connected to the GND terminal via the ground line 108.

  The full bridge circuit 102 includes a first transistor M1 to a fourth transistor M4 that are connected in an H-bridge form. In the present embodiment, the first transistor M1 to the fourth transistor M4 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), but IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, GaN (gallium nitride) FETs, or the like may be used. Good. The first transistor M1 and the second transistor M2 on the high side may use P-channel (or PNP type).

  In addition, a freewheeling (flywheel) diode is provided in parallel with each of the first transistor M1 to the fourth transistor M4, but this is not shown. The free-wheeling diode may be a MOSFET body diode or a discrete element.

The control circuit 200 performs so-called zero current switching in the normal state and repeats the following states φ1 to φ4.
・ First state φ1
1st transistor M1 = OFF
Second transistor M2 = ON
Third transistor M3 = ON
Fourth transistor M4 = OFF
・ Second state φ2
1st transistor M1 = OFF
Second transistor M2 = OFF
Third transistor M3 = OFF
Fourth transistor M4 = OFF
・ Third state φ3
1st transistor M1 = ON
Second transistor M2 = OFF
Third transistor M3 = OFF
4th transistor M4 = ON
・ Fourth state φ4
1st transistor M1 = OFF
Second transistor M2 = OFF
Third transistor M3 = OFF
Fourth transistor M4 = OFF

  The control circuit 200 includes a zero current detection circuit 202, a control logic 204, and a driver 208 for zero current switching.

The zero current detection circuit 202 compares at least one of the voltages V _AC1 and V _AC2 at the AC1 terminal and the AC2 terminal with a threshold voltage, and generates at least one detection signal ZC_DET1, ZC_DET2 indicating the comparison result. ZC_DET1 signal level transitions for each zero-cross timing of current _{I AC1.} ZC_DET2 signal level transitions for each zero-cross timing of current _{I AC2.} Note that the zero cross timing indicated by the ZC_DET1 signal and the ZC_DET2 signal may not indicate a strict current zero cross point in consideration of the delay time of the circuit but may indicate a time earlier than that.

  Based on the ZC_DET1 signal and the ZC_DET2 signal, the control logic 204 generates four control signals SG1 to SG4 instructing on and off of the four transistors M1 to M4 constituting the full bridge circuit 102.

  The configurations of the zero current detection circuit 202 and the control logic 204 are not particularly limited, and a known technique may be used.

In the present embodiment, the zero current detection circuit 202 includes a first comparator ZC_COMP1 and a second comparator ZC_COMP2. First comparator ZC_COMP1 the voltage _{V AC1} in AC1 terminal is compared with the threshold value voltage _{V ZC1,} generates a ZC_DET1 signal. Second comparator ZC_COMP2 the voltage _{V AC2} of AC2 terminal is compared with the threshold value voltage _{V ZC2,} generates a ZC_DET2 signal.

Threshold voltage _{V ZC1} and _{V ZC2} is set to near zero, typically slightly lower voltage range than zero - is set to (number mV~- tens mV). As the threshold value voltage V _ZC1, V _ZC2 low, zero current detection is earlier in time, higher, zero current detection is delayed temporally. Therefore the threshold voltage _{V ZC1, V ZC2} is determined in consideration of the propagation delay, etc. of the response speed and signal of the comparator.

The ZC_DET1 signal is at the first level (high level in the present embodiment) when V _AC1 > V _ZC and is at the second level (low level) when low. First comparator ZC_COMP1 is hysteresis _comparator, V AC1 _<when a _{V ZC1,} the threshold voltage _{V ZC1} is set to a high _value, V _AC1> when a _{V ZC1,} the threshold voltage _{V ZC1} is low ( _{Denoted as VZC3} for convenience).

The ZC_DET2 signal is at the first level (high level) when V _AC2 > V _{ZC2 and} at the second level (low level) when V _AC2 <V _ZC2 . The second comparator ZC_COMP2 is also composed of a hysteresis comparator. When V _AC2 <V _ZC2 , the threshold voltage V _ZC2 is set to a high value, and when V _AC2 > V _ZC2 , the threshold voltage V _ZC2 is low. It is set to a value (denoted as _VZC4 for convenience).

  The zero current detection circuit 202 may include a mask circuit for removing noise of the first comparator ZC_COMP1 and the second comparator ZC_COMP2.

The control logic 204 is
(1) When the ZC_DET1 signal becomes the first level (high level), the full bridge circuit 102 is changed from the first state φ1 to the second state φ2,
(2) When the ZC_DET2 signal becomes the second level (low level), the full bridge circuit 102 is changed from the second state φ2 to the third state φ3,
(3) When the ZC_DET2 signal becomes the first level (high level), the full bridge circuit 102 is changed from the third state φ3 to the fourth state φ4,
(4) When the ZC_DET1 signal becomes the second level (low level), the full bridge circuit 102 is changed from the fourth state φ4 to the first state φ1.

  The control logic 204 may be a state machine. The control logic 204 generates control signals SG1 to SG4 instructing on and off of the first transistor M1 to the fourth transistor M4. The driver 208 switches the first transistor M1 to the fourth transistor M4 on and off according to the gate signals SG1 to SG4. When the high-side transistors M1 and M2 are N-channel, the driver 208 is configured using a bootstrap circuit, but a bootstrap capacitor and the like are omitted here.

  With the above configuration, the full bridge circuit 102 is zero-current switched in a normal state, and high-efficiency operation is realized. Next, overvoltage protection will be described.

  The control circuit 200 includes a timing control unit 206 and an overvoltage detection comparator (OVP comparator) 210 for overvoltage protection.

The OVP comparator 210 asserts an overvoltage detection signal (OVP signal) S _OVP (for example, high level) when the voltage V _RECT of the rectifying line 106 of the full bridge circuit 102 exceeds the overvoltage threshold voltage V _OVP .

  The timing control unit 206 is inserted, for example, between the control logic 204 and the driver 208, is built in the control logic 204, or is built in the driver 208.

In response to the assertion of the OVP signal S _OVP , the timing control unit 206 makes the switching timing of at least one of the four transistors M1 to M4 different from the timing indicated by the control signals SG1 to SG4. In the present embodiment, the timings of all four control signals SG1 to SG4 are shifted from the optimum timing for zero current switching indicated by the control signals SG1 to SG4.

The timing control unit 206 includes a plurality of delay circuits 212, for example. Each delay circuit 212 can be switched between enabled and disabled in accordance with the OVP signal S _OVP , applies a delay τ _OVP to the corresponding control signal SG in the enabled state, and passes the control signal SG in the disabled state. The delay amount τ _OVP can be about several ns to several tens ns.

  The delay amount of the delay circuit 212 is preferably adjustable according to a set value stored in the register. A set value of the delay amount can be written to the register from an external microcomputer or the like.

  The above is the configuration of the synchronous rectifier circuit 100. Next, the operation will be described. FIG. 3 is an operation waveform diagram when the synchronous rectifier circuit 100 of FIG. 2 is normal. M1 to M4 indicate gate signals.

Prior to time t0, the first state φ1. At time t0, when the first voltage _{V AC1} in AC1 terminal exceeds a first threshold voltage _{V ZC1,} ZC_DET1 signal is the first level (high level), the control circuit 200, the transition to the second state φ2 Instruct. Note that for ease of understanding, ZC_DET1 signal _is shown as being at the same time the level transitions when the V AC1 _{= V ZC1,} actually the response delay of the comparator transitions ZC_DET1 signal is delayed from time t0. The same applies to the ZC_DET2 signal. Thereafter, at time t1 after the lapse of the control delay τ1, the gate signals SG2 and SC3 of the second transistor M2 and the third transistor M3 become low level and turn off. The control delay τ1 includes a detection delay of the zero current detection circuit (comparator) 202, an operation delay of the control logic 204, a propagation delay of the driver 208, and the like. The control delay τ1 (τ2~τ4) does not include the delay time tau _OVP to be added in overvoltage conditions described above.

At time t2, when the second voltage _{V AC2} of AC2 terminal falls below the threshold voltage _{V ZC4,} ZC_DET2 signal is the second level (low level), the control circuit 200 to make a transition to the third state φ3 . Thereafter, the fourth transistor M4 is turned on at time t3 after the lapse of the control delay τ2, and the first transistor M1 is turned on at a delayed time t4.

At time t5, when the second voltage _{V AC2} of AC2 terminal exceeds the second threshold voltage _{V ZC2,} ZC_DET2 signal is the first level (high level), the control circuit 200, a transition to the fourth state φ4 Instruct. Thereafter, at time t6 after the elapse of the control delay τ3, the gate signals SG1 and SG4 of the first transistor M1 and the fourth transistor M4 become low level, and the first transistor M1 and the fourth transistor M4 are turned off.

When the first voltage V _AC1 at the AC1 terminal falls below the threshold voltage V _ZC3 at time t7, the ZC_DET1 signal becomes the second level (low level), and the control circuit 200 instructs the transition to the first state φ1. . Thereafter, the third transistor M3 is turned on at time t8 after the lapse of the control delay τ4, and the second transistor M2 is turned on at a delayed time t9.

The state (actual transistor state) φ1 ′ to φ4 ′ of the full bridge circuit 102 transitions with a delay from the corresponding states φ1 to φ4 of the control circuit 200, respectively. The first threshold voltage _{V ZC1} ~ fourth threshold voltage _{V ZC4} of the control circuit 200, delayed state of the full bridge circuit 102 φ1'~φ4 'has a zero-cross point of the actual current _{I AC1, I AC2} It is determined to match.

Pay attention to the transition from the first state φ1 to the second state φ2.
The first voltage V _AC1 in the first state φ1 is given by I _AC1 × R _ON3 . R _ON3 is the on-resistance of the third transistor M3. The threshold voltage V _ZC1 may be determined such that an actual current zero current (I _AC1 = 0) is generated after a delay time τ1 has elapsed since V _AC1 crossed V _ZC1 .

If the slope of the current I _AC1 is α (A / s), the slope of the first voltage V _AC1 is α × R _ON3 (V / s). Therefore, ideal zero current switching can be realized by determining the threshold voltage V _ZC1 so as to satisfy the expression (1).
V _ZC1 = α × R _ON3 × τ1 (1)

Subsequently, the operation in the overvoltage state will be described. FIG. 4 is an operation waveform diagram in the overvoltage state. The alternate long and short dash line shows the waveform in the zero current switching of FIG. 3 for reference. The gate signals of the first transistor M1 to the fourth transistor M4 are delayed by a delay time τ _OVP compared to the waveform diagram of FIG. Due to this delay time τ _OVP , the current is inverted while the voltage is crossed, and a reactive power section is generated. In this section, since the load after the synchronous rectifier circuit 100 looks high impedance as viewed from the power transmission device, power is not supplied to the load. Thereby, the electric current supplied to the smoothing capacitor 104 and the rectification line 106 decreases, and an overvoltage state can be suppressed.

  The above is the operation of the synchronous rectifier circuit 100. According to this synchronous rectifier circuit 100, an overvoltage state can be suppressed.

  Since the capacitors C91 and C92 as shown in FIG. 1 are not required, the cost can be reduced, the number of IC pins can be reduced, and the circuit mounting area can be reduced.

  In addition, when the resonance frequency is shifted by the capacitors C91 and C92, overvoltage protection is gradually enabled over several cycles of the power signal S1. On the other hand, according to the present embodiment, the reactive power section can be generated on a cycle-by-cycle basis by the OVP comparator 210 and the timing control unit 206, so that high-speed overvoltage protection can be realized.

In addition, since the rise of the rectified voltage V _RECT can be suppressed more than before, the breakdown voltage required for the circuit may be lowered.

(Use)
Next, a preferred application of the synchronous rectifier circuit 100 will be described. FIG. 5 is a block diagram of a wireless power receiving apparatus 300 including the synchronous rectification circuit 100 of FIG. The wireless power receiving apparatus 300 includes a receiving coil L _RX , resonant capacitors Cs and Cd, a smoothing capacitor C _RECT (104), and a power receiving control IC 400. The synchronous rectifier circuit 100 is integrated in the power reception control IC 400. The power reception control IC 400 includes a regulator 310, a controller 312, and a modulator 314 in addition to the synchronous rectification circuit 100. The synchronous rectifier circuit 100 rectifies the current flowing through the receiving coil 302.

The regulator 310 stabilizes the rectified voltage V _RECT generated by the full bridge circuit 102 and the smoothing capacitor 104, and outputs the rectified voltage V _RECT from the output (OUT) pin to the outside.

The controller 312 controls the power reception control IC 400 as a whole and generates data to be transmitted to the wireless power transmission apparatus 902. This data may include a control error packet indicating an error between the rectified voltage V _RECT and the target value DP, a packet indicating the power received by the wireless power receiving apparatus 300, and the like. The modulator 314 modulates data (packet) from the controller 312 and superimposes it on the reception coil 302 via the COMM1 and COMM2 terminals.

  The wireless power receiving apparatus 300 may be employed for either an electromagnetic induction method or a magnetic resonance method. Examples of the former include the Qi standard established by WPC (Wireless power consortium) and the Air-Fuel Alliance standard. In the magnetic resonance method adopted by the Air-Fuel Alliance standard, a frequency band (for example, 6.78 MHz) higher than 150 k to 200 kHz of the electromagnetic induction method is used. Therefore, with respect to overvoltage protection, since a faster response is required, there is a possibility that the advantages of the synchronous rectifier circuit 100 according to the embodiment can be enjoyed more. Alternatively, it can also be used for non-contact power transmission (also referred to as non-contact power transmission or wireless power feeding) used for an electric shaver, electric toothbrush, cordless phone, game machine controller, electric tool, or the like.

  The wireless power receiving apparatus 300 is mounted on the electronic device 500. FIG. 6 is a diagram illustrating an electronic device 500 including the wireless power receiving apparatus 300. The electronic device 500 may be a mobile phone terminal, a tablet terminal, a notebook PC, a digital camera, a digital video camera, a portable audio device, a portable game device, or the like.

The housing 502 of the electronic device 500, in addition to the reception coil _{L RX} and the power reception control IC 400, the charging circuit 504 and the secondary battery 506 is housed. The charging circuit 504 receives the output voltage _VOUT of the power reception control IC 400 and charges the secondary battery 506. Note that the layout of these components is not particularly limited.

  The present invention has been described based on the embodiments. Those skilled in the art will understand that these embodiments are exemplifications, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way. Hereinafter, such modifications will be described.

(First modification)
In the embodiment, all the gate signals of the first transistor M1 to the fourth transistor M4 are delayed in the overvoltage state, but the present invention is not limited to this. For example, the timing control unit 206 may delay the gate signals of the two transistors M3 and M4 on the low side. Furthermore, since it is only necessary to keep away from ideal zero current switching in an overvoltage state, at least one gate signal may be delayed.

  Alternatively, the timing control unit 206 may advance the switching timing of each transistor earlier than the ideal timing of zero current switching in the overvoltage state.

(Second modification)
The amount of change in switching timing when the overvoltage detection signal S _OVP is asserted, for example, the delay amount τ _OVP , may depend on the slope of the voltage V _RECT of the rectifying line 106. An adaptive overvoltage protection can be realized by increasing the delay amount τ _OVP as the slope of the voltage V _RECT increases. The slope of the voltage V _RECT may be detected using a high-pass filter (differential circuit) or may be calculated from a digital value captured by an A / D converter.

(Third Modification)
The amount of change in switching timing when the overvoltage detection signal S _OVP is asserted, for example, the delay amount τ _OVP , may depend on the voltage level V _RECT of the rectifying line 106. By increasing the delay amount τ _OVP as the rectified voltage V _RECT is higher, adaptive overvoltage protection can be realized. The voltage level of the rectified voltage V _RECT may be captured by an A / D converter, or may be detected using a plurality of OVP comparators having different threshold values.

(Fourth modification)
In the embodiment, the case where the full bridge circuit 102 is integrated in the same IC as the control circuit 200 has been described. However, in high power applications, discrete elements may be used as the transistors M1 to M4 of the full bridge circuit 102. Good.

(5th modification)
In the embodiment, the threshold voltage _V ZC1 _{~V ZC4} was near zero, may be set to the rectified voltage _{V RECT} side.

(Sixth Modification)
The synchronous rectifier circuit 100 according to the embodiment can be suitably used as a rectifier circuit for wireless power feeding in which the frequency of the power signal is higher than that of commercial AC. The application of the synchronous rectifier circuit 100 is not limited to this, and can be used for various applications such as an AC / DC converter.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Synchronous rectification circuit, 102 ... Full bridge circuit, 104 ... Smoothing capacitor, 106 ... Rectification line, 108 ... Grounding line, 200 ... Control circuit, 202 ... Zero current detection circuit, 204 ... Control logic, 206 ... Timing control part, DESCRIPTION OF SYMBOLS 208 ... Driver, 210 ... OVP comparator, 300 ... Wireless power receiving apparatus, _LRX ... Reception coil, Cs, Cd ... Resonance capacitor, 310 ... Regulator, 312 ... Controller, 314 ... Modulator, 400 ... Power reception control IC, 500 ... Electronics Equipment: 502 ... Case, 504 ... Charging circuit, 506 ... Secondary battery, M1 ... First transistor, M2 ... Second transistor, M3 ... Third transistor, M4 ... Fourth transistor.

Claims (13)

A control circuit that is used in a wireless power receiving apparatus and that forms a synchronous rectifier circuit together with a full bridge circuit,
The control circuit includes:
A zero current detection circuit that compares at least one of the voltages of the first AC input and the second AC input to which the full bridge circuit is connected with a threshold voltage and generates at least one detection signal indicating the comparison result;
In response to the at least one detection signal, a control logic that generates four control signals for instructing on and off of the four transistors constituting the full bridge circuit;
An overvoltage detection comparator that asserts an overvoltage detection signal when the voltage of the rectification line of the full bridge circuit exceeds an overvoltage threshold voltage;
A timing control section that makes the switching timing of at least one of the four transistors different from the timing indicated by the control signal in response to the assertion of the overvoltage detection signal;
A control circuit comprising:   2. The control circuit according to claim 1, wherein the timing control unit changes the switching timing of at least two low-side transistors in response to the assertion of the overvoltage detection signal.   The control circuit according to claim 1, wherein the timing control unit changes switching timings of the four transistors in response to the assertion of the overvoltage detection signal.   4. The control according to claim 1, wherein the timing control unit includes a delay circuit that delays at least one of the four control signals in response to assertion of the overvoltage detection signal. 5. circuit.   The control circuit according to claim 4, wherein the delay amount of the delay circuit depends on a set value of a register.   The control circuit according to claim 4, wherein a delay amount when the overvoltage detection signal is asserted depends on a slope of a voltage of the rectification line.   The control circuit according to claim 4, wherein a delay amount when the overvoltage detection signal is asserted depends on a voltage level of the rectification line.   8. The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate. Full bridge circuit,
The control circuit according to any one of claims 1 to 8, which controls the full bridge circuit;
A synchronous rectifier circuit characterized by rectifying the current of the receiving coil. A power reception control circuit used in a wireless power receiving apparatus,
The control circuit according to any one of claims 1 to 8, which controls a full bridge circuit connected to the receiving coil;
A regulator for stabilizing a rectified voltage generated by the full bridge circuit;
A controller that generates data to be transmitted to the wireless power transmission device;
A modulator that modulates the data and superimposes the data on the receiving coil;
A power reception control circuit comprising: A receiving coil;
A full bridge circuit connected to the receiving coil;
A smoothing capacitor connected to the full bridge circuit;
The control circuit according to any one of claims 1 to 8, which controls the full bridge circuit;
A regulator for stabilizing a rectified voltage generated in the smoothing capacitor;
A wireless power receiving apparatus comprising:   An electronic apparatus comprising the wireless power receiving device according to claim 11. A control method of a full bridge circuit for rectifying a current flowing in a receiving coil of a wireless power receiving apparatus,
Generating four control signals that transition at a timing at which the full bridge circuit can be soft-switched based on voltages of the first AC input and the second AC input of the full bridge circuit;
Driving the full bridge circuit based on the four control signals;
When the rectified voltage, which is the output of the full bridge circuit, exceeds an overvoltage threshold voltage, delaying at least one of the four control signals to cause the full bridge circuit to perform a non-soft switching operation;
A control method comprising:

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