JP2017147851A - Electric power conversion system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric power conversion system capable of detecting imbalance of an output current in each electric power supply without using communication equipment.SOLUTION: Each of a master 10 and a slave 20 comprises: a switching circuit including a switch S1, a switch S2, and a main reactor L1; auxiliary resonance circuits 150 and 250 having a switch S3 and an auxiliary reactor L2; and a voltage detection part 51 that detects an inter-terminal voltage of the switch S1 or the switch S2. The master 10 comprises a controller 16 that generates a control signal GsA of the switch S3A on the basis of rising waveform or falling waveform of the inter-terminal electrode of the switches S1A and S2A. The slave 20 comprises a controller 26 that the control signal GsB of the switch S3B is equalized to the control signal GsA. The controller 16 or 26 observes a difference of the rising waveform or falling waveform in the master 10 and the slave 20, and detects imbalance of an output current.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power conversion device including a plurality of power supply devices connected in parallel to each other.

  As a power conversion apparatus including a plurality of power supply apparatuses connected in parallel to each other, there is a power supply system described in Patent Document 1. In the power supply system described in Patent Literature 1, in each power supply device, an output current is detected by a current sensor, an output current detected in another power supply device is acquired via a communication device, and an output current of all the power supply devices is obtained. The average value is calculated. In the power supply system, the output voltage is commanded to each power supply device so that the output current of each power supply device becomes the calculated average value, and the output current is balanced.

JP 2009-165247 A

  In the power supply system, since the communication device is used, there is a delay in acquiring other output current. Therefore, even if an imbalance occurs in the output power of each power supply device, a delay occurs in the detection of the imbalance. As a result, it may take time to balance the output current of each power supply device.

  In view of the above circumstances, it is a main object of the present invention to provide a power conversion device that can detect an imbalance in output current of each power supply device without using a communication device.

  The present invention comprises a first power supply device serving as a reference and at least one second power supply device, wherein the first power supply device and the second power supply device are connected in parallel to each other in a load, Each of the first power supply device and the second power supply device includes a main switch, a synchronous rectification switch, and a main magnetic component, and the main switch and the synchronous rectification switch are complementarily turned on and off. A switching circuit that converts an input voltage into a predetermined voltage and outputs the auxiliary circuit, and an auxiliary magnetic component, and the auxiliary switch is turned on when the main switch is turned off. An auxiliary switching circuit that releases energy for suppressing the voltage between terminals of the main switch, and a voltage that detects the voltage between terminals of the main switch or the synchronous rectification switch. A detection unit; and the first power supply device further generates a main signal that complementarily turns on and off the main switch and the synchronous rectification switch of the first power supply device, and the detected synchronous rectification A first control unit that generates an auxiliary signal for controlling the auxiliary switch of the first power supply device based on a rising waveform of a voltage between terminals of the switch or a falling waveform of a voltage between terminals of the main switch; The two-power-supply device further generates a main signal that complementarily turns on and off the main switch and the rectifier switch of the second power-supply device, and outputs an auxiliary signal that controls the auxiliary switch of the second power-supply device, A power conversion device including a second control unit configured to make the same signal as the auxiliary signal in the first power supply device, wherein the first control unit or the second control unit The control unit observes a difference in the rising waveform or a difference in the falling waveform between the first power supply device and the second power supply device, and imbalances output currents of the first power supply device and the second power supply device. Is detected.

  According to the present invention, in each power supply device, when the synchronous rectification switch is in the ON state, the auxiliary switch is turned on, whereby the auxiliary current flows in the auxiliary magnetic component and energy is accumulated. When the synchronous rectification switch is turned off with the auxiliary switch turned on, the energy stored in the second magnetic component is released to the main switch and the synchronous rectification switch side. As a result, the voltage between the terminals of the main switch becomes zero, and zero-volt switching (hereinafter referred to as ZVS) of the main switch is realized.

  Here, the longer the time during which the auxiliary switch and the synchronous rectifier switch are in the ON state simultaneously, the larger the auxiliary current flowing through the auxiliary magnetic component, and the greater the energy stored in the auxiliary magnetic component. When the energy stored in the auxiliary magnetic component increases, the voltage between the terminals of the synchronous rectification switch suddenly rises and the voltage between the terminals of the main switch suddenly falls when the energy accumulated in the auxiliary magnetic component is released. Therefore, auxiliary current information appears in the rising waveform of the voltage between the terminals of the synchronous rectification switch and the falling waveform of the voltage between the terminals of the main switch. Since the first power supply device generates an auxiliary signal for the auxiliary switch based on the rising waveform or the falling waveform, an optimal ZVS can be realized by adjusting the auxiliary current.

  On the other hand, since the auxiliary signal of the second power supply device is generated as the same signal as the auxiliary signal of the first power supply device, the auxiliary current of the second power supply device has the same magnitude as the auxiliary current of the first power supply device. However, the output currents of the first power supply device and the second power supply device may vary due to variations in the elements of the first power supply device and the second power supply device. Since the output current is an average current of the current flowing through the main magnetic component, when the output current varies, the current flowing through the main magnetic component also varies. The minimum auxiliary current required for realizing ZVS increases as the current flowing through the main magnetic component increases. Therefore, when the current flowing through the main magnetic component of the second power supply device is smaller than that of the first power supply device, the auxiliary current in the second power supply device is larger than the optimum case, and the rising waveform rises sharply, The falling waveform falls abruptly. In addition, when the current flowing through the main magnetic component of the second power supply device is larger than that of the first power supply device, the auxiliary current in the second power supply device becomes smaller than the optimum case, and the rising waveform rises slowly and The falling waveform falls gently. That is, the variation in the output current between the first power supply device and the second power supply device appears as a difference in the rising waveform and a difference in the falling waveform between the first power supply device and the second power supply device. Therefore, by observing the difference in the rising waveform or the difference in the falling waveform, it is possible to immediately detect the imbalance in the output current of each power supply device without using a communication device.

The figure which shows schematic structure of the power converter device which concerns on 1st Embodiment. The figure which shows the structure of the step-down converter of the multiphase which concerns on 1st Embodiment. (A) gate voltage of the upper arm of the step-down converter, (b) gate voltage of the lower arm, (c) gate voltage of the auxiliary switch, (d) voltage between terminals of the upper arm, (e) voltage between terminals of the lower arm, (F) Reactor current, (f) Auxiliary current time chart. The time chart which expanded the period A of FIG. The circuit diagram which shows the operation | movement aspect of a step-down converter. The circuit diagram which shows the operation | movement aspect of a step-down converter. The circuit diagram which shows the operation | movement aspect of a step-down converter. The circuit diagram which shows the operation | movement aspect of a step-down converter. The circuit diagram which shows the operation | movement aspect of a step-down converter. The circuit diagram which shows the operation | movement aspect of a step-down converter. The circuit diagram which shows the operation | movement aspect of a step-down converter. The figure which shows the structure of the transition time detector of a step-down converter. The time chart of (a) reactor current of master and slave, (b) auxiliary current, (c) voltage between terminals of upper arm, and (d) gate voltage of auxiliary switch when slave output current is small. The time chart of (a) reactor current of master and slave, (b) auxiliary current, (c) voltage between terminals of upper arm, and (d) gate voltage of auxiliary switch when slave output current is large. The block diagram which shows the function of the controller of a step-down converter. The figure which shows the count value of the ON time of (a) master PWM signal and (b) master PWM signal. (A) Master operation, (b) Master upper arm gate command, (c) Master PWM signal on-count value, (d) Slave operation, (e) Slave upper arm Gate command time chart. (A) Master operation, (b) Master upper arm gate command, (c) Master PWM signal on-count value, (d) Master PWM signal off-count value when the power converter is stopped, (e) (F) Time chart of slave upper gate command. The figure which shows the structure of the boost converter which concerns on 2nd Embodiment. The figure which shows the structure of the bidirectional | two-way type converter which concerns on 3rd Embodiment. The figure which shows the structure of the pressure | voltage fall converter which concerns on 4th Embodiment. The figure which shows the structure of the pressure | voltage fall converter which concerns on 5th Embodiment. The figure which shows the structure of the pressure | voltage fall converter which concerns on 6th Embodiment.

  Hereinafter, embodiments embodying a power conversion device will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals in the drawings, and the description of the same reference numerals is used.

(First embodiment)
First, a schematic configuration of the power conversion device according to the present embodiment will be described with reference to FIG. The power conversion device according to the present embodiment includes a plurality of power supply devices connected in parallel to each other. Specifically, the power conversion device according to the present embodiment includes a master 10 (first power supply device) serving as a reference for power conversion and one slave 20 (second power supply device). Yes. The master 10 includes a power conversion unit 15 and a control circuit unit 18, and the control circuit unit 18 controls the power conversion unit 15 to perform power conversion. The slave 20 includes a power conversion unit 25, a control circuit unit 28, and a time observer 29. The time observer 29 observes the control signal generated by the control circuit unit 18 of the master 10, and the control circuit part 28 is based on the control signal of the master 10 observed by the time observer 29. To control power. Hereinafter, details of the configurations of the master 10 and the slave 20 according to the present embodiment will be described with reference to FIG.

<Basic configuration of step-down converter>
In the present embodiment, the master 10 and the slave 20 are embodied as a step-down converter. The power conversion unit 15 of the master 10 includes a switch S1A, a switch S2A, a main reactor L1A, an auxiliary resonance circuit 150, a smoothing capacitor Cs1A, and a smoothing capacitor Cs2A. The auxiliary resonance circuit 150 includes a switch S3A, a diode D3A, an auxiliary reactor L2A, and a diode DsA. The control circuit unit 18 includes a controller 16 (first control unit) and a transition time detector 17.

  The power conversion unit 25 of the slave 20 includes a switch S1B, a switch S2B, a main reactor L1B, an auxiliary resonance circuit 250, a smoothing capacitor Cs1B, and a smoothing capacitor Cs2B. The auxiliary resonance circuit 250 includes a switch S3B, a diode D3B, an auxiliary reactor L2B, and a diode DsB. The control circuit unit 28 includes a controller 26 (second control unit) and a transition time detector 27. The basic configuration of the master 10 and the slave 20 is the same.

  Hereinafter, the switches S1A and S1B, the switches S2A and S2B, the main reactors L1A and L1B, the smoothing capacitors Cs1A and Cs1B, the smoothing capacitors Cs2A and Cs2B, are combined, and the switch S1, the switch S2, the main reactor L1, the smoothing capacitor Cs1, This is referred to as a smoothing capacitor Cs2. The switches S3A and S3B, the diodes D3A and D3B, the auxiliary reactors L2A and L2B, and the diodes DsA and DsB are collectively referred to as a switch S3, a diode D3, an auxiliary reactor L2, and a diode Ds. Furthermore, reactor currents IL1A and IL1B and auxiliary currents IL2A and IL2B are collectively referred to as reactor current IL1 and auxiliary current IL2. The inter-terminal voltages Vds1A and Vds1B of the switches S1A and S1B and the inter-terminal voltages Vds2A and Vds2B of the switches S2A and S2B are collectively referred to as an inter-terminal voltage Vds1 of the switch S1 and an inter-terminal voltage Vds2 of the switch S2.

  The switch S1 and the switch S2 are connected in series between the terminals 11 and 12 of the master 10 and the terminals 21 and 22 of the slave 20. In the present embodiment, N-channel MOSFETs are used as the switches S1 and S2. The drain terminal of the switch S1 is connected to the high potential side terminals 11 and 21, and the source terminal of the switch S2 is connected to the low potential side terminals 12 and 22. The source terminal of the switch S1 and the drain terminal of the switch S2 are connected at the connection point Po.

  A first end of both ends of the main reactor L1 (main magnetic component) is connected to the connection point Po. The second end of both ends of the main reactor L1 is connected to the terminals 13 and 23 on the high potential side. A power supply 70 is connected between the terminals 11 and 12 and between the terminals 21 and 22, and a load 80 is connected between the terminals 13 and 14 and between the terminals 23 and 24. Further, in parallel with the power source 70, between the drain terminal of the switch S1, which is the high potential side terminal of the series body of the switch S1 and the switch S2, and the source terminal of the switch S2, which is the low potential side terminal of the series body, A smoothing capacitor Cs1 (first smoothing capacitor) is connected. A smoothing capacitor Cs2 (second smoothing capacitor) is connected in parallel with the load 80 between the second end of the main reactor L1 and the source terminal of the switch S2. The smoothing capacitors Cs1 and Cs2 are for stabilizing the input voltage and the output voltage, respectively.

  Capacitors C1 and C2, which are capacitive components, are connected to the switches S1 and S2, respectively, in parallel. Capacitors C1 and C2 may be stray capacitances of transistors or may be external snubber capacitors. Further, diodes D1 and D2 are connected in antiparallel to the switches S1 and S2, respectively. The diodes D1 and D2 may be transistor body diodes or external diodes.

  The switches S1 and S2 are turned on and off in a complementary manner. When the switch S1 is in the on state, current is supplied from the power source 70 to the main reactor L1. When the switch S2 is in the on state, current is supplied from the main reactor L1 to the load 80. As a result, the input voltage of the power source 70 is stepped down to a predetermined voltage and applied to the load 80. That is, the upper arm switch S1 is a main switch that performs power conversion, and the lower arm switch S2 is a synchronous rectification switch that performs synchronous rectification. The switches S1 and S2 and the main reactor L1 constitute a switching circuit.

  The auxiliary resonance circuits 150 and 250 (auxiliary switching circuit) are circuits connected in parallel to the main reactor L1 at the first end of the main reactor L1. The auxiliary resonance circuits 150 and 250 include a switch S3, an auxiliary reactor L2 (auxiliary magnetic component), and a diode DS (auxiliary element). In the present embodiment, an N-channel MOSFET is used as the switch S3 (auxiliary switch). A diode D3 is connected to the switch S3 in antiparallel. The diode D3 may be a body diode of a transistor or an external diode. The source terminal of the switch S3 is connected to the first end of the main reactor L1, and the drain terminal of the switch S3 is connected to the first end of the auxiliary reactor L2. The cathode terminal of the diode Ds is connected to the second end of the auxiliary reactor L2, and the anode terminal of the diode Ds is connected to the second end of the main reactor L1.

  The controllers 16 and 26 (control unit) are microcomputers including a CPU, a memory, an I / O, and the like. The controllers 16 and 6 control the switching of the switches S1 and S2 to convert the input voltage into a predetermined voltage. That is, the controllers 16 and 26 generate gate command signals GpA, GnA, GpB, and GnB (main signals) for controlling on / off of the switches S1 and S2, and send them to drivers connected to the gate terminals of the switches S1 and S2. Send. Further, the controllers 16 and 26 control the switching of the switch S3 to cause the capacitors C1 and C2 and the auxiliary reactor L2 to resonate. That is, the controllers 16 and 26 generate gate command signals GsA and GsB (auxiliary signals) for controlling on / off of the switch S3 and transmit them to the driver connected to the gate terminal of the switch S3. The master 10 and the slave 20 are partially resonant circuits.

  The transition time detectors 17 and 27 detect the transition time of the switch S1 or the switch S2. The time observer 29 provided only in the slave 20 is composed of a microcomputer together with the controller 26, and observes gate command signals GpA and GsA for the switches S1A and S3A of the master 10 by the capture function of the microcomputer. The functions of the controllers 16 and 26, the transition time detectors 17 and 27, and the time observer 29, and details of the transition time will be described later.

<Basic operation of step-down converter>
Next, basic operations of the master 10 and the slave 20 will be described with reference to FIGS. The basic operations of the master 10 and the slave 20 are the same. FIG. 3 is a time chart showing operation modes of the master 10 and the slave 20. 3A to 3C show time charts of the gate voltages Vgs1, Vgs2, and Vgs3 of the switches S1 to S3, respectively. That is, FIGS. 3A to 3C show on / off of the switches S1 to S3. FIGS. 3D and 3E show the inter-terminal voltage Vds1 of the main switch and the inter-terminal voltage Vds2 of the synchronous rectification switch. The inter-terminal voltages Vds1 and Vds2 are inter-terminal voltages between the drain terminals and the source terminals of the switches S1 and S2.

  FIGS. 3F and 3G show the reactor current IL1 flowing through the main reactor L1 and the auxiliary current IL2 flowing through the auxiliary reactor L2, respectively. FIG. 4 is a time chart in which the period A in FIG. 3 is enlarged. The switch S1 and the switch S2 are alternately turned on and off, but at the time of switching on and off, a dead time during which both are turned off is sandwiched. The reactor current IL1 is positive in the direction flowing from the connection point Po side to the smoothing capacitor Cs2 side, and the auxiliary current IL2 is positive in the direction flowing from the diode Ds side to the switch S3 side.

  FIG. 5 is a circuit diagram showing an operation mode in a period from time t0 to immediately before time t1. During this period, only the switch S2 is turned on, and only the flyback current of the main reactor L1 flows.

  Next, FIG. 6 is a circuit diagram showing an operation mode in a period from time t1 to immediately before time t2. At time t1, the switch S3 is turned on, and only the switch S1 is in an off state during this period. During this period, the auxiliary current IL2 flows and magnetic energy is accumulated in the auxiliary reactor L2. The longer the period during which the switch S2 and the switch S3 are in the ON state at the same time, the more magnetic energy is stored in the auxiliary reactor L2.

  Next, FIG. 7 is a circuit diagram showing an operation mode during a resonance operation. When the switch S2 is turned off at the time t2, only the switch S3 is turned on, and the resonant operation of the capacitors C1 and C2 and the auxiliary reactor L2 occurs. As a result, the auxiliary current IL2 is distributed to the current flowing through the capacitors C1 and C2, and the potential at the connection point Po increases. That is, the voltage Vds2 between the terminals of the switch S2 increases and the voltage Vds1 between the terminals of the switch S1 decreases.

  Here, when the auxiliary current IL2 at the time point t2 when the switch S2 is turned off satisfies the condition of the following equation (1), the inter-terminal voltage Vds2 rises to the input voltage V1 due to the resonance operation. In the formula (1), C1 and C2 are capacitances of the capacitors C1 and C2, and L2 is an inductance of the auxiliary reactor L2. V1 is an input voltage and V2 is an output voltage. The derivation of equation (1) is omitted because it is publicly known (for example, see Japanese Patent Application Laid-Open No. 2004-12393).

  Next, FIG. 8 is a circuit diagram showing an operation mode in a state where the inter-terminal voltage Vds2 reaches the input voltage V1 and the inter-terminal voltage Vds1 becomes 0 by the resonance operation. When the inter-terminal voltage Vds1 becomes 0, the diode D1 is turned on, no current flows through the capacitor C1, and the resonance operation ends.

  Next, FIG. 9 is a circuit diagram showing an operation mode in a period from time t3 to immediately before time t4. At time t3, the diode D1 is on, the switch S1 is turned on, and only the switch S2 is off. When the diode D1 is in the on state, the switch S1 is turned on, thereby realizing the ZVS of the switch S1. By realizing the ZVS of the switch S1, the conduction loss of the switch S1 accompanying the switching of the switch S1 is minimized. Note that the period from time t2 to time t3 corresponds to dead time.

  Next, FIG. 10 is a circuit diagram showing an operation mode in a period from time t4 to immediately before time t5. At time t4, the switch S3 is turned off and only the switch S1 is turned on. In this period, the electric energy supplied from the power source 70 is stored in the main reactor L1.

  Next, FIG. 11 is a circuit diagram showing an operation mode at time t5. At time t5, the switch S1 is turned off and all switches are turned off.

<Optimal ZVS control>
As described above, ZVS of the switch S1 can be realized by turning off the switch S2 when the auxiliary current IL2 satisfies the condition of the expression (1). Therefore, it can be considered that the auxiliary current IL2 is detected by the current sensor, and the switch S2 is turned off when the detected auxiliary current IL2 satisfies the condition of the expression (1). However, in consideration of factors such as detection accuracy of the current sensor, fluctuations in the input voltage V1 and output voltage V2, variations in the capacitances C1 and C2, variations in the inductance L2, temperature characteristics, etc. In order to satisfy (1), the magnitude of the auxiliary current IL2 must be set with a margin.

  However, when the auxiliary current IL2 increases, the conduction loss of the switches S2 and S3 increases, and the overall circuit loss of the master 10 and slave 20 increases. In order to suppress the loss of the entire circuit of the master 10 and the slave 20, it is desirable to set the magnitude of the auxiliary current IL2 to a minimum value that achieves the ZVS of the switch S1.

  Here, the inventor has focused on the fact that the information on the auxiliary current IL2 appears in the rising waveform of the inter-terminal voltage Vds2 and the falling waveform of the inter-terminal voltage Vds1 after the switch S2 is turned off (see FIG. 4). . Since the sum of the inter-terminal voltage Vds1 and the inter-terminal voltage Vds2 is constant at the input voltage V1, the rising waveform of the inter-terminal voltage Vds2 and the falling waveform of the inter-terminal voltage Vds1 are complementary waveforms.

  As the magnetic energy stored in the auxiliary reactor L2 increases, the voltage across the capacitor C2 increases more rapidly when the switch S2 is turned off to cause a resonance operation. That is, the inter-terminal voltage Vds2 rises rapidly and the inter-terminal voltage Vds1 falls abruptly. Therefore, information on the auxiliary current IL2 appears in the rising waveform of the inter-terminal voltage Vds2 and the falling waveform of the inter-terminal voltage Vds1. The rising waveform and the falling waveform are transient phenomena including all factors such as fluctuations in input / output voltages, device variations, and temperature characteristics.

  Therefore, it is optimal to observe the rising waveform of the inter-terminal voltage Vds2 or the falling waveform of the inter-terminal voltage Vds1, and generate the control signal for the switch S3 so that the rising waveform or the falling waveform becomes a target waveform. ZVS control can be realized with a small auxiliary current IL2. In the present embodiment, the transition time from the start to the end of the inter-terminal voltage Vds2 or the transition time from the start to the end of the inter-terminal voltage Vds1 is detected as the rising waveform or the falling waveform. In the following, it is assumed that the transition time in the master 10 is TaA and the transition time in the slave 20 is TaB.

  FIG. 12 shows the configuration of the transition time detector 17 of the master 10 that detects the transition time. The transition time detector 27 of the slave 20 has the same configuration. The transition time detector 17 (transition time detection unit) includes a voltage detector 171 and an XOR circuit 173. The voltage detector 171 (voltage detection unit) includes resistors R1 to R4 and a comparator 172. A threshold Vth obtained by dividing the input voltage V1 by the resistors R1 and R2 is input to the non-inverting input terminal of the comparator 172. The inter-terminal voltage Vds <b> 2 is input to the inverting input terminal of the comparator 172. When the inter-terminal voltage Vds2 is less than the threshold value Vth, the output of the comparator 172 becomes “1”, and when the inter-terminal voltage Vds2 exceeds the threshold value Vth, the output of the comparator 172 becomes “0”.

  The output of the comparator 172 and the gate command signal GnA of the switch S2 are input to the XOR circuit 173. The output of the XOR circuit 173 becomes “1” after the switch S2 is turned off until the inter-terminal voltage Vds2 exceeds the threshold Vth, and becomes “0” when the inter-terminal voltage Vds2 exceeds the threshold Vth. Therefore, the transition time TaA is a period in which the output of the XOR circuit 173 is “1”. Therefore, the controller 16 detects, as the transition time TaA, the time when the output of the XOR circuit 173 becomes “1” by the capture function of the microcomputer.

  When the transition time TaA is detected from the falling waveform, the threshold Vth is set to 10% of the input voltage V1, for example. The inter-terminal voltage Vds1 is input to the non-inverting input terminal of the comparator 172, and the threshold Vth is input to the inverting input terminal of the comparator 172. Thereby, the output of the comparator 172 becomes “1” while the inter-terminal voltage Vd1 is larger than the threshold value Vth, and becomes “0” when the inter-terminal voltage Vds1 becomes less than the threshold value Vth.

<Current balance control>
In the master 10, the controller 16 controls the duty ratio of the gate command signals GpA and GnA for the switches S1A and S2A, and converts the input voltage into a target voltage. Further, in the master 10, the controller 16 controls the duty ratio of the gate command signal GsA to the switch S3A so that the detected transition time TaA becomes the target transition time Tr, thereby realizing the optimum ZVS of the switch S1A. .

  The target transition time Tr is a target value of the transition time that minimizes the auxiliary current IL2A and realizes optimal ZVS control. When 1/4 of the resonance period τr has elapsed from the start of resonance between the capacitors C1A and C2A and the auxiliary reactor L2A, all the energy stored in the auxiliary reactor L2A is transferred to the capacitors C1A and C2A, and the potential at the connection point Po. Rises to V1. Therefore, theoretically, if the target transition time Tr is ¼ of the resonance period τr, the loss of the master 10 can be minimized. In consideration of the delay of the transition time detector 17 and the switches S1A and S2A, etc., the target transition time Tr may be set to a value near ¼ of the resonance period τr. As a result of the simulation of the loss of the master 10 with respect to the transition time, when the target transition time Tr is in the range of 1/8 to 4/13 of the resonance period τr, the loss is increased as compared with the case where the loss is the lowest. It was found that it can be suppressed to about 10%. Therefore, the target transition time Tr is preferably set within a range of 1/8 to 4/13 of the resonance period τr. The target transition time Tr of the master 10 and the slave 20 is the same value.

  On the other hand, in the slave 20, the controller 26 generates gate command signals GpB and GnB for the switches S1B and S2B based on the gate command signal GpA for the switch S1A observed by the time observer 29, and sets the input voltage to the target voltage. Convert. Further, in the slave 20, the controller 26 controls the switch S3 from the gate command signal GsA for the switch S3A observed by the time observer 29 to the gate command signal GsB for the switch S3B.

  In order to make the gate command signal GsA and the gate command signal GsB the same signal, the switches S3A and S3B are turned on at the same timing. The increasing and decreasing gradients of the auxiliary currents IL2A and IL2B are determined by the inductance L2 of the auxiliary reactors L2A and L2B. Therefore, if the switches S3A and S3B are turned on at the same timing, the magnitudes of the auxiliary current IL2A and the auxiliary current IL2B become the same. However, variations in the output current between the master 10 and the slave 20 may occur due to variations in the elements of the master 10 and the slave 20. Since the output current is an average current of the reactor currents IL1A and IL2A, when the output current varies, the reactor currents IL1A and IL2A also vary.

  FIG. 13 shows (a) reactor currents IL1A and IL1B, (b) auxiliary currents IL2A and IL2b, (c) inter-terminal voltages Vds1A and Vds2B, and (d) gates when the output current of the slave 20 is smaller than that of the master 10. The time chart of voltage Vgs3A and Vgs3B is shown. In FIG. 13, the thing corresponding to the master 10 is shown by a solid line, and the thing corresponding to the slave 20 is shown by a broken line. 14A to 14D show time charts corresponding to FIGS. 13A to 13D when the output current of the slave 20 is larger than that of the master 10. FIG.

  As shown in the equation (1), the minimum auxiliary current IL2 required for the ZVS control increases as the reactor current IL1 increases. When the optimal ZVS control is realized by the master 10, the auxiliary current IL2A of the master 10 has an optimal magnitude. Under such conditions, when the reactor current IL1B is smaller than the reactor current IL1A and the auxiliary current IL2A and the auxiliary current IL2B are the same, the auxiliary current IL2B is larger than the optimum magnitude. Therefore, as shown in FIG. 13, the inter-terminal voltage Vds1B falls more rapidly than the inter-terminal voltage Vds1A. As a result, the transition time TaB of the slave 20 is shorter than the transition time TaA of the master 10. Since the transition time TaA is controlled to the target transition time Tr, the transition time TaB is shorter than the target transition time Tr, and the slave 20 cannot realize optimal ZVS control.

  Further, in a situation where the optimum ZVS control is realized by the master 10, when the reactor current IL1B is larger than the reactor current IL1A and the auxiliary current IL2A and the auxiliary current IL2B are the same, the auxiliary current IL2B is less than the optimum magnitude. It has become. Therefore, as shown in FIG. 14, the inter-terminal voltage Vds1B falls more gently than the inter-terminal voltage Vds1A. As a result, the transition time TaB of the slave 20 is longer than the transition time TaA of the master 10. Therefore, the transition time TaB is longer than the target transition time Tr, and the slave 20 cannot realize optimal ZVS control.

  Thus, the variation in the output current between the master 10 and the slave 20 appears as a difference in the falling waveforms of the inter-terminal voltages Vds1A and Vds1B. Similarly, the variation in the output current between the master 10 and the slave 20 appears as a difference between rising waveforms of the inter-terminal voltages Vds2A and Vds2B. Therefore, the controller 26 detects an imbalance between the output currents of the master 10 and the slave 20 by observing the difference in the rising waveform or the difference in the falling waveform. Specifically, the controller 26 detects an imbalance in output current from the difference between the transition time TaA of the master 10 and the transition time TaB of the slave 20. Since the transition time TaA of the master 10 is the target transition time Tr, the controller 26 may detect the output current imbalance from the difference between the target transition time Tr and the transition time TaB.

  Furthermore, the controller 26 corrects the ON time of the observed gate command signal GpA so that the transition time TaB becomes the target transition time Tr when the output current imbalance is detected, and the gate command signal GpB is generated. Increasing or decreasing the duty ratio of the gate command signal GpB increases or decreases the output current of the slave 20. Accordingly, the rising waveform and the falling waveform change, and the transition time TaB increases or decreases.

  Next, details of the functions of the controller 16 and the controller 26 will be described with reference to FIG. The controller 16 includes an upper / lower duty ratio calculation unit 161, a voltage deviation calculation unit 162, a voltage controller 163, an upper correction unit 164, a lower correction unit 165, a dead time correction unit 166, a time deviation calculation unit 167, and a transition time controller 168. And the function of the auxiliary duty ratio calculation unit 169.

  The upper and lower duty ratio calculation unit 161 calculates a theoretical value of the duty ratio (time ratio) of the switches S1A and S2A from the detected value of the input voltage V1, the detected value of the output voltage V2, and the target value of the output voltage V2. The voltage deviation calculation unit 162 calculates a voltage deviation between the detected output voltage V2 and the target voltage.

  The voltage controller 163 calculates the correction amount of the calculated duty ratio of the switches S1A and S2A so that the output voltage V2 becomes the target voltage based on the calculated voltage deviation. Specifically, when the detected value of the output voltage V2 is higher than the target value, the correction amount is calculated so as to decrease the theoretical value of the on time of the switch S1A, and the correction amount is increased so as to increase the theoretical value of the on time of the switch S2A. Is calculated. The upper correction unit 164 corrects the correction value calculated by the voltage controller 163 by subtracting the correction amount calculated by the voltage controller 163 from the theoretical value of the ON time of the switch S1A calculated by the vertical duty ratio calculation unit 161. Further, the lower correction unit 165 adds the correction amount calculated by the voltage controller 163 to the theoretical value of the ON time of the switch S2A calculated by the up / down duty ratio calculation unit 161 to correct. Furthermore, the dead time correction unit 166 provides the dead times to the duty ratios of the switches S1A and S2A calculated by the upper correction unit 164 and the lower correction unit 165, and generates gate command signals GpA and GnA that are PWM signals. .

  The time deviation calculation unit 167 calculates a time deviation between the detected transition time TaA and the target transition time Tr. The transition time controller 168 calculates the correction amount of the duty ratio of the switch S3A so that the transition time TaA becomes the target transition time Tr based on the calculated time deviation. Specifically, when the transition time TaA is longer than the target transition time Tr, since the auxiliary current IL2A is too small, the correction amount is calculated so that the ON timing of the switch S3A is advanced and the ON time is lengthened. When the transition time TaA is shorter than the target transition time Tr, since the auxiliary current IL2A is excessive, the on-timing of the switch S3A is delayed and the correction amount is calculated so as to shorten the on-time. The auxiliary duty ratio calculation unit 169 corrects the duty ratio of the switch S3A based on the correction amount calculated by the transition time controller 168, and generates a gate command signal GsA that is a PWM signal. One cycle of ON / OFF of the switch S3A is the same as one cycle of ON / OFF of the switches S1A and S2A.

  The loop from the vertical duty ratio calculation unit 161 to the dead time correction unit 166 is a loop that performs voltage conversion control for converting the input voltage V1 into a target voltage. On the other hand, the loop from the time deviation calculation unit 167 to the auxiliary duty ratio calculation unit 169 is a loop that performs ZVS control. That is, the voltage conversion control and the ZVS control are performed independently. Therefore, ZVS control can be performed at high speed.

  On the other hand, the controller 26 includes a time deviation calculator 261, a current balance controller 262, a gate command corrector 263, an upper on-time calculator 264, a lower on-time calculator 265, a dead time corrector 266, and an auxiliary on-time calculator. 267 and a dead time correction unit 268.

  The time deviation calculation unit 261 calculates a time deviation between the detected transition time TaB and the target transition time Tr. Based on the calculated time deviation, the current balance controller 262 calculates a correction amount for the ON time of the observed gate command signal GpA so that the transition time TaB becomes the target transition time Tr. Specifically, when the transition time TaB is longer than the target transition time Tr, since the output current of the slave 20 is larger than that of the master 10, the correction amount is calculated so as to shorten the on-time. When the transition time TaB is shorter than the target transition time Tr, the output current of the slave 20 is smaller than that of the master 10, so that the correction amount is calculated so as to lengthen the on time.

  The gate command correction unit 263 corrects the gate command signal GpA by subtracting the correction amount calculated by the current balance controller 262 from the ON time of the observed gate command signal GpA. The upper on-time calculating unit 264 calculates the on-time for the switch S1B from the corrected gate command signal GpA. Further, the lower on-time calculation unit 265 calculates the on-time for the switch S2B from the corrected gate command signal GpA. The dead time correction unit 266 generates gate command signals GpB and GnB, which are PWM signals, from the calculated ON times and dead times of the switches S1B and S2B.

  The auxiliary on-time calculating unit 267 calculates the observed on-time of the gate command signal GsA as the on-time of the gate command signal GsB. The dead time correction unit 268 generates a gate command signal GsB that is a PWM signal from the ON time and the dead time of the switch S3B.

  Since the ON time of the gate command signal GpA is corrected according to the time deviation between the transition time TaB and the target transition time Tr, and the switches S1B and S2B are controlled based on the corrected ON time, the master 10 and the slave 20 The output current can be balanced. Further, since the slave 20 also has an auxiliary current IL2B corresponding to the reactor current IL1B, an optimum ZVS can be realized.

  Next, details of the time observer 29 will be described with reference to FIG. The time observer 29 (signal observation unit) observes the ON times of the gate command signals GpA and GsA of the master 10 using the capture function of the microcomputer. Specifically, when detecting the rising event of the gate command signals GpA and GsA, the time observer 29 counts the ON time of the signal every time the clock is detected until the falling event is detected, and acquires the ON time. Further, when the time observer 29 detects the falling event of the gate command signal GpA, the time observer 29 counts the off time of the signal every time the clock is detected and observes the off time. Similarly, the controllers 16 and 26 detect the transition times TaA and TaB by counting the time when the outputs of the transition time detectors 17 and 27 are turned on by using the capture function of the microcomputer.

  Next, a method for starting the slave 20 will be described with reference to FIG. When the master 10 is activated, the controller 26 generates the gate command signals GpB and GnB only when the time observer 29 observes the ON time of the gate command signal GpA longer than the threshold time.

  An unintended surge voltage may be applied to the output from the controller 16 to the time observer 29 while the master 10 is stopped. It is desirable to avoid observing this surge voltage as the ON time of the gate command signal GpA and operating the slave 20. Therefore, the power conversion unit 25 of the slave 20 is activated only when an on-time longer than the threshold time is observed as a threshold time that is longer than a general surge voltage application time.

  As a result, as shown in FIG. 17, even when a surge voltage is applied to the output of the controller 16 at time t00 when the master 10 is stopped, the slave 20 continues to stop. Then, when the master 10 is activated at the time t10 and the on-time longer than the threshold time is observed by the time observer 29, the slave 20 is activated at the time t20 and the gate generated based on the observed on-time. Command signal GpB is output.

  Here, after the power conversion unit 15 of the master 10 is activated at the time t10, an activation command is sent from the controller 16 of the master 10 to the controller 26 of the slave 20 using a communication function such as CAN or I2C. The time when the power conversion unit 25 of the slave 20 is activated is later than the time t20. On the other hand, as described above, by observing the ON time of the gate command signal GpA in real time, the power conversion unit 15 of the master 10 is activated until the power conversion unit 25 of the slave 20 is activated. Delay can be suppressed.

  Next, a method for stopping the slave 20 will be described with reference to FIG. When the power conversion unit 15 is stopped, the controller 26 is observed by the time observer 29 that the off time of the gate command signal GpA is continued during the control period of the controller 16 of the master 10. However, the output of the gate command signals GpB and GnB is stopped. The control cycle of the controller 16 is the control cycle Tm of the microcomputer.

  The control cycle Tm may be longer than the cycle of the gate command signal GpA. For example, when the control cycle Tm is three times the cycle of the gate command signal GpA, the controller 16 transmits the ON pulse of the gate command signal GpA only once every three times. Even in such a case, the power conversion unit of the slave 20 can be detected only when the off time of the gate command signal GpA continues for the control period Tm or more in order to reliably detect the power conversion unit 15 of the master 10 being turned off. 25 was stopped.

  As a result, as shown in FIG. 18, when the power conversion unit 15 of the master 10 stops at time t30 and the off-time is continuously observed by the time observer 29 for the control cycle Tm, at time t40, The power conversion unit 25 of the slave 20 is stopped.

  Here, when the power conversion unit 15 of the master 10 is stopped at the time t30 and then a stop command is sent from the controller 16 of the master 10 to the controller 26 of the slave 20 using a communication function such as CAN or I2C. The time when the power conversion unit 31 of the slave 20 stops is later than the time t40. On the other hand, as described above, by observing the off time of the gate command signal GpA in real time, the power conversion unit 15 of the master 10 stops and the power conversion unit 25 of the slave 20 stops. The delay can be suppressed to the control cycle Tm.

  According to 1st Embodiment described above, there exist the following effects.

  The variation in output current between the master 10 and the slave 20 appears as a difference between rising waveforms of the inter-terminal voltages Vds2A and Vds2B and a difference between falling waveforms of the inter-terminal voltages Vds1A and Vds1B. Therefore, by observing the difference in the rising waveforms of the inter-terminal voltages Vds2A and Vds2B or the difference in the falling waveforms of the inter-terminal voltages Vds1A and Vds1B, it is possible to immediately detect the output current imbalance between the master 10 and the slave 20. it can. Further, since no current sensor or communication device is used, the cost can be reduced.

  When the switch S1 is turned on and the switch S2 is turned off, energy is accumulated in the main reactor L1. When the switch S1 is turned off and the switch S2 is turned on, a current is supplied from the main reactor L1 to the load 80, and the input voltage is converted into a predetermined voltage and output. Further, when the switch S3 is turned on and the switch S2 is turned off, a resonance operation occurs, current flows from the auxiliary resonance circuits 150 and 250 to the capacitors C1 and C2, and the voltage between the terminals of the switch S1 becomes zero. ZVS can be realized.

  In the master 10, the gate command signal GsA is generated so that the detected transition time TaA becomes the target transition time Tr. As a result, the master 10 can turn on the switch S3A at an appropriate timing to realize the optimum ZVS.

  In the slave 20, the gate command signal GpB is generated so that the detected transition time TaB becomes the target transition time Tr in the master 10. By changing the duty ratio of the gate command signal GpB, the output current of the slave 20 increases and decreases, the rising waveform of the inter-terminal voltage Vds2B and the falling waveform of the inter-terminal voltage Vds1B change, and the transition time TaB increases and decreases. Therefore, in the slave 20, the gate command signal GpB is generated so that the detected transition time TaB becomes the target transition time Tr, so that the output currents of the master 10 and the slave 20 can be balanced. Moreover, since the slave 20 also has the auxiliary current IL2B corresponding to the reactor current IL1B, the optimum ZVS can be realized.

  In the master 10, the duty ratios of the gate command signals GpA and GnA are controlled to convert the input voltage into the target voltage, and the duty ratio of the gate command signal GsA is controlled to realize the optimum ZVS. Since the voltage conversion control and the ZVS control are performed independently, the ZVS control can be performed at high speed.

  In the slave 20, the gate command signals GpA and GsA in the master 10 are observed. The ON time of the gate command signal GsA is set to the ON time of the gate command signal GsB. Furthermore, the ON time of the gate command signal GpA is corrected so that the detected value of the detected transition time TaB becomes the target transition time Tr, and the corrected ON time is set to the ON time of the gate command signal GpB. As a result, the output currents of the master 10 and the slave 20 can be balanced, and the optimum ZVS can be realized in the slave 20 as well.

  The gate command signal GpB is generated and output only when the on time of the gate command signal GpA longer than the threshold time is observed in the slave 20. Therefore, when an unintended surge voltage is input to the gate command signal GpA, the power conversion unit 25 of the slave 20 is not activated, and the unintended activation of the power conversion unit 25 can be suppressed.

  On the other hand, when the power conversion unit 15 in the master 10 is activated and the slave 20 observes the ON time of the gate command signal GpA longer than the threshold time, the power conversion unit 25 of the slave 20 is activated. At this time, when an activation command is sent from the master 10 to the slave 20 using a communication function, a delay occurs between the activation of the power conversion unit 15 of the master 10 and the activation of the power conversion unit 25 of the slave 20. . Therefore, current concentrates on the master 10 when the power conversion device is started, and the burden on the master 10 increases. On the other hand, by observing the ON time of the gate command signal GpA in real time, the delay from the activation of the power conversion unit 15 of the master 10 to the activation of the power conversion unit 25 of the slave 20 can be suppressed. As a result, increase of the burden of the master 10 at the time of starting can be suppressed.

  In the slave 20, the output of the gate command signal GpB in the slave 20 is stopped only when the off-time is continuously observed during the controller 16 control period Tm of the master 10. While the power conversion unit 15 of the master 10 is being driven, the power conversion unit 25 of the slave 20 is not stopped because the ON time exists within the control cycle.

  On the other hand, when the power conversion unit 15 of the master 10 is stopped and the off time is continuously observed in the slave 20 during the control period Tm, the power conversion unit 25 of the slave 20 is stopped. At this time, when a stop command is sent from the master 10 to the slave 20 using the communication function, a delay occurs between the stop of the power conversion unit 15 of the master 10 and the stop of the power conversion unit 25 of the slave 20. . Therefore, when the power converter is stopped, the current concentrates on the slave 20 that stops last, and the burden increases. On the other hand, by observing the off time of the gate command signal GpA in real time, the delay from the stop of the power conversion unit 15 of the master 10 to the stop of the power conversion unit 25 of the slave 20 can be suppressed. As a result, increase of the burden of the slave 20 at the time of a stop can be suppressed.

(Second Embodiment)
Next, the power converter according to the second embodiment will be described while referring to differences from the first embodiment. The power conversion apparatus according to the present embodiment includes a master 10A and a slave 20A that are connected in parallel to each other. The configuration of the master 10A is shown in FIG. A power source 80a is connected between the terminals 13 and 14 of the master 10A, and a load 70a is connected between the terminals 11 and 12. The master 10A is a boost converter that boosts the input voltage V2 of the power supply 80a and outputs the boosted voltage to the load 70a.

  The configuration of the auxiliary resonance circuit 150A of the master 10A is different from the configuration of the auxiliary resonance circuit 150 of the master 10. Although the configuration diagram of the slave 20A is omitted, the boost converter is similar to the master 10A, and the configuration of the auxiliary resonance circuit 250A is different from the configuration of the auxiliary resonance circuit 250 of the slave 20.

  The anode terminals of the diodes Ds of the auxiliary resonance circuits 150A and 250A are connected to the first end of the main reactor L1, and the cathode terminal of the diode Ds is connected to the first end of the auxiliary reactor L2. The drain terminal of the switch S3 is connected to the second end of the auxiliary reactor L2. The source terminal of the switch S3 is connected to the second end of the main reactor L1.

  In the master 10A and the slave 20A, the directions of the reactor current IL1 and the auxiliary current IL2 are opposite to those of the master 10 and slave 20, and the roles of the switches S1 and S2 are reversed. That is, the switch S2 becomes a main switch that performs power conversion, and the switch S1 becomes a synchronous rectification switch that performs synchronous rectification. When the switch S2 is in the on state, a current is supplied from the power supply 80a to the main reactor L1. When the switch S1 is in the on state, current is supplied from the main reactor L1 to the load 70a.

  In the present embodiment, when the voltage Vds2 between the terminals of the switch S2, which is the main switch, is 0, ZVS control for turning on the switch S2 is performed. In the present embodiment, the gate voltages Vgs1 and Vgs2 are obtained by inverting (a) and (b) in FIGS. 3 and 4 and the inter-terminal voltages Vds1 and Vds2 are obtained by (d) in FIGS. And (e) are reversed. Therefore, in this embodiment, the on-timing of the switch S3 is controlled based on the rising waveform of the inter-terminal voltage Vds1 or the falling waveform of the inter-terminal voltage Vds2. That is, the transition time TaA, TaB is detected from the start to the end of the inter-terminal voltage Vds1 or from the start to the end of the inter-terminal voltage Vds2.

  According to 2nd Embodiment described above, there exists an effect similar to 1st Embodiment.

(Third embodiment)
Next, the power converter according to the third embodiment will be described while referring to differences from the first embodiment. The power conversion device according to the present embodiment includes a master 10B and a slave 20B that are connected in parallel to each other. The configuration of the master 10B is shown in FIG. A power source 70b or a load 70b is connected between the terminals 11 and 12 of the master 10B, and a load 80b or a power source 80b is connected between the terminals 13 and 14. The master 10B is a bidirectional converter that performs a step-down operation that steps down the input voltage V1 of the power supply 70b and outputs it to the load 80b, and performs a step-up operation that steps up the input voltage V2 of the power supply 80b and outputs it to the load 70b. .

  In the master 10B, the configuration of the auxiliary resonance circuit 150B is different from the configuration of the auxiliary resonance circuit 150 of the master 10. Although the configuration diagram of the slave 20B is omitted, it is a bidirectional converter similar to the master 10B, and the configuration of the auxiliary resonance circuit 250B is different from the configuration of the auxiliary resonance circuit 250 of the slave 20.

  The auxiliary resonance circuits 150B and 250B are composed of two switches S3 and S4 and an auxiliary reactor L2, and a switch S4 is connected instead of the diode Ds. The switch S4 has a drain terminal connected to the second end of the auxiliary reactor L2, and a source terminal connected to the second end of the main reactor L1. That is, the auxiliary resonance circuits 150B and 250B are the switch S3 or the switch S4 whose auxiliary element is an auxiliary switch.

  When the master 10B and the slave 20B perform step-down operation, the switch S1 serves as a main switch, the switch S2 serves as a synchronous rectification switch, and the switch S3 serves as an auxiliary switch. When the master 10B and the slave 20B perform a boosting operation, the switch S2 serves as a main switch, the switch S1 serves as a synchronous rectification switch, and the switch S4 serves as an auxiliary switch. The controllers 16 and 26 have a step-down function and a step-up function, and perform step-down control or step-up control by switching as appropriate.

  According to 3rd Embodiment described above, there exists an effect similar to 1st Embodiment.

(Fourth embodiment)
Next, the power converter according to the fourth embodiment will be described while referring to differences from the first embodiment. The power conversion apparatus according to the present embodiment includes a master 10C and a slave 20C connected in parallel to each other. The configuration of the master 10C is shown in FIG. The master 10C is a step-down converter similar to the master 10.

  The configuration of the auxiliary resonance circuit 150C of the master 10C is different from the configuration of the auxiliary resonance circuit 150 of the master 10. Although the configuration diagram of the slave 20C is omitted, the configuration of the auxiliary resonance circuit 250C is different from the configuration of the auxiliary resonance circuit 250 of the slave 20. In the auxiliary resonance circuits 150C and 250C, the main reactor L1 and the auxiliary reactor L2 are magnetically coupled to each other. Therefore, the main reactor L1 and the auxiliary reactor L2 can be formed by winding two coils around a common core. In the equivalent circuit of the auxiliary resonance circuits 150C and 250C, the main reactor L1 side is a parallel circuit of the primary winding with the winding number N1 and the exciting inductance component, and the auxiliary reactor L2 side is the secondary winding with the winding number N2 and the leakage inductance. It becomes a series circuit with the component. The primary winding and the secondary winding constitute an ideal transformer, and the leakage inductance component is sufficiently smaller than the excitation inductance component. In this case, resonance operation occurs between the leakage inductance component and the capacitors C1 and C2. Therefore, the inductance L in Formula (1) becomes a leakage inductance value.

  Further, the polarity of the first end of the main reactor L1 and the polarity of the second end of the auxiliary reactor L2 are set to the same polarity. Thereby, the voltage applied to the leakage inductance component can be increased by a value obtained by multiplying the inter-terminal voltage of the excitation inductance component by the turn ratio N2 / N1. Thereby, the time for accumulating magnetic energy in the leakage inductance component can be shortened.

  According to 4th Embodiment described above, while there exists an effect similar to 1st Embodiment, there exist the following effects. Further, the configurations of the master 10C and the slave 20C according to this embodiment may be applied to the second and third embodiments.

  -The core of the main reactor L1 and the auxiliary reactor L2 can be made common, and the physique of the master 10C and the slave 20C can be suppressed.

  -By making the first end of the main reactor L1 and the second end of the auxiliary reactor L2 have the same polarity, the applied voltage of the leakage inductance component can be increased when the switch S3 is in the on state, and the magnetism to the leakage inductance component can be increased. Energy storage time can be shortened.

(Fifth embodiment)
Next, the power converter according to the fifth embodiment will be described while referring to differences from the fourth embodiment. The power conversion device according to the present embodiment includes a master 10D and a slave 20D connected in parallel to each other. The configuration of the master 10D is shown in FIG. Master 10D is a step-down converter similar to master 10C.

  The master 10D is different from the auxiliary resonance circuit 150C of the master 10C in the configuration of the auxiliary resonance circuit 150D. Although the configuration diagram of the slave 20D is omitted, the configuration of the auxiliary resonance circuit 250D is different from the configuration of the auxiliary resonance circuit 250C of the slave 20C. The anode terminals of the diodes D1 of the auxiliary resonance circuits 150D and 250D are connected to the ground potential. The ground potential is the same potential as the low potential side terminals 12 and 14 and the source terminal of the switch S2.

  In the case of the fourth embodiment, the anode potential of the diode D3 connected in antiparallel to the switch S3 is higher than the cathode potential during the period in which the switch S1 is in the on state. For this reason, the diode D3 becomes conductive, and the voltage Vds3 between the terminals of the switch S3 becomes zero. Thereafter, during the period when the switch S2 is in the ON state, the voltage Vds3 between the terminals of the switch S3 is the sum of the output voltage V2 and the voltage between the terminals of the secondary winding.

  On the other hand, in the case of the present embodiment, the voltage Vds3 between the terminals of the switch S3 becomes 0 due to the conduction of the diode D3 during the period when the switch S1 is in the ON state. Thereafter, during a period in which the switch S2 is in the ON state, the voltage between the terminals of the switch S3 is the voltage between the terminals of the secondary winding. Therefore, in the case of the present embodiment, compared to the fourth embodiment, the voltage across the terminals of the switch S3 can be decreased by the output voltage V2.

  The configuration in which the anode terminal of the diode D1 is connected to the ground potential is realized by magnetically coupling the first end of the main reactor L1 and the second end of the auxiliary reactor L2 so as to have the same polarity.

  According to the fifth embodiment described above, the same effects as those of the fourth embodiment can be obtained, and the switch S3 can be reduced in breakdown voltage. As a result, the switch S3 can be reduced in size. Further, the configurations of the master 10D and the slave 20D according to the present embodiment may be applied to the second and third embodiments.

(Sixth embodiment)
Next, the power converter according to the sixth embodiment will be described while referring to differences from the fourth embodiment. The power conversion device according to the present embodiment includes a master 10E and a slave 20E that are connected in parallel to each other. The configuration of the master 10E is shown in FIG. The master 10E is a step-down converter similar to the master 10C.

  The master 10E is different from the auxiliary resonance circuit 150C of the master 10C in the configuration of the auxiliary resonance circuit 150E. Although the configuration diagram of the slave 20E is omitted, the configuration of the auxiliary resonance circuit 250E is different from the configuration of the auxiliary resonance circuit 250C of the slave 20C. The anode terminal of the diode D1 of the auxiliary resonance circuit 15F is connected to the high potential side of the power source 70. That is, the anode terminal of the diode D1 is connected to the high potential side terminal 11 and the drain terminal of the switch S1.

  According to the sixth embodiment, the same effects as those of the fourth embodiment can be obtained, and the voltage across the terminals of the diode Ds can be made lower than that of the fourth embodiment during the ON state of the switch S1. Therefore, the withstand voltage of the diode Ds can be reduced. The configurations of the master 10E and the slave 20E according to this embodiment may be applied to the second and third embodiments.

(Other embodiments)
The inclination of the rising waveform or the falling waveform may be detected as the rising waveform or the falling waveform, and the turn-on timing of the switches S3 and S4 may be controlled based on the inclination. Further, for example, the time until the rising waveform rises to ½ of the threshold value Vth may be detected, and the time may be doubled to be the transition times TaA and TaB.

  The transition time TaA detected by the transition time detector 17 is sent to the time observer 29 (transition observation unit), and the controller 26 uses the transition time TaA observed by the time observer 29 and the transition time detector 27 to An output current imbalance may be detected from a difference from the detected transition time TaB. In this case, the time deviation calculation unit 261 calculates the time deviation using the transition time TaA instead of the target transition time Tr.

  A time observer may be provided on the master side, and the transition time TaB detected on the slave side may be sent to the master time observer. Then, the controller 16 may detect an imbalance in output current from the difference between the transition time TaA and the transition time TaB. In this case, the controller 16 may correct the ON time of the gate command signal GpA based on the time deviation between the transition time TaA and the transition time TaB, and send the corrected gate command signal GpA to the slave side. . The controller 26 can set the ON time of the corrected gate command signal GpA as it is as the ON time of the gate command signal GpB.

  In the power conversion apparatus, one master and a plurality of slaves may be connected in parallel to each other. In this case, the gate command signals GpA and GsA may be sent from the master to each slave in parallel, or may be sent from the master to one slave, and then sequentially sent from the slave to other slaves in series.

  The switches S1 to S3 are not limited to MOSFETs, and other types of switching elements such as IGBTs and bipolar transistors may be used.

  -Each of the main reactor L1 and the auxiliary reactor L2 may be a transformer.

  DESCRIPTION OF SYMBOLS 10 ... Master, 16 ... Controller, 20 ... Slave, 26 ... Controller, 26 ... Controller, 80, 70a, 70b, 80b ... Load, 150, 250 ... Auxiliary resonance circuit, Ds ... Diode, L1 ... Main reactor, L2 ... auxiliary reactor, S1, S2, S3 ... switch.

Claims (8)

A first power supply device serving as a reference, and at least one second power supply device, wherein the first power supply device and the second power supply device are connected in parallel to each other in a load;
The first power supply device and the second power supply device are respectively
A switching circuit comprising a main switch, a synchronous rectification switch, and a main magnetic component, wherein the main switch and the synchronous rectification switch are complementarily turned on and off to convert an input voltage into a predetermined voltage and output the voltage ,
An auxiliary switch and an auxiliary magnetic component, and the auxiliary switch is turned on when either the main switch or the synchronous rectification switch is in an off state, whereby the main switch and the synchronous rectification switch An auxiliary switching circuit that resonates between the capacitance component and the auxiliary magnetic component;
A voltage detection unit that detects a voltage between terminals of the main switch or the synchronous rectification switch,
The first power supply device further includes:
A main signal for complementarily turning on and off the main switch and the synchronous rectification switch of the first power supply device is generated, and the detected rising waveform of the voltage between the terminals of the synchronous rectification switch or the voltage between the terminals of the main switch A first control unit that generates an auxiliary signal for controlling the auxiliary switch of the first power supply device based on the falling waveform of
The second power supply device further includes:
A main signal for complementarily turning on and off the main switch and the rectifying switch of the second power supply device is generated, and an auxiliary signal for controlling the auxiliary switch of the second power supply device is generated as the auxiliary signal in the first power supply device. A power conversion device including a second control unit configured to make the same signal as the signal,
The first control unit or the second control unit observes the difference in the rising waveform or the difference in the falling waveform between the first power supply device and the second power supply device, and thereby detects the difference between the first power supply device and the second power supply device. A power conversion device that detects an imbalance in output current between two power supply devices. The switching circuit includes a main switch having a capacitance component in parallel, a synchronous rectification switch having a capacitance component in parallel and connected in series to the main switch, a first end and a second end as both ends, the main switch, A main magnetic component having the first end connected to a connection point with a synchronous rectification switch,
The auxiliary switching circuit is a circuit connected in parallel to the main magnetic component at the first end of the main magnetic component, and is different from the auxiliary switch, the auxiliary magnetic component, and the auxiliary switch. And an auxiliary element which is an auxiliary switch or a diode,
The main magnetic component is a main reactor,
The power converter according to claim 1, wherein the auxiliary magnetic component is an auxiliary reactor. When the main switch is on, current is supplied from the power source to the main reactor, and when the synchronous rectification switch is on, current is supplied from the main reactor to the load.
The first power supply device and the second power supply device are respectively
A first smoothing capacitor connected between a high potential side terminal and a low potential side terminal of a series body of the main switch and the synchronous rectification switch;
A second smoothing capacitor connected between the second end of the main reactor and the low potential side terminal of the series body;
When the auxiliary switch is in an ON state, it is a partial resonance type circuit that realizes zero-volt switching by flowing a current from the auxiliary switching circuit to a capacitive component provided in parallel with the main switch and the synchronous rectification switch. The power conversion device according to claim 2. The first power supply device and the second power supply device are respectively
Based on the detected voltage between the terminals of the main switch or the synchronous rectification switch, the transition time from the start to the end of the rise of the voltage between the terminals of the synchronous rectification switch or the fall of the voltage between the terminals of the main switch is detected. A transition time detection unit
The first controller is
Generating the auxiliary signal in the first power supply device so that the detected value of the transition time detected by the transition time detection unit of the first power supply device becomes a target value of the transition time;
The second controller is
The main signal in the second power supply device is generated so that a detection value of the transition time detected by the transition time detection unit of the second power supply device becomes the target value. The power converter according to 2 or 3. The first power supply device and the second power supply device are respectively
Transition from the terminal voltage of the main switch or the synchronous rectification switch detected by the voltage detection unit to the rise of the voltage of the terminal of the synchronous rectification switch or the fall of the voltage of the terminal of the main switch from the start to the end It has a transition time detector that detects time,
The second power supply device further includes:
A transition observation unit for observing a detection value of the transition time detected by the transition time detection unit of the first power supply device;
The first controller is
The auxiliary signal is generated so that the detected value of the transition time detected by the transition time detection unit of the first power supply device becomes a target value of the transition time,
The second controller is
The main power supply in the second power supply device is configured such that the detection value of the transition time detected by the transition time detection unit of the second power supply device becomes the detection value of the transition time observed by the transition observation unit. The power converter according to claim 2 or 3, wherein a signal is generated. The second power supply device
A signal observation unit for observing the main signal and the auxiliary signal in the first power supply device;
The first controller is
Controlling the time ratio of the main signal in the first power supply device to convert the input voltage to the target voltage, and controlling the time ratio of the auxiliary signal in the first power supply device to switch the zero voltage of the main switch Carry out the control,
The second controller is
The observed on-time of the auxiliary signal is set as the on-time of the auxiliary signal in the second power supply device, and the detected value of the transition time detected by the transition time detection unit of the second power supply device is: The observed ON time of the main signal is corrected so as to be the target value of the transition time in the first power supply device, and the corrected ON time is set as the ON time of the main signal in the second power supply device. The power conversion device according to claim 4, wherein:   The second control unit generates and outputs the main signal in the second power supply device on condition that the on time of the main signal longer than a threshold time is observed by the signal observation unit. The power converter according to claim 6, wherein   The second power supply unit is configured on the condition that the signal observing unit observes that the off time of the main signal continues during the control period of the first control unit. The power converter according to claim 6 or 7, wherein the output of the main signal in is stopped.

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