JP2017108271A - Bit synchronization circuit and bit synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish bit synchronization of high-speed serial signals that cannot be directly received by an FPGA transceiver.SOLUTION: A bit synchronization circuit 1 comprises: a pattern comparison part 23 for comparing a detection pattern consisting of a plurality of repetitive patterns being present in a high-speed serial signal with parallel data of all multiple lanes including bits of an estimated screw amount in the head in a low-speed serial signal obtained by dividing the high-speed serial signal, for each lane; a temporary leading lane position determination part 24 for determining a lane in which the detection pattern is detected in the head in the order of lanes as a temporary leading lane position based on comparison results; a bit discrimination part 26 for discriminating whether the detection patterns matched at the determined temporary leading pattern position are detected continuously as many as or more than preset times while keeping the order of lanes; and a processing part 28 for calculating a skew amount from a bit position in the case where the temporary leading lane position is discriminated satisfactory, performing deskew and outputting parallel data of a plurality of lanes while rearranging the parallel data in the order of serial bit streams.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a bit synchronization circuit and a bit synchronization method for absorbing a skew generated when a high-speed serial signal is divided into low-speed serial signals of a plurality of lanes and deserialized to establish bit synchronization.

  Conventionally, as an interface device in a multi-channel data transmission system that realizes bit synchronization when performing large-capacity data transmission, for example, one disclosed in Patent Document 1 below is known. In the interface device disclosed in Patent Document 1, a data transmission unit that selectively transmits multi-channel data and a multi-channel reference signal, a bit synchronization unit that performs bit synchronization of multi-channel reception data, and multi-channel reception data And a deskew unit for performing deskewing, enabling a significant reduction in design time, flexibility in layout, and high-density mounting, and realizing a large-capacity router or switch.

JP 2002-223208 A

  However, Patent Document 1 described above has a configuration in which a data transmission unit and a data reception unit are provided in an interface device, and data transmission bit synchronization is completed within a package of the interface device to output data. On the other hand, when a FPGA (field-programmable gate array) transceiver is configured using a CMOS IC as a receiver (receiver circuit) for receiving an external signal, a high-speed serial signal (for example, 32 Gbit / s) is used in the current CMOS technology. The above cannot be received directly. For this reason, if you want to analyze a high-speed serial signal that cannot be received directly by the FPGA transceiver with the FPGA, use a demultiplexer such as MMIC to divide the high-speed serial signal into low-speed serial signals of multiple lanes and handle the bit rate that the FPGA transceiver can handle. It was necessary to drop and connect.

  However, when the bit rate of the high-speed serial signal to be received is high when the high-speed serial signal is divided into a plurality of low-speed serial signals of multiple lanes by reducing the bit rate that can be handled by the FPGA transceiver as a receiver, the timing at which each FPGA transceiver deserializes is aligned. This causes a problem that it is difficult to reduce the bit skew between the FPGA transceivers to zero. When bit skew occurs, it has been considered that the original serial bit string cannot be restored.

  More specifically, the bit skew described above also occurs in each lane of a plurality of low-speed serial signals due to variations in the wiring length of the low-speed serial signal and variations in the clock phase of each receiver. This bit skew has a different value in each lane, and the amount of rotation of the bit position in each lane differs. As a result, a phase shift occurs in the signal output from each receiver. For this reason, in the conventional bit synchronization circuit, the user has appropriately dealt with the phase shift problem by appropriately adjusting the wiring length and clock phase of the low-speed serial signal from the demultiplexer to each receiver. However, with such a coping method, the work is cumbersome and the burden on the user is great, and there are individual differences in the adjustment work, and it takes time and effort to establish bit synchronization of the high-speed serial signal and restore it to the original serial string. It took time.

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a bit synchronization circuit and a bit synchronization method that can establish bit synchronization of a high-speed serial signal without burdening the user. It is said.

In order to achieve the above object, a bit synchronization circuit according to claim 1 of the present invention includes a demultiplexer 12 that divides a high-speed serial signal into low-speed serial signals of a plurality of lanes, and a plurality of lanes divided by the demultiplexer. A bit synchronization circuit 1 used in a receiving device 11 including a plurality of receivers 14 for converting a low-speed serial signal into parallel data,
A pattern comparison unit 23 that compares, for each lane, a detection pattern composed of a plurality of repetitive patterns existing in the bit string of the high-speed serial signal and parallel data of all the plurality of lanes starting from a bit of an assumed skew amount;
Based on the comparison result of the pattern comparison unit, it is determined whether or not the detection pattern is detected in the order of lanes, and the tentative lane position determination unit 24 determines the lane in which the detection pattern is detected at the head as the tentative head lane position. When,
The number of detection times of the detection pattern that coincides with the temporary head pattern position determined by the temporary head lane position determination unit is counted, and the temporary pattern is determined depending on whether the detection pattern is detected continuously for a set number of times or more while maintaining the lane order. A determination unit 26 for determining the quality of the first lane position;
A process of calculating a skew amount from a bit position when the determination unit determines that the temporary head lane position is good, performing a deskew, and rearranging parallel data of a plurality of lanes input from the receiver in order of a serial bit string and outputting the data And a unit 28.

The bit synchronization method according to claim 2 is a bit synchronization method that divides a high-speed serial signal into low-speed serial signals of a plurality of lanes and takes bit synchronization by using parallel data of the divided low-speed serial signals of the plurality of lanes as an input. There,
Comparing a detection pattern consisting of a plurality of repetitive patterns present in the bit string of the high-speed serial signal with parallel data of all the plurality of lanes starting from a bit of an assumed skew amount for each lane;
Determining whether or not the detection pattern is detected in lane order based on the result of the comparison, and determining the lane that has detected the detection pattern at the head as a temporary head lane position;
Counts the number of detection times of the detected pattern that matches at the determined temporary head pattern position, and determines whether the temporary head pattern position is good or not based on whether or not the detection pattern is detected continuously for a set number of times or more while maintaining the lane order. And steps to
And a step of calculating a skew amount from a bit position when the provisional head lane position is determined to be good, performing deskew, and rearranging the parallel data of the plurality of lanes in the order of serial bit strings and outputting them.

  According to the present invention, even when a high-speed serial signal cannot be directly received by the FPGA transceiver, the skew generated when the high-speed serial signal is divided into a plurality of low-speed serial signals of multiple lanes and deserialized without any burden on the user. Can be absorbed to establish bit synchronization.

It is a block diagram which shows an example of the internal structure of the bit synchronous circuit which concerns on this invention. It is a block diagram which shows schematic structure of the receiver containing the bit synchronous circuit which concerns on this invention. It is explanatory drawing which shows an example of the bit interleaving and lane division | segmentation of a detection pattern. FIG. 4 is a schematic explanatory diagram when a head lane position is determined using the detection pattern of FIG. 3.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

  The present invention divides, for example, a high-speed serial signal from a device under test (DUT) such as a PCIe device or a USB device accompanying input of a known pattern signal (test signal) into low-speed serial signals of a plurality of lanes. The present invention relates to a bit synchronization circuit and a bit synchronization method for establishing bit synchronization by absorbing (de-skew) skew in or between lanes generated when deserializing a lane low-speed serial signal and converting it into parallel data.

  As shown in FIGS. 1 and 2, the bit synchronization circuit 1 is incorporated as a part of the reception device 11 together with the demultiplexer 12, the clock generator 13, and the receiver 14.

  Although not particularly shown, the receiving apparatus 11 includes an error rate measuring apparatus together with a pattern generator that transmits a pattern signal (a known pattern based on a PRBS pattern or a programmable pattern) to a device under test (DUT) such as a PCIe device or a USB device. Configure. When the error rate measuring device inputs a known pattern signal from the pattern generator to the device under test as a test signal, the receiving device receives the signal (high-speed serial signal) from the device under test when the test signal is input. The bit error rate is measured by comparing the received signal with a known test signal.

  For example, the demultiplexer 12 can process a high-speed serial signal (for example, 32 Gbit / s) input from a device under test such as a PCIe device or a USB device in a plurality of lanes (for example, 4 Gbit / s) that can be handled by the subsequent receiver 14. Divide into 8 low-speed serial signals (DMUX).

  Note that the demultiplexer 12 of this example is illustrated as a single-stage configuration for the sake of simplicity, but can be appropriately configured with the number of stages according to the bit rate of the input high-speed serial signal. For example, in the case of dividing a 32 Gbit / s high-speed serial signal, the demultiplexer 12 has a two-stage configuration and is separated in stages from 32 Gbit / s → 16 Gbit / s → 4 Gbit / s. Further, the input high-speed serial signal is not limited to the signal from the device under test, and is intended for a bit rate signal that cannot be directly received by the receiver 14.

  The clock generator 13 generates a reference clock for the receiver 14 to capture the low-speed serial signal divided by the demultiplexer 12 and inputs the generated reference clock to the receiver 14.

  The receiver 14 is a receiving circuit composed of an FPGA transceiver using a CMOS IC, and a plurality of receivers 14 are provided corresponding to the number of low-speed serial signal lanes divided by the demultiplexer 12. Specifically, as shown in FIG. 2, when the high-speed serial signal is divided into eight-lane low-speed serial signals by the demultiplexer 12, a total of eight receivers 14 (14A, 14B) are provided, one for each lane. , 14C, 14D, 14E, 14F, 14G, 14H).

  The receiver 14 includes a CDR (Clock Data Recovery) 14a, a deserializer 14b, and a frequency divider 14c. In FIG. 2, the CDR 14a and the deserializer 14b are shown only in the receiver 14A, but all the receivers 14A to 14H include the CDR 14a, the deserializer 14b, and the frequency divider 14c.

  The CDR 14 a refers to the reference clock from the clock generator 13 and regenerates the clock signal from the low-speed serial signal input from the demultiplexer 12. The deserializer 14b receives the low-speed serial signal divided by the demultiplexer 12 at the timing of the clock signal (reproduced clock) from the CDR 14a, and the clock signal obtained by dividing the clock signal reproduced by the CDR 14a by the divider 14c. At this timing, the low-speed serial signal is deserialized, converted into parallel data, and output. As a result, 8-lane parallel data deserialized by each receiver 14 is input to the bit synchronization circuit 1.

  As shown in FIGS. 1 and 2, the bit synchronization circuit 1 has an input side connected to a plurality of receivers 14 (14 </ b> A to 14 </ b> H) in order to realize the above-described function of establishing bit synchronization, and a clock domain separation unit 21, The detection pattern generation unit 22, the pattern comparison unit 23, the provisional head lane position determination unit 24, the first delay unit 25, the determination unit 26, the second delay unit 27, and the processing unit 28 are configured by the FPGA.

  The clock domain separation unit 21 is connected to the input side and the output side of the pattern comparison unit 23, and includes a FIFO for adjusting the clock cycle. The clock domain separation unit 21 has a function of separating the clock domains because the pattern comparison unit 23 operates with another clock (4 × speed clock: clk × 4).

  The detection pattern generator 22 generates a detection pattern for comparison with the data to be compared (lanes 0 to 7) based on the parallel data from the receiver 14 in the pattern comparator 23. In order to synchronize with the high-speed serial signal received by the receiving device 11, the detection pattern is composed of a plurality of types of patterns having different bit arrangements based on the repetitive pattern existing in the bit string of the high-speed serial signal.

  More specifically, the detection pattern generation unit 22 of this example generates a plurality of types of detection patterns with a fixed value determined by the standard with the connection partner as a set value. For example, in the PCIe standard mode (Gen1, Gen2, Gen3, Gen4), 160 bits of 5 types (4 types for Gen1 and Gen2, 1 type for Gen3 and Gen4) are set values. Then, the detection pattern generation unit 22 selects a set value according to the mode, and assigns the selected set value to the pattern 0 → pattern 1 → pattern 2 →... → pattern 6 → pattern 7 in order of 1 bit from the MSB side. This is repeated to generate a detection pattern.

  Specifically, in the case of PCIe Gen3, as shown in FIG. 3, pt0 is pattern 0, pt1 is pattern 1, pt2 is pattern 3, pt4 is pattern 4, pt5 is pattern 5, pt6 is pattern 6, and pt7 is As in pattern 7, the setting value is assigned to the pattern 0 → pattern 1 → pattern 2 →... → pattern 6 → pattern 7 in order from the MSB (pt0) side of the set value, and this is repeated and eight types of different bit arrangements are repeated. Generate a detection pattern. In FIG. 3, the vertical axis represents the types of detection patterns (patterns 0 to 7) divided by bit interleaving, and the horizontal axis represents the bit position of one frame of each detection pattern.

  In this way, the detection pattern generation unit 22 bit-interleaves 160 bits of a repetitive pattern (set value according to the PCIe mode) present in the bit string of the high-speed serial signal into 8 lanes, for example, as shown in FIG. Eight types of patterns (pattern 0, pattern 1, pattern 2, pattern 3, pattern 4, pattern 5, pattern 6, pattern 7) are generated as detection patterns. Therefore, the detection patterns differ in the contents (bit arrangement) of the patterns 0 to 7 for each type of set value.

  In addition, a detection pattern switches and uses several types (combination of the patterns 0-7) according to a connection other party. Further, as shown in FIG. 3, the detection pattern is extended to 20 bits to improve accuracy, but is not limited to this bit length.

  The pattern comparison unit 23 is provided corresponding to the number of receivers 14, in other words, the number of lanes of parallel data. In this example, since eight receivers 14A to 14H are provided to output 8-lane parallel data, eight pattern comparison units 23 are provided corresponding to the respective receivers 14A to 14H.

  The pattern comparison unit 23 uses the parallel data taking into account the amount of skew that is expected to occur in the lane as the data to be compared, and compares the data to be compared with the detection pattern for each lane of the plurality of lanes. Output the result. In this example, the assumed skew amount is ± 8 bits (+8: 8 ways, ± 0: 1 ways, −8: 8 ways, 17 ways in total), and parallel data in the entire range of ± 8 bits is compared. Data.

  The pattern comparison unit 23 inputs the input data bus (16-bit width) from the corresponding receiver 14 to the three-stage shift register, connects the data of the three stages, and the skew amount in the lane (assumed skew amount ± 8) In order to deal with the difference due to (bit), data to be compared is generated by shifting the bit position (± 8 bits).

  The pattern comparison unit 23 compares the created data for comparison with all the detection patterns (patterns 0 to 7) in FIG. 3 and performs this comparison operation for each lane.

  For example, paying attention to pattern 0 in FIG. 3, all detection patterns (patterns 0 to 7) are compared with 17 types of data to be compared. The detection pattern (patterns 0 to 7) and the comparison data (17 patterns) are compared for each lane of a plurality of lanes. As a result, the pattern comparison unit 23 outputs 17 patterns × 8 patterns × 8 lanes = 1088 comparison results as a whole.

  The temporary head lane position determination unit 24 determines whether a necessary detection pattern is detected in the order of lanes based on the comparison result input from each pattern comparison unit 23, and detects the detection pattern necessary for the head. Is determined as the temporary top lane position.

  The necessary detection pattern means a combination in which the detection pattern patterns 0 to 7 are arranged in order. For example, when lane 1 is regarded as the head, pattern 0 to pattern 7 are arranged in lane order, such as pattern 0 for lane 1, pattern 1 for the next lane 2, and pattern 2 for the next lane 3. It is.

  As shown in A of FIG. 4, the temporary head lane position determination unit 24 determines Lane 0 as the temporary head lane position when detecting patterns 0 to 7 starting from Lane 0. Similarly, as shown in FIG. 4B, when patterns 0 to 7 are detected starting from lane 1, lane 1 is determined as the temporary head lane position. As shown in FIG. 4C, when patterns 0 to 7 are detected starting from lane 2, lane 2 is determined as the temporary head lane position. As shown in FIG. 4D, when patterns 0 to 7 are detected with lane 3 at the head, lane 3 is determined as a temporary head lane position. As shown in E of FIG. 4, when patterns 0 to 7 are detected starting from lane 4, lane 4 is determined as a temporary head lane position. As shown in F of FIG. 4, when patterns 0 to 7 are detected starting from lane 5, lane 5 is determined as a temporary head lane position. As shown in G of FIG. 4, when patterns 0 to 7 are detected starting from lane 6, lane 6 is determined as a temporary head lane position. As shown in FIG. 4H, when patterns 0 to 7 are detected starting from lane 7, lane 7 is determined as the temporary head lane position.

  In FIG. 4, the transition from lane 7 to lane 0 is illustrated in an expanded form so as to be easily understood. However, in practice, lane 0 → lane 1 →... → lane 6 → lane 7 → lane 0 is repeated. .

  In this way, the temporary head lane position determination unit 24 detects a combination in which patterns 0 to 7 are arranged in order starting from a certain lane (a combination starting from each lane: eight patterns A to H in FIG. 4), When this combination is detected, the lane is determined as the temporary head lane position, and temporary head lane position data (including positional shift information indicating how many bits are shifted in the lane) is output to the determination unit 26.

  The first delay unit 25 delays the comparison result from the pattern comparison unit 23, and compares the phase of the delayed comparison result with the temporary head lane position data from the temporary head lane position determination unit 24 to the determination unit 26. Match.

  Here, since the detection pattern length (160 bits) is not equal to the number of lanes (8 lanes) × 1 lane bit width (16 bits), the lane position and the bit position where the detection pattern 160 bits exist have periodicity. Moving. For this reason, the determination unit 26 calculates the lane position and the bit position where the detection pattern is generated, and determines whether or not the detection pattern is continuously detected for the set number of times or more at the calculated lane position and bit position. At this time, since the appearance frequency varies depending on the length of the pattern, the number of times of the pattern is set so that the number of times is large (for example, 10 times) for a short pattern and the number of times for a long pattern (for example, 8 times). It is set as appropriate according to the length.

  That is, the determination unit 26 predicts the movement destination of the detection pattern (the lane position where the detection pattern exists and the movement destination of the bit position) based on the temporary head pattern position data from the temporary head lane position determination unit 24, and the position Count the number of detections of matching patterns (number of matches) in, and determine whether the bit at the temporary head lane position is good or not based on whether or not matching is detected continuously while maintaining the lane order. . Then, when the detection unit 26 detects a detection pattern that matches at the temporary head lane position continuously while maintaining the lane order and satisfies the pattern detection condition, the determination unit 26 determines the lane determined as the temporary head pattern position. The head pattern position is determined, and the confirmed head pattern position data (including position shift information indicating how many bits are shifted in the lane) is output to the processing unit 28 as a determination result. Further, the determination unit 26 outputs the count value for each bit position when the detection pattern is continuously detected to the processing unit 28 as a determination result.

  The second delay unit 27 delays input data from each receiver 14 (parallel data in lanes 0 to 7), and the phase between the delayed input data and the determination result from the determination unit 26 to the processing unit 28. Adjust.

  When the determined head pattern position data is input from the determination unit 26, the processing unit 28 calculates a skew amount (intra-lane and inter-lane skew amounts: vertical and horizontal skew amounts in FIG. 3) from the bit position. Then, the deskew of the parallel data in lanes 0 to 7 is performed according to the calculated skew amount, and the deskewed parallel data is rearranged in the serial bit string order (the bit string order of the high-speed serial signal) and output. As a result, the processing unit 28 outputs serial data that is bit-synchronized with the high-speed serial signal.

  Next, a bit synchronization method for a high-speed serial signal using the above-described bit synchronization circuit 1 will be described. Here, an example will be described in which a high-speed serial signal is converted into an 8-lane low-speed serial signal by a demultiplexer, and the 8-lane low-speed serial signal is converted into parallel data (16 bits) by eight receivers 14. .

  In the bit synchronization circuit 1, when parallel data is input from each receiver 14, each pattern comparison unit 23 compares the detection pattern with the data to be compared. For example, in the pattern comparison unit 23 corresponding to lane 0, the parallel data from the receiver 14 is bit-shifted to generate 17 kinds of data to be compared of ± 8 bits, and the 17 kinds of data to be compared and the detected data are detected. The patterns (patterns 0 to 7) are compared, and all of them that match are found. The pattern comparison unit 23 corresponding to each of the other lanes 1 to 7 performs the same processing in parallel.

  Next, the temporary head lane position determination unit 24 acquires all the comparison results of 8 lanes from the pattern comparison unit 23, and determines whether the detection pattern is detected in the lane order based on the acquired comparison results. The lane where the head of the detection pattern exists is set as the temporary head lane position. At this time, the order of detection is, in lane units, lane 0 → lane 1 → ... → lane 6 → lane 7 → lane 0 → lane 1 → ..., but the lane where the head of the detection pattern exists Depends on startup. For this reason, the detection pattern (pattern 0) is not always detected in lane 0. It may also be found at multiple locations.

  After determining the temporary head lane position by the temporary head lane position determination unit 24, the determination unit 26 counts the number of detection pattern matches from the comparison result of the pattern comparison unit 23 thereafter. Here, since the number of synchronization bits of the pattern included in the input data is different from the number of bits for 8 lanes per clock (16 bits × 8 lanes = 128 bits), the pattern to be detected moves with periodicity.

  Therefore, the determination unit 26 predicts the movement destination of the detection pattern and counts the number of detections of the detection pattern that matches at that position. And it is discriminate | determined whether the detection which corresponds continuously over the setting frequency | count is observed, keeping a lane order. If the determination unit 26 detects that the lane order is maintained and matches continuously for a set number of times or more, the determination unit 26 determines that the lane determined as the temporary head pattern position is the determined head pattern position, and uses the determined head pattern position data as the determination result. The data is output to the processing unit 28.

  If the processing unit 28 determines that the temporary leading lane position is good from the determination result of the determination unit 26, the processing unit 28 performs deskewing of parallel data of a plurality of lanes input from the receiver 14 based on the skew amount when the pattern detection condition is satisfied. The parallel data of a plurality of lanes are rearranged in the order of serial bit strings and output. When the processing unit 28 determines that the temporary head lane position is defective, the processing unit 28 outputs a signal for clearing the temporary head lane position of the temporary head lane position determination unit 24 and the determination unit 26. By this clearing, the periodicity is checked again at the next lane position, and the determination unit 26 restarts the determination of the temporary head lane position.

  As described above, according to the bit synchronization circuit 1 of the present embodiment, the high-speed serial signal is divided into the low-speed serial signals of a plurality of lanes by the demultiplexer 12, and the repetitive pattern existing in the high-speed serial bit string is used as the detection pattern. The bit skew generated between the receivers (FPGA transceivers) 14 is estimated and deskewed, and the original serial bit string is restored to establish bit synchronization. As a result, even for high-speed serial signals that cannot be directly connected to the receiver (FPGA transceiver), the conventional adjustment of the wiring length and clock phase by the user is unnecessary, and the high-speed serial signal is not burdened to the user at all. Bit synchronization can be established by absorbing the skew in the lanes or between lanes that occurs when the signal is divided into a plurality of low-speed serial signals and deserialized. In addition, by performing bit skew estimation simultaneously for all bits, it is possible to establish deskew and bit synchronization at high speed.

  Although the best mode of the bit synchronization circuit and the bit synchronization method according to the present invention has been described above, the present invention is not limited to the description and drawings according to this mode. That is, it is a matter of course that all other forms, examples, operation techniques, and the like made by those skilled in the art based on this form are included in the scope of the present invention.

1 bit synchronization circuit 11 receiver 12 demultiplexer 13 clock generator 14 (14A to 14H) receiver 14a CDR
14b Deserializer 14c Frequency divider 21 Clock domain separation unit 22 Detection pattern generation unit 23 Pattern comparison unit 24 Temporary head lane position determination unit 25 First delay unit 26 Judgment unit 27 Second delay unit 28 Processing unit

Claims (2)

Reception including a demultiplexer (12) that divides the high-speed serial signal into low-speed serial signals of a plurality of lanes, and a plurality of receivers (14) that convert the low-speed serial signals of the plurality of lanes divided by the demultiplexer into parallel data. A bit synchronization circuit (1) used in the device (11),
A pattern comparison unit (23) for comparing, for each lane, a detection pattern composed of a plurality of repetitive patterns present in the bit string of the high-speed serial signal and parallel data of all the plurality of lanes starting from a bit of an assumed skew amount. When,
Based on the comparison result of the pattern comparison unit, it is determined whether or not the detection pattern is detected in lane order, and a tentative head lane position determination unit (determining a lane in which the detection pattern is detected at the head as a temporary head lane position) 24)
The number of detection times of the detection pattern that coincides with the temporary head pattern position determined by the temporary head lane position determination unit is counted, and the temporary pattern is determined depending on whether the detection pattern is detected continuously for a set number of times or more while maintaining the lane order. A determination unit (26) for determining the quality of the first lane position;
A process of calculating a skew amount from a bit position when the determination unit determines that the temporary head lane position is good, performing a deskew, and rearranging parallel data of a plurality of lanes input from the receiver in order of a serial bit string and outputting the data And a bit synchronization circuit. A bit synchronization method that divides a high-speed serial signal into low-speed serial signals of a plurality of lanes and takes bit synchronization using parallel data of the divided low-speed serial signals of the plurality of lanes as an input,
Comparing a detection pattern consisting of a plurality of repetitive patterns present in the bit string of the high-speed serial signal with parallel data of all the plurality of lanes starting from a bit of an assumed skew amount for each lane;
Determining whether or not the detection pattern is detected in lane order based on the result of the comparison, and determining the lane that has detected the detection pattern at the head as a temporary head lane position;
Counts the number of detection times of the detected pattern that matches at the determined temporary head pattern position, and determines whether the temporary head pattern position is good or not based on whether or not the detection pattern is detected continuously for a set number of times or more while maintaining the lane order. And steps to
A step of calculating a skew amount from a bit position when the provisional head lane position is determined to be good, performing deskew, and rearranging the parallel data of the plurality of lanes in the order of serial bit strings and outputting the bit. Synchronization method.

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