JP2017098950A - Frequency Synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of reducing time required to lock a frequency or a phase of a signal output from an oscillation section, of suppressing an idle tone even when the signal output from the oscillation section has a fluctuation at the time of locking thereof, and of effectively attenuating frequency components increasing phase noise of the oscillation section with a simple configuration.SOLUTION: A frequency synthesizer comprises: an oscillation section generating a first signal; a frequency ratio measurement section measuring a frequency ratio between the first signal and a second signal by using the first signal and the second signal; a comparison section comparing the frequency ratio measured by the frequency ratio measurement section with a target value of the frequency ratio; and a filter disposed before the comparison section. The frequency synthesizer adjusts a frequency of the first signal of the oscillation section based on comparison results of the comparison section.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a frequency synthesizer.

  A frequency synthesizer having a PLL (Phase Locked Loop) that locks the phase of a signal and an FLL (Frequency Locked Loop) that locks the frequency of the signal is known.

  Patent Document 1 discloses an FLL configuration for suppressing periodic quantization noise called an idle tone. In Patent Document 1, a clock signal output from a voltage controlled oscillator is input to a frequency delta sigma modulator (FDSM) to obtain a delta sigma modulated signal. This delta-sigma modulation signal is input to the comparison unit. Then, an idle tone having a phase opposite to that of the idle tone included in the delta sigma modulation signal when the frequency of the clock signal is locked is generated and input to the comparison unit, and the comparison unit includes the idle tone. Cancel the idle tone.

  Further, Patent Document 2 discloses a PLL configuration that uses a free-run counter and an accumulator, and enables locking of the phase as well as locking of the frequency of the clock signal.

  In the devices described in Patent Documents 1 and 2, the time required to lock the frequency and phase of the clock signal can be reduced.

US Pat. No. 6,690,215 US Pat. No. 7,592,874

  However, in the apparatus described in Patent Document 1, the anti-phase idle tone is generated assuming the clock signal that is an output when the frequency of the clock signal is locked. The amplitude and frequency of the anti-phase idle tone are generated. The component does not include fluctuation. For this reason, fluctuations in the amplitude and frequency components of the idle tone included in the delta sigma modulation signal when the clock signal fluctuates cannot be handled, and the idle tone included in the delta sigma modulation signal cannot be canceled. That is, there is a problem that two independent idle tones appear in the output, resulting in an increase in idle tones.

  The device described in Patent Document 2 has the same problem as the device described in Patent Document 1 except that the phase of the clock signal can be locked.

  An object of the present invention is to reduce the time required to lock the frequency or phase of a signal output from an oscillating unit with a simple configuration, and when the signal output from the oscillating unit at the time of locking has fluctuations However, it is an object of the present invention to provide a frequency synthesizer that can suppress idle tones and can effectively attenuate frequency components that increase the phase noise of an oscillation unit.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

The frequency synthesizer of the present invention includes an oscillation unit that generates a first signal,
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed in front of the comparison unit,
The frequency of the first signal of the oscillation unit is adjusted based on a comparison result of the comparison unit.

  As a result, the frequency of the first signal output from the oscillation unit can be locked with a simple configuration, and the time required for the locking can be reduced.

  In addition, since the configuration does not generate an idle tone of opposite phase (quantization noise caused by the idle tone), even when the first signal at the time of the lock is fluctuated, the steady-state characteristic is deteriorated as in the conventional example. No. That is, the idle tone does not increase even when the first signal at the time of locking has fluctuation.

  Moreover, the frequency component which increases the phase noise of an oscillation part can be effectively attenuated by a filter.

  In addition, the difference between the frequency ratio measured by the frequency ratio measurement unit and the target value of the frequency ratio can be obtained by the comparison unit, but the filter is arranged in front of the comparison unit. A signal in which the noise component is removed from the output signal and the SN ratio (signal noise ratio) is improved is input to the comparison unit. The bit width of the input signal to the comparison unit becomes larger than the bit width of the output signal of the frequency ratio measurement unit due to processing by the filter, so the bit width expressing the target value when comparing in the comparison unit is increased. Can be made. For this reason, adjustment resolution can be improved without devising, for example, providing a gain unit for multiplying the output signal of the frequency ratio measurement unit by a predetermined value relative to the comparison unit.

The frequency synthesizer of the present invention includes an oscillation unit that generates a first signal,
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed after the comparison unit,
The frequency of the first signal of the oscillation unit is adjusted based on a comparison result of the comparison unit.

  As a result, the frequency of the first signal output from the oscillation unit can be locked with a simple configuration, and the time required for the locking can be reduced.

  In addition, since the configuration does not generate an idle tone of opposite phase (quantization noise caused by the idle tone), even when the first signal at the time of the lock is fluctuated, the steady-state characteristic is deteriorated as in the conventional example. No. That is, the idle tone does not increase even when the first signal at the time of locking has fluctuation.

  Moreover, the frequency component which increases the phase noise of an oscillation part can be effectively attenuated by a filter. And since the filter is arrange | positioned after the comparison part, the frequency component which increases the phase noise of the oscillation part containing the quantization noise component etc. which arise in a comparison part can be attenuate | damped effectively.

  In addition, the difference between the frequency ratio measured by the frequency ratio measuring unit and the target value of the frequency ratio can be obtained by the comparison unit, but since the quantization error is large, the number of expression bits at the time of calculation can be suppressed.

In the frequency synthesizer of the present invention, an integration unit is provided between the comparison unit and the oscillation unit,
It is preferable that the phase of the first signal of the oscillation unit is adjusted based on a comparison result of the comparison unit.

  As a result, the phase of the first signal output from the oscillation unit can be locked with a simple configuration, and the time required for the locking can be reduced.

The frequency synthesizer of the present invention includes an oscillation unit that generates a first signal,
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed in front of the comparison unit;
A control amount calculation unit for obtaining a control amount of the oscillation unit based on a comparison result of the comparison unit; and
The control amount calculation unit is a first circuit unit that outputs the comparison result of the comparison unit multiplied by a predetermined value, and
A second circuit unit group composed of a plurality of second circuit units that perform different predetermined number of integrations on the comparison result of the comparison unit;
A third circuit unit group composed of a plurality of third circuit units that perform different predetermined number of differentiations on the comparison result of the comparison unit, and at least two different circuit units selected from the third circuit unit group,
At least one of the frequency and phase of the first signal of the oscillation unit is adjusted based on the control amount obtained by the control amount calculation unit.

  Accordingly, at least one of the frequency and phase of the first signal output from the oscillating unit can be locked with a simple configuration, and the time required for the locking can be reduced.

  In addition, since a plurality of types of circuit units are provided, the gain adjustment range is widened, and stability, transient characteristics, steady characteristics, and the like can be improved.

  In addition, since the configuration does not generate an idle tone of opposite phase (quantization noise caused by the idle tone), even when the first signal at the time of the lock is fluctuated, the steady-state characteristic is deteriorated as in the conventional example. No. That is, the idle tone does not increase even when the first signal at the time of locking has fluctuation.

  Moreover, the frequency component which increases the phase noise of an oscillation part can be effectively attenuated by a filter.

  In addition, the difference between the frequency ratio measured by the frequency ratio measurement unit and the target value of the frequency ratio can be obtained by the comparison unit, but the filter is arranged in front of the comparison unit. A signal in which the noise component is removed from the output signal and the SN ratio (signal noise ratio) is improved is input to the comparison unit. The bit width of the input signal to the comparison unit becomes larger than the bit width of the output signal of the frequency ratio measurement unit due to processing by the filter, so the bit width expressing the target value when comparing in the comparison unit is increased. Can be made. For this reason, adjustment resolution can be improved without devising, for example, providing a gain unit for multiplying the output signal of the frequency ratio measurement unit by a predetermined value relative to the comparison unit.

The frequency synthesizer of the present invention includes an oscillation unit that generates a first signal,
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed after the comparison unit;
A control amount calculation unit for obtaining a control amount of the oscillation unit based on a comparison result of the comparison unit; and
The control amount calculation unit is a first circuit unit that outputs the comparison result of the comparison unit multiplied by a predetermined value, and
A second circuit unit group composed of a plurality of second circuit units that perform different predetermined number of integrations on the comparison result of the comparison unit;
A third circuit unit group composed of a plurality of third circuit units that perform different predetermined number of differentiations on the comparison result of the comparison unit, and at least two different circuit units selected from the third circuit unit group,
At least one of the frequency and phase of the first signal of the oscillation unit is adjusted based on the control amount obtained by the control amount calculation unit.

  Accordingly, at least one of the frequency and phase of the first signal output from the oscillating unit can be locked with a simple configuration, and the time required for the locking can be reduced.

  In addition, since a plurality of types of circuit units are provided, the gain adjustment range is widened, and stability, transient characteristics, steady characteristics, and the like can be improved.

  In addition, since the configuration does not generate an idle tone of opposite phase (quantization noise caused by the idle tone), even when the first signal at the time of the lock is fluctuated, the steady-state characteristic is deteriorated as in the conventional example. No. That is, the idle tone does not increase even when the first signal at the time of locking has fluctuation.

  Moreover, the frequency component which increases the phase noise of an oscillation part can be effectively attenuated by a filter. And since the filter is arrange | positioned after the comparison part, the frequency component which increases the phase noise of the oscillation part containing the quantization noise component etc. which arise in a comparison part can be attenuate | damped effectively.

  In addition, the difference between the frequency ratio measured by the frequency ratio measuring unit and the target value of the frequency ratio can be obtained by the comparison unit, but since the quantization error is large, the number of expression bits at the time of calculation can be suppressed.

  In the frequency synthesizer of the present invention, it is preferable that the filter is disposed after the control amount calculation unit.

  Thereby, until processing is performed with the filter, the calculation is performed in a state where the quantization error is large, but the number of expression bits at the time of the calculation can be suppressed, so by arranging the filter after the control amount calculation unit, The scale of the arithmetic circuit up to the control amount calculation unit can be reduced.

  Further, since the filter is disposed after the control amount calculation unit, it is possible to effectively attenuate frequency components that increase the phase noise of the oscillation unit such as quantization noise components generated in the comparison unit.

  In the frequency synthesizer of the present invention, it is preferable that the comparison unit performs signal processing using a signed binary number expression.

  As a result, negative values can be handled, whereby the number and size of circuit elements can be reduced.

In the frequency synthesizer according to the aspect of the invention, it is preferable that the frequency ratio measurement unit includes a frequency delta sigma modulation unit that performs frequency delta sigma modulation on one of the first signal and the second signal.
Thereby, a highly accurate frequency ratio measurement can be performed with a simple configuration.

In the frequency synthesizer of the present invention, it is preferable that the frequency delta sigma modulation unit outputs an output signal in a bit stream format.
Thereby, the signal processing circuit can be simplified.

  In the frequency synthesizer of the present invention, it is preferable that the frequency delta sigma modulator outputs an output signal in a data stream format.

  As a result, the dynamic range of the comparison unit can be expanded, so that it is possible to cope with a large frequency fluctuation.

  In the frequency synthesizer of the present invention, it is preferable that the frequency ratio measurement unit includes a plurality of the frequency delta sigma modulation units connected in parallel.

  Thereby, idle tones can be further reduced. When the number of frequency delta-sigma modulation units is n (n is an arbitrary natural number equal to or greater than 2), for example, the idle tone can be reduced to about 1 / n1 / 2.

  In the frequency synthesizer according to the aspect of the invention, the frequency ratio measurement unit may include the plurality of frequency delta sigma modulation units for at least one of the first signal and the second signal input to the plurality of frequency delta sigma modulation units. It is preferable to have a phase adjustment unit that shifts the phase between them.

  Thereby, idle tones can be further reduced. When the number of frequency delta-sigma modulation units is n (n is an arbitrary natural number of 2 or more), for example, idle tones can be reduced to about 1 / n.

  In the frequency synthesizer of the present invention, it is preferable that the oscillation unit includes a digital-analog converter that converts a digital signal into an analog signal, and a voltage-controlled oscillator.

  Thereby, the adjustment of the oscillation frequency of the voltage controlled oscillator can be digitized, and the consistency with the digital signal processing up to the previous stage of the digital-analog converter is good.

In the frequency synthesizer of the present invention, the oscillating unit preferably includes a digitally controlled oscillator.
Thereby, a stable output can be obtained even with respect to environmental changes such as temperature changes.

It is a block diagram which shows 1st Embodiment of the frequency synthesizer of this invention. FIG. 2 is a block diagram illustrating a configuration example of an FDSM of the frequency synthesizer illustrated in FIG. 1. FIG. 2 is a block diagram illustrating a configuration example of an FDSM of the frequency synthesizer illustrated in FIG. 1. It is a block diagram which shows 2nd Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows 3rd Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the comparator of the frequency synthesizer shown in FIG. It is a block diagram which shows 4th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows 5th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the frequency ratio measurement part of the frequency synthesizer shown in FIG. It is a timing chart which shows an example of output reference signal Fcj and output clock signal Fxj. It is a timing chart which shows an example of output data OUTj. It is explanatory drawing which shows advance of the period of the output clock signal Fxj. It is a block diagram of the apparatus which parallelized FDSM simply. It is a timing chart of the apparatus shown in FIG. It is a block diagram which shows an example of a phase adjustment part. It is a block diagram which shows an example of a phase adjustment part. It is a block diagram which shows an example of a phase adjustment part. It is a block diagram which shows an example of a phase adjustment part. It is a block diagram which shows the structural example of the frequency ratio measurement part in case the frequency fx of the clock signal Fx is higher than the frequency fc of the reference signal Fc. It is a timing chart of the frequency ratio measurement part shown in FIG. It is a block diagram which shows the structural example of the frequency ratio measurement part in case the frequency fc of the reference signal Fc is higher than the frequency fx of the clock signal Fx. It is a timing chart which shows an example of output reference signal Fcj and output clock signal Fxj. 6 is a timing chart illustrating an example of output data OUTj of FDSM (j). It is a timing chart of the frequency ratio measurement part shown in FIG. It is a timing chart of the apparatus shown in FIG. 13 which deleted the phase adjustment part from the frequency ratio measurement part shown in FIG. It is a block diagram which shows the frequency ratio measurement part in 6th Embodiment of the frequency synthesizer of this invention. It is a timing chart which shows an example of output reference signal Fcj and output clock signal Fxj. 6 is a timing chart illustrating an example of output data OUTj of FDSM (j). 24 is a timing chart when n = 4 in the frequency ratio measurement unit shown in FIG. It is a timing chart of the apparatus which deleted the phase adjustment part from the frequency ratio measurement part shown in FIG. It is a timing chart which shows an example of output reference signal Fcj and output clock signal Fxj. 6 is a timing chart illustrating an example of output data OUTj of FDSM (j). 24 is a timing chart when n = 4 in the frequency ratio measurement unit shown in FIG. It is a timing chart of the apparatus which deleted the phase adjustment part from the frequency ratio measurement part shown in FIG. It is a block diagram which shows 7th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the control amount calculation part of the frequency synthesizer shown in FIG. It is a block diagram which shows the control amount calculation part in 8th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the control amount calculation part in 9th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the controlled variable calculation part in 10th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the control amount calculation part in 11th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the control amount calculation part in 12th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows the control amount calculation part in 13th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows 14th Embodiment of the frequency synthesizer of this invention. It is a block diagram which shows 15th Embodiment of the frequency synthesizer of this invention.

  Hereinafter, a frequency synthesizer of the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of the frequency synthesizer of the present invention. FIG. 2 is a block diagram showing a configuration example of the FDSM of the frequency synthesizer shown in FIG. FIG. 3 is a block diagram showing a configuration example of the FDSM of the frequency synthesizer shown in FIG.
As shown in FIG. 1, a frequency synthesizer 1 includes a frequency delta sigma modulation unit (hereinafter referred to as “FDSM (Frequency Delta Sigma Modulator)”) 11 that is an example of a frequency ratio measurement unit (frequency modulation unit), and a loop filter. (Filter) 12, comparator (comparator) 13, gain unit 16 with gain set to k0, integrator 71, DA converter (digital-analog converter) 14, and voltage controlled oscillator (VCO) 15. The FDSM 11, the loop filter 12, the comparator 13, the gain unit 16, the integration unit 71, the DA converter 14, and the voltage controlled oscillator 15 are connected in this order toward the output side. The value of the gain k0 of the gain unit 16 is not particularly limited, and is appropriately set according to various conditions.

  The DA converter 14 and the voltage controlled oscillator 15 constitute an oscillation unit that generates a clock signal (first signal). With such a configuration, the frequency synthesizer 1 can digitize the adjustment of the oscillation frequency of the voltage controlled oscillator 15 and has good consistency with the digital signal processing up to the preceding stage of the DA converter 14.

The loop filter 12 is disposed in front of the comparator 13, that is, between the FDSM 11 and the comparator 13. The loop filter 12 is not particularly limited, and for example, a low-pass filter or a lag / lead filter can be used.
Further, in the present embodiment, the integration unit 71 includes an adder 72 and a latch 73, and is arranged at the subsequent stage of the gain unit 16. The integration unit 71 latches the current data and the previous latch before the current data. The adder 72 adds the data latched in the register 73.

  The FDSM 11 is a circuit that performs frequency delta-sigma modulation on one of the clock signal (first signal) and the reference signal (second signal) output from the voltage-controlled oscillator 15. Using the reference signal, the frequency ratio between the clock signal and the reference signal is measured. In the present embodiment, a case where a clock signal is frequency delta-sigma modulated using a reference signal will be described as an example. In the case of frequency delta-sigma modulation of the reference signal using the clock signal, the description is omitted because the reference signal and the clock signal may be replaced in the description to be described later.

  As the FDSM 11, for example, an FDSM that outputs an output signal in a bit stream format (hereinafter also referred to as “bit stream configuration FDSM (bit stream type FDSM)”), an FDSM that outputs an output signal in a data stream format (hereinafter, “ FDSM having a data stream configuration (also referred to as “data stream type FDSM”) can be used.

  When an FDSM having a bit stream configuration is used, the signal processing circuit can be simplified. Further, when the FDSM having the data stream configuration is used, the dynamic range of the comparator 13 can be expanded, so that it is possible to cope with a case where the frequency fluctuation is large.

  Next, the FDSM 11 having the data stream structure and the FDSM 11 having the bit stream structure will be described. First, the FDSM 11 having the data stream structure will be described.

  As shown in FIG. 2, the FDSM 11 having a data stream configuration includes an up counter 21 that counts rising edges of a clock signal and outputs count data Dc indicating a count value, and count data Dc in synchronization with the rising edge of a reference signal. The first latch 22 that outputs the first data D1, the second latch 23 that latches the first data D1 in synchronization with the rising edge of the reference signal and outputs the second data D2, and the first data And a subtractor 24 that subtracts the second data D2 from D1 to generate output data OUT. The first latch 22 and the second latch 23 are composed of, for example, a D flip-flop circuit.

  In this example, the FDSM 11 is also called a primary frequency delta sigma modulator, which latches the count value of the clock signal twice by the output reference signal, and sequentially holds the count value of the clock signal using the rising edge of the reference signal as a trigger. To do. In this example, it is assumed that the latch operation is performed at the rising edge, but the latch operation may be performed at both the falling edge or the rising / falling edge. Further, the subtractor 24 calculates the difference between the two count values that are held, and outputs the increment of the count value of the clock signal that is observed while the reference signal transitions for one cycle without any dead time. When the frequency of the clock signal is fx and the frequency of the reference signal is fc, the frequency ratio is fx / fc. The FDSM 11 outputs the frequency ratio as a digital signal sequence.

  This digital signal sequence is called a data sequence / data stream. A digital signal sequence represented by 1 bit, which will be described later, is called a bit sequence / bit stream.

Next, the FDSM 11 having a bit stream configuration will be described.
As shown in FIG. 3, the FDSM 11 having the bit stream configuration is synchronized with the rising edge of the reference signal and the first latch 22 that latches the clock signal in synchronization with the rising edge of the reference signal and outputs the first data d1. A second latch 23 that latches the first data d1 and outputs the second data d2, and an exclusive OR that generates the output data OUT by calculating the exclusive OR of the first data d1 and the second data d2. Circuit 25. The first latch 22 and the second latch 23 are composed of, for example, a D flip-flop circuit.

  This FDSM 11 is different from the FDSM 11 having the data stream configuration. In the FDSM 11 having the data stream configuration, the count data Dc is held by the first latch 22, and the clock signal observed while the reference signal transitions for one cycle. While the increment of the count data Dc obtained by counting the rising edges is output as the output data OUT, in the FDSM 11, the high or low state of the clock signal is held by the first latch 22, and the reference signal is one cycle. The point is that the even / odd number of inversions during the transition is output as the output data OUT (0 if the number of inversions is even, and 1 if it is odd).

  By the way, since one cycle of the clock signal is composed of two inversion transitions of High and Low, the degree of change that the variation of the clock signal with respect to the reference signal exerts on the output data OUT is counted in the FDSM 11 of the data stream configuration. This is twice that of holding the value. Therefore, the behavior of the idle tone in the FDSM 11 having the bit stream configuration is the same as the behavior when the clock signal having a double frequency is input to the FDSM 11 in the FDSM 11 having the data stream configuration. The operation of the FDSM 11 having the bit stream configuration may be considered by replacing the frequency fx of the clock signal with the frequency 2fx as necessary in consideration of the above-described properties.

Next, the operation of the frequency synthesizer 1 will be described.
As shown in FIG. 1, the reference signal (second signal) and the clock signal (first signal) output from the voltage controlled oscillator 15 are input to the FDSM 11 of the frequency synthesizer 1, and the FDSM 11 described above. Predetermined processing is performed.

  The signal indicating the frequency output from the FDSM 11 is subjected to predetermined processing by the loop filter 12 and input to the comparator 13. For example, when a low-pass filter is used as the loop filter 12, the loop filter 12 blocks or reduces frequency components that are equal to or higher than a predetermined cutoff frequency. Further, a signal indicating a target value of the frequency ratio is input to the comparator 13, and the comparator 13 receives the target value and the signal output from the loop filter 12 (strictly speaking, in the gain unit 132. The frequency ratio indicated by the signal multiplied by k) is compared.

  The difference signal of the frequency ratio indicating the difference (frequency ratio deviation) between the target value, which is the comparison result of the comparator 13, and the frequency ratio indicated by the signal output from the FDSM 11 is multiplied by k0 by the gain unit 16, and the integration unit The digital signal is integrated by 71, converted from a digital signal to an analog signal by the DA converter 14, and input to the voltage controlled oscillator 15 as a control voltage signal (control voltage) of the voltage controlled oscillator 15. As a result, the oscillation frequency of the voltage controlled oscillator 15, that is, the frequency of the clock signal output from the voltage controlled oscillator 15, is adjusted and converged (locked) to the target value.

  As described above, according to the frequency synthesizer 1, the frequency of the clock signal output from the voltage controlled oscillator 15 can be locked with a simple configuration.

  Further, by using the FDSM 11, highly accurate frequency ratio measurement can be performed with a simple configuration, and the time required for the lock can be reduced.

  In addition, since the anti-phase idle tone (quantization noise caused by the idle tone) is not generated, the steady-state characteristic is not deteriorated even when the clock signal at the time of the lock is fluctuated. That is, it is possible to suppress idle tones even when there is fluctuation in the clock signal at the time of locking.

  Further, although a fractional spurious is generated in a fractional type PLL, the frequency synthesizer 1 has a configuration in which the fractional spurious is not generated, whereby a highly accurate frequency synthesizer can be realized.

  Further, since the signal to be processed is a digital signal up to the front of the DA converter 14, it is resistant to noise, and thereby high accuracy is obtained.

  Further, the frequency component that increases the phase noise of the voltage controlled oscillator 15 can be effectively attenuated by the loop filter 12.

  Further, the difference between the frequency ratio measured by the FDSM 11 by the comparator 13 and the target value of the frequency ratio can be obtained. However, since the loop filter 12 is arranged in front of the comparator 13, A signal whose noise ratio is removed from the output signal and whose SN ratio (signal-to-noise ratio) is improved is input to the comparator 13. Since the bit width of the input signal to the comparator 13 becomes larger than the bit width of the output signal of the FDSM 11 by the processing in the loop filter 12, the bit width representing the target value when the comparator 13 compares is set. Can be increased. For this reason, the adjustment resolution can be increased without devising the comparator 13 such as providing a gain unit for multiplying the output signal of the FDSM 11 by a predetermined value.

  The DA converter 14 and the voltage controlled oscillator 15 may be changed to a digitally controlled oscillator (DCO) that controls the oscillation frequency with a digital signal. Similarly, in each of the following embodiments, any combination of a DA converter and a voltage controlled oscillator and a digitally controlled oscillator may be used.

  Further, the FDSM 11 may be changed to the frequency ratio measuring unit 5 described in the fifth embodiment to be described later or the frequency ratio measuring unit 5 described in the sixth embodiment. Similarly, in each of the following embodiments, the bit stream configuration FDSM, the data stream configuration FDSM, the frequency ratio measurement unit 5 described in the fifth embodiment, and the frequency ratio measurement unit 5 described in the sixth embodiment Any of these may be used.

  In addition to the loop filter 12, another loop filter may be provided at another position, for example, between the comparator 13 and the gain unit 16, between the gain unit 16 and the DA converter 14, and the like. . Similarly, in each of the following embodiments, in addition to the loop filter 12, another loop filter may be provided at another position.

  Further, the comparator 13 may be configured to perform signal processing with a signed binary representation. The same applies to the following embodiments.

Second Embodiment
FIG. 4 is a block diagram showing a second embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the second embodiment will be described with a focus on the differences from the first embodiment described above, and the description of the same matters will be omitted.

  As shown in FIG. 4, the frequency synthesizer 1 of the second embodiment is an example of an FDSM 11, a loop filter 12, a comparator 13, an integrator 31, a gain unit 16, an integrator 71, and an oscillator. And a digitally controlled oscillator (DCO) 17 that controls the oscillation frequency with a digital signal. The FDSM 11, the loop filter 12, the comparator 13, the integrating unit 31, the gain unit 16, the integrating unit 71, and the digitally controlled oscillator 17 are connected in this order toward the output side.

  By using the digitally controlled oscillator 17 as the oscillating unit, it is possible to obtain a stable output against environmental changes such as temperature changes.

  The integrating unit 31 has a function of integrating the input frequency and converting it into a phase. In this embodiment, the integration unit 31 includes an adder 32 and a latch 33. The integration unit 31 is disposed between the comparator 13 and the gain unit 16 (digitally controlled oscillator 17). The adder 32 adds the data latched in the latch 33 immediately before the current data.

  By providing the integration unit 31, the frequency synthesizer has a PLL function.

  Thereby, the difference signal of the frequency ratio indicating the difference between the target value which is the comparison result of the comparator 13 and the frequency ratio indicated by the signal output from the loop filter 12 is converted into a signal indicating the phase difference by the integrating unit 31. Then, it is multiplied by k0 by the gain unit 16, integrated by the integration unit 71, and input to the digital control oscillator 17 as a digital control signal of the digital control oscillator 17. Thereby, the oscillation frequency of the digitally controlled oscillator 17, that is, the phase and frequency of the clock signal output from the digitally controlled oscillator 17 is adjusted, the phase converges to a predetermined value, and the frequency converges to the target value.

  According to the second embodiment as described above, the same effect as that of the first embodiment described above can be exhibited.

  In addition, the phase of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.

  In addition, since all the signals to be processed are digital signals, they are strong against noise, thereby obtaining high accuracy.

<Third Embodiment>
FIG. 5 is a block diagram showing a third embodiment of the frequency synthesizer of the present invention. FIG. 6 is a block diagram showing a comparator of the frequency synthesizer shown in FIG.

  Hereinafter, the third embodiment will be described with a focus on differences from the first embodiment described above, and descriptions of the same matters will be omitted.

  As shown in FIG. 5, the frequency synthesizer 1 of the third embodiment includes an FDSM 11, a comparator 13, a loop filter 12, a gain unit 16, an integration unit 71, a DA converter 14, and a voltage controlled oscillator 15. And have. The FDSM 11, the comparator 13, the loop filter 12, the gain unit 16, the integration unit 71, the DA converter 14, and the voltage control oscillator 15 are connected in this order toward the output side.

  Thus, in the present embodiment, the loop filter 12 is provided after the comparator 13, that is, between the comparator 13 and the voltage controlled oscillator 15, more specifically between the comparator 13 and the gain unit 16. Has been placed.

  As shown in FIG. 6, the comparator 13 includes a gain unit 132 whose gain is set to k and a subtracter 131. The value of the gain k of the gain unit 132 is not particularly limited, and is set as appropriate according to various conditions.

  The signal (FDSM output) output from the FDSM 11 is multiplied by k by the gain unit 132 and input to the subtracter 131. Therefore, the comparator 13 compares the target value of the frequency ratio with the frequency ratio indicated by the signal output from the FDSM 11 and multiplied by k by the gain unit 132. Further, the comparator 13 is configured to perform signal processing with a signed binary number expression.

  According to the third embodiment as described above, the same effects as those of the above-described first embodiment can be exhibited except for the effects due to the position of the loop filter 12.

  Further, since the loop filter 12 is arranged after the comparator 13, it can effectively attenuate the frequency component that increases the phase noise of the voltage controlled oscillator 15 including the quantization noise component and the like generated in the comparator 13. it can.

  Moreover, although the difference between the frequency ratio measured by the FDSM 11 and the target value of the frequency ratio is obtained by the comparator 13, the quantization error is large, so that the number of expression bits at the time of calculation can be suppressed.

  Further, by adopting a signed binary number expression, it is possible to handle negative values, thereby reducing the number and size of circuit elements.

<Fourth embodiment>
FIG. 7 is a block diagram showing a fourth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the fourth embodiment will be described with a focus on differences from the second embodiment and the third embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 7, the frequency synthesizer 1 of the fourth embodiment includes an FDSM 11, a comparator 13, a loop filter 12, an integrating unit 31, a gain unit 16 whose gain is set to k0, and an integrating unit 71. And a digitally controlled oscillator 17. The FDSM 11, the comparator 13, the loop filter 12, the integrating unit 31, the gain unit 16, the integrating unit 71, and the digitally controlled oscillator 17 are connected in this order toward the output side.

  The comparator 13 is the same as the comparator 13 of the third embodiment, and the comparator 13 is configured to perform signal processing with a signed binary number expression.

  According to the fourth embodiment as described above, the same effects as those of the second and third embodiments described above can be exhibited.

<Fifth Embodiment>
FIG. 8 is a block diagram showing a fifth embodiment of the frequency synthesizer of the present invention. FIG. 9 is a block diagram showing a frequency ratio measuring unit of the frequency synthesizer shown in FIG.

  Hereinafter, the fifth embodiment will be described with a focus on differences from the first embodiment described above, and descriptions of similar matters will be omitted.

  As shown in FIG. 8, the frequency synthesizer 1 of the fifth embodiment includes a frequency ratio measurement unit 5, a loop filter 12, a comparator 13, a gain unit 16, an integration unit 71, a DA converter 14, And a voltage controlled oscillator 15. The frequency ratio measuring unit 5, the loop filter 12, the comparator 13, the gain unit 16, the integrating unit 71, the DA converter 14, and the voltage controlled oscillator 15 are connected in this order toward the output side. ing.

  As shown in FIG. 9, the frequency ratio measurement unit 5 includes a phase adjustment unit 10, a plurality of FDSM (Frequency Delta Sigma Modulator) 11 connected in parallel (parallelized), and an adder 30. ing. The phase adjustment unit 10, each FDSM 11, and the adder 30 are connected in this order toward the output side. The FDSM 11 is an FDSM having a data stream configuration, and the same FDSM 11 as that described in the first embodiment can be used.

Hereinafter, the frequency ratio measuring unit 5 will be described in detail.
<1-1: Overall configuration>
FIG. 9 shows a block diagram of the frequency ratio measuring unit 5 in the fifth embodiment. As shown in this figure, the frequency ratio measuring unit 5 adjusts the phase of at least one of the clock signal Fx and the reference signal Fc, so that n (n is a natural number of 2 or more) sets of output clock signals Fx1 to Fxn and The phase adjustment unit 10 outputs the output reference signals Fc1 to Fcn, n FDSM (1) to FDSM (n) connected in parallel, and an adder 30.

  The j-th FDSM (j) (j is an arbitrary natural number between 1 and n) generates output data OUTj by frequency delta-sigma modulation of the output clock signal Fxj using the output reference signal Fcj. The adder 30 adds the output data OUT1 to OUTn to generate the frequency delta sigma modulation signal Y.

  The FDSM (j) counts rising edges of the output clock signal Fxj and outputs count data Dc indicating the count value, and latches the count data Dc in synchronization with the rising edges of the output reference signal Fcj. A first latch 22 that outputs the first data D1, a second latch 23 that latches the first data D1 in synchronization with the rising edge of the output reference signal Fcj and outputs the second data D2, and A subtractor 24 that subtracts the second data D2 from the first data D1 to generate output data OUTj. The first latch 22 and the second latch 23 are composed of, for example, a D flip-flop circuit. Note that FDSM (1) to FDSM (j-1) and FDSM (j + 1) to FDSM (n) are configured in the same manner as FDSM (j).

  The FDSM (j) in this example is also called a primary frequency delta sigma modulator, and the count value of the output clock signal Fxj is latched twice by the output reference signal Fcj, and triggered by the rising edge of the output reference signal Fcj The count value of the output clock signal Fxj is sequentially held. In this example, it is assumed that the latch operation is performed at the rising edge, but the latch operation may be performed at the falling edge. Further, the subtractor 24 calculates the difference between the two count values that are held, so that the increment of the count value of the output clock signal Fxj observed during the transition of the output reference signal Fcj for one cycle can be eliminated without the dead time. Output. When the frequency of the clock signal Fx is fx and the frequency of the reference signal Fc is fc, the frequency ratio is fx / fc. FDSM (j) outputs a frequency ratio as a digital signal sequence. The output data OUTj output from FDSM (j) includes a quantization error.

<1-2: Relationship between frequency delta-sigma modulation and idle tone>
Next, the relationship between frequency delta-sigma modulation and idle tone will be described. A signal (47.619047 kHz) having a period of 21 μS is considered as the clock signal Fx. Further, consider a signal (15.15 kHz) having a period of 66 μS as the reference signal Fc. This corresponds to the case where the frequency fx of the clock signal Fx is higher than the frequency fc of the reference signal Fc. The ratio between fx and fc is given by:
fx: fc = 1 / 21e-6: 1 / 66e-6 = 22: 7

  In this case, the time of 22 cycles of the clock signal Fx is equal to the time of 7 cycles of the reference signal Fc. That is, the same data string is repeated every 21 μS × 22 = 66 μS × 7 = 462 μS.

  Considering the operation of FDSM (j) at this time, the output clock signal Fxj advances by 22/7 period = 3 + 1/7 period while the output reference signal Fcj advances by one period, and the count value is 3 or 4 Only increase. Accordingly, 3 or 4 is output from the subtracter 24 as time elapses. When these relationships are represented by the case where the rising edges of the output reference signal Fcj and the output clock signal Fxj coincide with each other, the starting point is shown in FIG. FIG. 10 also shows that the rising edges coincide again after 462 μS from the moment when the rising edges of the output reference signal Fcj and the output clock signal Fxj coincide. In general, even when the rising edge of the output reference signal Fcj and the output clock signal Fxj do not coincide with each other, the pulse train corresponding to the phase shift is repeated in a cycle of 462 μS, but here it is simple. Therefore, the case where the starting point is the moment when the rising edges of the output reference signal Fcj and the output clock signal Fxj coincide is shown.

  In the data string of the actual output data OUTj of FDSM (j), a repetitive pattern “34333333” appears in a cycle of 462 μS as shown in FIG. In addition, since the outputs of the first latch 22 and the second latch 23 at the start of the operation of the FDSM (j) in FIG. 9 are indefinite, FIG. 11 shows a repeating pattern of the next second round in which the first 462 μS cycle is completed. Show. This repetitive pattern of the 462 μS cycle is easy to understand considering the progress of the cycle of the output clock signal Fxj shown in FIG. In the case of this example, the output clock signal Fxj advances by 3 + 1/7 period while the output reference signal Fcj advances for the first period. However, when attention is paid to the fourth period of the output clock signal Fxj, the third period of the output clock signal Fxj is noticed. It means that it has advanced by 1/7 period from the end. Such a non-integer appears because the frequency ratio or period ratio between the output clock signal Fxj and the output reference signal Fcj is not in an integer relationship, so that 1/7 period from the end of the third period of the output clock signal Fxj. The point advanced by this becomes the starting point of the phase of the output clock signal Fxj in the second period of the output reference signal Fcj. Then, at the end of the second period of the output reference signal Fcj, the output clock signal Fxj is advanced by 6 + 2/7 periods from the beginning. In view of this, every time the output reference signal Fcj advances seven cycles, the non-integer number of transitions is 0 (when the rising edge of the output clock signal Fxj and the output reference signal Fcj do not coincide with each other, The non-integer corresponding to the phase shift). Regardless of the level of the output clock signal Fxj, the noise caused by the frequency component of such a periodic repeating pattern is an idle tone.

  The idle tone is generated inside the FDSM (j) due to a quantization error based on the phase relationship between the output reference signal Fcj and the output clock signal Fxj. If there is no idle tone, the change in the output data OUTj of FDSM (j) represents the fluctuation or fluctuation of the output clock signal Fxj with respect to the output reference signal Fcj. The output data OUTj when there is no fluctuation or fluctuation in the signal Fxj can be regarded as a direct current when the influence of the idle tone is ignored. In other words, the change in the output data OUTj appears with the influence of the idle tone superimposed on the fluctuation of the output clock signal Fxj with respect to the output reference signal Fcj. The idle tone can be eliminated or reduced by filtering the output data OUTj of FDSM (j).

  However, the performance of the filter is limited, and if the frequency fx or variation of the output clock signal Fxj is unknown, there is a problem that the filter specification cannot be determined. Further, the fluctuation of the output clock signal Fxj with respect to the output reference signal Fcj in the filter rejection range and detection of fluctuation components are also prevented. Therefore, suppression of idle tone itself is an important issue in high-accuracy measurement using FDSM.

  Next, an idle tone when FDSMs are connected in parallel will be considered. FIG. 13 shows an example in which four FDSM (1) to FDSM (4) are simply parallelized and the output data OUT1 to OUT4 are added. This apparatus deletes the phase adjustment unit 10 from the frequency ratio measurement unit 5 shown in FIG. 9 and directly supplies the clock signal Fx and the reference signal Fc to the four FDSM (1) to FDSM (4).

  Here, when the clock signal Fx is the output clock signal Fxj shown in FIG. 10 and the reference signal Fc is the same as the output reference signal Fcj shown in FIG. 10, the timing chart of the apparatus shown in FIG. 13 is as shown in FIG. It becomes. Comparing FIG. 14 with FIG. 11, even if four FDSM (1) to FDSM (4) are parallelized, the repetition pattern of “3433333” of one FDSM (j) shown in FIG. It turns out that it has only changed to "12 12 12 12 12". That is, since the intensity of the frequency delta-sigma modulation signal Y is quadrupled but the quantization error is also quadrupled, the SN ratios (signal-to-noise ratio) of “3436333” and “12 16 12 12 12 12 12” are the same. I can say that. That is, it means that the influence of the idle tone that appears is not changed by simply connecting FDSMs in parallel. This is because, as is apparent from FIG. 14, the phase relationship of the idle tone is matched between the outputs of FDSM (1) to FDSM (4). Therefore, not only 4 parallel but also 5, 6, 7.

  Obviously, the phase of such an idle tone is determined by the phase relationship between two signals input to the FDSM. In addition, in order to disperse the phase relationship of idle tones among n parallel FDSM outputs, the relative positions of repeated patterns appearing in each single FDSM output constituting n parallels may be shifted, and for this purpose, the output input to each FDSM It is necessary to disperse the relative phase relationship between the parallel inputs of the clock signal and the output reference signal.

<1-3: Phase adjustment unit>
In the present embodiment, the phase adjustment unit 10 relatively adjusts the phases of the clock signal Fx and the reference signal Fc so that the phases of the idle tones of the output data OUT1 to OUTn are all different, and n sets of output clocks Signals and output reference signals (Fx1, Fc1), (Fx2, Fc2),... (Fxn, Fcn) are generated.

  Here, as shown in FIG. 15A, the phase adjustment unit 10 sequentially delays the clock signal Fx by the delay circuits DLx1 to DLxn-1 to generate the output clock signals Fx1 to Fxn, and the reference signal Fc to the delay circuits DLc1 to DLc1. Output reference signals Fc1 to Fcn are generated sequentially delayed by DLcn-1. Alternatively, as shown in FIG. 15B, in the phase adjustment unit 10, the clock signals Fx are sequentially delayed by the delay circuits DLx1 to DLxn-1 to generate the output clock signals Fx1 to Fxn, and the reference signal Fc is not delayed. The output reference signals Fc1 to Fcn may be used. Further, as shown in FIG. 15C, the phase adjustment unit 10 generates the output clock signals Fx1 to Fxn without delaying the clock signal Fx, and sequentially delays the reference signal Fc by the delay circuits DLc1 to DLcn-1. The output reference signals Fc1 to Fcn may be generated. Further, as shown in FIG. 15D, the phase adjustment unit 10 adjusts the phase so as to provide the maximum phase difference by wiring and inputting the delay signals in the increasing order of the delay amount applied to the clock signal Fx and the reference signal Fc. The unit 10 may be configured. Each delay circuit is not particularly limited. For example, an inverter or the like can be used.

<1-4: Determination of Delay Amount and How to Apply Delay to Signal>
Next, how to determine the delay amount and how to apply a delay to the signal will be described. As described above, the output data OUTj when the output clock signal Fxj and the output reference signal Fcj are respectively input to the FDSM (j) is a period determined by the ratio of the frequency fx of the clock signal Fx and the frequency fc of the reference signal Fc. It becomes a data string. When the output clock signal Fxj obtained by delaying the clock signal Fx and the reference signal Fc are input to the FDSM (j), compared to the case where the clock signal Fx is input without delay, it appears in the cycle of the data string and the data string. The repeat pattern does not change, but the start position of the repeat pattern is shifted. Comparing the output repeat pattern start position before and after applying the delay, the start position of the repeat pattern changes stepwise as the delay amount applied to the clock signal Fx increases. When the amount of delay applied to the clock signal Fx is equal to the Ka cycle of the clock signal Fx (Ka is a natural number), the relative phase relationship between the output clock signal Fxj and the reference signal Fc is before the delay (the clock signal Fx and the reference signal). (Relative phase relationship with the signal Fc) (condition A).

  Similarly, even when the clock signal Fx is input to the FDSM (j) without being delayed and the output reference signal Fcj that is delayed to the reference signal Fc is input to the FDSM (j), the reference signal Fc is delayed. Compared to the case where the input pattern is input without being changed, the repetition pattern of the output data OUTj and the cycle thereof are not changed, but the start position of the repetition pattern is shifted. Comparing the start position of the output repeated pattern before and after applying the delay, the start position of the repeated pattern changes stepwise as the amount of delay applied to the reference signal Fc increases. When the amount of delay applied to the reference signal Fc becomes equal to the Kb period (Kb is a natural number) of the reference signal Fc, the relative phase relationship between the clock signal Fx and the output reference signal Fcj is before the delay (the clock signal Fx and the reference signal Fc (Condition B).

  Here, the minimum delay amount τ among the delay amounts satisfying either the condition A or the condition B is equal to the shorter one of one cycle of the clock signal Fx and one cycle of the reference signal Fc, and the clock signal Fx Alternatively, the relative phase relationship when the delay amount applied to the reference signal Fc is increased by τ is equal to the state before the delay is applied. When the delay amount satisfies either the condition A or the condition B, the start position of the repeated pattern of the output data OUTj coincides with the case where no delay is applied. In order to disperse the idle tone, it is necessary to shift the start position of the repeated pattern.

  Therefore, the signal having the higher frequency of the clock signal Fx and the reference signal Fc is delayed in parallel so as to divide the delay amount τ equal to one period of the signal into n, thereby being parallelized. It is possible to disperse the relative phase relationship between the signal Fx and the reference signal Fc in parallel, thereby shifting the start position of the repetitive pattern, so that output data OUT1 of n-parallel FDSM (1) to FDSM (n) The phase relationship of the idle tone between .about.OUTn is dispersed.

  Next, assuming that the relative phase relationship between the clock signal Fx and the reference signal Fc and the delay amount at which the relative phase relationship becomes equal to T, even if the clock signal Fx is delayed and parallelized so that T is divided into n, Even if the reference signal Fc is delayed and parallelized so that T is divided into n without delaying the clock signal Fx, idle between the output data OUT1 to OUTn of n-parallel FDSM (1) to FDSM (n) Explain that the effect of distributing the phase relationship of the tones is the same.

  A configuration in which a signal obtained by delaying the reference signal Fc by δ is input to the FDSM (j), and a signal in which the clock signal Fx is advanced by δ without delaying the reference signal Fc is input to the FDSM (j). Even if compared, the relative phase relationship between the output clock signal Fxj and the output reference signal Fcj does not change. Therefore, instead of inputting the output reference signal Fcj obtained by delaying the reference signal Fc by δ to the FDSM (j), the output clock signal obtained by leading the clock signal Fx by δ without delaying the reference signal Fc. Even if Fxj is considered to be input to FDSM (j), there is no problem in discussing the data string of the output data OUTj.

  On the other hand, the preceding amount in which the relative phase relationship between the output clock signal Fxj and the output reference signal Fcj is equal is equal to the delay amount T. Therefore, if the delay amount or the preceding amount is a variable, the output clock signal Fxj and the output reference signal Fcj Can be said to have a period T.

  Here, even if the output clock signals Fx1 to Fxn preceded so as to divide the preceding amount T by n are input to FDSM (1) to FDSM (n) and parallelized, the delay amount T is delayed so as to be divided by n. Even if the output clock signals Fx1 to Fxn subjected to are input to FDSM (1) to FDSM (n) and parallelized, the relative phase relationship between the output clock signal and the output reference signal is within the period T in which the relative phase relationship is equal. There is no change in being dispersed.

  From this, “delay the reference signal Fc so that T is divided into n” → “precede the clock signal Fx so that T is divided into n” → “delay in the clock signal Fx so that T is divided into n” It can be understood that any one of “Apply” does not change even though the relative phase relationship is dispersed. This is true even if the clock signal Fx and the reference signal Fc are replaced.

  From the above, even if the clock signal Fx is delayed and parallelized so that T is divided into n, the reference signal Fc is delayed and parallelized so that T is divided into n without delaying the clock signal Fx, It can be said that the effect of dispersing the phase relationship of the idle tone among the output data OUT1 to OUTn of the n parallel FDSM (1) to FDSM (n) is the same.

  Here, as the delay amount T at which the relative phase relationship between the output clock signal Fxj and the output reference signal Fcj becomes equal, the Ka cycle (Ka is a natural number) of the clock signal Fx or the Kb cycle (Kb is a natural number) of the reference signal Fc. It can be selected to be equal to either, but when setting a large delay amount (Ka is 2 or more or Kb is 2 or more), there is a case where the dispersion of the phase relationship of idle tones may be biased. Become. Note that general conditions that cause no deviation in the dispersion of the phase relationship of idle tones will be described later.

  It is convenient if T is selected as the smallest delay amount of the relative phase relationship between the output clock signal Fxj and the output reference signal Fcj so that periodicity smaller than T need not be considered. That is, the delay amount T may be determined so as to be equal to one cycle of the higher frequency of the frequency fx of the clock signal Fx and the frequency fc of the reference signal Fc, and the delay amount T may be divided into n to be parallelized. When the frequency fx is higher than the frequency fc as in the example of FIG. 17, the delay amount is set so that one period of the clock signal Fx is divided into n, and the clock signal Fx or the reference signal Fc is delayed and parallelized. Thus, the relative phase relationship of the idle tone between the output data OUT1 to OUTn is dispersed, and the canceling effect can be used in the sum of the output data OUT1 to OUTn. The phase difference between the delayed signals is preferably a uniform delay that can ensure the maximum value as the minimum phase difference, and at this time, the maximum dispersion effect is obtained.

<1-4-1: When the frequency fx of the clock signal Fx is higher than the frequency fc of the reference signal Fc>
In the output clock signal Fxj and the output reference signal Fcj shown in FIG. 10, the minimum delay amount at which the relative phase relationship is equal is 21 μS which is equal to one cycle of the clock signal Fx from “fx> fc”. When n = 4, the frequency ratio measuring unit 5 can be configured as shown in FIG. Here, the delay amount of the delay circuits DLx1 to DLx3 is 21/4 μS. FIG. 17 shows a timing chart of the frequency ratio measuring unit 5 shown in FIG. As shown in the figure, since the patterns of the output data OUT1 to OUT4 are dispersed, the frequency delta sigma modulation signal Y is a dispersion of idle tones.

<1-4-2: When the frequency fc of the reference signal Fc is higher than the frequency fx of the clock signal Fx>
Next, a case where the frequency fc of the reference signal Fc is higher than the frequency fx of the clock signal Fx will be described. When n = 4, the frequency ratio measuring unit 5 can be configured as shown in FIG.

  The operation of FDSM (j) (j is a natural number equal to or less than n) replaces the frequency relationship with respect to the example of FIG. Consider a 21 μS signal (47.619047 kHz). The frequency ratio [fx: fc] between the clock signal Fx and the reference signal Fc is given by the following equation.

fx: fc = 1 / 66e-6: 1 / 21e-6 = 7: 22
Therefore, it can be seen that the time of 7 cycles of the clock signal Fx and 22 cycles of the reference signal Fc are equal, and the same data string is repeated every 66 μS × 7 = 21 μS × 22 = 462 μS. As shown in FIG. 19, the operation of FDSM (j) starts from the moment when the rising edges of the output reference signal Fcj and the output clock signal Fxj coincide with each other. Fxj advances by 7/22 cycles, and the count data Dc increases by 0 or 1.

  In this case, a data string “0100100100100100100100” having a period of 462 μS appears in the output data OUTj of FDSM (j) as shown in FIG. Note that the FDSM (j) in FIG. 20 also shows the data sequence of the next second cycle after the first 462 μS data sequence has completed since the outputs of the first latch 22 and the second latch 23 at the start of operation are indefinite. Yes.

  Since one cycle of the reference signal Fc having a frequency higher than that of the clock signal Fx is 21 μS, the delay amount of the delay circuits DLc1 to DLc3 shown in FIG. 18 is 21/4 μS. FIG. 21 shows a timing chart of the frequency ratio measuring unit 5 shown in FIG. As shown in the figure, since the patterns of the output data OUT1 to OUT4 are dispersed, the frequency delta sigma modulation signal Y is a dispersion of idle tones. On the other hand, a timing chart of the apparatus shown in FIG. 13 in which the phase adjustment unit 10 is deleted from the frequency ratio measurement unit 5 shown in FIG. 18 is as shown in FIG. In this case, the idle tone is not distributed and it is difficult to improve the SN ratio. However, as compared with the case where FDSM is used alone as the frequency ratio measuring unit 5, the idle tone is reduced and the SN ratio is improved.

  In the frequency ratio measuring unit 5 of the fifth embodiment, FDSM (1) to FDSM (n) generate output data OUT1 to OUTn in a data stream format. Further, as described above, the phase adjustment unit 10 sets one of the clock signal Fx and the reference signal Fc to Tx /, where Tx is a short cycle of one cycle of the clock signal Fx and one cycle of the reference signal Fc. Output clock signals Fx1 to Fxn and output reference signals Fc1 to Fcn are generated with a delay of n in order.

  Here, the cycle of the idle tone is determined according to one cycle of the clock signal Fx and one cycle of the reference signal Fc, but does not fall below Tx. On the other hand, the phase of the idle tone superimposed on each of the output data OUT1 to OUTn has n sets of output clock signals and output reference signals (Fx1, Fc1), (Fx2,) supplied to FDSM (1) to FDSM (n). Fc2),... (Fxn, Fcn). As described above, if one of the clock signal Fx and the reference signal Fc is sequentially delayed by Tx / n, the phase of the idle tone superimposed on each of the output data OUT1 to OUTn can be shifted by Tx / n. The phase of the idle tone superimposed on each of the output data OUT1 to OUTn can be dispersed.

  Further, as described with reference to FIGS. 15A to 15D, there are various modes for performing the delay. Since the phase of the idle tone is determined by the phase of the output clock signal and the output reference signal supplied to the FDSM, the clock signal Fx and the reference signal Fc are shifted so as to shift the phase of the idle tone superimposed on the output data OUT1 to OUTn by Tx / n. And the output reference signals (Fx1, Fc1), (Fx2, Fc2),... (Fxn, Fcn) may be generated.

  Specifically, when the phase difference between the output clock signal Fxi to be supplied to the i (i is an arbitrary natural number equal to or less than n−1) -th FDSM (i) and the output reference signal Fci is Pi, the phase adjustment unit 10 Adjust the phase of the clock signal Fx and the reference signal Fc relatively so that Tx / n = Pi + 1−Pi, and n sets of output clock signals and output reference signals (Fx1, Fc1), (Fx2 , Fc2),... (Fxn, Fcn) may be generated.

  Further, in the frequency ratio measuring unit 5 of the fifth embodiment, even if the clock signal Fx and the reference signal Fc are exchanged, the n-parallel FDSMs (1) to FDSM are obtained only by reversing the counting signal and the counting signal. (N) Since the effect of dispersing the phase of the idle tone corresponding to each is not impaired, there is no need to change the configuration (for example, when a normal count configuration in a frequency measurement device is used in a reciprocal configuration).

Next, the operation of the frequency synthesizer 1 will be described.
As shown in FIG. 8, the reference signal and the clock signal output from the digitally controlled oscillator 17 are input to the frequency ratio measuring unit 5 of the frequency synthesizer 1, and the predetermined processing described above is performed in the frequency ratio measuring unit 5. Done.

  The signal indicating the frequency ratio output from the frequency ratio measuring unit 5 is subjected to predetermined processing by the loop filter 12 and input to the comparator 13. For example, when a low-pass filter is used as the loop filter 12, the loop filter 12 blocks or reduces frequency components that are equal to or higher than a predetermined cutoff frequency. The comparator 13 receives a signal indicating the target value of the frequency ratio, and the comparator 13 compares the target value with the frequency ratio indicated by the signal output from the loop filter 12.

  The frequency ratio difference signal indicating the difference between the target value, which is the comparison result of the comparator 13, and the frequency ratio indicated by the signal output from the loop filter 12 is multiplied by k0 by the gain unit 16 and integrated by the integration unit 71. The digital control signal is input to the digital control oscillator 17 as a digital control signal of the digital control oscillator 17. As a result, the oscillation frequency of the digitally controlled oscillator 17, that is, the frequency of the clock signal output from the digitally controlled oscillator 17 is adjusted and converges to the target value.

  According to the fifth embodiment as described above, the same effect as that of the first embodiment described above can be exhibited.

  Further, the frequency synthesizer 1 can further reduce idle tones.

  That is, even when neither phase of the clock signal and the reference signal is shifted, the idle tone can be reduced to, for example, about 1 / n1 / 2 due to the influence of the signal fluctuation or the like.

Further, when the phase of at least one of the clock signal and the reference signal is shifted, for example, the idle tone can be reduced to about 1 / n.
The fifth embodiment can be applied to each embodiment.

<Sixth Embodiment>
FIG. 23 is a block diagram showing a frequency ratio measuring unit in the sixth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the sixth embodiment will be described with a focus on differences from the above-described fifth embodiment, and description of similar matters will be omitted.

  As shown in FIG. 23, in the frequency synthesizer 1 of the sixth embodiment, each FDSM 11 of the frequency ratio measuring unit 5 is an FDSM having a bit stream configuration, and the FDSM 11 is the same as that described in the first embodiment. Can be used.

Hereinafter, the frequency ratio measuring unit 5 will be described in detail.
<2-1: Overall configuration>
FIG. 23 shows a block diagram of the frequency ratio measuring unit 5 in the sixth embodiment. The frequency ratio measuring unit 5 is configured in the same manner as the frequency ratio measuring unit 5 in the fifth embodiment shown in FIG. 9 except for the detailed configuration of FDSM (1) to FDSM (j).

  The FDSM (j) latches the output clock signal Fxj in synchronization with the rising edge of the output reference signal Fcj and outputs the first data d1, and the first latch 22 in synchronization with the rising edge of the output reference signal Fcj. A second latch 23 that latches one data d1 and outputs second data d2, and an exclusive OR circuit 25 that generates an output data OUTj by calculating an exclusive OR of the first data d1 and the second data d2. With. The first latch 22 and the second latch 23 are composed of, for example, a D flip-flop circuit. Note that FDSM (1) to FDSM (j-1) and FDSM (j + 1) to FDSM (n) are configured in the same manner as FDSM (j).

  The FDSM (j) of the sixth embodiment is different from the FDSM (j) of the fifth embodiment shown in FIG. 9 in the fifth embodiment, in which the count data Dc is held by the first latch 22 and the output reference signal While the increment of the count data Dc obtained by counting the rising edge of the output clock signal Fxj observed while Fcj changes for one period is output as the output data OUTj, in the sixth embodiment, the first latch 22 Is that the output clock signal Fxj is held in the High or Low state, and the even / odd number of inversions during the one-cycle transition of the output reference signal Fcj is output as the output data OUTj (0 if the number of inversions is even, If it is odd, 1 is output).

  Incidentally, since one cycle of the output clock signal Fxj is composed of two inversion transitions of High and Low, the degree of change that the fluctuation of the output clock signal Fxj with respect to the output reference signal Fcj has on the output data OUTj is shown in FIG. This is twice as large as when the count value is held. Therefore, the behavior of the idle tone in the FDSM (j) having the bit stream configuration is the same as the behavior when the output clock signal Fxj having the double frequency is input to the FDSM (j) in the FDSM (j) of FIG. . The operation of the FDSM (j) in the sixth embodiment may be considered by replacing the frequency fx of the clock signal Fx with the frequency 2fx as necessary in consideration of the above-described properties.

<2-2: When the frequency 2fx is higher than the frequency fc>
Next, a case where the frequency 2fx (corresponding to the clock signal Fx) is higher than the frequency fc of the reference signal Fc will be described. A signal (47.619047 kHz) having a period of 21 μS is considered as the clock signal Fx. Further, consider a signal (15.15 kHz) having a period of 66 μS as the reference signal Fc. Since one cycle of the clock signal Fx is composed of two inversion transitions of High and Low, a value twice as high as the frequency fx is handled below. This corresponds to a case where the frequency 2fx that is twice the clock signal Fx is higher than the frequency fc of the reference signal Fc, and the frequency ratio 2fx: fc is given by the following equation.

2fx: fc = 2 / 21e-6: 1 / 66e-6 = 44: 7
In this case, the time when the clock signal Fx is inverted 44 times is equal to the time of 7 cycles of the reference signal Fc. That is, the same data string is repeated every 21/2 μS × 44 = 66 μS × 7 = 462 μS.

  Considering the operation of FDSM (j) at this time, the output clock signal Fxj undergoes an inversion transition 44/7 = 6 + 2/7 times while the output reference signal Fcj advances by one cycle. FIG. 24 shows these relationships as a starting point when the rising edges of the output reference signal Fcj and the output clock signal Fxj match.

  In the actual data string of the output data OUTj of FDSM (j), as shown in FIG. 25, a bit string of “0100100” appears at a cycle of 462 μS. 23, since the outputs of the first latch 22 and the second latch 23 at the start of operation are indefinite, FIG. 25 shows a repeating pattern of the second round after the first 462 μS cycle. Show.

  “2fx> fc”, and the behavior of the FDSM (j) corresponding to the bit stream is that a signal having a frequency twice the clock signal Fx is input to the FDSM (j) in the FDSM (j) corresponding to the data stream shown in FIG. Therefore, a delay may be applied so as to divide the clock signal Fx based on the half cycle.

  When n = 4, the configuration shown in FIG. 16 may be applied. Here, the delay time of the delay circuits DLx1 to DLx3 may be a time (21/8 μS) obtained by dividing the half cycle of the clock signal Fx into four equal parts. In this case, the timing chart is as shown in FIG. 26, and the start position of the repetitive pattern of the output data OUT1 to OUT4 is shifted, so that the idle tone is dispersed.

  If the clock signal Fx is not delayed and only four FDSM (1) to FDSM (4) are parallelized as shown in FIG. 13, the timing chart is as shown in FIG. In this case, it is difficult to improve the SN ratio of the frequency delta-sigma modulation signal Y because the start positions of the repeated patterns of the output data OUT1 to OUT4 match. However, as compared with the case where FDSM is used alone as the frequency ratio measuring unit 5, the idle tone is reduced and the SN ratio is improved.

<2-3: When frequency fc is higher than frequency 2fx>
Next, a case where the frequency fc of the reference signal Fc is higher than the frequency 2fx that is twice the clock signal Fx will be described.

The operation of FDSM (j) (j is a natural number equal to or less than n) replaces the frequency relationship with respect to the example of FIG. Consider a 21 μS signal (47.619047 kHz). Since one cycle of the clock signal Fx is composed of two inversion transitions of High and Low, a value twice as high as the frequency fx is handled below. This corresponds to the case where the frequency fc of the reference signal Fc is higher than the frequency 2fx that is twice the clock signal Fx, and the frequency ratio 2fx: fc is given by the following equation.
2fx: fc = 2 / 66e-6: 1 / 21e-6 = 7: 11

  Therefore, the time of 7 cycles of the clock signal Fx and the time of 11 cycles of the reference signal Fc are equal, and the same data string is repeated every 66/2 μS × 7 = 21 μS × 11 = 231 μS. As the operation of FDSM (j), as shown in FIG. 28, when the starting point is the moment when the rising edges of the output reference signal Fcj and the output clock signal Fxj coincide, the output clock signal is output while the output reference signal Fcj advances one cycle. Fxj advances by a period of 7/22, and reversely transitions only 7/22 × 2 = 7/11 times.

  In this case, as shown in FIG. 29, a bit string “01101101101” having a cycle of 231 μS appears in the output data OUTj of FDSM (j). In FIG. 23, since the outputs of the first latch 22 and the second latch 23 at the start of operation are indefinite, FIG. 29 shows the second bit sequence after the first bit sequence has been completed. .

  When n = 4, the configuration shown in FIG. 18 may be applied. Here, the delay time of the delay circuits DLc1 to DLc3 may be a time (21/4 μS) obtained by dividing one period of the reference signal Fc into four equal parts. In this case, the timing chart is as shown in FIG. 30, and the start position of the repeated pattern of the output data OUT1 to OUT4 is shifted, so that the idle tone is dispersed.

  If the clock signal Fx is not delayed and only four FDSM (1) to FDSM (4) are parallelized as shown in FIG. 13, the timing chart is as shown in FIG. In this case, it is difficult to improve the SN ratio of the frequency delta-sigma modulation signal Y because the start positions of the repeated patterns of the output data OUT1 to OUT4 match. However, as compared with the case where FDSM is used alone as the frequency ratio measuring unit 5, the idle tone is reduced and the SN ratio is improved.

  In the frequency ratio measuring unit 5 of the sixth embodiment, FDSM (1) to FDSM (n) generate output data OUT1 to OUTn in bit stream format. Further, as described above, the phase adjustment unit 10 sets one of the clock signal Fx and the reference signal Fc to Tx /, where Tx is a short cycle of the half cycle of the clock signal Fx and one cycle of the reference signal Fc. Output clock signals Fx1 to Fxn and output reference signals Fc1 to Fcn are sequentially delayed by n.

  Similarly to the frequency ratio measuring unit 5 of the fifth embodiment, the phase adjusting unit 10 of the sixth embodiment also shifts the phase of the idle tone superimposed on the output data OUT1 to OUTn by Tx / n. As described above, the phases of the clock signal Fx and the reference signal Fc are relatively adjusted to generate n sets of output clock signals and output reference signals (Fx1, Fc1), (Fx2, Fc2),... (Fxn, Fcn). do it.

  Specifically, when the phase difference between the output clock signal Fxi to be supplied to the i (i is an arbitrary natural number equal to or less than n−1) -th FDSM (i) and the output reference signal Fci is Pi, the phase adjustment unit 10 Adjust the phase of the clock signal Fx and the reference signal Fc relatively so that Tx / n = Pi + 1−Pi, and n sets of output clock signals and output reference signals (Fx1, Fc1), (Fx2 , Fc2),... (Fxn, Fcn) may be generated.

According to the sixth embodiment as described above, the same effect as that of the fifth embodiment described above can be exhibited.
The sixth embodiment can be applied to each embodiment.

<Seventh embodiment>
FIG. 32 is a block diagram showing a seventh embodiment of the frequency synthesizer of the present invention. FIG. 33 is a block diagram showing a control amount calculator of the frequency synthesizer shown in FIG.

  Hereinafter, the seventh embodiment will be described with a focus on differences from the first embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 32, the frequency synthesizer 1 of the seventh embodiment is an example of the FDSM 11, the loop filter 12, the comparator 13, the control amount calculation unit 6, and the oscillation unit. It has a digitally controlled oscillator (DCO) 17 to be controlled. The FDSM 11, the loop filter 12, the comparator 13, the control amount calculation unit 6, and the digital control oscillator 17 are connected in this order toward the output side.

  By using the digitally controlled oscillator 17 as the oscillating unit, it is possible to obtain a stable output against environmental changes such as temperature changes.

  The control amount calculation unit 6 has a function of obtaining the control amount of the digital control oscillator 17 based on the comparison result of the comparator 13. Hereinafter, the control amount calculation unit 6 will be described.

  Various forms are possible as the control amount calculation unit 6. In this embodiment, a general form of the control amount calculation unit 6 will be described, and specific configuration examples will be described in second to seventh embodiments described later. Will be described in the next section.

  As shown in FIG. 33, the control amount calculation unit 6 includes n gain units 16 each having a gain set to k0, a latch 63, and an adder 62 (in the illustrated configuration, n is a natural number of 2 or more). ) Integrating unit 61, gain unit 16 having a gain set to k1, gain unit 16 having a gain set to k2,..., Gain unit 16 having a gain set to kn, latch 66, M differential units 64 (m is a natural number of 2 or more in the configuration shown in the figure), a gain unit 16 with a gain set to k−1,..., A gain of k−. The gain unit 16 is set to m + 1, the gain unit 16 is set to k−m, the adder 67, and the integration unit 71. The gain value of each gain unit 16 is not particularly limited, and is set as appropriate according to various conditions.

  Further, in the present embodiment, the integrating unit 71 includes an adder 72 and a latch 73, and is disposed at a subsequent stage of the adder 67. The integrating unit 71 is a latch preceding the current data and the current data. The adder 72 adds the data latched in the register 73.

  In the present embodiment, in order to facilitate understanding of the control amount calculation unit 6, the above configuration will be described as an example. However, as will be described below, the control amount calculation unit 6 does not necessarily have all the configurations. You don't have to. Further, the description of the part “...” Is omitted.

  First, the gain unit 16 having a gain k0 constitutes a first circuit unit 60 that outputs the comparison result of the comparator 13 by multiplying it by a predetermined number.

  Further, the integration unit 61 and the gain unit 16 having a gain of k1 constitute a second circuit unit 68 that performs integration once for the comparison result of the comparator 13 and outputs the result by a predetermined multiplication.

  Further, the second circuit unit 68 configured to perform the integration twice and output the comparison result of the comparator 13 by the two integration units 61 connected in series and the gain unit 16 having a gain of k2 is configured. Is done.

  In addition, a second circuit unit 68 that performs integration n times and outputs the result of comparison of the comparator 13 by the n integration units 61 connected in series and the gain unit 16 having a gain kn is output. Composed.

  A plurality of (a plurality of types) of second circuit units 68 having different numbers of integrations constitute a second circuit unit group.

  Further, the differentiating unit 64 and the gain unit 16 having a gain of k−1 constitute a third circuit unit 69 that performs differentiation once with respect to the comparison result of the comparator 13 and outputs the result after a predetermined multiplication.

  In addition, the (m−1) differentiating units 64 connected in series and the gain unit 16 having a gain of k−m + 1 perform differentiation on the comparison result of the comparator 13 (m−1) times to a predetermined multiple. Thus, the third circuit unit 69 is configured to output.

  The third circuit unit outputs m times the differential result of the comparator 13 by m times and outputs the comparison result by the m differential units 64 connected in series and the gain unit 16 having a gain of k−m. 69 is configured.

  A third circuit unit group is configured by a plurality (a plurality of types) of third circuit units 69 having different numbers of differentiations.

  By providing such a control amount calculation unit 6, for example, PD control for frequency, PI control for frequency, PID control for frequency, PD control for phase, PI control for phase, PID control for phase, PIDD2 control for phase, etc. Various feedback controls can be performed. The “P” is proportional, the “I” is integration, the “D” is differentiation, and the “D2” is second-order differentiation.

  Here, the control amount calculation unit 6 does not necessarily include the first circuit unit 60, the plurality of second circuit units 68 in the second circuit unit group, and the plurality of third circuit units 69 in the previous third circuit unit group. You don't have to have everything.

  That is, the control amount calculation unit 6 includes the first circuit unit 60, the plurality of second circuit units 68 different in the second circuit unit group, and the plurality of third circuit units 69 different in the previous third circuit unit group. It suffices to have at least two different circuit units to be selected. Therefore, the control amount calculation unit 6 may be configured by, for example, a plurality of different circuit units in the second circuit unit group, an adder 67, and an integration unit 71, and in the third circuit unit group. A plurality of different circuit units, an adder 67 and an integration unit 71 may be included.

Next, the operation of the frequency synthesizer 1 will be described.
As shown in FIG. 32, the steps up to the comparator 13 are the same as in the first embodiment. A frequency ratio difference signal (output signal of the comparator 13) indicating the difference between the target value as the comparison result of the comparator 13 and the frequency ratio indicated by the signal output from the FDSM 11 is input to the control amount calculation unit 6. .

  The control amount calculation unit 6 obtains the control amount of the digitally controlled oscillator 17 based on the frequency ratio difference signal. Note that the control amount calculation method differs depending on the configuration of the control amount calculation unit 6, and the description thereof is omitted here.

  A signal indicating the control amount output from the control amount calculation unit 6 is input to the digital control oscillator 17 as a digital control signal of the digital control oscillator 17.

  As a result, the oscillation frequency of the digitally controlled oscillator 17, that is, the frequency of the clock signal output from the digitally controlled oscillator 17 is adjusted and converged (locked) to the target value. Alternatively, the phase and frequency of the clock signal output from the digital control oscillator 17 are adjusted, the phase converges to a predetermined value, and the frequency converges to the target value.

  According to the seventh embodiment as described above, it is possible to lock at least one of the frequency and the phase of the clock signal output from the digitally controlled oscillator 17 with a simple configuration, and the first embodiment described above. The same effect can be exhibited.

  In addition, since all the signals to be processed are digital signals, they are strong against noise, thereby obtaining high accuracy.

  In addition, since the control amount calculation unit 6 has a plurality of types of circuit units, the gain adjustment range is widened, and stability, transient characteristics, steady characteristics, and the like can be improved.

<Eighth Embodiment>
FIG. 34 is a block diagram showing a control amount calculation unit in the eighth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the eighth embodiment will be described with a focus on differences from the above-described seventh embodiment, and description of similar matters will be omitted.

  As shown in FIG. 34, the frequency synthesizer 1 of the eighth embodiment is configured to perform adjustment by performing PD control on the frequency.

  The control amount calculation unit 6 includes a gain unit 161 having a gain k0, a differentiation unit 64 including a latch 66 and a subtractor 65, a gain unit 162 having a gain k-1, an adder 67, and an integration unit 71. And have.

  A first circuit unit 60 is configured by the gain unit 161, and P control is performed on the frequency using a signal output from the first circuit unit 60.

  Further, the differentiation unit 64 and the gain unit 162 constitute a third circuit unit 691, and D control is performed on the frequency using a signal output from the third circuit unit 691.

  The signal output from the first circuit unit 60 and the signal output from the third circuit unit 691 are added by the adder 67, integrated by the integration unit 71, and output from the control amount calculation unit 6.

  Also according to the eighth embodiment as described above, the same effects as those of the seventh embodiment described above can be exhibited.

  In the eighth embodiment, the frequency of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.

  Further, the transient response characteristic can be improved, and the time required for the lock can be reduced as compared with the P control.

<Ninth Embodiment>
FIG. 35 is a block diagram showing a control amount calculation unit in the ninth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the ninth embodiment will be described focusing on differences from the above-described seventh embodiment, and description of similar matters will be omitted.

  As shown in FIG. 35, the frequency synthesizer 1 of the ninth embodiment is configured to perform adjustment by performing PID control on the frequency.

  The control amount calculation unit 6 includes a gain unit 161 having a gain of k0, an integration unit 61 including a latch 63 and an adder 62, a gain unit 163 having a gain of k1, a latch 63, and a subtractor 65. It has a differentiating unit 64, a gain unit 162 with a gain of k−1, an adder 67, and an integrating unit 71.

  A first circuit unit 60 is configured by the gain unit 161, and P control is performed on the frequency using a signal output from the first circuit unit 60.

  The integrating unit 61 and the gain unit 163 constitute a second circuit unit 681, and I control is performed on the frequency using the signal output from the second circuit unit 681.

  Further, the differentiation unit 64 and the gain unit 162 constitute a third circuit unit 691, and D control is performed on the frequency using a signal output from the third circuit unit 691.

  The signal output from the first circuit unit 60, the signal output from the second circuit unit 681, and the signal output from the third circuit unit 691 are added by the adder 67 and integrated by the integration unit 71. And output from the control amount calculation unit 6.

  According to the ninth embodiment as described above, the same effect as that of the seventh embodiment described above can be exhibited.

  In the ninth embodiment, the frequency and phase of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.

  Moreover, the transient response characteristic can be improved, the time required for the lock can be reduced, and the steady deviation from the target value can be made zero.

<Tenth Embodiment>
FIG. 36 is a block diagram showing a control amount calculation unit in the tenth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the tenth embodiment will be described with a focus on differences from the above-described seventh embodiment, and description of similar matters will be omitted.

  As shown in FIG. 36, the frequency synthesizer 1 of the tenth embodiment is configured to perform adjustment by performing PD control on the phase.

  The control amount calculation unit 6 includes a gain unit 161 having a gain k0, an integration unit 61 including a latch 63 and an adder 62, a gain unit 163 having a gain k1, an adder 67, and an integration unit 71. Have.

  The first circuit unit 60 is configured by the gain unit 161, and D control is performed on the phase using the signal output from the first circuit unit 60.

  Further, the integration unit 61 and the gain unit 163 constitute a second circuit unit 681, and P control is performed on the phase using the signal output from the second circuit unit 681.

  The signal output from the first circuit unit 60 and the signal output from the second circuit unit 681 are added by the adder 67, integrated by the integration unit 71, and output from the control amount calculation unit 6.

  Also according to the tenth embodiment as described above, the same effects as those of the seventh embodiment described above can be exhibited.

  In the tenth embodiment, the frequency and phase of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.

  Further, the transient response characteristic can be improved, and the time required for the lock can be reduced as compared with the P control.

<Eleventh embodiment>
FIG. 37 is a block diagram showing a control amount calculation unit in the eleventh embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the eleventh embodiment will be described with a focus on differences from the seventh embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 37, the frequency synthesizer 1 of the eleventh embodiment is configured to perform adjustment by performing PI control on the phase.

  The control amount calculation unit 6 includes two integration units 61 each including a latch 63 and an adder 62, a gain unit 163 having a gain k1, a gain unit 164 having a gain k2, an adder 67, and an integration unit 71. And have.

  The integrating unit 61 and the gain unit 163 constitute a second circuit unit 681, and P control is performed on the phase using the signal output from the second circuit unit 681.

  Further, the second circuit unit 682 is configured by the two integration units 61 and the gain unit 164 connected in series, and the I control is performed on the phase using the signal output from the second circuit unit 682. Is called.

  The signal output from the second circuit unit 681 and the signal output from the second circuit unit 682 are added by the adder 67, integrated by the integration unit 71, and output from the control amount calculation unit 6.

  According to the eleventh embodiment as described above, the same effects as those of the seventh embodiment described above can be exhibited.

In the eleventh embodiment, the frequency and phase of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.
Further, the steady deviation from the target value can be made zero.

<Twelfth embodiment>
FIG. 38 is a block diagram showing a control amount calculation unit in the twelfth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the twelfth embodiment will be described with a focus on differences from the seventh embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 38, the frequency synthesizer 1 of the twelfth embodiment is configured to perform adjustment by performing PID control on the phase.

  The control amount calculation unit 6 includes a gain unit 161 having a gain k0, two integration units 61 each including a latch 63 and an adder 62, a gain unit 163 having a gain k1, and a gain unit 164 having a gain k2. , An adder 67 and an integration unit 71.

  The first circuit unit 60 is configured by the gain unit 161, and D control is performed on the phase using the signal output from the first circuit unit 60.

  Further, the integration unit 61 and the gain unit 163 constitute a second circuit unit 681, and P control is performed on the phase using the signal output from the second circuit unit 681.

  Further, the second circuit unit 682 is configured by the two integration units 61 and the gain unit 164 connected in series, and the I control is performed on the phase using the signal output from the second circuit unit 682. Is called.

  The signal output from the first circuit unit 60, the signal output from the second circuit unit 681, and the signal output from the second circuit unit 682 are added by the adder 67 and integrated by the integration unit 71. And output from the control amount calculation unit 6.

  Also according to the twelfth embodiment as described above, the same effects as those of the seventh embodiment described above can be exhibited.

  In the twelfth embodiment, the frequency and phase of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.

  In addition, the transient response characteristic can be improved, the time required for the lock can be reduced, and the steady deviation from the target value can be made zero compared to P control and PI control.

<13th Embodiment>
FIG. 39 is a block diagram showing a control amount calculation unit in the thirteenth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the thirteenth embodiment will be described with a focus on differences from the seventh embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 39, the frequency synthesizer 1 of the thirteenth embodiment is configured to perform adjustment by performing PIDD2 (PIDD) control on the phase.

  The control amount calculation unit 6 includes a gain unit 161 having a gain k0, two integration units 61 each including a latch 63 and an adder 62, a gain unit 163 having a gain k1, and a gain unit 164 having a gain k2. , A differential unit 64 including a latch 66 and a subtracter 65, a gain unit 162 having a gain of k-1, an adder 67, and an integration unit 71.

  The first circuit unit 60 is configured by the gain unit 161, and D control is performed on the phase using the signal output from the first circuit unit 60.

  Further, the integration unit 61 and the gain unit 163 constitute a second circuit unit 681, and P control is performed on the phase using the signal output from the second circuit unit 681.

  Further, the second circuit unit 682 is configured by the two integration units 61 and the gain unit 164 connected in series, and the I control is performed on the phase using the signal output from the second circuit unit 682. Is called.

  The differentiation unit 64 and the gain unit 162 constitute a third circuit unit 691, and D2 control (second-order differentiation control) is performed on the phase using the signal output from the third circuit unit 691. .

  Also according to the thirteenth embodiment as described above, the same effects as in the seventh embodiment described above can be exhibited.

  In the thirteenth embodiment, the frequency and phase of the clock signal output from the digitally controlled oscillator 17 can be locked with a simple configuration.

  In addition, the transient response characteristic can be improved, the time required for the lock can be reduced, and the steady deviation from the target value can be made zero compared to P control and PI control.

  In addition, the gain adjustment range is wide, and even when the system dead time cannot be ignored, it is quick and strong against disturbance.

<Fourteenth embodiment>
FIG. 40 is a block diagram showing a fourteenth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the fourteenth embodiment will be described with a focus on differences from the third embodiment and the seventh embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 40, the frequency synthesizer 1 of the fourteenth embodiment includes an FDSM 11, a comparator 13, a loop filter 12, a control amount calculation unit 6, and a digital control oscillator 17. The FDSM 11, the comparator 13, the loop filter 12, the control amount calculation unit 6, and the digital control oscillator 17 are connected in this order toward the output side.

  Thus, in the present embodiment, the loop filter 12 is provided after the comparator 13, that is, between the comparator 13 and the digitally controlled oscillator 17, more specifically, between the comparator 13 and the control amount calculator 6. Arranged between.

  Similarly to the third embodiment, the comparator 13 includes a gain unit 132 and a subtracter 131 (see FIG. 6), and is configured to perform signal processing with a signed binary number expression.

  Further, the control amount calculation unit 6 is as described in the seventh embodiment. As the control amount calculation unit 6, for example, the control amount calculation unit 6 of the eighth to thirteenth embodiments can be used, and the same effects as those described in the eighth to thirteenth embodiments, respectively. Can be obtained.

  According to the fourteenth embodiment as described above, the same effects as those of the seventh embodiment described above can be exhibited except for the effects caused by the position of the loop filter 12.

  Moreover, about the effect resulting from the position of the loop filter 12, the effect similar to 3rd Embodiment mentioned above can be exhibited.

<Fifteenth embodiment>
FIG. 41 is a block diagram showing a fifteenth embodiment of the frequency synthesizer of the present invention.

  Hereinafter, the fifteenth embodiment will be described focusing on the differences from the third embodiment and the seventh embodiment described above, and description of similar matters will be omitted.

  As shown in FIG. 41, the frequency synthesizer 1 of the fifteenth embodiment includes an FDSM 11, a comparator 13, a control amount calculator 6, a loop filter 12, and a digitally controlled oscillator 17. The FDSM 11, the comparator 13, the control amount calculator 6, the loop filter 12, and the digitally controlled oscillator 17 are connected in this order toward the output side.

  Thus, in the present embodiment, the loop filter 12 is arranged after the control amount calculation unit 6, that is, between the control amount calculation unit 6 and the digital control oscillator 17.

  Similarly to the third embodiment, the comparator 13 includes a gain unit 132 and a subtracter 131 (see FIG. 6), and is configured to perform signal processing with a signed binary number expression.

  Further, the control amount calculation unit 6 is as described in the seventh embodiment. As the control amount calculation unit 6, for example, the control amount calculation unit 6 of the eighth to thirteenth embodiments can be used, and the same effects as those described in the eighth to thirteenth embodiments, respectively. Can be obtained.

  Also according to the fifteenth embodiment as described above, the same effects as those of the seventh embodiment described above can be exhibited except for the effects due to the position of the loop filter 12.

  Further, since the loop filter 12 is disposed after the control amount calculation unit 6, it effectively attenuates frequency components that increase phase noise of the digitally controlled oscillator 17 such as quantization noise components generated in the comparator 13. Can do.

  In addition, the calculation is performed with a large quantization error until the process is performed by the loop filter 12, but the number of expression bits at the time of the calculation can be suppressed. Therefore, the loop filter 12 is arranged after the control amount calculation unit 6. By doing so, the scale of the arithmetic circuit up to the control amount calculation unit 6 can be reduced.

  Further, by adopting a signed binary number expression, it is possible to handle negative values, thereby reducing the number and size of circuit elements.

  The frequency synthesizer of the present invention has been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part is replaced with an arbitrary configuration having the same function. be able to. Moreover, other arbitrary components may be added.

  Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments and modifications.

  In the above embodiment, two configuration examples of the frequency delta sigma modulation unit are given. However, in the present invention, the configuration of the frequency delta sigma modulation unit is not limited to this, and may be another configuration.

  In the embodiment, the frequency ratio measurement unit is configured using the frequency delta sigma modulation unit. However, the present invention is not limited to this, and for example, the frequency ratio measurement unit may be configured using a frequency modulation unit having another configuration. You may comprise a measurement part.

  Moreover, in the said embodiment, although the frequency divider is not provided, in this invention, it is not limited to this, The 1 or several frequency divider may be provided.

  DESCRIPTION OF SYMBOLS 1 ... Frequency synthesizer, 5 ... Frequency ratio measurement part, 6 ... Control amount calculation part, 60 ... 1st circuit part, 61 ... Integration part, 62 ... Adder, 63 ... Latch, 64 ... Differentiation part, 65 ... Subtractor, 66 ... Latch, 67 ... Adder, 68, 681, 682 ... Second circuit unit, 69, 691 ... Third circuit unit, 71 ... Integral unit, 72 ... Adder, 73 ... Latch, 11 ... FDSM, 12 ... Loop Filter, 13 ... Comparator, 131 ... Subtractor, 132 ... Gain unit, 14 ... DA converter, 15 ... Voltage controlled oscillator, 16, 161-164 ... Gain unit, 17 ... Digitally controlled oscillator, 21 ... Up counter, 22 ... 1st latch, 23 ... 2nd latch, 24 ... Subtractor, 25 ... Exclusive OR circuit, 31 ... Integration unit, 32 ... Adder, 33 ... Latch, 10 ... Phase adjustment unit, 30 ... Adder, Fx ... Clock signal, Fx1 Fxn: output clock signal, Fc: reference signal, Fc1-Fcn: output reference signal, OUT1-OUTn: output data, Y: frequency delta-sigma modulation signal, DLx1-DLxn-1, delay circuit, DLc1-DLcn-1: delay Circuit, D1, d1 ... first data, D2, d2 ... second data

Claims (14)

An oscillating unit for generating a first signal;
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed in front of the comparison unit,
A frequency synthesizer, wherein the frequency of the first signal of the oscillating unit is adjusted based on a comparison result of the comparing unit. An oscillating unit for generating a first signal;
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed after the comparison unit,
A frequency synthesizer, wherein the frequency of the first signal of the oscillating unit is adjusted based on a comparison result of the comparing unit. An integration unit between the comparison unit and the oscillation unit;
The frequency synthesizer according to claim 1 or 2, wherein a phase of the first signal of the oscillation unit is adjusted based on a comparison result of the comparison unit. An oscillating unit for generating a first signal;
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed in front of the comparison unit;
A control amount calculation unit for obtaining a control amount of the oscillation unit based on a comparison result of the comparison unit; and
The control amount calculation unit is a first circuit unit that outputs the comparison result of the comparison unit multiplied by a predetermined value, and
A second circuit unit group composed of a plurality of second circuit units that perform different predetermined number of integrations on the comparison result of the comparison unit;
A third circuit unit group composed of a plurality of third circuit units that perform different predetermined number of differentiations on the comparison result of the comparison unit, and at least two different circuit units selected from the third circuit unit group,
A frequency synthesizer, wherein at least one of a frequency and a phase of the first signal of the oscillation unit is adjusted based on the control amount obtained by the control amount calculation unit. An oscillating unit for generating a first signal;
A frequency ratio measurement unit that measures a frequency ratio between the first signal and the second signal using the first signal and the second signal;
A comparison unit that compares the frequency ratio measured by the frequency ratio measurement unit with a target value of the frequency ratio;
A filter disposed after the comparison unit;
A control amount calculation unit for obtaining a control amount of the oscillation unit based on a comparison result of the comparison unit; and
The control amount calculation unit is a first circuit unit that outputs the comparison result of the comparison unit multiplied by a predetermined value, and
A second circuit unit group composed of a plurality of second circuit units that perform different predetermined number of integrations on the comparison result of the comparison unit;
A third circuit unit group composed of a plurality of third circuit units that perform different predetermined number of differentiations on the comparison result of the comparison unit, and at least two different circuit units selected from the third circuit unit group,
A frequency synthesizer, wherein at least one of a frequency and a phase of the first signal of the oscillation unit is adjusted based on the control amount obtained by the control amount calculation unit.   The frequency synthesizer according to claim 5, wherein the filter is arranged after the control amount calculation unit.   The frequency synthesizer according to claim 1, wherein the comparison unit performs signal processing with a signed binary number expression.   8. The frequency ratio measurement unit according to claim 1, further comprising: a frequency delta sigma modulation unit that performs frequency delta sigma modulation on one of the first signal and the second signal. Frequency synthesizer.   The frequency synthesizer according to claim 8, wherein the frequency delta-sigma modulation unit outputs an output signal in a bit stream format.   The frequency synthesizer according to claim 8, wherein the frequency delta-sigma modulation unit outputs an output signal in a data stream format.   The frequency synthesizer according to any one of claims 8 to 10, wherein the frequency ratio measurement unit includes a plurality of the frequency delta sigma modulation units connected in parallel.   The frequency ratio measuring unit shifts a phase between the plurality of frequency delta sigma modulation units with respect to at least one of the first signal and the second signal input to the plurality of frequency delta sigma modulation units. The frequency synthesizer of Claim 11 which has a part.   The frequency synthesizer according to claim 1, wherein the oscillating unit includes a digital-analog converter that converts a digital signal into an analog signal, and a voltage-controlled oscillator.   The frequency synthesizer according to claim 1, wherein the oscillation unit includes a digitally controlled oscillator.

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