JP2017098811A - Modulation equipment, modulator and switchover method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide modulation equipment, a modulator and a switchover method, preventing a level fluctuation and the occurrence of an error due to a phase difference in modulation data at a switchover from an operating device to a standby device.SOLUTION: Modulation equipment 1000 includes a plurality of modulators 1, 2 which include: RF carrier phase adjustment units 13, 23 which adjusts RF carrier phases; modulation data generation units 14, 24 which generate modulation data; and clock phase adjustment units 16, 26 adjusts clock phases input to the modulation data generation units 14, 24; and a switchover unit 3 which, based on the match of the phases of the RF carriers and the clocks of an operating modulator and a standby modulator, switches from the operating modulator to the standby modulator.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a modulation device, a modulator, and a switching method, and more particularly, to a redundant configuration modulation device including a plurality of modulators, a modulator, and a switching method.

  The redundant modulation device detects the phase difference between the RF (Radio Frequency) carrier of the modulator of the active device and the modulator of the standby device, and rotates the phase of the RF carrier of the standby device to rotate the phase of the RF carrier of the active device It has a function to switch to a spare device after matching.

  This type of switching control technique is disclosed in Patent Document 1, for example. The broadcast transmission system described in Patent Document 1 detects a phase from a broadcast signal output from each of a plurality of transmitters, and the broadcast signal based on the phase difference detection result for the plurality of transmitters. Are instructed so that their output phases coincide with each other.

JP 2014-171081 A

  If the sampling frequency used to sample the input signal of the latter device (power amplifier, etc.) is high, if there is a phase difference in the modulation data of the input signal, the latter device detects the level fluctuation of the input signal and an error occurs. May occur. The above-mentioned Patent Document 1 does not disclose a configuration that can solve the problem of preventing the level fluctuation and the error occurrence due to the phase difference of the modulation data.

  It is a main object of the present invention to provide a modulation device, a modulator, and a switching method for preventing level fluctuations and errors due to a phase difference of modulation data in a redundant configuration modulation device.

  The modulation device of the present invention includes an RF carrier phase adjustment unit that adjusts the phase of an RF carrier, a modulation data generation unit that generates modulation data, and a clock phase adjustment unit that adjusts the phase of a clock input to the modulation data generation unit And a switching unit that switches from the current modulator to the spare modulator based on the coincidence of the phase of the RF carrier and clock of the working modulator and the spare modulator.

  The modulator of the present invention includes an RF carrier phase adjustment unit that adjusts the phase of an RF carrier, a modulation data generation unit that generates modulation data, and a clock phase adjustment unit that adjusts the phase of a clock input to the modulation data generation unit And having.

  The switching method of the present invention includes an RF carrier phase adjustment unit that adjusts the phase of an RF carrier, a modulation data generation unit that generates modulation data, and a clock phase adjustment unit that adjusts the phase of a clock input to the modulation data generation unit A switching method for switching a plurality of modulators, wherein the next spare modulator to be used is identified, and the current modulation is applied to the RF carrier phase adjustment unit and the clock phase adjustment unit of the spare modulator. Instructing the RF carrier and clock of the device to match the phase of the RF carrier and clock, and from the current modulator based on the phase match of the RF carrier and clock of the active modulator and the spare modulator Switch to the spare modulator.

  According to the present invention, it is possible to prevent level fluctuations and errors due to a phase difference of modulation data in a modulation device having a redundant configuration.

FIG. 1 is a block diagram showing the configuration of the first embodiment. FIG. 2 is a block diagram showing a configuration of the clock phase adjustment unit of FIG. FIG. 3 is a flowchart showing the switching operation of FIG. FIG. 4 is a block diagram illustrating a configuration of a modified example of the clock phase adjustment unit. FIG. 5 is a block diagram showing a configuration of another modification of the clock phase adjustment unit.

  FIG. 1 is a block diagram showing the configuration of the first embodiment. As shown in FIG. 1, the modulation apparatus 1000 includes a plurality of modulators 1 and 2, and a current modulator to a spare modulator based on the coincidence of phases of RF carriers and clocks of the current modulator and the spare modulator. The switching part 3 which switches to is provided. Each of the plurality of modulators 1 and 2 includes modulation units 11 and 21 that modulate modulation data with an RF carrier, RF carrier generation units 12 and 22 that generate an RF carrier, and an RF carrier that adjusts the phase of the RF carrier. Phase adjustment units 13 and 23 are provided. Each of the modulators 1 and 2 includes modulation data generation units 14 and 24 that generate modulation data, clock generation units 15 and 25 that generate clocks used to generate modulation data, and clock phase adjustment. Clock phase adjustment units 16 and 26 for performing the operation.

  The switching unit 3 identifies the next modulator to be used as the active unit among the plurality of modulators in the modulator 1000, and adjusts the RF carrier phase adjustment unit and clock phase adjustment of the spare unit modulator. Is instructed to match the phase of the RF carrier and the clock with the modulator of the working machine. When the switching unit 3 determines that the RF carrier and clock phases of the modulator of the current machine and the standby machine are the same, the switching unit 3 switches from the modulator of the current machine to the modulator of the standby machine.

  FIG. 2 is a block diagram showing a configuration of the clock phase adjustment unit of FIG. As shown in FIG. 2, the clock phase adjustment units 16 and 26 are output from the phase adjustment units 161 and 261 that adjust the phase of the clock signal input from the clock generation units 15 and 25 and the phase adjustment units 161 and 261, respectively. Clock dividers 162 and 262 that divide the signal and output it to the modulation data generators 14 and 24 are provided. As shown in FIG. 2, the clock phase adjusters 16 and 26 are connected to the outputs of the phase adjusters 161 and 261 and the outputs of the phase adjusters 261 and 161 of other modulators, and compare the phase of the signals. Clock phase control units 163 and 263 for controlling the phase adjustment units 161 and 261.

  The phase adjustment units 161 and 261 apply, for example, a high frequency clock input from the clock generation unit 25, for example, a 10 MHz clock, and a mounted high frequency oscillator, for example, a 10 MHz oscillator, to a PLL (Phase Lock Loop), and a 10 MHz clock without jitter. This is a PLL circuit that can generate and adjust the phase according to the input voltage.

  The clock phase control units 163 and 263 are, for example, circuits that output a voltage corresponding to the phase difference between two input signals.

  When the clock phase control unit 163 or 263 is used next, the clock phase control unit 163 or 263 matches the phase of the signal of the currently used modulator with the signal output from the phase adjustment unit 161 or 261 of its own device. The phase adjustment units 161 and 261 are controlled. Further, the clock phase control units 163 and 263 match the phase of the switching unit 3 when the phase of the signal of the currently active modulator and the phase of the signal output from the phase control units 161 and 261 of the own unit match. Report that.

  Next, the operation of this embodiment will be described. FIG. 3 is a flowchart showing the switching operation of FIG. First, the switching unit 3 specifies the modulator of the spare machine that will be the active machine next (step S1). The switching unit 3 instructs the RF carrier phase adjustment unit and the clock phase adjustment unit of the specified modulator to match the RF carrier phase and the clock phase of the active unit and the standby unit (step S2). Assuming that the current machine is the modulator 1 and the next spare machine to be the current machine is the modulator 2, the switching unit 3 instructs the RF carrier phase adjustment unit 23 and the clock phase adjustment unit 26 of the modulator 2.

  The clock phase adjustment unit 26 instructed from the switching unit 3 acquires the internal signal before frequency division from the clock phase adjustment unit 16 of the active machine (step S10). Then, the clock phase adjustment unit 26 instructed by the switching unit 3 compares the phase with the internal signal before frequency division in the clock phase adjustment unit 26 of the modulator 2 which is the own unit (step S11). The clock phase adjustment unit 26 compares the phases of the internal signals before frequency division by the clock phase adjustment unit to determine whether the phases of the current machine and the standby machine match (step S12). The phase of the internal signal in the clock phase adjustment unit 26 of the modulator 2 which is a machine (preliminary machine) is adjusted (step S13). If they match, it reports to the switching unit 3 that the clock phases match (step S14).

  Also, the RF carrier phase adjustment unit 23 instructed from the switching unit 3 acquires an RF carrier from the RF carrier generation unit 12 of the active machine (step S20). Then, the RF carrier phase adjustment unit 23 instructed from the switching unit 3 compares the phase with the RF carrier from the RF carrier generation unit 22 of the modulator 2 which is the own unit (step S21). The RF carrier phase adjustment unit 23 determines whether the phase of the RF carrier matches between the active machine and the spare machine (step S22). If not, the RF carrier of the modulator 2 that is the own machine (spare machine) Is adjusted (step S23). If they match, it reports to the switching unit 3 that the phase of the RF carrier matches between the active machine and the standby machine (step S24).

  The switching unit 3 determines whether the phases of both the RF carrier and the clock are the same between the active machine and the standby machine (step S3). If it is determined that the phases of both the RF carrier and the clock are the same between the active machine and the spare machine, the active machine and the spare machine are switched (step S4). Whether the phases of the RF carriers coincide with each other is determined based on a report from the RF carrier phase adjustment unit 23 of the modulator 2 of the standby machine that is the current machine. Similarly, whether or not the phases of the clocks are the same is determined based on a report from the clock phase adjustment unit 26 of the modulator 2 of the standby machine that is the next active machine.

  As described above, according to the present embodiment, the phase adjustment unit of the next active modulator changes the phase of the signal before frequency division of its own device before the frequency division of the currently active modulator. Control to match the phase of the signal. This makes it possible to match the phase of the clock, which is a reference for generating modulation data, with the accuracy of the signal before frequency division between the current machine and the spare machine. At the same time, the phase of the RF carrier is matched between the current machine and the spare machine. If it is determined that the phases of both the RF carrier and the clock are the same between the active machine and the spare machine, the active machine and the spare machine are switched. Therefore, when switching between the active machine and the spare machine, it is possible to reliably suppress occurrence of errors and output level fluctuations.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  For example, in the above-described embodiment, the clock phase control units 163 and 263 of the clock phase adjustment units 16 and 26 use the outputs of the phase adjustment units 161 and 261 and the outputs of the phase adjustment units 261 and 161 of other modulators. Although described as being connected, it is not limited to this. For example, as shown in FIG. 4, the clock phase control unit 363 of the clock phase adjustment unit 36 and the clock phase control unit 463 of the clock phase adjustment unit 46 are input to the phase adjustment units 361 and 461 and the phase adjustment units of other modulators. The phase adjustment units 361 and 461 may be controlled in accordance with the phase difference between the signals.

  In the above-described embodiment, the clock phase control unit has been described as comparing the output or input phase of the phase adjustment unit and controlling the phase to match, but as illustrated in FIG. In some cases, the outputs of the high-frequency PLL units 561 and 661 are input to the low-frequency PLL units 562 and 662. In such a configuration, the outputs of the high-frequency PLL units 561 and 661 in the previous stage are input to the clock phase control unit, and the clock phase control unit matches these phases. FIG. 5 is a block diagram showing a configuration of another modification of the clock phase adjustment unit. In this modification, the outputs of the high-frequency PLL units 561 and 661 are input to the low-frequency PLL units 562 and 662, the clocks output from the low-frequency PLL units 562 and 662 are divided, and the clocks used for generating modulation data It is an example of the structure which produces | generates. As shown in FIG. 5, the clock phase adjustment units 56 and 66 of the present modification include high-frequency PLL units 561 and 661, low-frequency PLL units 562 and 662, clock phase control units 563 and 663, and a clock divider unit. 162, 262.

  The high frequency PLL units 561 and 661 are free from jitter by applying a high frequency clock input from the clock generation units 15 and 25, for example, a 10 MHz clock, and a high frequency oscillator mounted on the high frequency PLL units 561 and 661, for example, a 10 MHz oscillator, to the PLL. Generate a high-frequency clock.

  The low-frequency PLL units 562 and 662 use this high-frequency clock to generate a low-frequency clock, for example, FS4, as a clock reference necessary for data generation. The low-frequency PLL units 562 and 662 compare the phase of the generated low-frequency clock, for example, FS4, with the FS4 oscillator mounted in the low-frequency PLL units 562 and 662, and adjust the phase to reduce the jitter-free clock. Output as a frequency clock.

  The clock dividers 162 and 262 divide the low-frequency clock input from the low-frequency PLL units 562 and 662, for example, FS4, generate a clock necessary for data generation, and supply the modulated data generators 14 and 24 to the modulated data generators 14 and 24. Output.

  It is assumed that the working machine is the modulator 1 and the next spare machine that becomes the working machine is the modulator 2. At the time of switching operation, in response to an instruction from the switching unit 3, the clock phase control unit 663 of the clock phase adjustment unit 66 of the modulator 2 of the standby unit that will be the next active unit has a high frequency PLL unit 561 of the modulator 1 that is the active unit. The clock phase control unit 663 of the spare machine receives a high frequency clock output from, for example, a 10 MHz clock. Then, the clock phase control unit 663 performs phase comparison with a high-frequency clock, for example, a 10 MHz clock, by the high-frequency PLL unit 661 of the modulator 2 that is a spare machine. As a result, the phase is adjusted on the side of the modulator 2 that is a spare unit, and the phase matches that of the high-frequency clock of the modulator 1 that is the active unit. Even if the high-frequency clock is divided in the subsequent stage to generate the low-frequency clock necessary for data generation, the phase with the current machine is not shifted. Therefore, the phase of the modulation data does not deviate from that of the current machine. By adjusting the phase of the clock that is the reference for data generation in this way, the phase of the modulated data can be matched between the current machine and the standby machine, and further by adjusting the RF carrier phase, Error generation and output level fluctuation can be suppressed.

  Like the configuration of this modification, the output of the high-frequency PLL unit is input to the low-frequency PLL unit, the clock output from the low-frequency PLL unit is divided, and the clock used for generating modulation data is generated. In this case, the phase adjustment of the clock on the active machine side and the clock on the standby machine side can be performed with accuracy of a high frequency clock, for example, 10 MHz clock.

DESCRIPTION OF SYMBOLS 1, 2 Modulator 3 Switching part 11, 21 Modulation part 12, 22 RF carrier generation part 13, 23 RF carrier phase adjustment part 14, 24 Modulation data generation part 15, 25 Clock generation part 16, 26, 36, 46, 56 , 66 Clock phase adjustment unit 161, 261, 361, 461 Phase adjustment unit 162, 262 Clock division unit 163, 263, 363, 463, 563, 663 Clock phase control unit 561, 661 High frequency PLL unit 562, 662 Low frequency PLL Part 1000 Modulator

Claims (7)

An RF carrier phase adjustment unit for adjusting the phase of the RF carrier;
A modulation data generation unit for generating modulation data;
A clock phase adjustment unit for adjusting the phase of the clock input to the modulation data generation unit;
A plurality of modulators having:
A switching unit for switching from the current modulator to the spare modulator based on the phase match of the RF carrier and the clock of the current modulator and the spare modulator;
A modulation device. The clock phase adjustment unit
A phase adjustment unit for adjusting the phase of the clock signal input from the clock generation unit;
A frequency divider that divides the signal output from the phase adjuster and outputs the signal to the modulated data generator;
A clock phase control unit that is connected to the phase adjustment unit of the active modulator and the backup modulator and controls the phase adjustment unit of the backup modulator by comparing the phase of the input signal;
The modulation device according to claim 1. The modulation device according to claim 2, wherein the clock phase adjustment unit is connected to an output of the phase adjustment unit of the active modulator and the spare modulator. The modulation device according to claim 2, wherein the clock phase adjustment unit is connected to an input of the phase adjustment unit of the current modulator and the spare modulator. The phase adjustment unit is configured to input the output of the high frequency PLL unit to the low frequency PLL unit,
The modulation device according to claim 2, wherein the clock phase adjustment unit is connected to an output of a high-frequency PLL unit of the active modulator and the spare modulator. An RF carrier phase adjustment unit for adjusting the phase of the RF carrier;
A modulation data generation unit for generating modulation data;
A clock phase adjustment unit for adjusting the phase of the clock input to the modulation data generation unit;
Modulator. A plurality of modulations having an RF carrier phase adjustment unit that adjusts the phase of an RF carrier, a modulation data generation unit that generates modulation data, and a clock phase adjustment unit that adjusts the phase of a clock input to the modulation data generation unit A switching method for switching the vessel,
Next, identify the active spare modulator,
Instructing the RF carrier phase adjustment unit and the clock phase adjustment unit of the spare modulator to match the phases of the RF carrier and the clock with the current modulator,
Switching from the working modulator to the spare modulator based on the phase match of the RF carrier and the clock of the working modulator and the spare modulator;
Switching method.

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