JP2017067960A - Display controller, method for controlling display controller, and display control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain reduction in power consumption while preventing generation of drop frames.SOLUTION: A level controller lowers the performance level of a CPU which controls different types of processing of a display (1) including a display driver (12) from a first time point (S13) in a frame period (P3) to a second time point (S15) in one frame period (P3) before a time point (S17) when transfer of image data ends, and restores the performance level of the CPU after the second time point.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a display control device and the like.

  When displaying a moving image, a so-called frame drop phenomenon may occur in which at least one frame image among a plurality of images constituting the moving image is not displayed (drawing in response to a drawing update request is not performed). When the number of dropped frames (image data) increases, the image data is not displayed, and the display becomes solid. For this reason, techniques for suppressing the occurrence of dropped frames have been developed. As an example of the technique, the invention described in Patent Document 1 can be cited.

  In the playback device of Patent Document 1, 60 FPS (frame per second) video data is output to a GPU (Graphics Processor Unit) when conditions set according to the acquired main processor capability are satisfied. On the other hand, when the condition is not satisfied, 30 FPS moving image data is output to the GPU.

JP 2011-171857 A (published September 1, 2011)

  In the technique of Patent Document 1, since it is necessary to reduce the frame rate more than necessary in order to sufficiently prevent frame dropping, there is a concern that the display quality of the image may be deteriorated. Therefore, it is impossible to prevent frame dropping while displaying an image with appropriate display quality. Further, in the technique of Patent Document 1, it may be possible to prevent frame dropping by increasing the performance level of the main processor, but this causes a problem of increasing the power consumption of the display device. As described above, the technique of Patent Document 1 cannot achieve both reduction of power consumption and prevention of frame dropping.

  The present invention has been completed to solve the above problems. The purpose is to realize a display control device or the like that can achieve both reduction in power consumption and prevention of frame dropping.

  A display control apparatus according to an aspect of the present invention is a display control apparatus that performs display control of an image displayed on a display panel, and transfers image data indicating an image for one frame displayed on the display panel. An instruction unit for instructing the transfer device, and the display control device from a first time point in one frame period to a second time point before the end of transfer of the image data in the one frame period. And a level control unit that lowers the performance level of the control device that controls various processes of the device including the level controller and restores the performance level of the control device after the second time point has elapsed. .

  A control method for a display control device according to an aspect of the present invention is a control method for a display control device that performs display control of an image displayed on a display panel, and an image for one frame displayed on the display panel. An instruction process for instructing the transfer device to transfer the image data shown from the first time point in one frame period to a second time point before the end of the transfer of the image data in the one frame period And a level control step of lowering the performance level of the control device that controls various processes of the device including the display control device and restoring the performance level of the control device after the second time point has elapsed. It is characterized by.

  According to one embodiment of the present invention, both reduction in power consumption and prevention of frame dropping can be achieved.

It is a block diagram which shows the structure of the display driver which concerns on embodiment of this invention. It is a block diagram which shows the structure of the display apparatus which concerns on embodiment of this invention. It is a timing chart which shows the control method by the display apparatus which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

(Schematic configuration of the display device 1)
First, a schematic configuration of the display device 1 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration of the display device 1 of the present embodiment. As shown in FIG. 2, the display device 1 includes a host 10 (display control device), a liquid crystal module 20, and a communication connection unit 30. Here, the case where the display device 1 is a mobile terminal will be described as an example. However, the present invention is not limited to this, and the display device 1 may be a stationary display device.

  The host 10 controls the display operation of the liquid crystal panel 21 (display panel), and includes an application execution unit 11, a display driver 12 (display control device), an image processing / output HW (hardware) 13 (transfer device), and a performance. A control unit 14 (level control unit), a clock / voltage control unit 15 and a timer 16 are provided.

  The application execution unit 11 generates image data by executing various applications that run on the mobile terminal. In addition, the application execution unit 11 issues a drawing update request, which is an image update request indicated by the generated image data, and transmits the drawing update request to the display driver 12. Here, unless otherwise specified, the image data means image data for one frame displayed on the liquid crystal panel 21.

  The display driver 12 performs display control of an image displayed on the liquid crystal panel 21. Specifically, when receiving a drawing update request from the application execution unit 11, the display driver 12 transmits an image transfer start instruction, which is an instruction to start transferring image data to the liquid crystal driver 22, to the image processing / output HW 13. Further, the display driver 12 receives from the image processing / output HW 13 a transfer end interrupt indicating that the transfer of the image data to the liquid crystal panel 21 in response to the drawing update request has ended. The display driver 12 transmits the image transfer start instruction to the image processing / output HW 13 by confirming reception of the transfer end interrupt.

  Further, the display driver 12 receives a Vsync interrupt from the liquid crystal driver 22. The Vsync interrupt is a signal used by the liquid crystal driver 22 to instruct the host 10 to start transferring image data of the next frame.

  The display device 1 includes a CPU (Central Processing Unit) (not shown). The display driver 12 transmits a performance change instruction (Qos (Quality of service) signal) for instructing a change in the performance level of the CPU to the performance control unit 14 as necessary. The CPU performance is a parameter related to the processing capability (processing speed) of the CPU, such as a clock frequency and a voltage value set in the CPU.

  The performance control unit 14 controls the lower limit value of the CPU performance level in accordance with the performance change instruction received from the display driver 12. This control includes processing for increasing or decreasing the lower limit value of the performance level. The performance control unit 14 receives similar performance change instructions from other members (not shown), and transmits a performance control instruction indicating the maximum value of the lower limit of the performance level determined according to each performance change instruction to the clock / voltage control unit 15. To do. When the performance control unit 14 lowers the CPU performance level, the performance control unit 14 can also reduce the CPU performance level to zero (that is, stop the CPU). The state in which the performance level of the CPU is zero is hereinafter referred to as a PC state (Power Collapse) state.

  The image processing / output HW 13, the clock / voltage control unit 15, and the timer 16 of the host 10 are realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like. The image processing / output HW 13, the clock / voltage control unit 15, and the timer 16 operate independently of the CPU.

  The image processing / output HW (hardware) 13 transfers (transmits) the image data to the liquid crystal driver 22 via the communication connection unit 30. Specifically, when receiving an image transfer start instruction from the display driver 12, the image processing / output HW 13 transmits image data to the liquid crystal driver 22 at the timing of receiving a Vsync interrupt from the liquid crystal driver 22. . By transmitting the image data at this timing, the occurrence of tearing in the liquid crystal panel 21 can be suppressed. The image processing / output HW 13 transmits a transfer end interrupt to the display driver 12 at the timing when the transfer of the image data to the liquid crystal driver 22 is completed. The image processing / output HW 13 sends image data to the liquid crystal module 20 via the communication connection unit 30.

  The clock / voltage control unit 15 controls the performance level of the CPU. Specifically, the clock / voltage control unit 15 changes the lower limit value of the performance level currently set in the CPU to the lower limit value of the performance level indicated by the performance control instruction received from the performance control unit 14. In addition, the clock / voltage control unit 15 controls the performance level of other hardware included in the display device 1 (the size of the clock frequency, voltage value, etc. set in the hardware).

  The timer 16 is activated when it receives an activation instruction transmitted from a member outside the timer 16 (for example, the display driver 12), and measures the elapsed time from that point. When the measurement time reaches the time designated at the start instruction, a predetermined completion interrupt indicating that the time measurement by the timer 16 is completed is transmitted to the external member that transmitted the start instruction to the timer 16.

  The liquid crystal module 20 displays an image indicated by the image data transferred from the host 10. The liquid crystal module 20 includes a liquid crystal panel 21 and a liquid crystal driver 22. The liquid crystal panel 21 and the liquid crystal driver 22 are disposed on a flexible printed circuit board and are physically connected to each other.

  The liquid crystal panel 21 includes a plurality of pixels and displays an image indicated by the image data based on the image data and the drive signal. Instead of the liquid crystal panel 21, an organic EL (electroluminescence) display, a plasma display, or the like may be used.

  The liquid crystal driver 22 controls the display operation of the liquid crystal panel 21 and, together with the image data received from the host 10, a drive signal (for example, a source signal, a gate signal, etc.) for driving the liquid crystal panel 21 is displayed on the liquid crystal panel. 21 is a chip to be supplied to 21. Specifically, the liquid crystal driver 22 includes a frame memory (not shown), a TG (timing generator), and the like. The frame memory is, for example, a video random access memory (VRAM) that can store one frame of image data. The received image is written into the frame memory. Then, the image data is read from the frame memory and output to the liquid crystal panel 21 in accordance with the timing indicated by the TG. The TG generates the drive signal and supplies it to the liquid crystal panel 21, and determines the timing for reading image data from the frame memory in accordance with the drive timing of the liquid crystal panel 21. Further, the TG generates a Vsync interrupt and transmits it to the host 10.

  The communication connection unit 30 includes a transmission line for connecting the host 10 and the liquid crystal module 20. The transmission line is a line (wiring or optical fiber or the like) for transferring a signal. The communication connection unit 30 is, for example, a communication interface conforming to MIPI (registered trademark, Mobile Industry Processor Interface) standard. However, the specification of the communication interface is not limited to this, and the communication connection unit 30 may include a transmission line. That is, the communication connection unit 30 only needs to be able to transmit at least image data from the image processing / output HW 13 to the liquid crystal driver 22 and to transmit a Vsync interrupt from the liquid crystal driver 22 to the image processing / output HW 13 and the display driver 12.

(Detailed configuration of display driver 12)
FIG. 1 is a block diagram showing the display driver of this embodiment. The display driver 12 includes an image transfer instruction unit 31 (instruction unit), a level control time calculation unit 32 (control unit), and a level control unit 33.

  The image transfer instruction unit 31 controls the transfer of the image data generated by the application execution unit 11 to the image processing / output HW 13. Specifically, upon receiving a drawing update request from the application execution unit 11, the image transfer instruction unit 31 transmits an image transfer start instruction to the image processing / output HW 13.

  The level control time calculation unit 32 calculates a time for controlling the performance level of the CPU (hereinafter, level control time) and notifies the level control unit 33 of the time. Details of this calculation will be described later.

  When the calculation of the level control time is completed, the level control unit 33 transmits a performance change instruction to the performance control unit 14. The level control unit 33 starts the timer 16 by simultaneously outputting a start instruction to the timer 16. At that time, the level control unit 33 notifies the timer 16 of the calculated level control time, thereby instructing the timer 16 to measure the elapsed time until the level control time is reached.

  The host 10 further includes a Vsync counter (not shown). The Vsync counter holds a predetermined value representing the elapsed time from the start time of the current frame period. The value of the Vsync counter is reset (becomes zero) when the current frame period is started, and then incremented by one for a certain time. The value of the Vsync counter at the end of the frame period is the counter maximum value Cm, which is treated as a value representing the length of one frame period (about 8.3 milliseconds in this embodiment).

(Details of control method in display device 1)
FIG. 3 is a timing chart showing a control method by the display device according to the embodiment of the present invention. As shown in this figure, when the display device 1 starts image drawing processing, the liquid crystal driver 22 first transmits a Vsync interrupt to the host 10 (S1). Thereby, the frame period P1 is started. In this embodiment, since the display device 1 displays an image at a 120 frame rate, the length of each frame period is 1/120 seconds (about 8.3 milliseconds).

  Although not shown, the display driver 12 receives a new image update request from the application execution unit 11 immediately after the start of the frame period P1. In response to this, the image transfer instruction unit 31 transmits an image transfer start instruction for instructing transfer of new image data to the image processing / output HW 13 at any point in time in the frame period P1 (S2, Instruction process). In response to this, the image processing / output HW 13 transfers the image data to the liquid crystal module 20 in the frame period P2 next to the current frame period P1. That is, no image data is transferred in the current frame period P1.

  Thereafter, the image transfer instruction unit 31 transmits an instruction completion notification to the level control time calculation unit 32. In response to this, the level control time calculation unit 32 checks the current state T1 of the image processing / output HW13. Specifically, the level control time calculation unit 32 checks whether the image processing / output HW 13 is currently transferring image data. As shown in FIG. 3, the image processing / output HW 13 does not transfer image data in the frame period P1. Therefore, the level control time calculation unit 32 confirms that the image data is not being transferred as the state T1.

  The level control time calculation unit 32 further acquires the current value (counter value C1) of the Vsync counter. Based on the state T1 of the image processing / output HW 13 (that image data is not being transferred) and the current value of the Vsync counter (counter value C1), the level control time calculation unit 32 performs level control according to the following equation (1). Calculate time.

Level control time = (Cm−C1) ÷ Cm × Tf + Tf−α (1)
Here, Cm is the maximum counter value that can be taken by the Vsync counter. Tf is the length (time) of one frame period. α is a predetermined constant, and represents a length (time) from a point in time before the end of transfer of image data in one frame period to the end point of the one frame period.

  The level control time calculation unit 32 notifies the level control unit 33 of the calculated level control time. In response to this, the level control unit 33 transmits a start instruction to the timer 16 and transmits a performance change instruction to the performance control unit 14 (S3, level control step). As a result, the timer 16 starts and continues to measure the elapsed time until the level control time designated by the level control unit 33 is reached. On the other hand, the performance control unit 14 transmits to the clock / voltage control unit 15 a performance control instruction for shifting the CPU to the PC state. In response to this, the clock / voltage control unit 15 shifts the CPU to the PC state. As a result, the CPU stops the operation, and the PC state becomes valid in the display device 1 (S4). Thereby, the power consumption of the subsequent display apparatus 1 is reduced.

  Thereafter, the liquid crystal driver 22 transmits the next Vsync interrupt to the host 10 (S5). As a result, the frame period P1 ends and the next frame period P2 starts. At this time, the PC state is still valid. Accordingly, at this time, the display driver 12 is stopped. On the other hand, since the image processing / output HW 13 can operate independently of the control by the CPU, the image data transfer starts based on the image transfer start instruction received from the display driver 12 in the previous frame period P1 (S6).

  In the frame period P2, when a certain time has elapsed since the start of image data transfer, the elapsed time from the start of the timer 16 reaches the level control time set in the timer 16. Thereby, the timer 16 transmits a completion interrupt to the display driver 12 (S6), and then stops the operation.

  In FIG. 2 and FIG. 3, it is described that a completion interrupt is transmitted from the timer 16 to the display driver 12 for simplification of explanation. This means that the display driver 12 returns to the operable state again by the completion interrupt output from the timer 16. Actually, the completion interrupt from the timer 16 is transmitted to CPU control hardware (CPU control unit) (not shown), which transmits an instruction to release the PC state of the CPU to the clock / voltage control unit 15. As a result, a predetermined clock and voltage are supplied to the CPU, thereby releasing the PC state of the CPU, that is, the CPU becomes operable, and the CPU is activated.

  When the CPU is activated, the PC state of the display device 1 is released again (S8). Here, the CPU performance level is restored to the original level. After this, the CPU continues to be prohibited from falling into the PC state. The release of the PC state occurs before the completion of the transfer of the image data in the frame period P2, and the transfer of the image data continues after the release. When completing the transfer of the image data, the image processing / output HW 13 transmits a transfer end interrupt to the display driver 12 (S9).

  Although not shown, the display driver 12 receives a new image update request from the application execution unit 11 during transfer of image data in the frame period P2. After S9, since the CPU is prohibited from falling into the PC state, the CPU maintains a state in which the CPU can react to the interrupt in a short time. Therefore, the display driver 12 receives the transfer end interrupt. Thus, it is possible to promptly respond to a new drawing update request from the application execution unit 11. That is, the image transfer instruction unit 31 transmits an image transfer start instruction for instructing transfer of the next image data to the image processing / output HW 13 within the frame period P2 after S9 (S10). Thus, when the display driver 12 receives a drawing update request from the application execution unit 11 in the frame period P2, the display driver 12 can output an image transfer start instruction to the image processing / output HW 13 within the same frame period P2. That is, the transmission of the image transfer start instruction does not shift to the next frame period P3, so that frame dropping can be prevented.

  After S10, the image transfer instruction unit 31 outputs an instruction completion notification to the level control time calculation unit 32. Thereafter, the liquid crystal driver 22 transmits the next Vsync interrupt to the host 10 (S11). As a result, the frame period P2 ends and the next frame period P3 starts. Since the image processing / output HW 13 has received an image transfer start instruction from the display driver 12 in the previous frame period P2, transfer of the next image data starts from the start of the frame period P3 (S12).

  Here, an example is shown in which the level control time calculation unit 32 starts calculating the level control time when a certain time has elapsed from the start of the current frame period P3. In this example, first, the state T2 of the image processing / output HW 13 in the current frame period P3, that is, whether the image processing / output HW 13 is transferring image data is checked. As shown in FIG. 3, the image processing / output HW 13 is transferring image data when the level control time calculation unit 32 starts calculating the level control time in the frame period P3. Therefore, the level control time calculation unit 32 confirms that the image data is being transferred as the state T2.

  The level control time calculation unit 32 further acquires the current value (counter value C2) of the Vsync counter. The level control time calculation unit 32 calculates the level control time according to the following equation (2) based on the state T1 (transfer of image data) of the image processing / output HW 13 and the current value (counter value C2) of the Vsync counter. calculate.

Level control time = (Cm−C2) ÷ Cm × Tf−α (2)
Here, Cm is the same as Tf, and α is the same as in equation (1).

  The level control time calculation unit 32 notifies the level control unit 33 of the calculated level control time. In response to this, the level control unit 33 transmits a start instruction to the timer 16 and transmits a performance change instruction to the performance control unit 14 (S13). As a result, the timer 16 starts and continues to measure the elapsed time until the level control time designated by the level control unit 33 is reached. On the other hand, the performance control unit 14 transmits a performance control instruction for shifting the CPU to the PC state to the clock / voltage control unit 15 unless there is an instruction to set a lower limit value of the performance level from another member (not shown). To do. In response to this, the clock / voltage control unit 15 shifts the CPU to the PC state. As a result, the CPU can stop the operation, and the PC state becomes valid in the display device 1 (S14). In this example, as shown in FIG. 3, the PC state becomes valid during the transfer of the image data.

  In the frame period P3, when a certain time has elapsed since the start of image data transfer, the elapsed time from the start of the timer 16 reaches the level control time set in the timer 16. Thereby, the timer 16 transmits a completion interrupt to the display driver 12 (S15). Thereby, the CPU becomes operable by the above-described procedure, that is, the PC state of the CPU is released (S16). As a result, the display driver 12 can operate again under the control of the CPU.

  Since the release of the PC state occurs before the completion of the transfer of the image data in the frame period P2, the transfer of the image data is continued after the release. When completing the transfer of the image data in the frame period P3, the image processing / output HW 13 transmits a transfer end interrupt to the display driver 12 (S17).

  In the frame period P3, the display driver 12 has not received a drawing update request from the application execution unit 11. Accordingly, after receiving the transfer end interrupt in the frame period P3, the display driver 12 does not transmit a next image transfer start instruction to the display driver 12.

  The frame period P3 ends while the PC state is released. The liquid crystal driver 22 transmits the next Vsync interrupt to the host 10 (S18), thereby starting the next frame period. Since the image processing / output HW 13 has not received an image transfer start instruction in the previous frame period P3, it does not transfer image data in the current frame period. After the start of the current frame period, the PC state is continued without being released without updating the drawing of the image.

  The performance control unit 14 outputs a performance control instruction for shifting the CPU to the PC state to the clock / voltage control unit 15 when there is no image drawing update for a certain period. As a result, the PC state of the CPU becomes valid (S19), and the subsequent power consumption of the display device 1 is reduced.

(Advantages of the display device 1)
As shown in FIG. 3, the display device 1 starts from the start start time (S3, third time) of the timer 16 after the transmission time (S2) of the image transfer start instruction in the frame period P1 (one frame period). Until the completion of the timer 16 in the frame period P2 (S7, second time point), the CPU state of the CPU becomes valid. Thereby, the power consumption of the display apparatus 1 within this period is reduced. Further, after the timer 16 is completed, the CPU state of the CPU is immediately released (the CPU is in an operable state), so that the display driver 12 performs the next operation (S10) before the end of the frame period P2. The image transfer start instruction can be output to the image processing / output HW 13. As a result, the image data is reliably transferred in the frame period P3 next to the frame period P2 for which the drawing execution request has been received from the application execution unit 11, so that frame dropping can be prevented.

  As described above, the display device 1 can achieve both reduction in power consumption and prevention of frame dropping. The same applies to the frame period P3. That is, in the frame period P3, the PC state is valid from the start start time (S13, first time) of the timer 16 to the completion time (S15, second time), and the completion time of the timer 16 is reached. After the elapse of time, the PC state of the CPU is immediately released (S16). Therefore, if necessary, the image transfer start instruction is surely transmitted to the image processing / output HW 13 before the end of the frame period P3. Can do.

[Embodiment 2]
The application execution unit 11, the display driver 12, and the performance control unit 14 are realized by software using, for example, a CPU.

  In this case, the display device 1 includes a CPU (control device that controls various processes of the display device 1 (device) including the host 10) that executes instructions of a program (display control program) that is software that implements each function, ROM (Read Only Memory) or storage device (these are referred to as “recording media”) in which programs and various data are recorded so as to be readable by a computer (or CPU), RAM (Random Access Memory) for expanding the programs, etc. I have. And the objective of this invention is achieved when a computer (or CPU) reads the said program from the said recording medium and runs it. As the recording medium, a “non-temporary tangible medium” such as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. The program may be supplied to the computer via an arbitrary transmission medium (such as a communication network or a broadcast wave) that can transmit the program. The present invention can also be realized in the form of a data signal embedded in a carrier wave in which the program is embodied by electronic transmission.

  Note that the application execution unit 11, the display driver 12, and the performance control unit 14 may be realized by hardware.

[Summary]
A display control apparatus according to aspect 1 of the present invention is a display control apparatus that performs display control of an image displayed on a display panel, and transfers image data indicating an image for one frame displayed on the display panel. An instruction unit for instructing the transfer device, and the display control device from a first time point in one frame period to a second time point before the end of transfer of the image data in the one frame period. And a level control unit that lowers the performance level of the control device that controls various processes of the device including the level controller and restores the performance level of the control device after the second time point has elapsed. .

  According to said structure, since the performance level of a control apparatus falls from the 1st time point to the 2nd time point in 1 frame period, power consumption is reduced. Furthermore, since the performance level of the control device is restored after the second time has elapsed, the processing of the instruction unit is not delayed. As a result, since the instruction unit can instruct the control device to transfer new image data after the second time point has elapsed, there is no omission of transfer of image data in each frame period. Thereby, it is possible to prevent the occurrence of frame dropping of images.

  As described above, according to the display control apparatus of the present invention, it is possible to achieve both reduction of power consumption and prevention of frame dropping.

  The display control device according to aspect 2 of the present invention is the display control device according to aspect 1, wherein the level control unit includes the transfer device at a third time after the time when the instruction unit instructs the transfer device to transfer the image data. When the image data is transferred, the performance level is lowered from the third time point in the current one frame period to the second time point in the current one frame period. It is said.

  According to the configuration described above, the display control apparatus can start a decrease in the performance level of the control apparatus at an appropriate timing after instructing the transfer apparatus to transfer the image data.

  The display control apparatus according to aspect 3 of the present invention is the display control apparatus according to aspect 1, wherein the level control unit includes the transfer device at a third time after the time when the instruction unit instructs the transfer device to transfer the image data. Is not transferring the image, from the third time point in the current one frame period to the second time point in the next one frame period of the current one frame period, It is characterized by lowering the performance level.

  According to said structure, since the performance level of a control apparatus can be reduced for a longer period, power consumption can be reduced more.

  The display control device according to aspect 4 of the present invention is characterized in that, in any one of the above aspects 1 to 3, the level control unit stops the control device when the performance level is lowered.

  According to said structure, since a control apparatus stops for a fixed period within 1 frame period, power consumption can be reduced to the maximum.

  A control method for a display control device according to aspect 5 of the present invention is a control method for a display control device that performs display control of an image displayed on a display panel, wherein an image for one frame displayed on the display panel is displayed. An instruction process for instructing the transfer device to transfer the image data shown from the first time point in one frame period to a second time point before the end of the transfer of the image data in the one frame period And a level control step of lowering the performance level of the control device that controls various processes of the device including the display control device and restoring the performance level of the control device after the second time point has elapsed. It is characterized by.

  According to the above configuration, it is possible to achieve both reduction in power consumption and prevention of frame dropping.

  Furthermore, the display control apparatus according to each aspect of the present invention may be realized by a computer. In this case, the display control apparatus is operated by causing the computer to operate as each unit (software element) included in the display control apparatus. A display control program for a display control apparatus realized by a computer and a computer-readable recording medium on which the display control program is recorded also fall within the scope of the present invention.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention. A new technical feature can also be formed by combining the technical means disclosed in each embodiment.

1 Display device (device including display control device) 12 Display driver (display control device)
21 Liquid crystal panel (display panel) 31 Image transfer instruction section (instruction section)
32 level control time calculation unit (level control unit) 33 level control unit

Claims (6)

A display control device that performs display control of an image displayed on a display panel,
An instruction unit that instructs the transfer device to transfer image data indicating an image of one frame displayed on the display panel;
Various processes of the apparatus including the display control apparatus are controlled from a first time point in one frame period to a second time point before the end of transfer of the image data in the one frame period. A display control device comprising: a level control unit that lowers the performance level of the control device and restores the performance level of the control device after the second time point has elapsed.   The level control unit, when the transfer device is transferring the image data at a third time after the time when the instruction unit instructs the transfer device to transfer the image data, The display control apparatus according to claim 1, wherein the performance level is decreased from the third time point to a second time point in the current one frame period.   The level control unit, when the transfer device is not transferring the image at a third time after the time when the instruction unit instructs the transfer device to transfer the image data, 2. The display according to claim 1, wherein a performance level of the control device is lowered from the third time point to the second time point in the next one frame period after the current one frame period. Control device.   The display control apparatus according to claim 1, wherein the level control unit stops the control apparatus when the performance level is lowered. A control method of a display control device that performs display control of an image displayed on a display panel,
An instruction step for instructing a transfer device to transfer image data indicating an image of one frame displayed on the display panel;
Various processes of the apparatus including the display control apparatus are controlled from a first time point in one frame period to a second time point before the end of transfer of the image data in the one frame period. A control method for a display control device, comprising: a level control step of reducing the performance level of the control device and restoring the performance level of the control device after the second time point has elapsed.   A display control program for causing a computer to function as the display control device according to claim 1, wherein the display control program causes the computer to function as an instruction unit and a level control unit.

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