JP2017062758A - Control system and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control system capable of preventing degradation of control capacity and resolution in a piece of equipment to be controlled irrespective of increase of capacity of an execution program.SOLUTION: The control system has an input-output module 126 that includes: a condition determination section that determines whether or not an interrupt condition associated with an interrupt program is satisfied; and an interrupt program execution section that executes the interrupt program when the condition determination section determines that the interrupt condition is satisfied. The calculation module 122 includes non-interrupt program execution section that refers to an execution result by the interrupt program execution section and executes a non-interrupt program.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a control system and a control method including an arithmetic module and an input module.

  In a large-scale control system, a programmable controller in which necessary functions are distributed among a plurality of modules may be employed from the viewpoint of system configuration and ease of maintenance. The programmable controller is composed of, for example, a plurality of types of modules such as an arithmetic module, a communication module, an input / output module (input module + output module), and a power supply module, and the number of modules can be changed according to the control target. , Enhance the maintenance and expandability of the system.

  In a programmable controller, for example, a communication module downloads an execution program for executing an application to an arithmetic module, and the arithmetic module uses the downloaded execution program to input data from a lower controlled device through an input / output module. Collecting and executing arithmetic processing are performed, and the arithmetic result is transmitted to a lower-level controlled device through an input / output module (for example, Patent Document 1).

JP 2014-120187 A

  As described above, in the programmable controller, the arithmetic module controls other modules and lower-level controlled devices using the execution program. Processing of an arithmetic module based on such an execution program is roughly divided into interrupt processing executed based on the establishment of the interrupt condition and non-interrupt processing that is not subject to time restrictions due to the interrupt processing. . In the arithmetic module, non-interrupt processing is executed periodically, and when the interrupt condition is satisfied, the interrupt processing is executed preferentially, and the remaining time other than the interrupt processing is effectively used to perform the non-interrupt processing. Was running.

  However, with the diversification of applications, the capacity of execution programs has increased, and the processing time for both interrupt processing and non-interrupt processing has become longer, making it difficult to complete within the expected processing time. . Here, if the non-interrupt processing cycle is simply lengthened, the information update frequency is also lowered, leading to deterioration in the control capability and resolution of the controlled device. In addition, since the processing result of the interrupt process is also transmitted to the input / output module only periodically, the timing at which the processing result of the interrupt process is transmitted is delayed with an increase in the period of the non-interrupt process.

  Therefore, in view of such a problem, the present invention provides a control system and a control method capable of preventing deterioration of control capability and resolution of a controlled device regardless of increase in the capacity of an execution program. It is aimed.

  In order to solve the above problems, the control system of the present invention includes an input module for inputting data from the outside, and an arithmetic module connected to the input module through a bus and performing an operation based on data received from the input module. Then, the program executed in the control system includes an interrupt program triggered by the establishment of the interrupt condition and a non-interrupt program excluding the interrupt program. A condition determination unit that determines whether or not an associated interrupt condition is satisfied, and an interrupt program execution unit that executes an interrupt program when it is determined that the interrupt condition is satisfied The arithmetic module includes a non-interrupt program execution unit that refers to an execution result of the interrupt program execution unit and executes a non-interrupt program. To.

  You may further provide the program replication part which replicates an interruption program to an input module at a predetermined opportunity.

  The predetermined trigger is when the arithmetic module and the input module are activated, and the program duplicating unit may duplicate the interrupt program from the arithmetic module to the input module.

  The input module may further include a history notification unit that transmits information indicating that the interrupt process is completed to the arithmetic module when the interrupt program execution unit completes the interrupt process based on the interrupt program.

  The input module includes an AD converter that converts an external analog signal into a digital signal, and an AD control circuit that performs conversion control of the AD converter, and the interrupt program execution unit performs arbitrary digital processing during the execution of the interrupt program. When a signal is required, the AD control circuit executes AD converter conversion control, and after the AD converter conversion is completed, only a digital signal is normalized to generate a normalized digital signal, and an interrupt program is generated by the normalized digital signal. May be executed.

  The input module includes a DA converter that converts a digital signal to an analog signal and outputs the analog signal to the outside, and a DA control circuit that performs conversion control of the DA converter. The interrupt program execution unit is in the middle of executing the interrupt program. When an arbitrary digital signal is generated, only the arbitrary digital signal may be denormalized to generate a denormalized digital signal, and the DA control circuit may be caused to execute conversion control of the DA converter by the denormalized digital signal. .

  The input module includes an AD converter that converts an external analog signal into a digital signal, and an AD control circuit that performs conversion control of the AD converter, and the AD control circuit executes conversion control of the AD converter at a predetermined cycle. Holds the converted digital signal, and the interrupt program execution unit normalizes and normalizes only the arbitrary digital signal held in the AD control circuit when an arbitrary digital signal is required during the execution of the interrupt program A digital signal may be generated and the interrupt program may be executed with the normalized digital signal.

  The input module includes a DA converter that converts a digital signal to an analog signal and outputs the analog signal to the outside, and a DA control circuit that performs conversion control of the DA converter. The interrupt program execution unit is in the middle of executing the interrupt program. When an arbitrary digital signal is generated, only the arbitrary digital signal is denormalized to generate a denormalized digital signal, and the non-normalized digital signal is held in the DA control circuit. Conversion control of the DA converter may be executed by a signal.

  The input module includes a first input module and a second input module, and the bus includes a first bus that connects the arithmetic module and the first input module, and a second bus that connects the arithmetic module and the second input module. The arithmetic module inputs data from the first input module through the first bus at every predetermined tact time, and the interrupt program execution unit of the second input module has a predetermined timing not related to the tact time. The data of the second input module may be input to the arithmetic module through the second bus.

  The arithmetic module outputs data to the first input module through the first bus at every predetermined tact time, and outputs data to the second input module through the second bus at a predetermined timing not related to the tact time. May be.

  The first bus may be a serial transmission method, and the second bus may be a parallel transmission method.

  A book using a control system comprising an input module for inputting data from the outside, and an arithmetic module connected to the input module through a bus and performing an operation based on data received from the input module, in order to solve the above problem In the control method of the invention, the program executed in the control system includes an interrupt program triggered by the establishment of the interrupt condition, and a non-interrupt program excluding the interrupt program. It is determined whether the interrupt condition associated with the interrupt program is satisfied. If it is determined that the interrupt condition is satisfied, the interrupt program is executed, and the operation module executes the execution result of the interrupt program. And a non-interrupt program is executed.

  According to the present invention, it is possible to prevent deterioration in control capability and resolution of a controlled device regardless of increase in the capacity of an execution program.

It is the external view which showed the rough connection relation of each apparatus which comprises a control system. It is explanatory drawing which showed the schematic structure of the control system. It is a timing chart for demonstrating the timing of the process based on an execution program. It is a figure which shows an example of the hardware constitutions of a calculation module. It is a figure which shows an example of the hardware constitutions of an input / output module. It is a timing chart explaining the flow of processing of an arithmetic module and an input / output module. It is explanatory drawing for demonstrating the process of a program duplication part. It is explanatory drawing for demonstrating the flow of a process of a non-interrupt program execution part and an interrupt program execution part. It is the block diagram which showed the structure of the input / output part. It is a timing chart which showed an example of processing of an interruption program. It is the timing chart which showed the other example of the processing of the interruption program. It is the timing chart which showed the further another example of the processing of the interruption program. It is a timing chart for explaining an example of non-interrupt processing. It is a timing chart for explaining other examples of non-interrupt processing.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiment are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are not illustrated. To do.

(First embodiment: control system 100)
FIG. 1 is an external view showing a schematic connection relationship of each device constituting the control system 100, and FIG. 2 is an explanatory diagram showing a schematic configuration of the control system 100. The control system 100 includes a management device 110, a programmable controller 120, and a controlled device 130. In addition, the management device 110 and the programmable controller 120 are connected to each other by a network wiring 140 based on Ethernet (registered trademark) such as a Giga (G) base. Furthermore, the programmable controller 120 and the controlled device 130 are connected to each other through a dedicated connection wiring 142 so that communication and signal transmission are possible.

  The management device 110 collectively controls the plurality of programmable controllers 120 so that the entire control system 100 operates in accordance with a process defined in the application. For example, the management apparatus 110 collects status information and control results from the individual programmable controllers 120, and outputs various control commands to the individual programmable controllers 120 according to the collected contents.

  The programmable controller 120 is also called a PLC (Programmable Logic Controller), and includes a plurality of modules such as an arithmetic module 122, a communication module 124, an input / output (I / O) module 126, and a power supply module 128 as shown in FIG. Consists of. Each module is detachably fixed to the base board, and each module except the power supply module 128 is connected through a bus on the base board. For example, a serial transmission type first bus (not shown) and a parallel transmission type second bus (not shown) are prepared as such buses. In the present embodiment, the plurality of input / output modules 126 are connected to the arithmetic module 122 through either the first bus or the second bus, respectively.

  Here, the arithmetic module 122 downloads an execution program, which is a program divided for each programmable controller 120, from the management device 110 in order to realize an application defined in the control system 100, and executes the execution program. Or the operation status of the programmable controller 120 is displayed on a monitor (not shown). At that time, the controlled device 130 is controlled based on the control command received from the management device 110, the sensor detection result of the controlled device 130 input through the input / output module 126, and the like.

  The communication module 124 is connected to the management apparatus 110, the other programmable controller 120, and another module through the network wiring 140 by Ethernet (registered trademark), and can establish communication with each other.

  The input / output module 126 is a module in which an input module that performs input management from the controlled device 130 (external) and an output module that manages output to the controlled device 130 are combined. For example, if the controlled device 130 is a sensor, the sensor detection result is collected, and if the controlled device 130 is an electric motor, a control command represented by a discrete is transmitted and the control result is collected. The power supply module 128 supplies power to each module such as the arithmetic module 122, the communication module 124, and the input / output module 126.

  The controlled device 130 includes, for example, sensors that detect various states in FA (Factory Automation), and electric devices such as an electric motor and an encoder that operate according to detection results of the sensors.

  Such a control system 100 can be applied to various control objects. For example, when the control system 100 is applied to a production execution system (MES), a motion control unit, a center sealer unit, and a film unit as the controlled device 130 are used. The programmable controller 120 is connected to production equipment such as (Film Unit). Then, the arithmetic module 122 of the programmable controller 120 takes in the operation state of the production equipment from the input / output module 126 as input data, processes the input data using the execution program, and then issues a command to the production equipment through the input / output module 126. Do. Such an application is realized by the following execution program.

  FIG. 3 is a timing chart for explaining processing timing based on the execution program. In general, the processing of the arithmetic module 122 based on the execution program includes an interrupt process (a process triggered by the establishment of the interrupt condition) executed based on the establishment of the interrupt condition in the input / output module 126, and an interrupt. It is broadly divided into non-interrupt processing that is not subject to time restrictions due to interrupt processing. Here, a program used for interrupt processing is an interrupt program, and a program used for non-interrupt processing is a non-interrupt program. In the present embodiment, a condition based on an input state (for example, a state of a discrete signal or a count value) to the input / output module 126 will be described as an interrupt condition.

  For example, as shown in FIG. 3A, the arithmetic module 122 executes non-interrupt processing periodically (for example, every tact time 20 msec) using a non-interrupt program, and inputs data at the beginning of the cycle. At the end of the cycle, the processing result is output. Here, when the interrupt condition is satisfied in the input / output module 126, the arithmetic module 122 preferentially executes the interrupt process using the interrupt program as shown in FIG. Execute the non-interrupt process using the available time effectively. Specifically, when an interrupt process occurs, the non-interrupt process is interrupted until the interrupt process ends, and the non-interrupt process is resumed after the interrupt process ends. At the end of the cycle, the processing results of the interrupt processing and non-interrupt processing are output.

  However, when the capacity of the execution program for realizing the application increases with the diversification of the application, the time spent for the interrupt process becomes longer and the surplus time becomes shorter as shown in FIG. On the other hand, as with the interrupt process, the time spent for the non-interrupt process becomes longer, but the process cannot be completed within the reduced time. Here, if the cycle for executing the non-interrupt processing is simply lengthened, the surplus time can be prolonged, but the information update frequency is lowered, and the control capability and resolution of the controlled device 130 are deteriorated. . In particular, since the processing result of the interrupt processing is also transmitted to the input / output module 126 only periodically (only at the end of the cycle), an interrupt that requires an immediate reaction that changes the control method when a predetermined upper and lower limit value is reached. Even in the case of processing, the reaction becomes slow as the period of non-interrupt processing becomes longer.

  Therefore, in this embodiment, part or all of the interrupt processing is performed by another module (here, the input / output module 126), and the arithmetic module 122 mainly performs non-interrupt processing (remaining interrupt processing). To achieve distributed processing. For example, as shown in FIG. 3C, suddenly generated interrupt processing is completely executed in the input / output module 126, and in parallel, non-interrupt processing is periodically executed by the arithmetic module 122. . With this configuration, even when an interrupt process requiring an immediate reaction occurs, the interrupt process is quickly executed in the input / output module 126 without being affected by the cycle of the non-interrupt process in the arithmetic module 122. Since the result can be reflected immediately, it is possible to prevent deterioration of the control capability and resolution of the controlled device 130 regardless of the increase in the capacity of the execution program.

  In the present embodiment, an interrupt program for performing such an interrupt process is automatically arranged in the input / output module 126 at a predetermined timing, such as at the time of activation. With this configuration, it is possible to avoid complicated installation work for each module, and it is possible to immediately start the interrupt process even when the input / output module 126 is newly installed or replaced. Hereinafter, the hardware configurations of the arithmetic module 122 and the input / output module 126 that realize such an object will be described in detail.

(Calculation module 122)
FIG. 4 is a diagram illustrating an example of a hardware configuration of the arithmetic module 122. 4 includes an I / F unit 150, a nonvolatile memory 152, a shared memory 154, a specific memory 156, and a control unit 158.

  The I / F unit 150 can establish communication with the communication module 124 and the input / output module 126 through the first bus and the second bus, and can communicate with the management device 110 and other programmable controllers 120 through the communication module 124. it can.

  The non-volatile memory 152 includes a storage medium such as a ROM, EEPROM, flash memory, and HDD, and holds a system program that is a basic program for operating the computer, and an execution program (non-interrupt program and interrupt program). . The shared memory 154 is configured by a storage medium such as a RAM, and stores input data and output data updated by the control unit 158 executing a non-interrupt program. The I / F unit 150, the nonvolatile memory 152, and the shared memory 154 are connected to be accessible via a common bus 160. Therefore, the non-volatile memory 152 and the shared memory 154 also accept access from other modules.

  For example, when a memory area that can be used as a shared work area is divided and allocated to each module, the shared memory 154 is associated with the allocated memory area. Therefore, there is no memory of another module in the memory area allocated to the arithmetic module 122, and when the memory area is accessed, only the shared memory 154 of the arithmetic module 122 can be read or written.

  Like the shared memory 154, the private memory 156 is configured by a storage medium such as a RAM, and stores input data and internal data updated by the control unit 158 executing a non-interrupt program. However, the private memory 156 is not connected to the common bus 160 and can be accessed only from the control unit 158. Such access restriction to the memory can be realized by a decoder using an FPGA (Field-Programmable Gate Array) or the like.

  The control unit 158 includes a semiconductor integrated circuit including a central processing unit (CPU) and the like, reads a non-interrupt program from the non-volatile memory 152, develops it in the specific memory 156, and executes a non-interrupt process. The control unit 158 functions as functional units such as a program duplication unit 170, a non-interrupt program execution unit 172, and a history management unit 174. The operation of the functional unit will be described in detail later.

(I / O module 126)
FIG. 5 is a diagram illustrating an example of a hardware configuration of the input / output module 126. In this embodiment, a plurality of input / output modules 126 are prepared. Here, the input / output module 126 that operates at a relatively high speed among the plurality of input / output modules 126 will be described. The input / output module 126 illustrated in FIG. 5 includes an I / F unit 180, a nonvolatile memory 182, a shared memory 184, a specific memory 186, an input / output unit 188, and a control unit 190.

  The I / F unit 180 establishes communication with the arithmetic module 122, the communication module 124, and the input / output module 126 through the first bus and the second bus.

  The nonvolatile memory 182 includes a storage medium such as a ROM, an EEPROM, a flash memory, and an HDD (Hard Disk Drive), and holds a system program. The shared memory 184 includes a storage medium such as a RAM, and stores an interrupt program that is a part of the execution program, input data, and output data that is updated when the control unit 190 executes the interrupt program. The I / F unit 180, the nonvolatile memory 182, the shared memory 184, and the input / output unit 188 are connected to each other via a common bus 192. Therefore, the nonvolatile memory 182 and the shared memory 184 also accept access from other modules. However, the arrangement location of each of the plurality of shared memories 184 may be a module having a high access frequency to the shared memory 184. For example, since the input / output module 126 has a high access frequency to the shared memory 184, the shared memory 184 is arranged in the input / output module 126.

  Like the shared memory 184, the private memory 186 is configured by a storage medium such as a RAM, and stores input data and internal data that is updated when the control unit 190 executes an interrupt program. However, the private memory 186 is not connected to the common bus 192 and can be accessed only from the control unit 190.

  The input / output unit 188 is connected to the controlled device 130 and performs communication and signal transmission with the controlled device 130. For example, the input / output unit 188 includes an FPGA, an AD converter, a DA converter, a photocoupler, a transistor, and the like, and inputs / outputs analog signals, digital signals, rectangular waves (counter input), and the like. In particular, for analog signals, as described later, the individual conversion control for the AD converter and the DA converter is performed by the FPGA, thereby distributing the processing load.

  The control unit 190 is composed of a semiconductor integrated circuit including a central processing unit (CPU) having the same specifications as the arithmetic module 122. The control unit 190 reads an interrupt program from the shared memory 184, develops it in the private memory 186, and performs interrupt processing. Run. The control unit 190 also functions as functional units such as the condition determination unit 200, the interrupt program execution unit 202, and the history notification unit 204. The operation of the functional unit will be described in detail later. Hereinafter, the processing flow of the arithmetic module 122 and the input / output module 126 for performing the duplication processing of the interrupt program to the input / output module 126 and the interrupt processing will be described.

(Program replication processing S300)
FIG. 6 is a timing chart for explaining the flow of processing (control method) of the arithmetic module 122 and the input / output module 126. When the control system 100 is activated and the supply of power to the arithmetic module 122 and the input / output module 126 is started, the control unit 158 of the arithmetic module 122 and the control unit 190 of the input / output module 126 each have a unique system program. The program copying unit 170 of the arithmetic module 122 expands the memories 156 and 186, and the interrupt program among the execution programs stored in the nonvolatile memory 152 is copied to the input / output module 126 in response to the activation (S300). ). Note that the interrupt program in the non-volatile memory 152 is not deleted by the duplication and is held as it is.

  FIG. 7 is an explanatory diagram for explaining the processing of the program duplicating unit 170. For example, the execution program in the control system 100 can be divided into six independent programs (not affected by other programs), which are divided into three non-interrupt programs and interrupt program 3 Suppose that However, at this point, each of the six programs has been compiled and is in an executable format. The program duplicating unit 170 duplicates three of these interrupt programs to the input / output module 126 connected to the controlled device 130 controlled by the interrupt program.

  Here, each interrupt program is given a replication status, which is information relating to the interrupt processing. Therefore, the program duplicating unit 170 reads the duplication status attached to the interrupt program, and if the identifier of the input / output module 126 is registered as a duplication destination, the program duplicating unit 170 stores the duplication status in the input / output module 126 specified by the identifier. Duplicate the interrupt program associated with the replication status. The input / output module 126 holds the interrupt program received from the arithmetic module 122 at a predetermined memory location in the shared memory 184. Note that the replication status includes an interrupt port number and an interrupt condition in addition to the identifier. Here, the interrupt port number indicates the number of the port (interrupt terminal) to be interrupted in the input / output unit 188, and the interrupt condition is input to the condition for generating the interrupt, for example, the interrupt port number Whether the discrete signal is TRUE or FALSE, or whether the count value obtained by counting the output signals from the servo, etc. has reached a predetermined value is shown.

  In the example of FIG. 7, since the identifiers of the interrupt program (1) and the interrupt program (2) are “1”, the program duplicating unit 170 determines that the interrupt program (1) and the interrupt program (2) Is copied to a predetermined memory location in the shared memory 184 of the input / output module (1) specified by the identifier “1”. Since the identifier of the interrupt program (3) is “2”, the program duplicating unit 170 shares the interrupt program (3) with the input / output module (2) identified by the identifier “2”. Copy to memory 184.

  Subsequently, the program duplication unit 170 secures a memory area as a work area for each interrupt program. Specifically, as shown in FIG. 7, the program duplicating unit 170 duplicates the interrupt program (1) to the shared memory 184 of the input / output module (1) and is predetermined for the interrupt program (1). A memory area (1) having a sufficient capacity is secured in the shared memory 184 of the input / output module (1). Similarly, the program duplication unit 170 secures a memory area (2) having a predetermined capacity for the interrupt program (2) in the shared memory 184 of the input / output module (1), and the interrupt program (3). A memory area (3) having a predetermined capacity is secured in the shared memory 184 of the input / output module (2).

(Non-interrupt program setting process S302)
FIG. 8 is an explanatory diagram for explaining the flow of processing of the non-interrupt program execution unit 172 and the interrupt program execution unit 202. As described above, when the duplication of the interrupt program is completed, the non-interrupt program execution unit 172 of the arithmetic module 122 prepares to execute the non-interrupt program. Specifically, the non-interrupt program execution unit 172 reads the non-interrupt programs (1) to (3) from the nonvolatile memory 152 and expands them in the private memory 156 as shown in FIG.

(Interrupt program setting process S304)
Similarly, when duplication of the interrupt program is completed as described above, the interrupt program execution unit 202 of the input / output module 126 prepares for execution of the interrupt program. Specifically, as shown in FIG. 8, the interrupt program execution unit 202 of the input / output module (1) reads the interrupt programs (1) and (2) from the shared memory 184 and expands them in the private memory 186. Similarly, the interrupt program execution unit 202 of the input / output module (2) reads the interrupt program (3) from the shared memory 184 and expands it in the private memory 186.

(Non-interrupt program execution process S310)
Subsequently, the non-interrupt program execution unit 172 executes the non-interrupt program using the non-interrupt program expanded in the private memory 156. Here, the non-interrupt program execution unit 172 refers to the execution result of the interrupt program execution unit 202 of the input / output module 126 described later (reads data from the shared memory 184) as necessary, for example, every 20 msec. The execution result of the non-interrupt program is derived.

(Condition determination process S312)
The condition determining unit 200 determines whether or not an interrupt condition associated with the interrupt program is satisfied. Referring to the replication status in FIG. 7, in this embodiment, interrupt conditions “1234”, “TRUE”, and “5678” are associated with interrupt programs (1) to (3), respectively. Therefore, the condition determination unit 200 of the input / output module (1) refers to the count value specified according to the operation of the servo or the like specified by the interrupt port number “1”, and the count value is “1234”. If it matches, it is determined that the interrupt condition of the interrupt program (1) is satisfied. Once it is determined that the interrupt condition is satisfied, the count value is reset to zero.

  Similarly, the condition determination unit 200 of the input / output module (1) refers to the discrete signal specified by the interrupt port number “3”, and if the discrete signal is TRUE, the interrupt determination of the interrupt program (2). It is determined that the inclusion condition is satisfied. The condition determination unit 200 of the input / output module (2) refers to the count value specified according to the operation of the servo or the like specified by the interrupt port number “1”, and the count value is “5678”. If it matches, it is determined that the interrupt condition of the interrupt program (3) is satisfied.

(Interrupt program execution process S314)
When the condition determining unit 200 determines that a predetermined interrupt condition is satisfied, the interrupt program executing unit 202 executes an interrupt program corresponding to the interrupt condition. For example, when the condition determination unit 200 of the input / output module (1) determines that the count value specified by the interrupt port number “1” has reached “1234”, the interrupt program execution unit 202 sets the interrupt program (1) is executed. The interrupt program execution unit 202 stores the processing result of the interrupt process based on the interrupt program (1) in the memory area (1) secured in the shared memory 184 by the program replication unit 170. In this way, the non-interrupt program execution unit 172 of the arithmetic module 122 can read the processing result from the shared memory 184 at an arbitrary timing.

  Here, the interrupt program execution unit 202 executes the interrupt program independently and with the highest priority without being restricted by the periodic processing by the non-interrupt program execution unit 172, and quickly reflects the processing result. be able to. Therefore, for example, for an interrupt process that requires an immediate reaction that changes the control method when a predetermined upper and lower limit value is reached, the reaction time can be shortened. In addition, since it is not limited by the non-interrupt program execution unit 172 (not affected by the cycle of the non-interrupt process), the interrupt process can be repeatedly executed in a shorter time than the cycle of the non-interrupt process It is also possible to implement interrupt processing at a high frequency. In this way, it is possible to prevent deterioration of the control capability and resolution of the controlled device 130 regardless of the increase in the capacity of the execution program.

  In addition, when an interruption due to a discrete signal occurs in the input / output module 126, the input / output module 126 originally replaces the discrete signal with a bus signal and transmits it to the arithmetic module 122, and the arithmetic module 122 sets the condition. In the present embodiment, the interrupt processing is performed after the determination. In this embodiment, the processing can be completed in the input / output module 126 without replacing with the bus signal, so that the time spent for the interrupt processing itself is shortened. be able to.

(History notification process S316)
When the interrupt program execution unit 202 completes the interrupt process based on the interrupt program, the history notification unit 204 transmits information indicating that the interrupt process has been completed to the arithmetic module 122. This is for managing whether or not the interrupt processing is performed as expected in the arithmetic module 122.

(History management process S318)
When the history management unit 174 receives information indicating that the interrupt processing has been completed from the history notification unit 204, the history management unit 174 manages the information as a history (log), and whether the number and timing of the interrupt processing are within the assumed range. If it is determined whether or not it deviates from the assumed range, an error process is performed assuming that an error has occurred in the interrupt process.

  In the control system 100 described above, the execution program is distributedly processed by the arithmetic module 122 and the input / output module 126, thereby increasing the processing load of the arithmetic module 122 even if the capacity of the execution program is increased. In addition, the interrupt process can be quickly executed at a timing independent of the non-interrupt process, and the control capability and resolution of the controlled device 130 can be prevented from deteriorating.

  In addition, since the interrupt program for performing such interrupt processing is automatically arranged in the input / output module 126 at the time of startup, it is possible to avoid complicated installation work for each module and to newly install the input / output module 126. Alternatively, even in the case of replacement, the interrupt process can be started immediately. Therefore, even if the existing input / output module 126 is replaced with the input / output module 126 in the shipping state in which the execution program is not installed, the same state as the existing input / output module 126 can be quickly restored, so that maintainability is improved. be able to.

(Second Embodiment)
As described above, the processing load of the arithmetic module 122 itself can be reduced by distributing the processing that should be originally executed by the arithmetic module 122 to the input / output module 126. However, on the other hand, the processing load of the input / output module 126 may increase by the processing load reduced by the arithmetic module 122. Therefore, in particular, the processing load on the input / output module 126 that is allocated to the AD converter and the DA converter is reduced, and the processing load on the input / output module 126 is reduced.

  FIG. 9 is a block diagram showing the configuration of the input / output unit 188. The input / output unit 188 of the input / output module 126 includes an AD converter 220, a DA converter 222, and an FPGA 224.

  The AD converter 220 converts an external analog signal into a digital signal. The DA converter 222 converts a digital signal into an analog signal and outputs it to the outside. The FPGA 224 also functions as an AD control circuit 224a that performs conversion control of the AD converter 220 and a DA control circuit 224b that performs conversion control of the DA converter. The AD control circuit 224a is provided with a buffer for holding the digital signal converted by the AD converter 220, and the DA control circuit 224b is provided with a buffer for holding the digital signal to be converted by the DA converter 222. ing.

  FIG. 10 is a timing chart showing an example of interrupt program processing. In the example of FIG. 10, the AD control circuit 224a and the DA control circuit 224b are mainly used, and AD conversion and DA conversion are repeated at a predetermined cycle (for example, 25 μsec), and a digital signal is generated by the AD converter 220 in the middle. As a result, the interrupt program is executed.

  Specifically, the AD control circuit 224a starts conversion control of the AD converter 220 based on a predetermined cycle, for example, at time (a), holds the converted digital signal, and at time (b), the control unit 190 Through normalization, the digital signal is normalized to generate a normalized digital signal.

  Such normalization includes the following processing. In other words, the AD control circuit 224a uses the control unit 190 to convert the analog value adjustment processing for adjusting the offset and gain, which are the hardware characteristics of the AD converter 220, and the output value (for example, 65536) of the AD converter 220 to be used by the interrupt program. A scale conversion process for converting to (for example, 10000) and a moving average process for indicating an average of a plurality of digital values (for example, 8 and 16) in the past are performed.

  Since the AD converter 220 used here has a plurality of channels (for example, four channels) and the digital value of which channel is used by the interrupt program cannot be grasped, normalization is performed for all the plurality of channels. The total time is increased by the number of channels.

  When a series of processing for AD conversion ends, the DA control circuit 224b denormalizes the digital signal held in the buffer of the DA control circuit 224b through the control unit 190 at time (c). A digital signal is generated, and conversion control of the DA converter 222 is executed by the non-normalized digital signal. In this way, an analog signal is output from the DA converter 222.

  Such denormalization includes the following processing. That is, the DA control circuit 224b is a scale conversion process that converts the use range (for example, 10000) of the interrupt program into an output value (for example, 65536) of the DA converter 222 through the control unit 190, and the hardware characteristics of the DA converter 222. Performs analog value adjustment processing to adjust offset and gain.

  Note that the DA converter 222 used here has a plurality of (for example, four) channels, and since it is impossible to grasp which channel output is required by the interrupt program, denormalization is performed for all the plurality of channels. The total time is increased by the number of channels.

  In this way, while AD conversion and DA conversion are repeated at a predetermined cycle, the AD control circuit 224a mainly plays a role in operating the interrupt program. Specifically, the AD control circuit 224a triggers an interrupt process to the control unit 190 when the normalized digital signal is generated, and executes the interrupt program to the interrupt program execution unit 202 from the time point (d). Let Then, when the processing of the normalized digital signal is completed in the interrupt program, at time (e), the DA control circuit 224b holds the normalized digital signal, and the DA control circuit 224b displays the processing result of the interrupt program. This is reflected in the DA converter 222.

  However, in the control unit 190, since the AD converter 220 and the DA converter 222 are periodically performed with accurate time, normalization processing and denormalization processing for all channels of the digital signal are given priority. Therefore, as shown by hatching in FIG. 10, the asynchronous interrupt program is executed exclusively with the digital signal normalization process and the denormalization process. As a result, the interrupt program is interrupted and resumed. Repeatedly, the time until the interrupt program is completed is prolonged, and as a result, the time when the processing result is reflected in the DA converter 222 is delayed.

  Therefore, in the present embodiment, digital signal normalization processing and denormalization processing are kept to the minimum necessary, and even when normalization processing and denormalization processing are executed, only the necessary channels are limited. That frees up time for the interrupt program.

  FIG. 11 is a timing chart showing another example of interrupt program processing. In the example of FIG. 11, the interrupt program execution unit 202 of the control unit 190 is the main body, and performs the minimum necessary AD conversion and DA conversion in response to a request from the interrupt program.

  Specifically, the interrupt program execution unit 202 accesses an analog signal address connected to the AD converter 220, for example, when an arbitrary digital signal is required at the time point (a) during the execution of the interrupt program. Is detected, the AD control circuit 224a is caused to execute conversion control of the AD converter 220. Thus, AD conversion is started from time (b).

  Then, when the conversion of the AD converter is completed, the AD control circuit 224a holds the converted digital signal at the time point (c), normalizes the digital signal through the control unit 190, and generates a normalized digital signal. Such normalization includes analog value adjustment processing, scale conversion processing, and moving average processing as described with reference to FIG.

  However, here, only a channel that requires a digital signal is normalized from among a plurality of channels provided in the AD converter 220. Therefore, the processing time spent for the normalization process is 1 / the number of channels (here, 1/4) compared to FIG. This is due to the following reason. That is, when the interrupt processing is executed by the arithmetic module 122 as in the prior art, the arithmetic module 122 cannot grasp which channel of the input / output module 126 corresponds to an input / output that requires a digital signal. In the example 11, since the interrupt processing is executed by the input / output module 126 itself, it is possible to grasp the correspondence between the input / output that requires a digital signal and the channel.

  Subsequently, the interrupt program execution unit 202 executes the interrupt program using the normalized digital signal. When an arbitrary digital signal is generated as a processing result at the time point (d), the arbitrary digital signal is denormalized. The denormalized digital signal is generated and held in the buffer of the DA control circuit 224b. Such denormalization includes a scale conversion process and an analog value adjustment process, as described with reference to FIG.

  However, here, only a channel for which a digital signal is to be output is denormalized among a plurality of channels provided in the DA converter 222. Therefore, the processing time spent for the denormalization processing is 1 / the number of channels (here, 1/4) compared to FIG.

  Finally, the interrupt program execution unit 202 causes the DA control circuit 224b to execute conversion control of the DA converter 222 by the non-normalized digital signal at the time point (e). In this way, an analog signal is output from the DA converter 222.

  Since the AD conversion and DA conversion are not periodically performed in the process of FIG. 11 as compared with the process of FIG. 10, the digital signal normalization process or the denormalization process associated with the AD conversion or DA conversion is performed. I will not. In addition, the control unit 190 mainly performs normalization processing and denormalization processing only on necessary channels, and does not execute normalization processing or denormalization processing on other channels (the previous value is used as it is). ).

  Therefore, as indicated by hatching in FIG. 11, it can be understood that the interrupt program is terminated in a shorter time than in FIG. 10 without being interrupted by the normalization process or the denormalization process. As described above, in the example of FIG. 11, it is possible to secure the execution time of the interrupt program and to effectively use the resources.

  In other processing, digital signal normalization processing and denormalization processing are kept to the minimum necessary, and even when normalization processing and denormalization processing are executed, they are limited to only necessary channels. Thus, the processing time can be released to the interrupt program accordingly.

  FIG. 12 is a timing chart showing still another example of interrupt program processing. In the example of FIG. 12, the AD control circuit 224a and the DA control circuit 224b are mainly used, and while the AD conversion and DA conversion are repeated at a predetermined cycle (for example, 25 μsec), the interrupt program execution unit of the control unit 190 is in the middle. 202 is the main body, and processes digital signals in response to a request from an interrupt program.

  Specifically, the AD control circuit 224a starts the conversion control of the AD converter 220 based on a predetermined cycle, for example, at the time point (a), and holds the converted digital signal in the buffer. Also, the DA control circuit 224b performs conversion control of the DA converter 222 based on a predetermined cycle independent of the AD control circuit 224a, for example, at a time point (b), by the denormalized digital signal held in the buffer of the DA control circuit 224b. Execute. In this way, an analog signal is output from the DA converter 222. Here, AD conversion and DA conversion excluding normalization processing and non-normalization processing are periodically performed.

  Then, the interrupt program execution unit 202 of the control unit 190, when an arbitrary digital signal is required at the time (c) during the execution of the interrupt program, for example, for the address of the analog signal connected to the AD converter 220 At time (d), the latest digital signal after conversion held in the AD control circuit 224a is read, and the digital signal is normalized to generate a normalized digital signal. Such normalization includes analog value adjustment processing, scale conversion processing, and moving average processing as described with reference to FIG. Here, at the time point (d), the AD converter 220 starts the next conversion. However, since the conversion result is not generated, the previous conversion result is used.

  However, here too, only the channels that require a digital signal among the channels provided in the AD converter 220 are normalized. Therefore, the processing time spent for the normalization process is 1 / the number of channels (here, 1/4) compared to FIG.

  Subsequently, the interrupt program execution unit 202 executes the interrupt program with the normalized digital signal. When an arbitrary digital signal is generated as a processing result at the time point (e), the arbitrary digital signal is denormalized. The denormalized digital signal is generated and held in the buffer of the DA control circuit 224b. Such denormalization includes a scale conversion process and an analog value adjustment process, as described with reference to FIG.

  However, here too, only the channel for which a digital signal is to be output is denormalized from among a plurality of channels provided in the DA converter 222. Therefore, the processing time spent for the denormalization processing is 1 / the number of channels (here, 1/4) compared to FIG.

  Then, the DA control circuit 224b performs conversion control of the DA converter 222 by the denormalized digital signal held in the buffer.

  In the process of FIG. 12 as well, the digital signal normalization process and the denormalization process are not periodically performed as compared with the process of FIG. Further, in AD conversion and DA conversion executed mainly by the control unit 190, normalization processing and denormalization processing are executed only for necessary channels, and normalization processing and denormalization processing for other channels are performed. Is not executed (the previous value is used as it is).

  Therefore, as indicated by hatching in FIG. 12, the interrupt program is not interrupted by normalization processing or denormalization processing, and does not wait for AD conversion. It can be understood that the process is completed in a shorter time compared to FIG. Thus, in the example of FIG. 12, it is possible to secure the execution time of the interrupt program and to further effectively use the resources.

  In addition, since the load of normalization processing and denormalization processing is minimized, the drive time of the control unit 190 is shortened, and heat generation and power consumption can be suppressed.

(Third embodiment)
As described with reference to FIG. 3, the execution program is roughly divided into an interrupt program and a non-interrupt program, and interrupt processing based on the interrupt program can be completely assigned to the input / output module 126. Then, the arithmetic module 122 can acquire the result of the interrupt process from the input / output module 126 by the non-interrupt process based on the non-interrupt program.

  FIG. 13 is a timing chart for explaining an example of non-interrupt processing. First, when an interrupt process occurs at the time point (a), the interrupt program execution unit 202 of the input / output module 126 executes an arithmetic process based on the interrupt program, and the processing result is obtained at the time point (b). It is held in the shared memory 184.

  Subsequently, the arithmetic module 122 periodically executes non-interrupt processing based on the non-interrupt program, and acquires input data from the shared memory 184 of the input / output module 126 at the start time (c). Then, the input data is calculated at a point (d) in the middle of execution of the non-interrupt program, and the output data as the calculation result is held in the shared memory 184 at the end point (e) of the cycle. Finally, the interrupt program execution unit 202 of the input / output module 126 acquires output data from the shared memory 184 at an arbitrary time point (f).

  As described above, by periodically executing the non-interrupt processing, the input / output of data can be accurately synchronized with the tact time. However, the input response time that is processed by the non-interrupt program after the input data is generated and the output response time that is processed by the non-interrupt program until the output data is reflected become long. Such input response time and output response time are affected by tact time. For example, if the number of input / output modules 126 and the number of input / outputs used in the input / output modules 126 increase and the non-interrupt processing becomes longer accordingly, the tact time must be increased, and accordingly, the input response Longer time and output response time. If it does so, there exists a possibility that the control precision and responsiveness of the control system 100 whole may fall.

  Here, when input / output responsiveness is required, a programmable controller 120 is provided separately, and in the independent programmable controller 120, the arithmetic processing and the number of input / outputs are minimized to shorten the tact time. It is also possible to execute input / output processing at high speed and transmit / receive the result via the communication module 124. However, such a method increases the size of the control system 100.

  Therefore, in the programmable controller 120, processing that prioritizes synchronization over responsiveness and processing that prioritizes responsiveness over synchronization are divided, and the bus and the input / output module 126 are individually assigned to each. Specifically, as described above, a plurality of buses such as a serial transmission type first bus and a parallel transmission type second bus are prepared on the base board and connected to different input / output modules 126, respectively. Here, the serial transmission method is a method in which information is sequentially transmitted one bit at a time to a line less than the number of data bits, and the parallel transmission method is a method in which all information is transferred to each line at least for a line having the number of data bits. A method of transmitting simultaneously in parallel.

  For example, an arbitrary input / output module 126 (hereinafter simply referred to as a first input / output module) is connected to the arithmetic module 122 only through the first bus, and an arbitrary other input / output module 126 (hereinafter simply referred to as a second input / output module). Is connected to the arithmetic module 122 only through the second bus. The first input / output module (first input module) through the first bus is processed periodically as shown in FIG. 13, and the second input / output module (second input module) through the second bus is processed. As described below, high-speed processing is performed, and processing that prioritizes such synchronization and processing that prioritizes responsiveness are executed in parallel.

  FIG. 14 is a timing chart for explaining another example of non-interrupt processing. Here, not the periodic process described with reference to FIG. 13 but an interrupt process for starting the process at the timing when the data is generated is performed. When an interrupt process occurs at the time point (a), the interrupt program execution unit 202 of the input / output module 126 executes an arithmetic process based on the interrupt program, and the processing result is shared memory at the time point (b). It is held at 184, and the arithmetic module 122 is notified that the input data is ready (interrupt notification).

  Subsequently, the arithmetic module 122 executes a non-interrupt process based on the non-interrupt program, and receives input data from the shared memory 184 of the input / output module 126 at a time point (c) according to the transmission from the input / output module 126. , The input data is calculated, the output data that is the result of the calculation is held in the shared memory 184 at the end of the cycle (d), and the input / output module 126 is ready for the input data. Communicate (interrupt notice). Finally, the interrupt program execution unit 202 of the input / output module 126 acquires the output data from the shared memory 184 at the time (e) in response to the transmission from the arithmetic module 122.

  Here, interrupt notification is performed at the timing when data is generated, and data is transmitted and received between modules immediately after data is generated, regardless of tact time, so input response time and output response time are shortened It becomes possible to do.

  As described with reference to FIGS. 13 and 14, the following effects can be obtained by executing in parallel the processing that gives priority to synchrony over responsiveness and the processing that gives priority to responsiveness over synchrony. In other words, the first input / output module through the first bus can accurately synchronize the input and output of data with the tact time as usual. In addition, since the input response time and output response time can be shortened by the second input / output module through the second bus, the number of input / output modules 126 and the number of input / outputs used in the input / output module 126 are increased. Even if the non-interrupt process becomes longer and the tact time has to be increased, the control accuracy and responsiveness of the entire control system 100 can be improved.

  As described above, by adopting a plurality of transmission schemes and distributing input / output utilizing each characteristic, it is possible to improve the processing efficiency and versatility of the control system 100 as a whole. In addition, both the synchronism and the quick response can be realized with a small number of modules by the small programmable controller 120.

  Also provided are a program that causes a computer to function as the control system 100, and a storage medium such as a computer-readable flexible disk, magneto-optical disk, ROM, CD, DVD, or BD on which the program is recorded. Here, the program refers to data processing means described in an arbitrary language or description method.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to this embodiment. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Is done.

  For example, in the embodiment described above, for the sake of convenience of explanation, an example in which an interrupt program is used in the input / output module 126 and a non-interrupt program other than the interrupt program is used in the arithmetic module 122 has been described. The interrupt program assigned to the output module 126 may be a part of all the interrupt programs included in the execution program, and the remaining interrupt programs can be used in the arithmetic module 122 itself. Therefore, the non-interrupt programs include all programs except the interrupt program assigned to the input / output module 126.

  Further, in the above-described embodiment, the example in which the program duplication unit 170 is provided in the arithmetic module 122 has been described. However, the present invention is not limited to this, and the input / output module 126, other modules, or the management apparatus 110 is not limited thereto. It may be provided. Similarly, an example in which the interrupt program to be copied is held in the nonvolatile memory 152 of the arithmetic module 122 has been described, but the held memory may be any memory in the control system 100. Good. In the above-described embodiment, an example in which the interrupt program is copied to the input / output module 126 has been described. However, the non-interrupt program is held in one of the memories and the non-interrupt program is triggered at a predetermined opportunity. May be copied to the arithmetic module 122.

  In the above-described embodiment, the control system 100 is started as a predetermined trigger for copying the interrupt program. However, any other timing is not excluded, and various timings are selected. can do. In the above-described embodiment, the example in which the interrupt program is copied to the shared memory 184 of the input / output module 126 every time the control system 100 is activated has been described. However, the input / output module 126 holds the interrupt program. If the memory to be used is non-volatile, it may be determined whether or not the interrupt program has already been duplicated in the memory, and the interrupt program may be duplicated only when it has not been duplicated.

  In the above-described embodiment, the control system 100 has been described as an example, but the present invention can be applied to various devices such as a distributed control device (DCS). In the above-described embodiment, an example is given in which data is input from the outside through the input / output module 126 in which the input module and the output module are combined. However, the output module is not an essential configuration, and at least the input module is included. The present embodiment can be applied.

  In the above-described embodiment, an example in which an interrupt program among the execution programs is copied to the input / output module 126 and the interrupt process is executed by the input / output module 126 has been described. When connected by two buses, a part of the interrupt processing can be further allocated to the arithmetic module 122 to distribute the interrupt processing.

  In the above-described embodiment, the first bus of the serial transmission method and the second bus of the parallel transmission method are described as the plurality of buses. However, the present invention is not limited to this, and the plurality of buses are all serially transmitted. It may be a system or a parallel transmission system. In the above-described embodiment, an example in which the input / output module 126 having the control unit 190 is connected to any bus has been described. However, the input / output module 126 connected to the first bus that does not require responsiveness. May be an input / output module that manages input / output by an FPGA or the like that does not have the control unit 190.

  Note that each step of the control method of the present specification does not necessarily have to be processed in time series in the order described as the timing chart, and may include processing in parallel or by a subroutine.

  The present invention can be used in a control system and a control method including an arithmetic module and an input module.

100 control system 122 arithmetic module 126 input / output module (input module, first input module, second input module)
170 Program replication unit 172 Non-interrupt program execution unit 174 History management unit 200 Condition determination unit 202 Interrupt program execution unit 204 History notification unit 220 AD converter 222 DA converter 224a AD control circuit 224b DA control circuit

Claims (12)

A control system comprising: an input module for inputting data from the outside; and an arithmetic module connected to the input module through a bus and performing an operation based on data received from the input module,
The program executed in the control system includes an interrupt program triggered by the establishment of the interrupt condition, and a non-interrupt program excluding the interrupt program,
The input module is
A condition determination unit for determining whether or not an interrupt condition associated with the interrupt program is satisfied;
When it is determined that the interrupt condition is satisfied, an interrupt program execution unit that executes the interrupt program;
With
The arithmetic module is
A control system comprising a non-interrupt program execution unit that refers to an execution result of the interrupt program execution unit and executes the non-interrupt program.   The control system according to claim 1, further comprising a program duplicating unit that duplicates the interrupt program to the input module at a predetermined opportunity. The predetermined opportunity is when the arithmetic module and the input module are activated,
The control system according to claim 2, wherein the program duplicating unit duplicates the interrupt program from the arithmetic module to the input module.   The input module further includes a history notification unit that transmits information indicating that the interrupt process is completed to the arithmetic module when the interrupt program execution unit completes the interrupt process based on the interrupt program. The control system according to any one of claims 1 to 3. The input module includes an AD converter that converts an external analog signal into a digital signal, and an AD control circuit that performs conversion control of the AD converter,
The interrupt program execution unit
When an arbitrary digital signal is required during the execution of the interrupt program, the AD control circuit executes conversion control of the AD converter,
After the conversion of the AD converter is completed, only the arbitrary digital signal is normalized to generate a normalized digital signal,
The control system according to any one of claims 1 to 4, wherein the interrupt program is executed by the normalized digital signal. The input module includes a DA converter that converts a digital signal into an analog signal and outputs the analog signal, and a DA control circuit that performs conversion control of the DA converter,
The interrupt program execution unit
When an arbitrary digital signal is generated during the execution of the interrupt program, only the arbitrary digital signal is denormalized to generate a denormalized digital signal,
6. The control system according to claim 5, wherein the DA control circuit is caused to execute conversion control of the DA converter by the non-normalized digital signal. The input module includes an AD converter that converts an external analog signal into a digital signal, and an AD control circuit that performs conversion control of the AD converter,
The AD control circuit includes:
Execute conversion control of the AD converter at a predetermined cycle;
Hold the converted digital signal,
The interrupt program execution unit
When an arbitrary digital signal is required during the execution of the interrupt program, only the arbitrary digital signal held in the AD control circuit is normalized to generate a normalized digital signal,
The control system according to any one of claims 1 to 4, wherein the interrupt program is executed by the normalized digital signal. The input module includes a DA converter that converts a digital signal into an analog signal and outputs the analog signal, and a DA control circuit that performs conversion control of the DA converter,
The interrupt program execution unit
When an arbitrary digital signal is generated during the execution of the interrupt program, only the arbitrary digital signal is denormalized to generate a denormalized digital signal,
Holding the non-normalized digital signal in the DA control circuit;
The DA control circuit
8. The control system according to claim 7, wherein conversion control of the DA converter is executed by the non-normalized digital signal. The input module includes a first input module and a second input module;
The bus includes a first bus that connects the arithmetic module and the first input module, and a second bus that connects the arithmetic module and the second input module,
The arithmetic module inputs data from the first input module through the first bus every predetermined tact time,
The interrupt program execution unit of the second input module causes the operation module to input data of the second input module through the second bus at a predetermined timing not related to the tact time. The control system according to any one of claims 1 to 8. The arithmetic module is
Data is output to the first input module through the first bus at every predetermined tact time,
The control system according to claim 9, wherein data is output to the second input module through the second bus at a predetermined timing not related to the tact time. The first bus is a serial transmission method,
The control system according to claim 9 or 10, wherein the second bus is a parallel transmission system. A control method using a control system comprising: an input module that inputs data from outside; and an arithmetic module that is connected to the input module through a bus and performs an operation based on data received from the input module,
The program executed in the control system includes an interrupt program triggered by the establishment of the interrupt condition, and a non-interrupt program excluding the interrupt program,
The input module is
Determining whether an interrupt condition associated with the interrupt program is satisfied;
If it is determined that the interrupt condition is satisfied, the interrupt program is executed,
The arithmetic module is
A control method comprising: executing the non-interrupt program with reference to an execution result of the interrupt program.

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