JP2017058951A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system capable of efficient memory access.SOLUTION: A memory system comprises: a first tag region 4b for storing address information corresponding to data within a first data region 4a; a second tag region 4c for associating and storing the address information with priority information; an access information transmission unit 11 for transmitting access information to a nonvolatile memory; a priority update unit 12 for updating the priority information within the second tag region on the basis of the access information; a first hit determination unit 13 corresponding to the first tag region; a second hit determination unit 14 corresponding to the second tag region; a determination unit 16 for determining storage control information on whether reading object data should be stored in the first data region or not on the basis of a determination result by the second hit determination unit; and an access control unit 17 for performing control to store the reading object data read out from the second data region with lower access priority than the first data region in the first data region.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a memory system.

  As referred to as the memory wall problem, the time required for memory access and the power consumption are major factors that hinder the performance improvement of the arithmetic core.

  For this reason, measures have been taken to increase the capacity or hierarchization of cache memory that is faster than the main memory. In addition, SRAM (Static Random Access Memory), which is generally used as a cache memory, is high-speed but expensive, and therefore studies are being made to use nonvolatile memory such as MRAM (Magnetoresistive RAM) as cache memory. .

  However, the nonvolatile memory generally has a problem that there is a limit to the number of times that data can be rewritten and power consumption during writing is large.

  In addition, as the number of types of data used by the arithmetic core increases, the frequency of data replacement between cache memories in each hierarchy increases, and the number of rewrites increases.

JP 2007-249971 A

  The problem to be solved by the present invention is to provide a memory system capable of efficiently performing memory access.

According to the present embodiment, a first data area for storing data;
A first tag area for storing address information corresponding to the data stored in the first data area;
A second tag area for storing address information and priority information in association with each other;
An access information transmitter for transmitting access information to the nonvolatile memory;
A priority update unit that updates the priority information in the second tag area based on the access information;
A first hit determination unit for determining whether address information of data to be read is stored in the first tag area;
A second hit determination unit for determining whether address information of the data to be read is stored in the second tag area;
A determination unit that determines storage control information related to whether to store the data to be read in the first data area based on a determination result by the second hit determination unit;
When the determination unit determines to store the data to be read in the first data area based on the storage control information, the read from the second data area having a lower access priority than the first data area There is provided a memory system including an access control unit that performs control to store target data in the first data area.

1 is a block diagram showing a schematic configuration of a memory system according to a first embodiment. The block diagram which shows the internal structure of L2 cache by 1st Embodiment. 5 is a flowchart showing processing operations of the memory system according to the first embodiment. The figure which shows the hit / miss determination result of L2 cache in 1st Embodiment. The figure which shows the hit / miss determination result of L1 cache and L2 cache when there is no 2nd tag area. The block diagram which shows schematic structure of the processor system by 2nd Embodiment. The block diagram which shows the internal structure of L2 cache and L3 cache in the memory system by 2nd Embodiment. 9 is a flowchart showing processing operations of the memory system according to the second embodiment. The figure which shows the hit / miss determination result of L2 cache in 2nd Embodiment. The figure which shows the hit / miss determination result of the comparative example when the 2nd tag area | region in L3 cache does not have priority information. 10 is a flowchart showing processing operations of the memory system according to the third embodiment. The figure which shows the example of the 1st tag area | region and 2nd tag area | region integrated physically. The figure which shows the example which provides a 1-bit access flag in a 2nd tag area | region.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the characteristic configurations and operations in the memory system and the processor system will be mainly described. However, configurations and operations omitted in the following description may exist in the memory system and the processor system.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a memory system 1 according to the first embodiment. 1 includes a primary cache memory (L1 cache) 3 connected to a processor core (CPU: Central Processing Unit) 2, and a secondary cache memory (L2 cache) 4 connected to an L1 cache 3. And a main memory 5 connected to the L2 cache 4.

  The L1 and L2 caches 3 and 4 store at least a part of data stored in the main memory 5 or data to be stored in the main memory 5. Each of the caches 3 and 4 has a tag unit that holds address information that can uniquely identify data held therein. There are various types of tag unit implementations, such as those that hold a dedicated memory area and those that hold a part of the memory area that holds data. In this embodiment, all of these can be combined. .

  FIG. 1 shows an example in which a two-level cache memory up to the L2 cache 4 is provided. Hereinafter, for simplification, an example having a two-level cache structure up to the L2 cache 4 will be described.

  The processor core 2, L1 cache 3, and L2 cache 4 other than the main memory 5 are integrated on one chip, for example. Alternatively, the processor core 2 and the L1 cache 3 are integrated on one chip, the L2 cache 4 is integrated on another chip, and these are directly joined by metal wiring based on a stacked structure of chips. Also good. In the present embodiment, the L1 and L2 caches 3 and 4 are referred to as a memory system 1. The main memory 5 may or may not be included in the memory system 1.

  The L1 and L2 caches 3 and 4 are constituted by semiconductor memories that can be accessed at a higher speed than the main memory 5. There are various variations in the data placement policy for each cache. For example, there is an Inclusion method. In this case, all of the data stored in the L1 cache 3 is stored in the L2 cache 4.

  In addition, for example, there is an Exclusion method. In this method, for example, the same data is not arranged in the L1 cache 3 and the L2 cache 4. Further, for example, there is a hybrid method of the inclusion method and the exclusion method. In this method, for example, there is data that is held redundantly in the L1 cache 3 and the L2 cache 4, and there is data that is held exclusively.

  These methods are data arrangement policies between the two caches 3 and 4, and various combinations are conceivable in a multi-level cache configuration. For example, the Inclusion method may be used in all layers. For example, the L1 cache 3 and the L2 cache 4 may be an exclusive method, and the L2 cache 4 and the main memory 5 may be an inclusion method. The system shown in the present embodiment can be combined with the various data arrangement policies described above.

  There are various cache update methods, but this embodiment can be combined with all of them. For example, the write method at the time of cache write hit may be write-through or write-back. Further, the write method at the time of cache write miss may be write allocate or no write allocate.

  The memory capacity of the L2 cache 4 is greater than or equal to the memory capacity of the L1 cache 3. Thus, the higher the cache memory, the larger the memory capacity. Therefore, it is desirable to use a high-level cache memory having a high degree of integration and a low leakage power that tends to be proportional to the capacity. As such a memory, for example, a nonvolatile memory such as an MRAM (Magnetoresistive Random Access Memory) can be considered. For example, an SRAM or DRAM using a low leakage power process may be used.

  Since the main memory 5 has a larger memory capacity than the L1 and L2 caches 3 and 4, the main memory 5 is often composed of one or more chips separate from the chip on which the processor core 2 and the like are mounted. A memory cell constituting the main memory 5 is, for example, a DRAM (Dynamic RAM) cell. It should be noted that the processor core 2 and the like may be mixedly mounted on one chip by using a technique such as TSV (Through Silicon Via).

  The physical address corresponding to the virtual address issued by the processor core 2 is first sent to the L1 cache 3 with the highest priority. When data corresponding to the physical address (hereinafter, target data) is in the L1 cache 3, the processor core 2 accesses the data. The memory capacity of the L1 cache 3 is, for example, about several tens of kilobytes.

  If the target data is not in the L1 cache 3, the corresponding physical address is sent to the L2 cache 4. When there is target data in the L2 cache 4, the processor core 2 accesses the data. The memory capacity of the L2 cache 4 is, for example, about several hundred kilobytes to several megabytes.

  If the target data is not in the L2 cache 4, the corresponding physical address is sent to the main memory 5. In the present embodiment, it is assumed that all data stored in the L2 cache 4 is stored in the main memory 5. The present embodiment is not limited to the inter-cache data arrangement policy described above. The main memory 5 stores page unit data. In general, data in units of pages is arranged in the main memory 5 and the auxiliary storage device. In the present embodiment, it is assumed that all data is arranged in the main memory 5 for simplification. In the present embodiment, when there is target data in the main memory 5, the processor core 2 accesses the data. The memory capacity of the main memory 5 is, for example, about several GB.

  In this way, the L1 and L2 caches 3 and 4 are hierarchized, and the larger the degree (lower hierarchy) cache memory, the larger the memory capacity.

  In the following, for the sake of simplification, the tag arrays of the L1 and L2 caches 3 and 4 are described as being managed by an LRU (Least Recently Used) algorithm. However, this embodiment can be combined with various data priority management algorithms other than LRU. For example, it may be combined with NRU (Not Recently Used) or a random replacement algorithm. In the following description, the tag array is shown as a fully associative cache for the sake of simplicity. However, the present embodiment can be applied to various cache systems, and may be set associative or a direct map, for example.

  In the present embodiment, it is assumed that data with high access frequency is highly re-referenced data. The priority in the cache is an index for determining data to be deleted from the cache, for example. For example, when filling data in the cache, data with low priority is deleted from the cache. In the LRU algorithm, MRU (Most Recently Used) data has the highest priority, and LRU data has the lowest priority. In addition, the priority of data that does not exist in the cache (data that does not exist between MRU and LRU) may be lower than that of data that exists in the cache.

  In the first embodiment, when data is stored in the cache, the priority in storing in the cache is determined based on the priority information of the data. In some cases, if the priority of data to be stored in the cache is low, the data need not be stored in the cache. By performing such control, low re-reference data is prevented from being stored in the cache as high priority data. Further, highly re-referenced data can be held in the cache, and a reduction in cache misses and a reduction in the number of cache writes can be expected.

  FIG. 2 is a block diagram showing an internal configuration of the L2 cache (first memory) 4 in the memory system 1 according to the first embodiment. As shown in FIG. 2, the L2 cache 4 includes a first data area 4a, a first tag area 4b, a second tag area 4c, and an L2 cache controller 6. A main memory (second memory) 5 is provided in a lower hierarchy of the L2 cache 4.

  The first data area 4a is an area for storing data whose priority is higher than a predetermined level, and is composed of a nonvolatile memory. The type of the nonvolatile memory is not particularly limited, but is, for example, an MRAM (Magnetoresistive Random Access Memory). MRAM can be integrated at higher speed and higher than SRAM, and can reduce power consumption due to low leakage power. The first data area 4a has a plurality of cache lines, and data is stored and read out in units of cache lines.

  The first tag area 4b stores address information corresponding to the data stored in the first data area 4a. More specifically, the first tag area 4b stores corresponding address information for each cache line in the first data area 4a.

  The first tag area 4b in FIG. 2 stores priority information 4b2 in association with each address information 4b1. For example, the smaller the priority information value, the higher the priority of the corresponding address information and data. FIG. 2 shows an example in which address information and data with higher priority are stored toward the head address side of the first tag area 4b and the first data area 4a.

  Note that providing priority information in the first tag area 4b is not essential. Even if there is no priority information in the first tag area 4b, priorities may be assigned in the order in which the address information is stored, or each address information stored in the first tag area 4b is set to the same priority. Also good. Hereinafter, an example in which priority information is stored in the first tag area 4b will be described.

  The second tag area 4c stores address information 4c1 and priority information 4c2 in association with each other. Data corresponding to each address information in the second tag area 4 c is stored in the first data area 4 a or the main memory 5.

  For example, the second tag area 4c has a larger amount of memory than the first tag area 4b, and stores past address information that the processor core 2 has accessed the L2 cache 4 over a longer period than the first tag. As will be described later, the address information stored in the first tag area 4b may be redundantly stored in the second tag area 4c, or only the address information not stored in the first tag area 4b is stored in the first tag area 4b. You may store in 2 tag area | region 4c.

  The priority information 4c2 in the second tag area 4c and the priority information 4b2 in the first tag area 4b are associated in advance. For example, the priority information 0 to 5 in the second tag area 4c is associated with the priority information 0 in the first tag area 4b. In this case, when data corresponding to any one of the priority information 0 to 5 in the second tag area 4c is stored in the first data area 4a, the priority information 0 in the first tag area 4b is stored. The corresponding data is stored in the corresponding cache line. Note that such association of priority information may be changed afterwards or dynamically.

  The L2 cache controller 6 includes an access information transmission unit 11, a priority update unit 12, a first hit determination unit 13, a second hit determination unit 14, a priority acquisition unit 15, and a priority determination unit 16. Have.

  The access information transmission unit 11 transmits access information for the L2 cache 4. The transmission destination of the access information is the priority update unit 12. The access information includes address information of data accessed to the L2 cache 4. The access information transmission unit 11 transmits the access information to the priority update unit 12 every time at least a part of the L2 cache 4 is accessed.

  The priority update unit 12 updates the priority information in the second tag area 4c based on the access information. For example, the priority information is updated so that the address information having a higher access frequency has a higher priority. Moreover, the priority update part 12 makes a priority low, so that there is a low possibility of being re-referenced. The priority update unit 12 may not store in the second tag area 4c data that has a low possibility of being re-referenced, that is, data with low priority.

  For example, when updating the address information in the second tag area 4c, the priority update unit 12 updates at least one priority information in the second tag area 4c. The address information in the second tag area 4c is updated, for example, when the data is evicted from the first data area 4a, when the data is read from the main memory 5, or the address to be updated by the priority update unit. This is performed when information is not present in the second tag area.

  The first hit determination unit 13 determines whether the address information of the data to be read is stored in the first tag area 4b. Here, the data to be read is data requested to be read from the processor core 2.

  The second hit determination unit 14 determines whether the first hit determination unit 13 determines that it is not stored in the first tag area 4b or whether it is stored in the first tag area by the first hit determination unit At the same time, it is determined whether the address information of the data to be read is stored in the second tag area 4c.

  The priority acquisition unit 15 determines whether the second hit determination unit 14 determines that the second hit determination unit 14 stores the second tag area 4c or whether the second hit determination unit stores the second tag area 4c. Simultaneously with the determination, priority information corresponding to the address information of the read target data is acquired from the second tag area 4c.

  The priority determination unit 16 determines whether to store the data to be read in the first data area 4a based on the acquired priority information. For example, if the priority information corresponding to the address information of the read target data is 0 to 8, the priority determination unit 16 determines that the read target data is stored in the first data area 4a, and the priority information If is greater than 8, it is determined that the data to be read is not stored in the first data area 4a.

  Thereby, only the data corresponding to the address information with high priority among the address information stored in the second tag area 4c can be stored in the first data area 4a. This means that the first data area 4a preferentially stores data whose priority is higher than a predetermined level (high re-reference data).

  The L2 cache controller 6 may have an access control unit 17. When the priority determination unit 16 determines that the data to be read is stored in the first data area 4a, the access control unit 17 reads the data to be read from the main memory 5 (second data area) and reads the first data Control to store in the area 4a is performed.

  FIG. 3 is a flowchart showing the processing operation of the memory system 1 according to the first embodiment. This flowchart shows the processing operation when the processor core 2 makes a read request, misses in the L1 cache 3, and reaches the L2 cache 4.

  First, it is determined whether or not the first tag area 4b is hit (step S1). Here, the first hit determination unit 13 determines whether the address information of the data to be read is stored in the first tag area 4b.

  For example, if it is determined that the first tag area 4b is missed, it is determined whether or not the second tag area 4c is hit (step S2). Here, the second hit determination unit 14 determines whether the address information of the data to be read is stored in the second tag area 4c.

  For example, when it is determined that the second tag area 4c is hit, the priority acquisition unit 15 acquires priority information from the second tag area 4c (step S3). On the other hand, if it is determined that the second tag area 4c is not hit, for example, the process proceeds to step S7 described later.

  In parallel with the processing of steps S2 and S3, the L2 cache controller 6 requests the data to be read from the main memory 5 (step S4). In response to this request, the L2 cache controller 6 acquires the data read from the main memory 5 (step S5) and transfers it to the processor core 2 via the L1 cache 3 (step S6).

  When the process of step S3 or step S6 ends, the priority determination unit 16 determines whether or not the data read from the second tag area 4c or the main memory 5 is stored in the L2 cache 4. Moreover, the priority update part 12 updates the priority information of the 2nd tag area | region 4c (step S7).

  Next, the L2 cache controller 6 performs control of storing or not storing the data read from the second tag area 4c or the main memory 5 in the first data area 4a according to the determination in step S7 (step S8).

  Here, various policies can be considered as the policy for determining whether or not the priority determination unit 16 stores data in the L2 cache 4 in step S7 (that is, storage control information regarding whether or not to store data). It is done. For example, address information with a priority of 0 to 5 in the second tag area 4c is stored in the first tag area 4b as address information with a priority of 0 in the first tag area 4b, and the address information in the second tag area 4c is stored. Address information with a priority higher than 5 is included in the first tag area 4b as address information with a priority of 3 in the first tag area 4b, including low priority address information not stored in the second tag area 4c. A policy to be stored may be adopted. Here, it is assumed that the smaller the numerical value of the priority, the higher the priority. Alternatively, a policy may be adopted in which low priority address information not stored in the second tag area 4c is not stored in the first tag area 4b. A policy (storage control information) may be employed in which address information with a priority higher than 5 in the second tag area 4c is not stored in the first tag area 4b.

  On the other hand, if it is determined in step S1 that the first tag area 4b is hit, the L2 cache controller 6 reads the data to be read from the first data area 4a and transfers it to the processor core 2 via the L1 cache 3. (Step S9). In parallel with the process of step S9, the access information transmitting unit 11 transmits the access information to the second tag area 4c of the L2 cache 4 (step S10). The access information to be transmitted includes address information that has a read request and hits the first tag area 4b. The priority update unit 12 updates the priority information of the second tag area 4c based on the received access information (step S11). More specifically, the priority update unit 12 updates the priority information so as to increase the priority corresponding to the address information hit in the first tag area 4b.

  FIG. 4 is a diagram showing the hit / miss determination result of the L2 cache 4 in the first embodiment. In the example of FIG. 4, the processor core 2 makes a read request in the order of data a, b, c, a, d, b, a, c over 8 cycles. That is, the processor core 2 shows an example in which a read request is made for data a every 3 cycles and data b every 4 cycles. L2_Hit? In FIG. 4 is “O” when the L2 cache 4 is hit, and “X” when it misses. access Data represents data accessed to the L2 cache 4. L1 represents address information corresponding to data stored in the L1 cache 3. L2_0 and L2_1 represent priority information 4b2 of data stored in the first data area 4a in the L2 cache 4, in which address information 4b1 of the data is stored. L2_0 has a higher priority than L2_1. 2tag_0 to 2tag_3 represent priority information 4c2 in the second tag area 4c in the L2 cache 4, in which address information 4c1 of data accessed in the past is stored. This indicates that 2tag_0 has the highest priority and 2tag_3 has the lowest priority.

  First, it is assumed that there is a read request for data a in cycle C1. At this time, it is assumed that no data is stored in the L1 cache 3 and the L2 cache 4. The L1 cache 3 has a memory capacity for one cache line, the first data area 4a and the first tag area 4b in the L2 cache 4 have a memory capacity for two cache lines, and the second tag area 4c. Has a memory capacity of 4 cache lines.

  In the next cycle C2, the data a requested to be read in the cycle C1 and its address information are stored in the L1 cache 3 and also stored in the first data area 4a and the first tag area 4b in the L2 cache 4. The Address information of data a is stored in the second tag area 4c. In cycle C2, it is assumed that there is a read request for data b.

  In the next cycle C3, since the L1 cache 3 has a cache miss in cycle C2, it is replaced with the data b and its address information. In cycle C2, since a cache miss has occurred in both the first tag area 4b and the second tag area 4c in the L2 cache 4, the first data area 4a and the first tag area 4b are replaced with the data b and its address information. Is done. In the second tag area 4c, the address information of the data b is additionally stored without replacing the address information of the data a. In cycle C3, it is assumed that there is a request for reading data c.

  In the next cycle C4, since the L1 cache 3 has a cache miss in cycle C3, it is replaced with data c and its address information. In cycle C3, since a cache miss has occurred in both the first tag area 4b and the second tag area 4c in the L2 cache 4, the first data area 4a and the first tag area 4b are replaced with the data c and its address information. Is done. In the second tag area 4c, the address information of the data c is additionally stored without replacing the address information of the data a and b. In cycle C4, it is assumed that there is a read request for data a.

  In the next cycle C5, the L1 cache 3 is replaced with data a and its address information because a cache miss occurred in cycle C4. In cycle C4, since a cache hit occurs in the second tag area 4c in the L2 cache 4, data a and its address information are additionally stored in the first data area 4a and the first tag area 4b. Further, the priority of the address information corresponding to the data a in the second tag area 4c is raised to the highest value. In cycle C5, it is assumed that there is a read request for data d.

  In the next cycle C6, the L1 cache 3 is replaced with the data d and its address information because of a cache miss in the cycle C5. In cycle C5, since the cache miss has occurred in both the first tag area 4b and the second tag area 4c in the L2 cache 4, the data c in the first data area 4a and the first tag area 4b is the data d and its data c. Replaced with address information. In the second tag area 4c, the address information of the data d is additionally stored without replacing the address information of the data a, b, c. In cycle C3, it is assumed that there is a request for reading data b.

  In the next cycle C7, the L1 cache 3 is replaced with the data b and its address information because of a cache miss in the cycle C6. In cycle C6, since a cache miss has occurred in both the first tag area 4b and the second tag area 4c in the L2 cache 4, the data c in the first data area 4a and the first tag area 4b is the data d and its data c. Replaced with address information. In the second tag area 4c, the address information of the data d is additionally stored without replacing the address information of the data a, b, c. In cycle C7, it is assumed that there is a read request for data a. As a result, the first tag area 4b in the L2 cache 4 is hit, and the data a is read from the first data area 4a and transferred to the processor core 2.

  In the next cycle C8, the L1 cache 3 has a cache miss in cycle C7, and is therefore replaced with data a and its address information. Further, in cycle C7, the data a and b in the first data area 4a and the first tag area 4b do not change because a cache hit occurs in both the first tag area 4b and the second tag area 4c in the L2 cache 4. . In the second tag area 4c, the priority of the data a is the highest, and then the data is stored in the order of the data b, d, and c.

  As can be seen from FIG. 4, data a having a read request every three cycles is stored in the L2 cache 4 in preference to data b having a read request every four cycles. As a result, data that is more likely to be re-referenced can be preferentially stored in the L2 cache 4.

  FIG. 5 is a diagram showing hit / miss determination results of the L1 cache 3 and the L2 cache 4 when there is no second tag area 4c. In FIG. 5, the arrangement order of the data requested to be read is the same as in FIG. 4, and the memory capacities of the L1 cache 3 and the L2 cache 4 are also the same as in FIG. In FIG. 5, since only the two data that have been requested to be read most recently can be stored in the L2 cache 4, even if there is a read request for the same data at least three cycles apart, the L2 cache 4 is not hit. On the other hand, as shown in FIG. 4, this embodiment has a second tag area 4c for storing address information of the four data requested to be read most recently, and hits the second tag area 4c. Since data is stored in the first data area 4a based on the determination result, data with high access frequency can be reliably stored in the first data area 4a.

  Thus, in the present embodiment, the L2 cache 4 is provided with the second tag area 4c separately from the original first tag area 4b, and the address information and priority information are associated with the second tag area 4c. Even if there is a read request for data stored and not stored in the first data area 4a of the L2 cache 4, data is stored in the first data area 4a based on the priority information in the second tag area 4c. Can be determined. As a result, writing of data that is not highly re-referenced data to the L2 cache 4 can be suppressed, and the number of writes to the L2 cache 4 can be reduced. As a result, high-priority data can be stored in the first data area 4a while suppressing high-priority data in the first data area 4a from being pushed out, and the hit rate to the L2 cache 4 can be improved. More specifically, by providing the second tag region 4c, it is possible to improve the hit rate for data that is highly likely to be re-referenced. As a result, the frequency of data replacement in the L2 cache can be suppressed, and the number of writes to the L2 cache 4 can be reduced. Therefore, the L2 cache 4 can be configured using a non-volatile memory such as an MRAM with a limited number of writes.

(Second Embodiment)
FIG. 6 is a block diagram showing a schematic configuration of a processor system according to the second embodiment. The processor system shown in FIG. 6 includes an L3 cache 7 between the L2 cache 4 and the main memory 5 shown in FIG. The L3 cache 7 is accessed when the data requested to be read misses the L2 cache 4 and performs hit / miss determination. When there is a hit, the requested data is read from the L3 cache 7 and transferred to the L2 cache 4. If a miss occurs, the L3 cache 7 transfers a read request to the main memory 5.

  The L3 cache 7 in FIG. 6 has a larger memory capacity than the L2 cache 4. In this embodiment, as in the first embodiment, the tag arrays of the L1 cache 3, the L2 cache 4, and the L3 cache 7 are managed by the LRU algorithm, but various data priority management algorithms other than the LRU are used. It is also possible to combine with. In the following, for the sake of simplification, an example of a fully associative cache using a tag array will be described. However, the present embodiment can be applied to various cache methods, and may be set associative or a direct map, for example.

  FIG. 7 is a block diagram showing an internal configuration of the L2 cache 4 and the L3 cache 7 in the memory system 1 according to the second embodiment. As illustrated in FIG. 7, the L2 cache 4 includes a first tag area 4 b, a first data area 4 a, and an L2 cache controller 6. The L3 cache 7 includes a second tag area 7a, a second data area 7b, and an L3 cache controller 8. The L3 cache 7 has a larger memory capacity than the L2 cache 4. Therefore, the second tag area 7a is larger than the first tag area 4b, and the second data area 7b is larger than the first data area 4a.

  The first data area 4a and the second data area 7b are configured by a non-volatile memory such as an MRAM, and the first tag area 4b and the second tag area 7a are configured by a high-speed volatile memory such as an SRAM. Note that the first tag area 4b and the second tag area 7a may be formed of a nonvolatile memory.

  Each of the first tag area 4b and the second tag area 7a stores address information 4b1 and 7a1 in association with priority information 4b2 and 7a2.

  The L2 cache controller 6 includes an access information transmission unit 11, a first hit determination unit 13, and a priority determination unit 16. The L3 cache controller 8 includes a priority update unit 12, a second hit determination unit 14, a priority acquisition unit 15, and an access control unit 17.

  The access information transmission unit 11 in the L2 cache controller 6 transmits access information to the L2 cache 4 to the L3 cache controller 8. The first hit determination unit 13 determines whether or not the address information requested to be read is stored in the first tag area 4b in the L2 cache 4. The priority determination unit 16 determines whether to store the data to be read in the first data area 4a based on the priority information acquired by the priority acquisition unit 15 for the address information requested to be read. .

  The priority update unit 12 in the L3 cache controller 8 updates the priority information in the second tag area 7a based on the access information transmitted from the access information transmission unit 11. When the data to be read misses in the L2 cache 4, the second hit determination unit 14 determines whether the address information of this data is stored in the second tag area 7 a in the L3 cache 7. The priority acquisition unit 15 acquires corresponding priority information from the second tag area 7a when the address information of the data to be read hits the second tag area 7a. This priority information is sent to the priority determination unit 16 in the L2 cache controller 6.

  FIG. 8 is a flowchart showing the processing operation of the memory system 1 according to the second embodiment. First, it is determined whether or not the data to be read hits the L2 cache 4 (step S21). Here, the first hit determination unit 13 determines whether the address information of the data to be read is stored in the first tag area 4 b in the L2 cache 4.

  If it is determined in step S21 that the data is hit, the L2 cache controller 6 reads the data to be read from the L2 cache 4 and transfers it to the processor core 2 via the L1 cache 3 (step S22).

  If it is determined in step S21 that a miss has occurred, it is determined whether or not the data to be read hits the L3 cache 7 (step S23). Here, the second hit determination unit 14 determines whether or not the address information of the data to be read is stored in the second tag area 7a1 in the L3 cache 7. If it is determined in step S23 that the data has been hit, the L3 cache controller 8 reads the data to be read from the L3 cache 7 and transfers it to the processor core 2 via the L1 cache 3 (step S24).

  If it is determined in step S23 that the L3 cache 7 has been missed, the L3 cache controller 8 reads the data to be read from the main memory 5 and stores it in the L3 cache 7, and also stores it in the processor core 2 via the L1 cache 3. Transfer (step S25).

  When the process of step S22, S24, or S25 ends, the priority acquisition unit 15 acquires priority information from the second tag area 7a in the L3 cache 7 and transmits it to the L2 cache controller 6 (step S26).

  Next, the priority determination unit 16 in the L2 cache controller 6 stores the data read from the L3 cache 7 or the main memory 5 in the L2 cache 4 based on the priority information transmitted in step S26. To decide. Moreover, the priority update part 12 updates the priority information of the 2nd tag area | region 7a (step S27).

  Next, the L2 cache controller 6 performs control of storing or not storing the data read from the second tag area 7a or the main memory 5 in the first data area 4a according to the determination in step S27 (step S28).

  Various policies for determining whether or not the priority determination unit 16 stores data in the L2 cache 4 in step S27 can be considered as in step S7 of FIG. 3, and any policy may be selected.

  FIG. 9 is a diagram showing the hit / miss determination result of the L2 cache 4 in the second embodiment. The example of FIG. 9 shows an example in which the processor core 2 issues a read request in the order of data a, x1, x2, a, x3, x4, and a over 8 cycles. Thus, FIG. 9 shows an example in which the processor core 2 issues a read request for data a every three cycles. 9, L2_Hit ?, access Data, L1, L2_0, and L2_1 are the same as those in FIG. L3_0 to L3_5 represent priority information 7a2 of data stored in the second data area 7b in the L3 cache 7, in which address information 7a1 of the data is stored. This indicates that L3_0 has the highest priority and L3_5 has the lowest priority.

  First, it is assumed that there is a read request for data a in cycle C1. At this time, it is assumed that no data is stored in the L1 cache 3, the L2 cache 4, and the L3 cache 7. The L1 cache 3 has a memory capacity for one cache line, the L2 cache 4 has a memory capacity for two cache lines, and the L3 cache 7 has a memory capacity for six cache lines.

  In the next cycle C2, the data a requested to be read in the cycle C1 is not stored in any of the L1 cache 3, the L2 cache 4 and the L3 cache 7, and therefore misses in these caches. Then, the data a is read from the main memory 5 and the data a and its address information are stored in the L1 cache 3 and the L3 cache 7, but the priority information of the data a is the second tag area in the L3 cache 7. Since the data is not stored in 7a1, the data a is not stored in the L2 cache 4. In cycle C2, it is assumed that there is a read request for data x1.

  In the next cycle C3, the data x1 requested to be read in the cycle C2 misses in the L1 cache 3, the L2 cache 4 and the L3 cache 7, and this data x1 is read from the main memory 5, and the data x1 and its data x1 are read. Address information is stored in the L1 cache 3 and the L3 cache 7. Since the L1 cache 3 has only a memory capacity for one cache line, the data a is overwritten on the data x1. Since the L3 cache 7 has a memory capacity of 6 cache lines, both the data a and the data x1 are stored in the L3 cache 7, and the priority of the data x1 accessed most recently is set higher than the priority of the data a. Is done. Until the cycle C3, since the priority information of the data x1 is not stored in the second tag area 7a1 in the L3 cache 7, the data x1 is not stored in the L2 cache 4. In cycle C3, it is assumed that there is a read request for data x2.

  In the next cycle C4, the data x2 requested to be read in the cycle C3 misses in the L1 cache 3, the L2 cache 4 and the L3 cache 7, and this data x2 is read from the main memory 5, and the data x2 and its data x2 are read. Address information is stored in the L1 cache 3 and the L3 cache 7. Since the L1 cache 3 has only a memory capacity for one cache line, the data x1 is overwritten with the data x2. Since the L3 cache 7 has a memory capacity for six cache lines, the data a, x1, and x2 are all stored in the L3 cache 7, and priority information that lowers the priority in the order of the data x2, x1, and a is generated. That is, the data accessed more recently has a higher priority. Until the cycle C4, since the priority information of the data x2 is not stored in the second tag area 7a1 in the L3 cache 7, the data x2 is not stored in the L2 cache 4. In cycle C4, it is assumed that there is a request for reading data a.

  In the next cycle C5, the data a requested to be read in the cycle C4 misses in the L1 cache 3 and the L2 cache 4 and hits in the L3 cache 7. Therefore, data a is read from the L3 cache 7 and stored in the L1 cache 3 and the L2 cache 4. Since the L1 cache 3 has only a memory capacity for one cache line, the data x2 is overwritten with the data a. The priority in the L3 cache 7 is changed, and priority information in which the priority decreases in the order of data a, x2, and x1 is generated. In cycle C5, it is assumed that there is a read request for data x3.

  In the next cycle C6, the data x3 requested to be read in the cycle C5 misses in the L1 cache 3, the L2 cache 4 and the L3 cache 7, and this data x3 is read from the main memory 5, and the data x3 and its data x3 are read. Address information is stored in the L1 cache 3 and the L3 cache 7. Since the L1 cache 3 has only a memory capacity for one cache line, the data a is overwritten on the data x3. Since the L3 cache 7 has a memory capacity for six cache lines, priority information whose priority decreases in the order of the data x3, a, x2, and x1 is generated. That is, the data accessed more recently has a higher priority. Until the cycle C6, since the priority information of the data x3 is not stored in the second tag area 7a1 in the L3 cache 7, the data x3 is not stored in the L2 cache 4. In cycle C6, it is assumed that there is a read request for data x4.

  In the next cycle C7, the data x4 requested to be read in cycle C6 misses in the L1 cache 3, the L2 cache 4 and the L3 cache 7, and this data x4 is read from the main memory 5, and the data x4 and its data x4 are read. Address information is stored in the L1 cache 3 and the L3 cache 7. Since the L1 cache 3 has only a memory capacity for one cache line, the data x3 is overwritten with the data x4. Since the L3 cache 7 has a memory capacity for six cache lines, priority information whose priority decreases in the order of the data x4, x3, a, x2, and x1 is generated. That is, the data accessed more recently has a higher priority. Until the cycle C7, since the priority information of the data x4 is not stored in the second tag area 7a1 in the L3 cache 7, the data x4 is not stored in the L2 cache 4. In cycle C7, it is assumed that there is a request for reading data a. As a result, the L2 cache 4 is hit.

  FIG. 10 is a diagram showing a hit / miss determination result of a comparative example when the second tag area 7a in the L3 cache 7 does not have priority information. 10, the arrangement order of the data requested to be read is the same as that in FIG. 9, and the memory capacities of the L1 cache 3 and the L2 cache 4 are also the same as those in FIG. In FIG. 10, since only the two data requested to be read most recently can be stored in the L2 cache 4, even if there is a read request for the same data at least three cycles apart, the L2 cache 4 is not hit. On the other hand, in the present embodiment, as shown in FIG. 9, only high priority data is stored in the L2 cache 4 based on the priority information stored in the second tag area 7a in the L3 cache 7. Therefore, even if there is a read request for the same data at least three cycles apart, the L2 cache 4 can be hit.

  As described above, in the second embodiment, since priority information is provided in association with each address information in the second tag area 7a in the L3 cache 7, the priority of the data accessed to the L3 cache 7 is grasped. can do. Therefore, it is possible to determine whether or not to store data in the L2 cache 4 based on this priority information, and data that is highly likely to be re-referenced can be stored in priority in the L2 cache 4. Thereby, the hit rate to the L2 cache 4 can be improved.

(Third embodiment)
The third embodiment employs a victim cache (Victim Cache method). Here, the victim cache is not stored in the upper-level cache when transferring lower-level data to the processor core 2, but is transferred to the lower-level cache when evicting data from the upper-level cache. A method for storing data.

  The memory system 1 according to the third embodiment includes a three-level cache of an L1 cache 3, an L2 cache 4, and an L3 cache 7, as in FIG. Note that a cache having four or more layers may be provided.

  FIG. 11 is a flowchart showing the processing operation of the memory system 1 according to the third embodiment. First, it is determined whether or not the L2 cache 4 has been hit (step S31). If it is determined in step S31 that the data has been hit, the data to be read is read from the L2 cache 4 and transferred to the processor core 2 via the L1 cache 3 (step S32). Then, the process of FIG. 11 is complete | finished.

  If it is determined in step S31 that the L2 cache 4 has been missed, it is determined whether or not the L3 cache 7 has been hit (step S33). If it is determined that the L3 cache 7 has been hit, data is transferred from the L3 cache 7 to the processor core 2 via the L1 cache 3 (step S34). If it is determined that the L3 cache 7 has missed, data is transferred from the main memory 5 to the processor core 2 via the L1 cache 3 (step S35). At this time, data from the main memory 5 is not transferred to the L3 cache 7.

  When the process of step S34 or S35 is completed, the priority acquisition unit 15 then acquires priority information from the second tag area 7a in the L3 cache 7 and transmits it to the L2 cache controller 6 (step S36). .

  Next, the priority determination unit 16 in the L2 cache controller 6 stores the data read from the L3 cache 7 or the main memory 5 in the L2 cache 4 based on the priority information transmitted in step S36. To decide. (Step S37).

  Next, the L2 cache controller 6 performs control of storing or not storing the data read from the second tag area 7a or the main memory 5 in the first data area 4a according to the determination in step S37 (step S38).

  Various policies for determining whether or not the priority determination unit 16 stores data in the L2 cache 4 in step S37 can be considered as in step S7 of FIG. 3, and any policy may be selected.

  When storing data in the L2 cache 4, it is determined whether or not another data has been expelled from the L2 cache 4 (step S39). When another data is evicted, the evicted data is stored in the second data area 7b in the L3 cache 7, and the priority information in the second tag area 7a is updated (step S40). Further, when data is evicted from the L1 cache 3, it may be stored in the second data area 7b in the L3 cache 7 and the priority information in the second tag area 7a may be updated. When data is evicted from the L1 cache 3, if the data is not stored in the L2 cache 4, it is stored in the second data area 7b in the L3 cache 7, and priority information in the second tag area 7a is stored. It may be updated.

  As described above, in the third embodiment, even when the victim cache method is employed, data that is re-referenced to the L2 cache 4 can be preferentially stored.

  In the first to third embodiments described above, the memory system 1 including a plurality of hierarchical cache memories has been described. However, the present invention can be widely applied to memories other than the cache memory. Here, the term “memory” is intended to include both a physical space memory and a virtual space memory, and the present invention can be applied to, for example, a TLB (Translation Lookaside Buffer), a page buffer, and the like.

(Mounting form of the first tag and the second tag)
In the first to third embodiments, for the sake of simplification, the number of sets that is the premise of the first tag area 4b is the same as the number of sets that is the premise of the second tag area 4c. However, the present embodiment is not limited to a configuration in which the number of sets of the first tag area 4b and the second tag area 4c is the same. For example, the number of sets of the first tag area 4b may be larger than the number of sets of the second tag area 4c, and the number of sets of the first tag area 4b may be smaller than the number of sets of the second tag area 4c. When the memory capacity of the cache memory is the same, the data amount per entry of the tag memory of the cache memory having a large number of sets is smaller than the data amount per entry of the tag memory of the cache memory having a small number of sets. Therefore, for example, even if the data amount stored in the second tag region 4c is larger than the data amount stored in the first tag region 4b, the number of sets of the second tag region 4c is increased, thereby increasing the tag memory. Can be suppressed.

  In 1st-3rd embodiment, the 2nd tag area | region 4c showed the example holding more information than the 1st tag area | region 4b. However, the second tag area 4c may have a smaller memory capacity than the first tag area 4b.

  The first tag area 4b and the second tag area 4c in the first to third embodiments may be physically integrated into one tag area. FIG. 12 shows an example of the first tag area 4b and the second tag area 4c integrated. In the example of FIG. 12, the first tag area 4b includes address information of priorities 1 to 3 in the tag array 21, corresponding data array addresses, and corresponding priority information. The first data area 4 a includes data in the data area in the data array 22. The second tag area 4c includes address information of priorities 1 to 5 in the tag array 21 and corresponding priority information.

  In the example of FIG. 12, at the time of access, the tag address in the tag array 21 and the corresponding data address are read, the read tag address is compared with the accessed address, and if it hits, the read data address corresponds. Data to be read is read from the data array 22.

(When the data granularity of the first and second areas is different)
In the first to third embodiments, for simplification, the line size of the first tag area 4b and the line size of the second tag area 4c are the same. However, the present embodiment is not limited to the configuration in which the line sizes of the first tag region 4b and the second tag region 4c are the same. For example, the line size of the first tag region 4b may be larger than the line size of the second tag region 4c, or the line size of the first tag region 4b may be smaller than the line size of the second tag region 4c.

  For example, consider an embodiment in which the line size of the first tag region 4b is smaller than the line size of the second tag region 4c. The data indicated by one entry in the second tag area 4b includes a plurality of data in the first tag area 4b. For example, as shown in FIG. 13, a case is considered where the data indicated by one entry in the second tag area 4b includes four data indicated by one entry in the first tag area 4b. The numerical values shown at both ends of the first data and the second data in FIG. 13 indicate the head address and the end address of the data. In this example, as shown in the first to third embodiments, among the data indicated by one entry in the second tag area 4c, data of 0 to 8 bytes is accessed, and then 0 to 8 bytes of data is accessed. Assume that data has been accessed. In this case, since the same entry in the second tag area 4c is continuously accessed, it is determined that the priority of this entry is high, and data of 0 to 8 bytes is used as the high priority data in the first data area. 4a is assumed to be written. This can be suppressed, for example, by providing a mechanism (detailed access profiler) that profiles the access to the second data area 7b in more detail.

  For example, as shown in FIG. 13, a method of providing a 1-bit access flag 4d for every 8 bytes of the second data area 7b in the second tag area 4c is conceivable. In this case, a 4-bit access flag 4d is provided for each entry in the second tag area 4c. The access flag 4d is information indicating which of the four 8-byte areas in one entry is accessed. Using the access flag and the priority information of the second tag area 4c, for example, when the priority of the second tag area 4c is high and the access flag is set, the first data area 4a is set as high priority data. It is conceivable that data is written to the first data area 4a as low priority data when the priority of the second tag area 4c is high and the access flag is not set. The operation of the 4-bit access flag will be described using the above example. In the initial state, for example, the 4-bit access flag is set to 0. If there is an 8-byte access from 0x0, the corresponding flag is set to 1. Also, the priority of the entry in the second tag area 4c including 8 bytes of data from 0x0 is set in the MRU. If there is access to 8 bytes of data from the next 0x8, the entry in the second tag area 4c is MRU, but the access flag corresponding to 8 bytes from 0x8 is 0 at the time of access, so low priority data Is written in the first data area 4a. In addition, an access flag corresponding to data of 0 to 8 bytes is set to 1.

  For example, for each entry in the second tag area 4c, a method of holding some access address information indicating which position in the second tag area 4c was accessed in a near time zone is conceivable. When there is continuous access to the same entry in the second tag area 4c, the access address information is used. For example, when the priority in the second tag area 4c is high and the access address information exists, the high priority Data is written to the first data area 4a, and when the priority of the second tag area 4c is high and there is no access address information, it is written to the first data area 4a as low priority data. In the case of non-consecutive access to the same entry, if the priority of the second tag area 4c is high, it is written as high priority data in the first data area 4a regardless of the access address information, and the priority of the second tag area 4c Is low, data is written as low priority data in the first data area 4a regardless of the access address information. Whether the access is continuous may be determined from the priority of the second tag area 4c, for example. For example, if the accessed data is MRU, it may be determined that the access is continuous, and if not, it may be determined that the access is not continuous. The operation of the access address information will be described using the above example. For simplification, an example in which one piece of access address information is held is shown. First, when there is access to data of 8 bytes from 0x0, the priority update unit 12 sets the priority of the corresponding entry to MRU, and sets 0x0 to access address information existing in the entry of the second tag area 4c. set. Next, when there is an access to data of 8 bytes from 0x8, the priority acquisition unit 15 acquires the priority and access address information of the second tag area 4c. Although the priority of the second tag area 4c is MRU, the access address information is 0x0, which is different from 0x8, so it is written in the first data area 4c as low priority data. Finally, the access address information is overwritten with 0x8.

(Combination with short retention technology)
The first to third embodiments described above can be combined with a short retention technique. The short retention technique means that, for example, in an MRAM, at least two writing units are provided. For example, a first writing unit that performs writing with high energy and realizes long-term retention, and a second writing unit that realizes energy saving by performing writing with low energy although it is a short-time retention. Say. For example, in the first to third embodiments, if the priority obtained from the second tag area 4c is high, the first data area 4a is written by the first writing means and obtained from the second tag area 4c. If the given priority is low, a mode in which the second data is written to the first data area 4a can be considered.

(Coherency)
When the cache memory described in the first to third embodiments holds a state related to coherency such as the MESI protocol, the state of coherency may be stored in the second tag area 4c. The coherency state may be stored only in the second tag area 4c. For example, based on the priority information of the second tag area 4c, the state relating to coherency is held in the entry of the second tag area 4c corresponding to the data transferred to the upper layer when not written to the first data area 4a. For example, when the first tag area 4b is smaller than the second tag area 4c, the second tag area 4c can hold a state relating to a lot of data coherency. As a specific operation, for example, data rewrite information in the upper hierarchy of the cache is sent to the cache, and the state regarding the coherency of the entry in the second tag area 4c is changed to Modify. Alternatively, an area for storing data other than the address of data stored in the first data area 4c may be provided in the first tag area 4b, and a state related to coherency may be stored in the area.

(Dynamic method)
The storage policy in the first data area 4a based on the priority information of the second tag area 4c may be dynamically controlled. For example, the access frequency information may be acquired for each address in the second tag area 4c, and the storage policy in the first data area 4a may be determined based on the priority information and the access frequency information. For example, data having a high priority and high access frequency in the second tag area 4c is stored in the first data area 4a, and data having a high priority and low access frequency in the second tag area 4c is stored. Prohibit storage in The access frequency information includes, for example, the number of hits per unit time. The unit time is, for example, the number of unit execution cycles, the number of unit execution instructions, or the number of unit cache accesses. For example, in general LRU, since the access frequency is not considered in the priority determination, such control may be effective. If the access frequency is considered in the priority determination in the second data area 7b, such control is not necessarily performed.

  In steps S1 and S2 of FIG. 3, steps S21 and S23 of FIG. 8, and steps S31 and S33 of FIG. 11, when the first hit determination unit 13 makes a mistake, the determination process of the second hit determination unit 14 is performed. However, the processes of the first hit determination unit 13 and the second hit determination unit 14 may be performed in parallel.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 memory system, 2 processor core, 3 L1 cache, 4 L2 cache, 4a first data area, 4b first tag area, 4c second tag area,
5 main memory, 6 L2 cache controller, 11 access information transmission unit, 12 priority update unit, 13 first hit determination unit, 14 second hit determination unit, 15 priority acquisition unit, 16 priority determination unit, 17 access control Part,

Claims (19)

A first data area for storing data;
A first tag area for storing address information corresponding to the data stored in the first data area;
A second tag area for storing address information and priority information in association with each other;
An access information transmitter for transmitting access information to the nonvolatile memory;
A priority update unit that updates the priority information in the second tag area based on the access information;
A first hit determination unit for determining whether address information of data to be read is stored in the first tag area;
A second hit determination unit for determining whether address information of the data to be read is stored in the second tag area;
A determination unit that determines storage control information related to whether to store the data to be read in the first data area based on a determination result by the second hit determination unit;
When the determination unit determines to store the data to be read in the first data area based on the storage control information, the read from the second data area having a lower access priority than the first data area An access control unit that performs control to store target data in the first data area. The second tag area includes priority information of at least two types of priority, a first priority and a second priority lower than the first priority.
Priority for acquiring priority information corresponding to the address information of the read target data from the second tag area when the second hit determination unit determines that the second hit area is stored in the second tag area With an acquisition unit,
The memory system according to claim 1, wherein the determination unit determines storage control information related to whether to store the data to be read in the first data area based on the priority information. The first tag area stores address information corresponding to data stored in the first data area and priority information in association with each other,
The priority information of the first tag area includes priority information of at least two types of priority, that is, a third priority and a fourth priority lower than the third priority.
The determination unit reads the data to be read from the second data area and stores the data in the first data area based on the priority information in the corresponding second tag area. 3. The memory system according to claim 1, wherein priority information of address information stored in the tag area is determined.   The determination unit prohibits storing the data to be read out in the first data area when the second hit determination unit determines that the data is not stored in the second tag area. The memory system according to claim 1, wherein control information is selected.   When the priority information acquired by the priority acquisition unit is the priority information of the first priority in the second tag area, the determination unit determines the data to be read out as the first data area. And when the priority information acquired by the priority acquisition unit is the priority information of the second priority in the second tag area, the data to be read is stored in the first data area. 4. The memory system according to claim 2, wherein storage control information that prohibits storage is selected.   The determination unit stores the data to be read in the first data area and the first data area when the second hit determination unit determines that the second hit area is not stored in the second tag area. 4. The memory system according to claim 2, wherein storage control information for storing the priority information of the second priority is selected in a tag area.   When the priority information acquired by the priority acquisition unit is the priority information of the first priority in the second tag area, the determination unit determines the data to be read out as the first data area. And storing control information for storing the priority information of the first priority in the first tag area, and the priority information acquired by the priority acquisition unit is stored in the second tag area. In the case of the priority information of the second priority, storage control for storing the data to be read in the first data area and storing the priority information of the second priority in the first tag area 4. The memory system according to claim 2, wherein information is selected.   The access control unit stores data for storing priority information of the third priority in the first tag area in the first data area by a first writing unit, and stores the data in the first tag area in the first tag area. 4. The memory system according to claim 2, wherein data for storing priority information of four priorities is stored in the first data area by a second writing means. A first memory having the first data area, the first tag area and the second tag area;
The memory system according to claim 1, further comprising: a second memory having the second data area and having a lower access priority than the first memory. A first memory having the first data area and the first tag area;
9. The memory system according to claim 1, further comprising: a second memory having the second data area and the second tag area and having a lower access priority than the first memory.   The memory system according to claim 9 or 10, wherein the first memory and the second memory are cache memories having different hierarchies.   The memory system according to claim 9, wherein the priority update unit updates at least a part of the priority information in the second tag area every time the first memory is accessed.   11. The priority update unit updates at least a part of priority information in the second tag area when data of a memory having a different hierarchy from the second memory is expelled from the second memory. Or the memory system according to 11; A first memory for storing the first tag area;
A second memory for storing the second tag area,
The memory system according to claim 1. The first tag area and the second tag area are stored in a common memory;
The memory system according to claim 1.   The memory system according to claim 1, wherein the size of the address information for one entry in the first tag area is different from the size of the address information for one entry in the second tag area. The data amount for one entry in the first data area is different from the data amount for one entry in the second data area;
The second tag area stores flag information indicating an access position in the second data area,
The memory system according to claim 1, wherein the determination unit determines storage control information based on the flag information.   The memory system according to claim 1, wherein the first data area includes a nonvolatile memory.   The memory system according to claim 18, wherein the nonvolatile memory is an MRAM (Magnetoresistive Random Access Memory).