JP2017004070A - Power saving control of cpu mounted on image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide control for reducing power consumption of a CPU on the basis of a return factor at the time when an image formation apparatus returns from a sleep state.SOLUTION: A CPU core power supply circuit 501 is a circuit for generating power for operating CPU cores 505, 507 and caches 506, 508 and supplying the power to a CPU 301. The CPU core power supply circuit changes the generated power supply voltage by communicating with a CPU power supply control part 504 receiving an instruction from the CPU cores. The power supply voltage can be set in accordance with the CPU cores and the value of the power supply voltage is selected from the plural values. A clock generation circuit 502 is a circuit for generating a reference clock of an operation clock supplied to the CPU cores. A PLL 503 is a circuit for generating the operation clock supplied to the CPU cores. The PLL can change the frequency of the operation clock to be supplied with the instruction from the CPU.SELECTED DRAWING: Figure 5

Description

  The present invention relates to control for reducing power consumption of a CPU based on a return factor when an image forming apparatus returns from a sleep state.

  Conventionally, as a control for reducing the power consumption of the CPU, it is possible to reduce the power consumption by setting the power supply voltage during operation of the CPU to be lower than normal. Further, it is possible to reduce power consumption by changing the operating frequency during CPU operation to an operating frequency lower than normal.

  The CPU disclosed in Patent Document 1 is supplied with an operation clock having a normal operation frequency and a normal operation voltage in a normal operation state. When the CPU enters a standby state, an operation clock having an energy saving frequency lower than the normal operating frequency is supplied to the CPU, and an energy saving voltage value lower than the normal operating voltage value is supplied to the CPU.

Japanese Patent Laid-Open No. 10-31531

  Patent Document 1 discloses a technique for reducing the frequency of an operation clock supplied to a CPU under a predetermined condition. The electronic device of Patent Document 1 shifts from the standby state to the normal operation state by returning the frequency of the operation clock supplied to the CPU to the normal operation frequency when any operation is required.

  In Patent Document 1, when any operation is required (hereinafter referred to as a recovery factor), the frequency of the operation clock supplied to the CPU is uniformly returned to the normal operation frequency. However, there are cases where it is better not to return the operating clock frequency to the normal operating frequency depending on the type of return factor.

  For example, when the return factor is a print job or the like, and the processing load to be executed after returning from the standby state is high, the operation clock frequency is increased to shorten the time until the print job is completed. It is better to shorten the CPU drive time. However, when the return factor is a network inquiry or the like, the processing load to be executed after returning from the standby state is low. Therefore, if the operating clock frequency is increased, the CPU power consumption may increase. .

  SUMMARY An advantage of some aspects of the invention is that the power consumption of the CPU is reduced by changing the frequency of the clock supplied to the CPU in accordance with a return factor for returning the image forming apparatus from the power saving state. .

In order to achieve the above object, the present invention provides:
In the image forming apparatus (10) having the power saving state,
Return factor detection means (S605) for detecting a return factor when returning from the power saving state;
A CPU (301) for performing processing in the image forming apparatus (10);
Power supply means (501) for supplying power to the CPU (301);
Clock supply means (503) for supplying a clock to the CPU (301);
A clock frequency setting means (503) for setting a clock frequency supplied from the clock supply means (503);
It is possible to select a power supply voltage and a clock frequency for the CPU (301) when the image forming apparatus (10) is restored based on a restoration factor detected by the restoration factor detection means. To do.

  According to the image forming apparatus of the present invention, it is possible to simplify the power control setting for the CPU by performing the power control of the CPU based on the return factor from the sleep state, thereby reducing the CPU power. Is possible.

Configuration diagram of a network system to which an image forming apparatus can be applied External view of image forming device Controller block diagram Hardware configuration diagram for controller power control Hardware configuration diagram for CPU power consumption reduction control Setting flowchart for reducing power consumption of CPU Setting flowchart for reducing power consumption of CPU Hardware configuration diagram for CPU power consumption reduction control Setting flowchart for reducing power consumption of CPU Hardware configuration diagram for CPU power consumption reduction control Setting flowchart for reducing power consumption of CPU FIG. 10 is a block diagram illustrating an example of a hardware configuration related to power consumption reduction control of the CPU 301 in the fourth embodiment. The flowchart which performs the setting for reducing the power consumption of CPU301 in Example 4. FIG. The flowchart which performs setting in order to reduce the power consumption of CPU301 in Example 4.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

[Example 1]
FIG. 1 is a block diagram showing an example of the configuration of a network system to which an image forming apparatus according to an embodiment of the present invention can be applied. In the example shown in FIG. 1, the host computers 40 and 50 and the image forming apparatuses (10, 20, and 30) are connected to the LAN 60. However, in the system of the present invention, the number of connections is not limited. . In this embodiment, the LAN is applied as a method for connecting devices, but the present invention is not limited to this. For example, an arbitrary network such as a WAN (public line) can be applied.

  Host computers (hereinafter referred to as PCs) 40 and 50 have the functions of a general personal computer. The PCs 40 and 50 can send and receive files and send and receive e-mails using the FTP and SMB protocols via the LAN 60 and WAN. Further, it is possible to issue a print command from the PCs 40 and 50 to the image forming apparatuses 10, 20 and 30 via a printer driver.

  Further, the PCs 40 and 50 can periodically inquire of the image forming apparatuses 10, 20, and 30 about the state of the image forming apparatus, and the image forming apparatuses 10, 20, and 30 can be requested by the PCs 40 and 50. Information such as whether printing is possible can be returned.

  The image forming apparatus 10 and the image forming apparatus 20 are apparatuses having the same configuration. The image forming apparatuses 10 and 20 have a scanner unit. The image forming apparatus 30 is an image forming apparatus having only a print function, and does not have the scanner unit included in the image forming apparatuses 10 and 20.

  In the following, for the sake of simplicity of explanation, the configuration of the image forming apparatus 10 will be described in detail while focusing on the image forming apparatus 10, and the same applies to the image forming apparatus 20. The image forming apparatus 30 is the same as the image forming apparatus 10 except for the scanner unit.

  The image forming apparatus 10 includes a scanner unit 13 that is an image input device, a printer unit 14 that is an image output device, a controller 11 that controls operation of the entire image forming apparatus 10, and an operation unit 12 that is a user interface (UI). Have Hereinafter, the appearance of the image forming apparatus 10 will be described.

  FIG. 2 is a diagram illustrating an example of the appearance of the image forming apparatus 10. The scanner unit 13 has a plurality of CCDs. If the sensitivity of each CCD is different, it is recognized that each pixel has a different density even if the density of each pixel on the document is the same. Therefore, the scanner unit 13 first performs exposure scanning on a white plate (uniformly white plate), converts the amount of reflected light obtained by the exposure scanning into an electrical signal, and outputs it to the controller 11.

  Next, a configuration for scanning the image on the document will be described. The scanner unit 13 converts information of an image into an electrical signal by inputting reflected light obtained by exposing and scanning the image on the document to the CCD. Further, the scanner unit 13 converts the electrical signal into a luminance signal composed of R, G, and B colors, and outputs the luminance signal to the controller 11 as image data.

  The document is set on the tray 202 of the document feeder 201. When the user instructs to start reading from the operation unit 12, a document reading instruction is given from the controller 11 to the scanner unit 13. Upon receiving this instruction, the scanner unit 13 feeds the documents one by one from the tray 202 of the document feeder 201 and performs a document reading operation. The document reading method may be a method of scanning the document by placing the document on a glass surface (not shown) and moving the exposure unit instead of the automatic feeding method by the document feeder 201.

  The printer unit 14 is an image forming device that forms image data received from the controller 11 on a sheet. In this embodiment, the image forming method is an electrophotographic method using a photosensitive drum or a photosensitive belt, but the present invention is not limited to this. For example, the present invention can be applied to other printing methods such as an ink jet method and a sublimation method in which ink is ejected from a minute nozzle array and printed on a sheet. The printer unit 14 is provided with a plurality of paper cassettes 203, 204, and 205 that allow selection of different paper sizes or different paper orientations. The paper after printing is discharged to the paper discharge tray 206.

  FIG. 3 is a block diagram for explaining the configuration of the controller 11 of the image forming apparatus 10 in more detail. The controller 11 is electrically connected to the scanner unit 13 and the printer unit 14. On the other hand, the controller 11 is connected to the PCs 40 and 50, an external device, and the like via the LAN 60. Thereby, the controller 11 can input and output image data and device information.

  The CPU 301 comprehensively controls access to various connected devices based on a control program or the like stored in the ROM 303 and also comprehensively controls various processes performed in the controller 11. A RAM 302 is a system work memory for the operation of the CPU 301 and also a memory for temporarily storing image data. The RAM 302 includes an SRAM that can retain data even after the power is turned off, and a DRAM that erases the stored content after the power is turned off.

  The ROM 303 stores a boot program for the apparatus. The HDD 304 is a hard disk drive and can store system software and image data. The operation unit I / F 305 is an interface unit for connecting the system bus 307 and the operation unit 12. The operation unit I / F 305 receives image data to be displayed on the operation unit 12 from the system bus 307 and outputs the image data to the operation unit 12. The operation unit I / F 305 outputs information input from the operation unit 12 to the system bus 307.

  The LAN controller 306 is connected to the LAN 60 and the system bus 307 and controls communication between the image forming apparatus and the network by inputting and outputting information. The image bus 308 is a transmission path for exchanging image data, and is configured by a PCI bus or IEEE1394.

  The image processing unit 309 is for performing image processing, and can read image data stored in the RAM 302 and perform image processing such as enlargement or reduction of JPEG, JBIG, etc., and color adjustment.

  A scanner image processing unit 310 corrects, processes, and edits image data received from the scanner unit 13 via the scanner I / F 311. The scanner image processing unit 310 determines whether the received image data is a color document or a monochrome document, and determines whether the received image data is a character document or a photographic document. Then, the scanner image processing unit 310 attaches the determination result to the image data. Such accompanying information is referred to as attribute data.

  The printer image processing unit 312 performs image processing on the image data with reference to attribute data attached to the image data. The image data after the image processing is output to the printer unit 14 via the printer I / F 313.

  The power supply control unit 320 controls power supply state changes such as power supply control at start-up and power-off and transition / return to a power saving state. This is a part for detecting a return factor (for example, FAX reception, switch press, etc.) when returning from the power saving state, and the power control unit performs power control when shifting to the standby state according to each return factor. In addition, upon receiving a command from the CPU 301 or a signal for detecting return from a power saving state such as a Wake signal 402 to be described later, the first power supply unit 409 or the second power supply unit 410 sends each signal to each device. Controls whether to supply power.

  FIG. 4 is a block diagram illustrating an example of a hardware configuration relating to power control of the controller 11. The power control unit 320 receives a command from the CPU 301, a signal for detecting recovery from the sleep state from the LAN controller 306 (Wake 1 signal 402, Wake 2 signal 403, etc.), and the first power supply unit 409 or the The second power supply unit 410 controls whether to supply power to each device.

  The first power supply unit 409 corresponds to the power supplied even when the image forming apparatus is in the sleep state, and supplies, for example, 5V power (first power) (first power supply unit). The second power supply unit 410 corresponds to a power supply that is turned off when the image forming apparatus is in a sleep state, and supplies, for example, 12V power (second power) (second power supply unit). That is, the second power supplied from the second power supply unit 410 is higher in voltage than the first power supplied from the first power supply unit 409.

  The power supply control unit 320 controls the control signals 404 to 408 and supplies the second power to the devices 305 and 309 to 313 in the standby state in which the job can be executed, as well as the devices 301 to 304 and the LAN controller 306. The power supply is controlled so as to supply the first power to the power supply control unit 320 itself. In addition, the power supply control unit 320 controls the control signals 404 to 408 and shuts off the power supply to the devices 301 to 304, 305, and 309 to 313 in the sleep state in which power consumption is limited, and the LAN controller 306 In addition, the power supply control unit 320 performs control for continuously supplying the first power.

  That is, when shifting from the standby state to the sleep state, the power supply control unit 320 controls the second power supplied to the devices 301 to 305 and 309 to 313 to be cut off.

  The Wake 1 signal (first return signal) 402 notifies the power controller 320 of the fact from the LAN controller 306 when the LAN controller 306 receives a job packet via the network 60 in the sleep state. It is a signal for. When the power control unit 320 detects the Wake 1 signal, the power control unit 320 controls the control signals 404 to 408 to select the power to be supplied to each device.

  The Wake 2 signal (second return signal) 403 is a packet (for example, the state of the image forming apparatus 10) when the LAN controller 306 is not a job packet via the network 60 and is not a proxy response possible packet when in the sleep state. This is a signal for notifying the power controller 320 from the LAN controller 306 when an inquiry is received. When the power control unit 320 detects the Wake2 signal, the power control unit 320 controls the control signals 404 to 408 and selects the power to be supplied to each device (details will be described later).

  The control signals 404 to 408 are signals for controlling whether to supply power to each device. The switches 411 to 415 are switches controlled by control signals 404 to 408. The power supply control unit 320 controls the switches 411 to 415 with the control signals 404 to 408, whereby the power supply state for each device can be changed. The switches 411 to 415 can be realized by FETs, relay switches, or the like. The control signal 404 and the switch 413 control power supply to the LAN controller 306.

  The switch 413 controls the power supply to the LAN controller 306 when the image forming apparatus 10 is in the standby state and the sleep state, and stops the power supply to the LAN controller 306 when the image forming apparatus 10 is in the off state. doing. That is, the switch 413 switches between supplying and stopping power from the first power supply unit 409 to the LAN controller 306 (first switching unit).

  The control signal 405 and the switch 414 control the first power supply to the RAM 302. The switch 414 controls the power supply to the LARAM 302 when the image forming apparatus 10 is in the standby state and the sleep state, and stops the power supply to the RAM 302 when the image forming apparatus 10 is in the off state. That is, the switch 414 switches between supply and stop of power from the first power supply unit 409 to the RAM 302.

  A control signal 406 and a switch 415 control the first power supply to the CPU 301, ROM 303, and HDD 304. That is, the switch 415 switches the supply and stop of power from the first power supply unit 409 to the CPU 301, the ROM 303, and the HDD 304 (second switching unit). When the image forming apparatus 10 is in the standby state, power is supplied to the CPU 301, the ROM 303, and the HDD 304. When the image forming apparatus 10 is in the sleep state and the off state, control is performed so that the power to the CPU 301, the ROM 303, and the HDD 304 is stopped. doing. That is, the switch 415 switches between supply and stop of power from the first power supply unit 409 to the RAM 302.

  The control signal 407 and the switch 411 control the supply of AC power to the first power supply unit 409. The control signal 407 and the switch 411 are turned on by the power supply controller 320 when a switch 410 described later is turned on. This makes it possible to supply power to the controller 11 even when the user turns off the switch 410. At this time, the power supply control unit 320 detects that the switch 410 is turned off by a signal 416 for acquiring the on / off state of the switch 410, and notifies the CPU 301 of the fact that the normal shutdown process is performed. Then, the power supply to each device can be turned off.

  The switch 410 is a switch for the user to turn on / off the power to the image forming apparatus 10. When the user turns on the switch 410, AC power is supplied to the first power supply unit 409. Become.

  The control signal 408 and the switch 412 control the supply of AC power to the second power supply unit 410. The control signal 408 and the switch 412 control the second power supply to each device. For example, the power supply to the image processing unit 309 will be described. In the sleep state, the switch 412 is turned off and the power supply is stopped. In the standby state, the switch 412 is turned on and the second power supply unit 410 supplies power. Is done. That is, the switch 412 is controlled to be turned on and off by the power supply control unit 320, and switches between supply and stop of power from the second power supply unit 410 (third switching unit).

  The first power supply unit 409 converts AC power into DC power and supplies the first power to the power control unit 320 and the like. The first power supplied from the first power supply unit 409 is a power source provided to supply power to the power control unit 320 and the like even when the image forming apparatus 10 shifts to the sleep state. In addition to the power supply control unit 320, the first power supply is also supplied to the LAN controller 306 for detecting an incoming call from the network 60 for returning from the sleep state.

  The second power supply unit 410 converts AC power into DC power and supplies the second power to each device. The second power supplied from the second power supply unit 410 is a power that stops the power supply when the image forming apparatus 10 is in the sleep state. The second power supply unit 410 is provided to reduce power consumption in the sleep state and supply power to various devices that do not require power supply in the sleep state.

  FIG. 5 is a block diagram illustrating an example of a hardware configuration related to power consumption reduction control of the CPU 301.

  The CPU core power supply circuit 501 is a circuit that generates power to operate the CPU cores 505 and 507 and the caches 506 and 508 and supplies the power to the CPU 301. The CPU core power supply circuit 501 can change the power supply voltage to be generated by communicating with the CPU power supply control unit 504 that has received an instruction from the CPU cores 505 and 507. The power supply voltage can be set in accordance with the CPU cores 505 and 507, and the value of the power supply voltage can be selected from a plurality. The power consumption can be reduced by setting the power supply voltage low.

  The clock generation circuit 502 is a circuit for generating a reference clock of an operation clock supplied to the CPU cores 505 and 507. The Phase Locked Loop (PLL) 503 is a circuit for generating an operation clock to be supplied to the CPU cores 505 and 507. The PLL 503 can change the frequency of the operation clock to be supplied in accordance with instructions from the CPUs 505 and 507. Power consumption can be reduced by lowering the operating clock frequency.

  The CPU power supply control unit 504 receives a power supply voltage change instruction from the CPU cores 505 and 507 and notifies the CPU core power supply circuit 501 of the instruction. A bus 512 that connects the CPU power supply control unit 504 and the CPU core power supply circuit 501 is a serial bus that can perform bidirectional communication.

  The CPU cores 505 and 507 are circuits for performing actual program execution and arithmetic processing in the main part of the CPU. The CPU cores 505 and 507 have a configuration in which a power supply voltage to be input can be selected from a plurality. A higher voltage is selected when priority is given to processing speed over power consumption, and conversely power consumption over processing speed. If you want to prioritize, select a lower voltage. In addition, the CPU cores 505 and 507 have a configuration in which an operating frequency can be selected from a plurality of operating frequencies. When the processing speed is given priority over the power consumption, a higher operating frequency is selected, and conversely, the power consumption is higher than the processing speed. If you want to prioritize, select a lower operating frequency.

  Here, the CPU 301 includes two CPU cores. However, the number of CPU cores may be one or more. Further, the CPU core 505 and the CPU core 507 are not necessarily the same. For example, the CPU core 505 may be capable of processing at higher speed than the CPU core 505. Caches 506 and 508 are storage devices for speeding up data communication between the CPU and the storage device and ensuring the CPU processing speed. A bus 510 is an internal bus for performing communication between modules in the CPU.

  The clock 511 is a clock signal generated by the clock generation circuit and input to the CPU 301, and is a reference clock for generating a CPU operation clock. The operation clocks 513 and 514 are CPU operation clock signals, and are input to the CPU cores 505 and 507 as clock signals at the operation frequency from the PLL 503 to which the clock 511 is input. The operation clocks 513 and 514 can select a frequency output from the PLL 503 according to an instruction from the CPU cores 505 and 507, and are output at a frequency according to the selection.

  FIG. 6 is a flowchart showing the hardware operation from when the return factor is detected until the CPU 301 operates. In step S601, it is determined whether or not the power control unit 320 has detected a factor as to whether or not to return from the sleep state. If the power supply control unit 320 determines that a return factor has been detected, the process proceeds to S602; otherwise, the state of S601 is maintained.

  In step S <b> 602, the CPU core power supply circuit 501 that the power supply control unit 320 supplies to the CPU cores 505 and 507 and the caches 506 and 508 is turned on. Here, the power supply voltage generated by the CPU core power supply circuit 501 is a high voltage among the power supply voltages usable by the CPU cores 505 and 507 and the caches 506 and 508. By supplying a high voltage, the CPU 301 can operate at high speed and can shorten the return time from the sleep state. It is also possible to supply a low voltage with priority on power consumption.

  In step S <b> 603, the clock generation circuit 502 oscillates the clock 511 with respect to the PLL 503 of the CPU 301. The PLL 503 to which the clock 511 is input oscillates the operation clocks 513 and 514 with respect to the CPU cores 505 and 507. Here, the operation clocks 513 and 514 generated by the PLL 503 supply a clock having a higher frequency among the operation frequencies usable by the CPU cores 505 and 507. By supplying a clock with a high frequency, the CPU 301 can operate at high speed, and the recovery time from the sleep state can be shortened. It is also possible to supply a low-frequency clock giving priority to power consumption.

FIG. 7 is a flowchart in which the CPU 301 performs settings for reducing power consumption.
In step S <b> 701, the CPU core 505 acquires a return factor detected by the power control unit 320. The power supply control unit 320 holds the factor so that the CPU core 505 can acquire the factor when detecting the factor of return from sleep.

  In step S <b> 702, the CPU core 505 determines whether the return factor acquired from the power control unit 320 is a print job. For example, when the Wake1 signal 402 returns from the sleep state, a print job is received. Therefore, the CPU core 505 determines that the job has been received, and when the Wake2 signal 403 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that a job has not been received. The LAN controller 306 determines whether the Wake signals 402 and 403 are selected, and performs signal selection.

  When receiving the packet, the LAN controller 306 analyzes the packet and determines whether the packet is a Wake On LAN (WOL) packet or a packet capable of proxy response. When it is determined that the packet is a WOL packet, the LAN controller 306 confirms the destination port number. When the destination port number is “9100”, the LAN controller 306 determines that the job is a job, asserts the Wake1 signal 402, and does not specify the destination. When the number and the LAN controller 306 determine, the Wake2 signal 403 is asserted. Based on the state of the Wake signals 402 and 403 from the LAN controller 306, the power supply control unit 320 determines whether or not the return factor is a job.

  In step S <b> 703, since the job and the CPU core 505 have determined in step S <b> 702, the CPU core 505 sets a high power supply voltage for high-speed operation to the CPU core power supply circuit 501 via the CPU power supply control unit 504. As a result, a high power supply voltage is supplied to the CPU cores 505 and 507 and the caches 506 and 508, and high-speed processing can be executed.

  In step S <b> 704, since the job and the CPU core 505 have determined in step S <b> 702, the CPU core 505 sets a high operating frequency for high-speed operation in the PLL 503. As a result, it is possible to supply the operating clocks 513 and 514 having a high operating frequency to the CPU cores 505 and 507 and execute high-speed processing. By performing the setting for high-speed operation in S703 and S704, the job can be processed in a short time.

  In step S705, since the CPU core 505 determines that the job is not a job in step S702, the CPU core 505 passes the CPU power supply control unit 504 to the CPU core power supply circuit 501 with a low power supply voltage for low power consumption operation. Set up. As a result, a low power supply voltage can be supplied to the CPU cores 505 and 507 and the caches 506 and 508 to reduce power consumption.

  In step S <b> 706, since the CPU core 505 determines that the job is not a job in step S <b> 702, the CPU core 505 sets a low operating frequency for low power consumption operation in the PLL 503. As a result, it is possible to supply operation clocks 513 and 514 having a low operation frequency to the CPU cores 505 and 507, thereby reducing power consumption. By implementing the setting for low speed operation in S705 and S706, the CPU 301 can operate with low power consumption.

  In step S707, it is determined whether or not the job received by the CPU 301 as a return factor has ended. If it is determined that the job is finished, the process proceeds to S705. In step S708, the CPU 301 determines whether a job is detected. If it is determined that a job has been received, the process proceeds to S703. If it is determined that no job has been detected, the process proceeds to S709. Here, it is assumed that the job returns from the sleep state and the user requests a copy operation or a send operation.

  In step S709, it is determined whether the CPU 301 has detected a sleep transition factor. If it is determined that the sleep transition factor is detected, the process proceeds to S710. If the sleep transition factor is not detected, the process proceeds to S708. The sleep transition factor here assumes a case where a sleep transition factor due to timer detection or a switch press by the user is detected.

  In step S <b> 710, the CPU 301 performs processing for causing the image forming apparatus 10 to transition to the sleep state in accordance with the CPU 301 detecting the cause of sleep transition.

  In this way, by switching between setting the CPU 301 to the high speed operation state or the low speed operation state according to the return factor from the sleep state, the power consumption by the CPU 301 can be reduced and stable for the user. It is possible to provide processing power. Further, the system control can be simplified while the voltage and frequency are dynamically changed by switching the operation state of the CPU 301 depending on the return factor.

  It should be noted that the configuration and contents of the various data described above are not limited to this, and it goes without saying that the various data and configurations are configured according to the application and purpose.

  Although one embodiment has been described above, the present invention can take an embodiment as, for example, a system, apparatus, method, program, or storage medium. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

  Moreover, all the structures which combined said each Example are also contained in this invention. Furthermore, the present invention can be applied to a system composed of a plurality of devices (for example, a computer, an interface device, a reader, a printer, etc.), and can also be applied to a device composed of a single device (a multifunction device, a printer, a facsimile device, etc.). It is also possible to do.

[Example 2]
In the first embodiment, the example in which the operation state of the CPU cores 505 and 507 is set according to the return factor when the image processing apparatus 10 returns from the sleep state has been described.

  In the second embodiment, an example in which the operation states of the CPU cores 505 and 507 are set from both the return factor from the sleep state and the shift factor to the sleep after the return will be described.

  FIG. 8 is a flowchart for setting to reduce the power consumption of the CPU 301 in the second embodiment. In step S <b> 801, the CPU core 505 acquires a return factor detected by the power control unit 320. The power supply control unit 320 holds the factor so that the CPU core 505 can acquire the factor when detecting the factor of return from sleep.

  In step S <b> 802, the CPU core 505 determines whether the return factor acquired from the power control unit 320 is a print job. For example, when the Wake1 signal 402 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that the job has been received, and when the Wake2 signal 403 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that a job has not been received. The LAN controller 306 determines whether the Wake signals 402 and 403 are selected, and performs signal selection.

  When receiving the packet, the LAN controller 306 analyzes the packet and determines whether the packet is a Wake On LAN (WOL) packet or a packet capable of proxy response. When it is determined that the packet is a WOL packet, the LAN controller 306 confirms the destination port number. When the destination port number is “9100”, the LAN controller 306 determines that the job is a job, asserts the Wake1 signal 402, and does not specify the destination. When the number and the LAN controller 306 determine, the Wake2 signal 403 is asserted. Based on the states of the Wake signals 402 and 403 from the LAN controller 306, the power control unit 320 determines whether or not the return factor is a print job.

  In S803, since the job and the CPU core 505 have determined in S802, the CPU core 505 sets a high power supply voltage for high-speed operation to the CPU core power supply circuit 501 via the CPU power supply control unit 504. As a result, a high power supply voltage is supplied to the CPU cores 505 and 507 and the caches 506 and 508, and high-speed processing can be executed.

  In S804, since the job and the CPU core 505 have determined in S802, the CPU core 505 sets a high operating frequency for high-speed operation in the PLL 503. As a result, it is possible to supply the operating clocks 513 and 514 having a high operating frequency to the CPU cores 505 and 507 and execute high-speed processing. By performing the setting for high-speed operation in S803 and S804, the job can be processed in a short time.

  In step S805, the CPU core 505 determines whether the return factor acquired from the power control unit 320 is a network packet. If it is determined that the return factor is a network packet, the process proceeds to S806. If it is determined that the return factor is not a network packet, the process proceeds to S807. For example, when the Wake2 signal 403 is used to return from the sleep state, the job packet is not received, but other WOL packets are received, so that the return factor is determined to be a network packet. It is determined that this is not a cause of return due to network packets.

  In step S <b> 806, it is determined whether or not the image forming apparatus 10 can be immediately shifted to the sleep state after the CPU 505 performs processing on the network packet. If it is possible to shift to sleep immediately after the network packet response, the process proceeds to S803. If it is not possible to shift to sleep immediately, the process proceeds to S807. For example, when the second power supply unit is turned off when the network packet is restored, the CPU 301, the ROM 303, and the HDD 304 are energized from the first power supply unit, and the CPU 301 immediately transitions to the sleep state after processing the network packet. Can be considered.

  In this case, the CPU 301 performs processing in a high-speed operation state, and power consumption can be reduced by shifting to sleep immediately after processing. Further, for example, when the network packet cannot be immediately shifted to the sleep state by using a timer or the like after returning from the sleep with the network packet, the CPU 301 may reduce the total power consumption for the CPU 301 by processing the network packet in the low-speed operation state. Is possible.

  In step S <b> 807, the CPU core 505 determines that the return factor is not a job and cannot shift to sleep immediately after network packet processing, so the CPU core 505 sends a CPU power supply control unit 504 to the CPU core power supply circuit 501. Set a low power supply voltage for low power consumption operation. As a result, a low power supply voltage can be supplied to the CPU cores 505 and 507 and the caches 506 and 508 to reduce power consumption.

  In step S808, since the SCPU core 505 determines that the return factor is not a job and cannot shift to sleep immediately after network packet processing, the CPU core 505 sets a low operating frequency for low power consumption operation in the PLL 503. As a result, it is possible to supply operation clocks 513 and 514 having a low operation frequency to the CPU cores 505 and 507, thereby reducing power consumption. By performing the setting for low-speed operation in S807 and S808, the CPU 301 can operate with low power consumption.

  In step S809, the CPU 301 determines whether the job received as a return factor has ended. If it is determined that the job has been completed, the process proceeds to S807. In step S810, the CPU 301 determines whether the network packet processing has been completed. If it is determined that the network packet processing has been completed, the process proceeds to S813. If it is determined that the network packet process has not been completed, the process proceeds to S809.

  In step S811, the CPU 301 determines whether a job has been detected. If it is determined that a job has been received, the process proceeds to S803. If it is determined that no job has been detected, the process proceeds to S812. Here, it is assumed that the job returns from the sleep state and the user requests a copy operation or a send operation.

  In step S812, the CPU 301 determines whether a sleep transition factor has been detected. If it is determined that the sleep transition factor is detected, the process proceeds to S813. If the sleep transition factor is not detected, the process proceeds to S811. The sleep transition factor here assumes a case where a sleep transition factor due to timer detection or a switch press by the user is detected. In step S <b> 813, the CPU 301 performs processing for causing the image forming apparatus 10 to transition to the sleep state in accordance with the CPU 301 detecting the sleep transition factor.

  As described above, the power consumption by the CPU 301 is switched by switching the CPU 301 to the high speed operation state or the low speed operation state according to the return factor from the sleep state and whether or not the sleep can be immediately performed after the return. Can be reduced, and a certain processing capability can be provided to the user. Further, it is possible to avoid the complexity of the system control by switching the operation state of the CPU 301 depending on the return factor and whether or not the sleep can be immediately shifted after the return.

It should be noted that the configuration and contents of the various data described above are not limited to this, and it goes without saying that the various data and configurations are configured according to the application and purpose.
Although one embodiment has been described above, the present invention can take an embodiment as, for example, a system, apparatus, method, program, or storage medium. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

  Moreover, all the structures which combined said each Example are also contained in this invention. Furthermore, the present invention can be applied to a system composed of a plurality of devices (for example, a computer, an interface device, a reader, a printer, etc.), and can also be applied to a device composed of a single device (a multifunction device, a printer, a facsimile device, etc.). It is also possible to do.

[Example 3]
In the first and second embodiments, the example in which the operation state of the CPU cores 505 and 507 is set based on the return factor when the image processing apparatus 10 returns from the sleep state has been described. In the third embodiment, an example will be described in which power supply switching to the CPU cores 505 and 507 is performed according to a return factor when returning from the sleep state.

  FIG. 9 is a block diagram illustrating an example of a hardware configuration related to power consumption reduction control of the CPU 301 in the third embodiment. A control signal 901 is a control signal for controlling turning off / on of power supplied to the CPU core 507 and Cache 508.

  The switches 902 and 903 are switches for controlling the on / off of the power supplied to the CPU core 507 and the Cache 508. Switch control is performed by a control signal 801. When the switch is on, power is supplied to the CPU core 507 and the cache 508. When the switch is off, power supply is stopped to the CPU core 507 and the cache 508.

  FIG. 10 is a flowchart showing the hardware operation from when the return factor is detected until the CPU 301 operates. In step S1001, it is determined whether or not the power control unit 320 has detected a factor as to whether or not to return from the sleep state. If the power supply control unit 320 determines that a return factor has been detected, the process proceeds to S1002, and if not, the state of S1001 is maintained.

  In step S <b> 1002, the power supply control unit 320 turns on the CPU core power supply circuit 501 supplied to the CPU cores 505 and 507 and the caches 506 and 508. Inside the CPU 301, the CPU core 507 and the Cache 508 are kept off. In step S <b> 1003, the clock generation circuit 502 oscillates the clock 511 with respect to the PLL 503 of the CPU 301. The PLL 503 to which the clock 511 is input oscillates the operation clock 513 to the CPU core 505.

  FIG. 11 is a flowchart for performing setting for reducing power consumption of the CPU 301 in the third embodiment. In step S1101, the CPU core 505 acquires the return factor detected by the power supply control unit 320. The power supply control unit 320 holds the factor so that the CPU core 505 can acquire the factor when detecting the factor of return from sleep.

  In step S1102, the CPU core 505 determines whether the return factor acquired from the power supply control unit 320 is a job. For example, when the Wake1 signal 402 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that the job has been received, and when the Wake2 signal 403 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that a job has not been received. The LAN controller 306 determines whether the Wake signals 402 and 403 are selected, and performs signal selection.

  When receiving the packet, the LAN controller 306 analyzes the packet and determines whether the packet is a Wake On LAN (WOL) packet or a packet capable of proxy response. When it is determined that the packet is a WOL packet, the LAN controller 306 confirms the destination port number. When the destination port number is “9100”, the LAN controller 306 determines that the job is a job, asserts the Wake1 signal 402, and does not specify the destination. When the number and the LAN controller 306 determine, the Wake2 signal 403 is asserted. Based on the state of the Wake signals 402 and 403 from the LAN controller 306, the power supply control unit 320 determines whether or not the return factor is a job.

  In step S1103, since the job and the CPU core 505 have determined in step S1102, the CPU core 505 turns on the control signal 901 to turn on the switches 902 and 903, thereby supplying power to the CPU core 507 and the cache 508. As a result, power is supplied to the CPU cores 505 and 507 and the caches 506 and 508 so that all the CPU cores can be used, and a plurality of CPU cores can be used at the same time so that high-speed processing can be executed. It becomes.

  In step S <b> 1104, since the CPU and the CPU core 505 make a determination in step S <b> 1102, the CPU core 505 performs setting to oscillate the operation clock 514 to the PLL 503. As a result, since the operation clocks 513 and 514 are supplied to the CPU cores 505 and 507, high-speed processing can be executed by making all the CPU cores usable. By making all the CPU cores and caches usable in S1103 and S1104, the CPU enters a high-speed operation state and can process a job in a short time.

  In step S <b> 1105, the CPU core 505 determines that the job is not a job in step S <b> 1102. As a result, the operation clock 514 for the CPU core 507 is stopped, so that power consumption can be reduced.

  In S1106, since the CPU core 505 determines that the job is not a job in S1102, the CPU core 505 turns off the control signal 901. As a result, the switches 902 and 903 are turned off, and the power supply to the CPU core 507 and Cache 508 is stopped. A low power supply voltage for low power consumption operation is set for the CPU core power supply circuit 501. By performing the setting for low-speed operation in S1105 and S1106, the operation of the CPU core 507 and the Cache 508 is stopped, so that the low power consumption operation can be performed.

  In step S1107, it is determined whether the job received by the CPU 301 as a return factor has ended. If it is determined that the job is finished, the process proceeds to S1105. In step S1108, the CPU 301 determines whether a job is detected. If it is determined that the job is received, the process proceeds to S1103. If it is determined that the job is not detected, the process proceeds to S1109. Here, it is assumed that the job returns from the sleep state and the user requests a copy operation or a send operation.

  In step S1109, the CPU 301 determines whether a sleep transition factor has been detected. If it is determined that the sleep transition factor is detected, the process proceeds to S1110. If the sleep transition factor is not detected, the process proceeds to S1108. The sleep transition factor here assumes a case where a sleep transition factor due to timer detection or a switch press by the user is detected.

  In step S <b> 1110, the CPU 301 performs a process of causing the image forming apparatus 10 to transition to the sleep state as the CPU 301 detects the sleep transition factor.

  As described above, by switching between setting the CPU 301 to the high-speed operation state or the low-speed operation state in accordance with the return factor from the sleep state, the power consumption by the CPU 301 can be reduced, and a certain amount can be given to the user. It is possible to provide processing power. Further, the system control can be simplified while the voltage and frequency are dynamically changed by switching the operation state of the CPU 301 depending on the return factor.

  It should be noted that the configuration and contents of the various data described above are not limited to this, and it goes without saying that the various data and configurations are configured according to the application and purpose.

  Although one embodiment has been described above, the present invention can take an embodiment as, for example, a system, apparatus, method, program, or storage medium. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

  Moreover, all the structures which combined said each Example are also contained in this invention. Furthermore, the present invention can be applied to a system composed of a plurality of devices (for example, a computer, an interface device, a reader, a printer, etc.), and can also be applied to a device composed of a single device (a multifunction device, a printer, a facsimile device, etc.). It is also possible to do.

[Example 4]
In the first and second embodiments, the example in which the operation state of the CPU cores 505 and 507 is set based on the return factor when the image processing apparatus 10 returns from the sleep state has been described. Further, in the third embodiment, the example in which the power supply is switched to the CPU cores 505 and 507 according to the return factor when returning from the sleep state has been described. In the fourth embodiment, an example in which the power supply is switched to the caches 506 and 508 according to the return factor when returning from the sleep state will be described.

  FIG. 12 is a block diagram illustrating an example of a hardware configuration related to power consumption reduction control of the CPU 301 in the fourth embodiment. A control signal 1201 is a control signal for controlling the on / off of the power supplied to the caches 507 and 508.

  The switches 1202 and 1203 are switches for controlling the on / off of the power supplied to the caches 507 and 508. Switch control is performed by a control signal 1201, power is supplied to the caches 507 and 508 when on, and power supply to the caches 507 and 508 is stopped when off.

  FIG. 13 is a flowchart for performing setting for reducing power consumption of the CPU 301 in the fourth embodiment.

  In step S1301, it is determined whether or not the power control unit 320 has detected a factor as to whether or not to return from the sleep state. If the power supply control unit 320 determines that a return factor has been detected, the process proceeds to S1302, and if not, the state of S1301 is maintained.

  In step S1302, the CPU core power supply circuit 501 supplied to the CPU cores 505 and 507 and the caches 506 and 508 by the power supply control unit 320 is turned on. In the CPU 301, the caches 507 and 508 are kept turned off. In S <b> 1303, the clock generation circuit 502 oscillates the clock 511 with respect to the PLL 503 of the CPU 301. The PLL 503 to which the clock 511 is input oscillates the operation clocks 513 and 514 with respect to the CPU cores 505 and 507.

  FIG. 14 is a flowchart for setting to reduce the power consumption of the CPU 301 in the fourth embodiment.

  In step S1401, the CPU core 505 acquires a return factor detected by the power control unit 320. The power supply control unit 320 holds the factor so that the CPU core 505 can acquire the factor when detecting the factor of return from sleep.

  In step S1402, the CPU core 505 determines whether the return factor acquired from the power control unit 320 is a job. For example, when the Wake1 signal 402 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that the job has been received, and when the Wake2 signal 403 returns from the sleep state, the job packet is received. Therefore, the CPU core 505 determines that a job has not been received. The LAN controller 306 determines whether the Wake signals 402 and 403 are selected, and performs signal selection.

  When receiving the packet, the LAN controller 306 analyzes the packet and determines whether the packet is a Wake On LAN (WOL) packet or a packet capable of proxy response. When it is determined that the packet is a WOL packet, the LAN controller 306 confirms the destination port number. When the destination port number is “9100”, the LAN controller 306 determines that the job is a job, asserts the Wake1 signal 402, and does not specify the destination. When the number and the LAN controller 306 determine, the Wake2 signal 403 is asserted. Based on the state of the Wake signals 402 and 403 from the LAN controller 306, the power supply control unit 320 determines whether or not the return factor is a job.

  In S1403, since the job and the CPU core 505 have determined in S1402, when the CPU core 505 turns on the control signal 1201, the switches 1202 and 1203 are turned on to supply power to the CPU core 507 and Cache 508. As a result, power is supplied to the CPU cores 505 and 507 and the caches 506 and 508, whereby high-speed processing can be executed, and jobs can be processed in a short time.

  In step S1405, since the CPU core 505 determines that the job is not a job in step S1402, the CPU core 505 performs setting to turn off the control signal 1201. As a result, the power supply to the caches 506 and 508 is stopped, so that the processing capacity of the CPU 301 is reduced compared to the state in which the caches 506 and 508 are energized and usable, but the power consumption can be reduced.

  In step S1407, it is determined whether or not the job received by the CPU 301 as a return factor has ended. If it is determined that the job has been completed, the process advances to step S1405.

  In step S1408, the CPU 301 determines whether a job is detected. If it is determined that a job has been received, the process advances to step S1403. If it is determined that no job has been detected, the process advances to step S1409. Here, it is assumed that the job returns from the sleep state and the user requests a copy operation or a send operation.

  In step S1409, the CPU 301 determines whether a sleep transition factor is detected. If it is determined that a sleep transition factor is detected, the process proceeds to S1410. If a sleep transition factor is not detected, the process proceeds to S1408. The sleep transition factor here assumes a case where a sleep transition factor due to timer detection or a switch press by the user is detected.

  In step S <b> 1410, the CPU 301 performs processing for causing the image forming apparatus 10 to transition to the sleep state in accordance with the CPU 301 detecting the cause of sleep transition.

  As described above, by switching between setting the CPU 301 to the high-speed operation state or the low-speed operation state in accordance with the return factor from the sleep state, the power consumption by the CPU 301 can be reduced, and a certain amount can be given to the user. It is possible to provide processing power. Further, it is possible to avoid the complexity of system control by switching the operation state of the CPU 301 depending on the return factor.

  It should be noted that the configuration and contents of the various data described above are not limited to this, and it goes without saying that the various data and configurations are configured according to the application and purpose.

  Although one embodiment has been described above, the present invention can take an embodiment as, for example, a system, apparatus, method, program, or storage medium. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

  Moreover, all the structures which combined said each Example are also contained in this invention. Furthermore, the present invention can be applied to a system composed of a plurality of devices (for example, a computer, an interface device, a reader, a printer, etc.), and can also be applied to a device composed of a single device (a multifunction device, a printer, a facsimile device, etc.). It is also possible to do.

[Other Examples]
Furthermore, the present invention can be applied to a system constituted by a plurality of devices (for example, a computer, an interface device, a reader, a printer, etc.), and can also be applied to an apparatus (multifunction device, printer, facsimile machine, etc.) comprising a single device. It is also possible.

  Another object of the present invention is that a computer (or CPU or MPU) of a system or apparatus reads and executes the program code from a storage medium that stores the program code for realizing the procedure of the flowchart shown in the above-described embodiment. Is also achieved. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment. Therefore, the program code and a storage medium storing the program code also constitute one of the present invention.

  As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code is actually used. A case where part or all of the processing is performed and the functions of the above-described embodiments are realized by the processing is also included.

  Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion board is based on the instruction of the program code. The CPU of the function expansion unit or the like performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

301 CPU, 501 CPU core power supply circuit, 502 clock generation circuit,
503 PLL, 505 CPU core (A), 506 CPU core (B),
507 Cache (A), 508 Cache (B)

Claims (20)

In the image forming apparatus (10) having the power saving state,
Return factor detection means (S605) for detecting a return factor when returning from the power saving state;
A CPU (301) for performing processing in the image forming apparatus (10);
Power supply means (501) for supplying power to the CPU (301);
Clock supply means (503) for supplying a clock to the CPU (301);
A clock frequency setting means (503) for setting a clock frequency supplied from the clock supply means (503);
It is possible to select a power supply voltage and a clock frequency for the CPU (301) when the image forming apparatus (10) is restored based on a restoration factor detected by the restoration factor detection means. Image forming apparatus. When the return factor detected by the return factor detection means is a job from the network (60), the power supply voltage supplied to the CPU (301) is a high voltage value by the power supply voltage setting means (512). The image forming apparatus according to claim 1, wherein When the return factor detected by the return factor detection means is not a job from the network (60), the power supply voltage supplied to the CPU (301) is set to a low voltage value by the power supply voltage setting means (512). The image forming apparatus according to claim 1, wherein the image forming apparatus is set. When the return factor detected by the return factor detection means is a job from the network (60), the clock supplied to the CPU (301) is set to a high frequency by the clock frequency setting means (512). The image forming apparatus according to claim 1. If the return factor detected by the return factor detection means is not a job from the network (60), the clock supplied to the CPU (301) is set to a low frequency by the clock frequency setting means (512). The image forming apparatus according to claim 1. In the image forming apparatus (10) having the power saving state,
Return factor detection means (S705) for detecting a return factor when returning from the power saving state;
A power saving state transition determining means (S709) for determining whether or not the power saving state can be shifted when the return factor is returned by a response to the network packet;
A CPU (301) for performing processing in the image forming apparatus (10);
Power supply means (501) for supplying power to the CPU (301);
Power supply voltage setting means (512) for setting a power supply voltage value supplied from the power supply means (501);
Clock supply means (503) for supplying a clock to the CPU (301);
A clock frequency setting means (503) for setting a clock frequency supplied from the clock supply means (503);
The power supply voltage and clock for the CPU (301) when the image forming apparatus (10) is restored based on both the restoration factor detected by the restoration factor detection means and the power saving state transition judgment means (S709). An image forming apparatus capable of selecting a frequency. When the return factor detected by the return factor detection means is a job from the network (60), the power supply voltage supplied to the CPU (301) is a high voltage value by the power supply voltage setting means (512). The image forming apparatus according to claim 6, wherein: When the return factor detected by the return factor detection means is the network (60) but is not a job, and when it is possible to shift to the power saving state immediately after network packet processing by the power saving state transition determination means (S709). The image forming apparatus according to claim 6, wherein the power supply voltage supplied to the CPU (301) is set to a high voltage value by the power supply voltage setting means (512). If the return factor detected by the return factor detection means is not the network (60) or if the power saving state transition determination means (S709) cannot immediately enter the power saving state after the network packet processing, the CPU (301 7. The image forming apparatus according to claim 6, wherein the power supply voltage supplied to the power supply voltage setting unit is set to a low voltage value by the power supply voltage setting means (512). When the return factor detected by the return factor detection means is a job from the network (60), the clock supplied to the CPU (301) is set to a high frequency by the clock frequency setting means (512). The image forming apparatus according to claim 6. When the return factor detected by the return factor detection means is the network (60) but is not a job, and when it is possible to shift to the power saving state immediately after network packet processing by the power saving state transition determination means (S709). The image forming apparatus according to claim 6, wherein the clock supplied to the CPU (301) is set to a high frequency by the clock frequency setting means (512). If the return factor detected by the return factor detection means is not the network (60) or if the power saving state transition determination means (S709) cannot immediately enter the power saving state after the network packet processing, the CPU (301 7. The image forming apparatus according to claim 6, wherein the clock supplied to () is set to a low frequency by the clock frequency setting means (512). In the image forming apparatus (10) having the power saving state,
Return factor detection means (S605) for detecting a return factor when returning from the power saving state;
A CPU (301) that performs processing in the image forming apparatus (10) and includes a plurality of CPU cores (505, 507) inside;
Power supply means (501, 801, 802, 803) for supplying power to each core in the CPU (301);
Clock supply means (503) for supplying a clock to the CPU (301);
Clock output setting means (503) for setting output / stop of a clock supplied from the clock supply means (503),
It is possible to select power supply and clock supply to the core in the CPU (301) when the image forming apparatus (10) returns based on the return factor detected by the return factor detection means. An image forming apparatus. When the return factor detected by the return factor detection means is a job from the network (60), the power supply voltage setting means (512, 801, 802, 803) is applied to all the cores in the CPU (301). The image forming apparatus according to claim 13, wherein the power is supplied by the above-described method. If the return factor detected by the return factor detection means is not a job from the network (60), the power supply voltage setting means (512, 801, 802, 803) for some cores in the CPU (301). The image forming apparatus according to claim 13, wherein the power is supplied by the above-described method. When the return factor detected by the return factor detection means is a job from the network (60), the clock supply means (503) supplies the clock to all the cores in the CPU (301). The image forming apparatus according to claim 13. If the return factor detected by the return factor detection means is not a job from the network (60), the clock supply means (503) supplies a clock to some cores in the CPU (301). The image forming apparatus according to claim 13. In the image forming apparatus (10) having the power saving state,
Return factor detection means (S605) for detecting a return factor when returning from the power saving state;
A CPU (301) that performs processing in the image forming apparatus (10) and includes a plurality of CPU cores (505, 507) inside;
Power supply means (501, 1001, 1002, 1003) for supplying power to each core and cache in the CPU (301);
Clock supply means (503) for supplying a clock to the CPU (301);
Clock output setting means (503) for setting output / stop of a clock supplied from the clock supply means (503),
It is possible to select power supply to the cache (506, 508) in the CPU (301) when the image forming apparatus (10) returns based on the return factor detected by the return factor detection means. An image forming apparatus. When the return factor detected by the return factor detection means is a job from the network (60), the above-described processing is performed for all cores (505, 507) and caches (506, 508) in the CPU (301). 14. The image forming apparatus according to claim 13, wherein power is supplied by a power supply voltage setting unit (512, 1001, 1002, 1003). If the return factor detected by the return factor detection means is not a job from the network (60), the power source voltage setting means (512, 801, 802, 803) only applies to the core in the CPU (301). 19. The image forming apparatus according to claim 18, wherein power supply is performed and power supply to the caches (506, 508) is stopped.