JP2016167527A - Semiconductor module and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module excellent in connection reliability even under a high temperature environment.SOLUTION: A semiconductor module according to the present embodiment comprises: a substrate having a wiring layer; a semiconductor element which is mounted on the substrate and has an electrode on a surface; and a conductive plate bonded to the electrode of the semiconductor element via a sintered metal layer. The electrode on the surface of the semiconductor element is divided into a plurality of electrodes by gate wiring parts which are inactive areas, and in the sintered metal layer, a sintered density of regions on the inactive areas is lower than that of the other regions.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor module having a sintered bonding layer and a manufacturing method thereof.

  A semiconductor module such as an IGBT module handles a large current of several tens to several hundreds A per semiconductor chip, and thus generates a large amount of heat from the semiconductor chip. In recent years, further miniaturization of semiconductor modules has been demanded, and the heat generation density tends to increase more and more. Conventionally, solder having a melting point of about 300 ° C. and a lead content of 85% or more has been used for joining a semiconductor chip and a wiring layer in order to ensure heat resistance.

  However, lead-free semiconductor devices have become necessary from the viewpoint of limiting the burden on the global environment. As lead-free solder materials, Sn—Cu solder, Sn—Ag solder, Sn—Sb solder, etc. are known, but all have a melting point of about 200 ° C. and cannot secure heat resistance.

  Therefore, as an alternative to solder bonding, sintered bonding utilizing the low-temperature firing function of metal nanoparticles is expected. In the case of metal nanoparticles having a particle size of 100 nm or less, as the number of constituent atoms decreases, the surface area with respect to the volume of the particles increases rapidly, so that the melting point and sintering temperature of the particles are significantly reduced compared to the bulk state. By utilizing this phenomenon and joining metal particles by sintering them at a low temperature, the metal particles after joining change into a bulk metal. At the same time, the materials to be joined are joined by metal bonding, and thus have extremely high heat resistance and high heat dissipation.

  On the other hand, the main electrode of a semiconductor chip made of Si or SiC is connected to another chip or electrode by a wiring material such as a wire or ribbon made of copper or aluminum. When the operating temperature of the semiconductor chip is increased, the thermal expansion coefficient of the semiconductor chip and the wiring material are different, so that the joint portion is destroyed due to thermal fatigue while switching operation (energization ON / OFF operation) is repeated. There was a problem.

  Therefore, as a technique for improving the reliability of wiring connection, Patent Document 1 discloses a connection with a large difference in thermal expansion coefficient using a metal plate having a thermal expansion coefficient intermediate between the wiring member and the semiconductor chip from the viewpoint of stress buffering. A method of eliminating the part has been proposed. Further, Patent Document 1 describes that a material containing sinterable silver fine particles is used as a bonding material for bonding a semiconductor chip and a metal plate.

  Further, Patent Document 2 uses a metal plate having a structure in which a gate wiring part has a convex shape, and without applying an adhesive to the gate wiring part on the semiconductor chip, the semiconductor chip is formed with a conductive adhesive. And a semiconductor module in which a metal plate is bonded.

JP 2012-28684 A JP 2008-108780 A

  If it connects with a wiring material via the metal plate (conductive plate) connected on the semiconductor chip using the joining material like patent document 1, the thermal stress of a wiring junction part can be reduced and connection reliability improves. It is valid. However, the bonded portion between the circuit surface of the insulating substrate and the semiconductor chip (hereinafter referred to as a lower chip bonded portion) and the bonded portion between the main electrode on the upper surface of the semiconductor chip and the conductive plate (hereinafter referred to as an upper chip bonded portion) are sintered. In the case of the metal layer, there is a problem that thermal strain accompanying a temperature change around the semiconductor device during operation of the semiconductor chip concentrates on the on-chip junction. This is because, while deformation is restrained by the insulating substrate at the joint portion below the chip, the joint portion on the chip has a structure that is easy to move without restraining deformation. In particular, a sintered metal layer made of copper is harder than conventional solder materials and has a problem that it is difficult to absorb thermal strain at the joint. Furthermore, when the operating temperature of the semiconductor chip increases, and particularly when the junction temperature (Tj) exceeds 150 ° C., the thermal stress concentrated on the on-chip junction increases. Concentration of thermal strain and thermal stress on the on-chip junction may cause damage at the bonding interface starting from the bonding layer end of the on-chip bonding or damage to the semiconductor chip end, which is desirable in a high-temperature operating environment. Reliability cannot be obtained.

  In addition, the formation of the sintered metal layer requires a pressurization process, which may damage the gate wiring part during pressurization and may cause a short circuit between the gate wiring part and the emitter wiring part as an initial failure. It was the main factor to reduce.

  When a bent portion is provided on the metal plate as in Patent Document 2, stress concentration occurs at the end portion of the bent portion due to the spring action, and a defect that the metal plate peels off from the bonded portion due to the conductive adhesive tends to occur.

  Accordingly, an object of the present invention is to provide a semiconductor module that is excellent in connection reliability even in a high temperature environment.

  A semiconductor module of the present invention includes a substrate having a wiring layer, a semiconductor element mounted on the substrate and having an electrode on the surface, and a conductive plate bonded to the electrode of the semiconductor element via a sintered metal layer, The electrode is divided into a plurality of electrodes by the gate wiring portion, and the sintered metal layer is characterized in that the upper region of the gate wiring portion has a lower sintering density than the upper region of the electrode.

  According to the present invention, a semiconductor module having excellent connection reliability even in a high temperature environment can be provided.

It is a top view of the insulation type semiconductor device concerning one embodiment of the present invention. It is sectional drawing of the insulation type semiconductor device which concerns on one Embodiment of this invention. FIG. 2 is an enlarged view of the semiconductor device according to FIG. It is a figure which shows the detailed structure of the semiconductor chip mounting part which concerns on Example 1 of this invention. It is a figure which shows the application pattern of the joining material which concerns on Example 1. FIG. 6 is a diagram illustrating a detailed structure of a semiconductor element mounting portion according to Comparative Example 1. FIG. It is a figure which shows the application pattern of the joining material which concerns on the comparative example 1. FIG. It is a figure which shows the power cycle tolerance of Example 1 and Comparative Example 1. It is the schematic diagram which showed the cross-sectional state of the semiconductor module of the comparative example 1 after a power cycle test.

  A mode for carrying out the present invention will be described with reference to FIGS. FIG. 1A is a plan view of an insulating semiconductor module to which the present invention is applied, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. .

  The power semiconductor module according to FIG. 1 includes a substrate 103, a semiconductor element 101 mounted on the substrate and having an electrode 106 ′ on the surface, a conductive plate 150 joined to the electrode 106 ′ via a sintered metal layer 105, Is provided. 1 indicate the case 111, the external terminal 112, the bonding wire 113, and the sealing material 114, respectively.

  A wiring member such as a wire or a ribbon is connected to the conductive plate connected to the surface electrode of the semiconductor element, and is connected to another chip or electrode by the wiring member. The conductive plate is required to have a role of relieving thermal stress due to a difference in thermal expansion coefficient between the semiconductor element and the wiring member and a role of radiating heat from the semiconductor element.

  As the conductive plate, it is preferable to use a material having a thermal expansion coefficient intermediate between the semiconductor element and the wiring member and having a thermal conductivity of 100 W / mK or more. Furthermore, it is preferable to use a material having a higher thermal conductivity in the horizontal direction than the direction perpendicular to the electrode surface of the semiconductor element as the conductive member. Before the heat generated in the semiconductor element is transmitted to the wiring such as the upper wires and ribbons, heat is diffused in the plane along the element surface of the conductive plate, and a good soaking effect is obtained. This is because the wire or ribbon is not peeled off and the wiring connection reliability is improved as a whole chip. For example, use a material in which graphite fiber and metal (copper, aluminum, etc.) having thermal conductivity anisotropy such as thermal conductivity of a certain surface of 20 W / mK and orthogonal thermal conductivity of 2000 W / mK are combined. Can do. Further, a material in which layers having different thermal conductivities such as a copper / invar / copper cladding material are laminated can also be used. This is because the thermal conductivity (13 W / mK) of Invar (iron-nickel alloy) is smaller than the thermal conductivity (400 W / mK) of copper, so it is difficult for the heat generated in the semiconductor chip to be transmitted to the upper part. This is because the heat propagates and is soaked. Furthermore, the coefficient of thermal expansion is changed to Si or SiC (3 to 5 ppm / K) and the wiring member (Al about 23 ppm / K, Al by the ratio of copper (thermal expansion coefficient about 16 ppm / K) and Invar (thermal expansion coefficient about 1 ppm / K). This is because it can be adjusted to an intermediate preferable value of Cu of about 16 ppm / K) and thermal stress can be reduced. For example, by setting the copper / invar / copper ratio to 1/1/1, a thermal expansion coefficient of about 11 ppm / K can be obtained, and it is not necessary to make a connection portion of a material having a large thermal expansion difference. As a result, both the wiring connection reliability and the connection reliability of the conductive member to the chip can be improved.

  In addition, it is preferable that a electrically conductive board is flat form from viewpoints, such as stress relaxation and processing cost.

The substrate 103 used in this embodiment includes an insulating substrate and a wiring layer. The insulating substrate only needs to retain the voltage resistance and strength required by the semiconductor device, and a ceramic plate is appropriate. As the ceramic plate, an oxide material such as Al ₂ O ₃ or a nitride material of AlN or SiN having high thermal conductivity and strength is preferable. Hereinafter, a semiconductor module using a ceramic insulating substrate as the insulating substrate will be described.

  2 is a detailed cross-sectional view of the periphery of the element of the semiconductor module according to FIG. In FIG. 2, the wiring layer 102 on the ceramic insulating substrate 103 and the collector electrode 106 'of the semiconductor element 101 are joined by a sintered metal layer 105 (first sintered metal layer). The emitter electrode 106 of the semiconductor element and the conductive plate 150 are joined by a sintered metal layer 105 ′ (second sintered metal layer). The conductive plate 150 is connected to the wiring layer 104 on the ceramic insulating substrate 103 by a copper ribbon 113. The wiring layer 102 provided on the back surface of the ceramic insulating substrate 103 is bonded to the support member 110 via the solder layer 109. The wiring layer 102 and the gate wiring portion 104 are, for example, copper wiring.

  As the semiconductor element, an IGBT chip, a MOS • FET, a thyristor, a gate turn-off thyristor, a triac, or the like can be used. The semiconductor element has electrodes on the front surface and the back surface, and the electrode provided on the front surface is divided into a plurality of electrodes by the gate wiring portion. Note that the position of the gate electrode may be the end portion or the middle of the semiconductor element.

  A sintered metal layer 105 ′ for joining the semiconductor element 101 and the conductive plate 150 will be described with reference to FIG. The electrode on the surface of the semiconductor element is divided into a plurality of electrodes (active area 106) by the gate wiring portion 104 which is an inactive area, and the sintered metal layer 105 ′ has a region on the gate wiring region. The sintered density is lower than that. As described above, the sintered metal layer (second sintered bonding layer) 105 ′ for bonding the semiconductor element 101 and the conductive plate 150 is sintered in the region located on the gate wiring which is the inactive area of the semiconductor element. By making the density lower than the portion on the active area, thermal strain concentrated on the gate wiring portion can be suppressed. As a result, the connection reliability of the bonding layer on the chip can be improved.

  Further, when the main electrode of the semiconductor element is divided into a plurality of electrodes by the gate wiring part which is an inactive area, the gate wiring part is damaged by the sintered layer of the joint part on the chip. In some cases, a short circuit failure occurs between the main electrode and the emitter and a main breakdown voltage drop failure occurs between the emitter and the collector. By controlling the sintering density of the sintered metal layer that joins the semiconductor element and the conductive plate, damage to the gate wiring region can be suppressed.

  Here, the sintered metal layer refers to a sintered layer in which metal particles are metal-bonded, and may include an unsintered metal. By including an unsintered part, the heat-resistant fatigue life of a sintered layer can be improved.

  The thickness of the sintered metal layer on the main electrode on the surface of the semiconductor element is preferably larger than the height (thickness) of the gate wiring portion. With such a configuration, the gate wiring portion can be made non-pressurized or low-pressurized in the pressurization process when forming the sintered metal layer. As a result, damage to the gate wiring portion can be suppressed, and a short circuit between the gate wiring portion and the emitter wiring portion can be suppressed.

  In the present invention, when the substrate and the semiconductor element are bonded together by the sintered metal layer, the substrate and the semiconductor element are more bonded than the sintered metal layer (second sintered metal layer) that bonds the electrode of the semiconductor element and the conductive plate. From the viewpoint of improving heat dissipation, it is preferable that the sintered metal layer (first sintered metal layer) for bonding the layers has a high rigidity.

  From the viewpoint of reducing thermal resistance and improving adhesiveness, the sintered metal layer has a sintered density of 30 to 60% in the region on the gate wiring portion (porosity of 40 to 70%) and a sintered density in the region on the electrode. It is preferable that it is 60 to 90% (porosity 10 to 40%). A hollow portion may be provided on the gate wiring portion. Moreover, it is desirable that the sintering density of the bonding layer on the active area is higher by 10% or more than the sintering density on the non-active area. This is because, according to the simulation analysis, by increasing the sintered density of the bonding layer on the active area by 10% or more, the thermal stress resistance is improved about twice. As a result, it becomes possible to improve the power cycle resistance by 10 times or more compared to the conventional solder. The sintered density can be measured by separating the metal part and the void part from the cross-sectional photograph of the joint part by binarization and calculating the ratio of the void part to the observed joining layer.

  The sintered density can be adjusted by changing the heating conditions and pressure conditions during heating when forming the sintered metal layer, and the application amount of the bonding material. Moreover, the application amount of the bonding material can be adjusted by changing the density of the mask pattern used for applying the paste or changing the dropping amount during dispensing.

  The method for adjusting the sintered density of the sintered metal layer (second sintered metal layer) for joining the semiconductor element and the conductive plate is not particularly limited. For example, a paste is used using a dispenser so as to correspond to the active area. After applying the bonding material, the conductive plate is placed in place, the conductive plate and the semiconductor chip are pressed onto the circuit board and heated, and the bonding material is printed on the active area on the semiconductor device. Examples thereof include a method of pressurizing and heating, a method of printing and forming a bonding material on the conductive plate so as to correspond to the active area pattern of the semiconductor chip, and pressurizing and heating. For example, in the case of a structure having a hollow portion on the gate wiring portion, after applying a bonding material only on the electrode on the surface of the semiconductor element, a conductive plate is placed on the bonding material and sintered under pressure. In the sintered metal layer for joining the semiconductor element and the conductive plate by the step of joining the semiconductor element and the conductive plate, the sintering density of the on-electrode joining layer is made higher than the sintered density on the gate wiring portion. Can do.

  The bonding material for forming the sintered bonding layer includes at least one of metal particles, metal oxide particles, metal salt particles having an average particle diameter of 1 nm to 5 μm, and a solvent. Examples of metal particles include silver, copper, gold, platinum, palladium, rhodium, osmium, ruthenium, iridium, iron, tin, zinc, cobalt, nickel, chromium, titanium, tantalum, tungsten, indium, silicon, and aluminum. It is possible to use an alloy composed of one kind of metal or two or more kinds of metals. As oxide particles, gold oxide, primary silver oxide, secondary silver oxide, and cupric oxide can be used. As the metal salt particles, silver acetate, silver neodecanoate or the like can be used as the carboxylic acid metal salt. When the average particle size is larger than 5 μm, it becomes difficult to form copper metal particles having a particle size of 100 nm or less during bonding, which increases gaps between the particles and makes it difficult to obtain a dense bonding layer. is there. The reason why the thickness is 1 nm or more is that it is difficult to actually produce a particle precursor when the average particle is less than 1 nm.

  As the bonding material, it is preferable to use a material containing copper oxide particles. This is because by bonding copper oxide particles to each other in a hydrogen atmosphere, excellent bonding strength can be obtained particularly for Cu electrodes and Ni electrodes. In addition, since metal oxide particles made of copper oxide generate only oxygen during reduction, residues after bonding are hardly left and the volume reduction rate is very small.

  In order to improve dispersibility in an organic solvent, it is preferable to coat metal particles with an organic substance. For example, organic substances such as amino groups containing nitrogen atoms, alcohol groups containing oxygen atoms, carboxyl groups, and sulfone groups containing sulfur groups are suitable. Among these, a carboxyl group is preferable as a dispersion material because of its high binding property to metal particles. For example, pentanoic acid, hexanoic acid, heptanoic acid, octanoic acid, nonanoic acid, decanoic acid, undecanoic acid, dodecanoic acid, tridecanoic acid, tetradecanoic acid, pentadecanoic acid, hexadecanoic acid, heptadecanoic acid, octadecanoic acid, nonadecanoic acid, icosanoic acid, Examples include oleic acid. Among them, the alkyl carboxylic acid having 10 or more carbon atoms is preferably selected because the one having a larger number of carbon atoms is excellent in dispersibility.

  The solvent is preferably an organic substance in which metal particles are dispersed in an organic solvent and does not remain in the bonding layer after bonding. For example, alcohols such as toluene, methanol, and ethanol, hexane, heptane, octane, decane, dodecane, cyclopentane, cyclohexane, cyclooctane, benzene, toluene, xylene, ethylbenzene, water, and the like can be used. Among these, alcohols are preferred because they have a particularly low glycol-based melting point and a low environmental load because they are alcohol-based.

  As a bonding method for forming the sintered bonding layer, a known method can be applied. The bonding material is applied by, for example, a method of applying only to a necessary portion using a metal mask having an opening on the application portion, a method of applying to a required portion using a dispenser, a water-repellent resin containing silicone, fluorine, or the like. A method of applying with a metal mask or a mesh-like mask that opens only the necessary part, applying a photosensitive water-repellent resin on a substrate or electronic component, removing the part where the bonding material is applied by exposure and development, A method of applying the bonding paste to the opening, or after applying the water-repellent resin to the substrate or electronic component, removing the portion to which the bonding material is applied with a laser, and then applying the bonding paste to the opening The method etc. are mentioned. These application methods can be combined according to the area and shape of the electrodes to be joined.

  In order to form a sintered metal layer, it is preferable to go through a process of sintering under pressure. By applying heat and a pressure of 0.01 to 5 MPa, metal particles having a particle size of 100 nm or less are generated from the metal particle precursor. A metal bond is formed by fusing metal particles while discharging organic substances. The atmosphere during bonding may be a reducing atmosphere containing hydrogen or formic acid, or a non-oxidizing atmosphere. The metal particles contained in the bonding material become pure metal ultrafine particles by heat reduction at the time of bonding, and then fuse together to become a bulk. The melting temperature after becoming bulk is the same as the melting temperature of metals in the normal bulk state, and the ultrafine metal particles are melted by low-temperature heating, and after melting, they are heated to the melting temperature in the bulk state. It does not re-melt until Therefore, although it can join at low temperature, since a melting temperature improves after joining, when joining other electronic components after that, there exists a merit that a junction part does not remelt. As the sintered bonding layer, sintered silver can be applied in addition to sintered copper, but it is more preferable to use sintered copper. This is because sintered copper has less vacancy diffusion than sintered silver, and void generation due to temperature rise is suppressed.

  Examples of the present invention will be described below, but the present invention is not limited to the following embodiments.

  In Example 1, a power semiconductor module according to FIG. 3 was produced. As the semiconductor element 101, a 12 mm × 12 mm IGBT chip was used. The electrode structure on the collector side of this IGBT is Al / Ti / Ni and the outermost surface is Ni. The emitter side of the IGBT is Al / Ni and the outermost surface is Ni.

  A method for forming the sintered bonding layer 105 and the sintered bonding layer 105 ′ of Example 1 will be described. As the bonding material, a material containing copper oxide particles having an average particle diameter of 1 nm to 5 μm and an organic solvent was used. As a bonding material for forming the sintered metal layers 105 and 105 ′, a mixture of 88 wt% cupric oxide particles (purified after bonding) and 12 wt% diethylene glycol monobutyl ether was used.

  A bonding material was printed with a metal mask at a bonding portion on the wiring layer 102 of the ceramic insulating substrate 103. The semiconductor chip 101 was placed on the printed bonding material, and preheating was performed by applying heat at 60 ° C. for about 10 minutes in the atmosphere. Preliminary heating can remove unnecessary organic solvent components and suppress gas generation. About the structure after preheating, after raising the temperature to 300 degreeC in the pressurization state (0.5 MPa) and hydrogen, it hold | maintained for 15 minutes. In this embodiment, the pressure is kept applied, but pressurization at the time of holding at 300 ° C. is not essential. Through the above process, the collector electrode 106 ′ of the semiconductor element 101 and the wiring layer 102 were joined by the sintered joining layer 105.

  Next, a bonding material was applied to the bonding portion (active area) of the emitter electrode 106 of the semiconductor chip 101 by a dispenser. FIG. 4 shows the application state of the bonding material on the semiconductor element. As shown in FIG. 4, the bonding material was applied only on the emitter electrode portion. A conductive plate 150 is placed on the semiconductor chip 101 and placed in a pressurized state at 0.8 MPa. Subsequent steps were performed by joining the emitter electrode 106 of the semiconductor chip 101 with the sintered metal layer 105 ′ under the same conditions as the sintered metal layer 105.

  Through the above manufacturing process, the sintered metal layer 105 having a sintered density of about 70% (porosity 30%) and the sintered density on the active area of about 70% (porosity 30%) A power semiconductor module including a sintered metal layer 105 ′ having a sintered density of about 50% (a porosity of 50%) was produced. Even when the bonding material was applied only to the junction of the emitter electrode, the bonding material protruded by pressurization, and a sintered metal layer was formed also in the inactive area. In Example 1, the thickness of the sintered bonding layers 105 and 105 ′ was 80 μm.

  In Example 2, an example will be described in which sintered bonding layers 105 ′ having different sintering densities are formed by adjusting predrying conditions during bonding. The structure of the power semiconductor module is the same as that of the first embodiment except that the method for forming the sintered metal layer is different.

  A bonding material was printed with a metal mask on a bonding portion on the wiring layer 102 of the ceramic insulating substrate 103, and the semiconductor chip 101 was disposed thereon. Next, a bonding material is applied by a dispenser to the active area, which is a bonding position of the emitter electrode 106 of the semiconductor chip 101, and the conductive plate 150 is disposed thereon. In that state, heat at 60 ° C. in the atmosphere is applied for about 20 minutes. Next, a pressure is applied at 0.1 MPa, and the temperature is increased to 300 ° C. in hydrogen at a rate of temperature increase of 5 ° C./min and held for 15 minutes. Through the above process, the semiconductor chip 101 and the wiring layer 102, and the emitter electrode 106 and the conductive plate 150 of the semiconductor chip 101 were bonded via the sintered bonding layer 105 '.

  The sintered density of the sintered bonding layer 105 is about 70% (porosity 30%), and the sintered density of the sintered bonding layer 105 ′ is about 80% on the active area (porosity 20%), on the inactive area. Was in an uncoated state. Since the semiconductor chip and the conductive plate were simultaneously pressure bonded, the sintered density of the bonding layer 105 ′ was higher than that of the bonding layer 105. Furthermore, since the pre-drying was performed for a long time after the bonding material was applied, sintering proceeded without covering the non-active area even when the conductive plate was placed and pressed.

(Comparative Example 1)
In Comparative Example 1, a power semiconductor module according to FIG. 5 was produced. The only difference between the power semiconductor module according to Comparative Example 1 and the power semiconductor module according to Example 1 is the sintered metal layer 105 ′ that joins the electrode of the semiconductor element and the conductive plate. In the power semiconductor module according to Comparative Example 1, in the sintered metal layer 105 ′, the sintered density is constant in the region on the gate wiring and the region on the electrode.

  When the bonding material is applied to the emitter electrode of the semiconductor element 101, sintering is performed under the same conditions as in Example 1 except that the bonding material is printed and applied on the entire surface of the semiconductor element using a metal mask as shown in FIG. A metal layer 105 ′ was formed to produce a power semiconductor module. The sintered density was about 70% (porosity 30%) on both the active area and the non-active area.

<Power cycle test>
A power cycle test was performed on the semiconductor modules manufactured in Examples 1 and 2 and Comparative Example 1. The power cycle test is one of reliability tests for semiconductor modules.

  The semiconductor element is caused to flow by supplying a predetermined current to the semiconductor element for a predetermined period of time, causing the semiconductor chip itself to generate heat, raising the temperature to 150 ° C. (hereinafter referred to as Tjmax 150 ° C.), turning off the current, cooling to room temperature, and energizing again. The heat generation and cooling of itself were repeated.

  The results of the power cycle test of Example 1 and Comparative Example 1 are shown in FIG. In FIG. 5, the horizontal axis represents the number of cycles of heat generation and cooling, and the vertical axis represents the transition of the Tjmax value. In the future, it is conceivable that heat generation will increase with the miniaturization of semiconductor chips and semiconductor modules. For this reason, the Tjmax value is set to 150 ° C. in order to be able to cope with higher temperatures. However, when the junction between the semiconductor element and the insulating substrate and the junction between the semiconductor element and the conductive plate are damaged and further progressed, The value rises. In this test, the lifetime was determined when the rate of increase exceeded 15% of the initial value.

  In FIG. 5, in Comparative Example 1, a short circuit failure occurred between the gate wiring and the emitter wiring at about 10,000 times, and the test could not be continued. On the other hand, in Example 1, the cycle life was about 500,000 times, and the reliability could be greatly improved. Moreover, it was the cycle life of Example 2. The reason why the life of Example 2 was improved compared to Example 1 is considered to be that the damage to the semiconductor element was reduced because the applied pressure in the firing process when forming the sintered metal layer was reduced.

  When the damaged part and damage state of the semiconductor module of Comparative Example 1 after the power cycle test were examined, crack progress could be confirmed in the conductive plate on the semiconductor chip, the sintered bonding layer, and the sintered bonding layer under the semiconductor chip. There wasn't. However, a small crack was confirmed in the gate wiring portion on the semiconductor chip, and it was confirmed that the gate wiring was damaged. In FIG. 8, the schematic diagram which showed the cross-sectional state of the semiconductor module of the comparative example 1 after a power cycle test is shown. If cracks occur in the gate wiring portion, the gate wiring may be increased in resistance. Further, when the crack further progresses and reaches the lower part of the emitter electrode forming the active area electrode, a short circuit may occur between the gate and the emitter. It was found that this was the cause of the low life. In order to investigate this cause, thermal strain distribution analysis was performed by a finite element method in a structure in which a conductive plate was installed on a semiconductor chip. As a result, it was confirmed that a large thermal strain was generated in the gate electrode portion, and it was confirmed that it was necessary to reduce the thermal strain at this portion. Moreover, the influence at the time of pressurization is also large. That is, the sintered layer applied more pressure than necessary to the gate wiring portion, resulting in damage. It is conceivable that this damaged portion is the base point for occurrence of cracks.

  On the other hand, in the semiconductor module of this example, the thermal strain concentrated on the gate electrode portion of the on-chip junction is reduced, and the life of the junction can be extended.

  In the semiconductor module of this structure, the semiconductor chip 101 and the insulating wiring board having a thermal expansion coefficient of about 9 ppm / ° C., and the semiconductor chip and the conductive plate having a thermal expansion coefficient of about 9 ppm / ° C. are bonded via a bonding material. Further, it is possible to reduce the thermal stress caused by the difference in thermal expansion of each member that becomes prominent in a high temperature environment. Ideally, by matching the thermal expansion coefficient of the bonding material to that of the wiring board, the thermal stress generated in the bonding material is minimized, and long-term reliability is improved. Since the conductive plate is connected with a copper ribbon, higher reliability can be secured than conventional aluminum wire bonding.

  The semiconductor device of the present invention can be applied to various power conversion devices. By applying the semiconductor device of the present invention to the power conversion device, long-term reliability can be ensured even if it can be mounted in a place of a high temperature environment and does not have a dedicated cooler.

  Further, the inverter device and the electric motor can be incorporated as a power source in a high-speed vehicle or an electric vehicle. In this car, the drive mechanism from the power source to the wheels has been simplified, so the shock at the time of shifting is reduced and smooth running is possible compared to the conventional car that has been shifting due to the difference in gear engagement ratio. Thus, vibration and noise can be reduced as compared with the conventional case.

  Furthermore, the inverter device incorporating the semiconductor device of this embodiment can be incorporated into an air conditioner. In this case, higher efficiency can be obtained than when a conventional AC motor is used. Thereby, the power consumption at the time of air-conditioning machine use can be reduced. Moreover, the time until the room temperature reaches the set temperature from the start of operation can be shortened compared to the case where the conventional AC motor is used.

  The same effect as that of the present embodiment can be enjoyed even when the semiconductor device is incorporated in a device that stirs or flows another fluid, such as a washing machine or a fluid circulation device.

DESCRIPTION OF SYMBOLS 101 ... Semiconductor element, 102 ... Wiring layer, 103 ... Insulating substrate, 104 ... Gate wiring part (inactive area), 104 '... Gate electrode part, 105, 105' ... Sintered joining layer, 106 ... Emitter electrode (active area) ), 106 '... collector electrode, 107 ... protective film, 108 ... bonding material, 110 ... support member, 150 ... conductive plate, 113 ... bonding wire

Claims (10)

A semiconductor module comprising: a substrate having a wiring layer; a semiconductor element mounted on the substrate and having an electrode on a surface; and a conductive plate joined via an electrode of the semiconductor element and a sintered metal layer;
The electrode is divided into a plurality of electrodes by a gate wiring portion,
The sintered metal layer has a lower sintered density in a region above the gate wiring portion than in a region above the electrode. The semiconductor module according to claim 1,
The semiconductor module according to claim 1, wherein the sintered metal layer has a cavity in a region on the gate wiring portion. The semiconductor module according to claim 1,
The semiconductor module according to claim 1, wherein the conductive plate has a flat plate shape. The semiconductor module according to claim 1,
The semiconductor module according to claim 1, wherein a thickness of the sintered metal layer above the electrode is larger than a thickness of the gate wiring portion. A semiconductor module according to claim 1,
The semiconductor module, wherein the sintered metal layer includes an unsintered metal. A semiconductor module according to claim 1,
The semiconductor module, wherein the sintered metal layer contains copper. A semiconductor module according to claim 1,
The semiconductor module, wherein the substrate and the semiconductor element are joined by a sintered layer in which metal particles are metal-bonded. The semiconductor module according to claim 7,
The sintered module for joining the substrate and the semiconductor element has higher rigidity than the sintered metal layer for joining the electrode and the conductive plate. The semiconductor module according to claim 1,
A copper wiring member for electrically connecting the conductive plate and the wiring layer;
The semiconductor module according to claim 1, wherein the wiring member is in the form of a wire or a ribbon. A method of manufacturing a semiconductor module according to claim 1,
After the bonding material is applied only on the conductive plate and the electrode on the surface of the semiconductor element, the conductive plate is placed on the bonding material and sintered under pressure to bond the semiconductor element and the conductive plate. The manufacturing method of the semiconductor module characterized by including the process to do.

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