JP2016161729A - Semiconductor integrated circuit for display, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for display, in which the deterioration in yield due to the defective product resulting from the misunderstanding or the stress on the semiconductor integrated circuit for display caused by the excessive writing is prevented.SOLUTION: The semiconductor integrated circuit for display includes: a signal processing circuit 6 that processes image data and synchronous signals; a register 9 that stores the display setting information of a liquid crystal display device; a nonvolatile memory 14 that stores the display setting information of the register partly or entirely; a control circuit 13 that controls the writing sequence of the nonvolatile memory, the writing sequence being executed by the command supplied from a host system 5; an analysis circuit 12 that analyzes whether the sequence has been executed correctly for each command; and in the register, a command register 11 that accepts the command and a count register 10 that holds the number of times of writing in the nonvolatile memory. If the analysis result indicates the correct processing, the analysis circuit counts the number of times of writing at the same time as writing the setting information in the nonvolatile memory.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a display semiconductor integrated circuit having a nonvolatile memory having a predetermined writing sequence.

  2. Description of the Related Art In recent years, a dot matrix type liquid crystal panel in which a plurality of display pixels are two-dimensionally arranged in a matrix, for example, is used as a display device for portable electronic devices such as mobile phones and PDAs. Inside the device are mounted a display control device in the form of a semiconductor integrated circuit for controlling the display of the liquid crystal panel, a driver circuit for driving the liquid crystal panel, or a liquid crystal display device incorporating such a driver circuit. By the way, liquid crystal display devices have different specifications such as gamma characteristics, drive voltage, operation clock frequency, etc., depending on the type of liquid crystal used and the driving method, and there are variations in characteristics due to manufacturing variations. Therefore, a manufacturer that provides a display drive device increases the versatility of the device by configuring the display drive device so that it can be applied to liquid crystal display devices with different specifications and liquid crystal display devices with manufacturing variations. Devised to reduce manufacturing costs.

Patent Document 1 Japanese Patent Application Laid-Open No. 2004-184944

  2. Description of the Related Art Conventionally, a register is provided inside a display semiconductor integrated circuit as a measure for enabling driving even liquid crystal display devices having different specifications. Along with this internal register, a non-volatile memory such as EPROM is provided outside the display semiconductor integrated circuit, and setting information such as drive conditions is transferred from the non-volatile memory to the internal register at the initial setting when the power is turned on. This method has been put to practical use.

  When a display device is manufactured using a display semiconductor integrated circuit, there is a variation in characteristics due to manufacturing variations. Therefore, setting information is written in advance in a nonvolatile memory built in the display semiconductor integrated circuit during the manufacturing process. . For example, flicker or the like is one element that fluctuates due to manufacturing variations of the panel, and each unique value is written in the nonvolatile memory. At that time, a writing sequence program defined by each semiconductor manufacturer is used as a method for writing setting information to the nonvolatile memory. For example, Patent Document 1 discloses an invention in which data is written to a nonvolatile memory by a writing program. According to Japanese Patent Laid-Open No. 2004-26883, since the use side does not need to manage the number of times of writing, even if a problem occurs during the execution of the program, the use side cannot be grasped and used. In this case, even though there is a limit on the number of times of writing, the user side was not able to grasp at all what kind of process the number of times of writing was changing, and remained uneasy about the number of times of writing. . In addition, there is a possibility that writing is performed in excess of a predetermined number of times of writing.

  On the other hand, even when the limit number was not exceeded, it was mistakenly regarded as exceeding and was treated as a defective product, which deteriorated the yield.

  Furthermore, various setting information is written into the non-volatile memory by a write sequence from the host system. However, in the course of the write sequence, some commands may not be executed, or even if wrong commands are executed, the result may not be known to the host system. In such a case, it is not known whether the writing has not been completed, and since it was not possible to know whether the number of times of writing exceeded the number of times of writing, if the number of times of the number of times was exceeded, unnecessary stress was applied to the nonvolatile memory. It was.

  The present invention has been made to solve the above-mentioned problems, confirms that a command based on a write sequence (program) is correctly executed, manages the number of times of writing and writing to a nonvolatile memory, and excessively It is intended to prevent the yield of a defective product from being deteriorated due to stress applied to the display semiconductor integrated circuit due to incorrect writing or misidentification.

  In order to solve the above problems, a display semiconductor integrated circuit according to the present invention includes a signal processing circuit that processes pixel data and a synchronization signal necessary for display, a register that records display setting information of a display device, and a register. A non-volatile memory for recording display setting information or all display setting information, a control circuit for controlling a write sequence of the non-volatile memory executed by a command supplied from a host system, and whether or not the command is correctly executed for each command An analysis circuit for analyzing, and the register includes a command register for receiving the command supplied from the host system, and a count register for holding a write count of the nonvolatile memory, According to the analysis result, the setting information is written to the non-volatile memory and at the same time Ability to count, and having a.

  According to the present invention, writing to the nonvolatile memory is performed during the manufacturing process. Therefore, according to the present invention, by confirming that the command based on the write sequence is correctly executed by the analysis circuit, it is possible to manage the number of times of writing and the writing in the nonvolatile memory, and to give the semiconductor integrated circuit by excessive writing. Yield deterioration due to stress and misperception can be prevented.

  In addition, according to the present invention, since the operation of the command is confirmed by the analysis circuit and then the write operation to the nonvolatile memory is executed, efficient and correct writing can be performed.

It is a top view which shows the liquid crystal display device using the semiconductor integrated circuit of this invention. It is sectional drawing which shows the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a block diagram showing the whole structure of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a flowchart figure which shows the write-in sequence of the non-volatile memory of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a block diagram of the analysis circuit which analyzes the command based on the writing sequence of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a block diagram of the comparison circuit 1 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is explanatory drawing of the operation | movement waveform of the comparison circuit 1 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a block diagram of the comparison circuit 2 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is explanatory drawing of the operation | movement waveform of the comparison circuit 2 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a block diagram of the comparison circuit 3 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is explanatory drawing of the operation | movement waveform of the comparison circuit 3 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a truth table of the comparator at the time of 1 bit in the comparison circuit 3 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of the present invention. It is a detailed circuit diagram of the 8-bit circuit of the comparison circuit 3 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of the present invention. It is a block diagram of the comparison circuit 4 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is explanatory drawing of the operation waveform of the comparison circuit 4 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is a detailed circuit diagram of an 8-bit circuit of the comparison circuit 4 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of the present invention. It is a block diagram of the comparison circuit 5 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention. It is explanatory drawing of an operation waveform when the waiting time of the comparison circuit 5 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention is short. It is explanatory drawing of an operation waveform when the waiting time of the comparison circuit 5 in the analysis circuit of the liquid crystal display device using the semiconductor integrated circuit of this invention is long.

[Configuration of Example]
An embodiment of the present invention will be described below.

  1A and 1B show a liquid crystal display device using a semiconductor integrated circuit of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view.

  The liquid crystal display device 1 includes a liquid crystal display panel 3, a semiconductor integrated circuit 2 on the liquid crystal display panel 3, a flexible substrate 4 attached to the liquid crystal panel 3, and the liquid crystal not shown in the present case. The display panel 3 and the backlight arranged to face each other.

  FIG. 2 is a block diagram showing the configuration of the liquid crystal display device and the host system.

  The host system 5 outputs display data, a synchronization signal, and various setting information, and is connected to the tip of the flexible substrate 4 shown in FIG. The liquid crystal display device 1 includes a semiconductor integrated circuit 2 that receives and processes information output from the host system 5, and a liquid crystal display panel 3 that receives a liquid crystal display drive signal output from the semiconductor integrated circuit 2. It is configured.

  The semiconductor integrated circuit 2 includes a signal processing circuit 6 for driving the liquid crystal display panel 3, a register 9 for storing various setting information (for example, a driving method such as normally white / black), and the like. A nonvolatile memory 14 for writing part or all of the contents of the register 9, a control circuit 13 for controlling writing, and a command according to a predetermined writing sequence output from the host system 5 are correctly executed. And an analysis circuit 12 for outputting a signal for instructing whether to execute writing to the control circuit 13 and a signal for instructing whether to count the number of times of writing based on the analysis result.

  The register 9 includes a command register 11 that stores a command according to a write sequence output from the host system 5, and a count register 10 that stores the number of writes in the nonvolatile memory 14.

  In the above configuration, reference numeral 2 denotes a semiconductor integrated circuit that performs display by driving a liquid crystal display panel in an active matrix system, and 3 denotes a liquid crystal display panel that is driven by the semiconductor integrated circuit 2.

  The signal processing circuit 6 built in the semiconductor integrated circuit 2 is connected to a host system 5 as a control device separately from the liquid crystal display panel 3, and the host system 5 is set in the semiconductor integrated circuit 2. It is connected to a register 9 for recording information.

  The semiconductor integrated circuit 2 is provided with an external terminal to which a write voltage necessary for writing to the nonvolatile memory 14 is applied and a reset signal terminal for initializing the semiconductor integrated circuit 2. Here, it goes without saying that the application of the write voltage may be performed by other input means not described as being performed by the host system.

  Further, the semiconductor integrated circuit 2 of this embodiment has a control circuit 13 for writing / reading setting information to / from the non-volatile memory 14 by a command supplied from the host system 5 and a write sequence described below for each command. And an analysis circuit 12 for analyzing whether or not the event is correctly executed.

  The register 9 of this embodiment includes a count register 10 that indicates the number of times of writing and a command register 11 that indicates a command to be executed based on the contents of the writing sequence. Can be recognized. That is, when there is an instruction from the host system 5, the value of the count register 10 in the register 9 is read to the host system 5, and the user recognizes the number of times of writing.

(Description of operation of the embodiment)
FIG. 3 is a flowchart showing a write sequence of the nonvolatile memory 14. Although the description of the write operation is not particularly limited, the semiconductor integrated circuit 2 of the present embodiment executes the write operation in a write sequence corresponding to the command code. Further, the analysis circuit 12 performs an operation check for each command, and based on the result of the operation check, it is determined whether or not correct command processing has been performed. When correct command processing is performed, the setting information is written into the nonvolatile memory 14 and the number of times of writing is counted at the same time.

  Next, the operation of the analysis circuit 12 will be described with reference to FIG.

  The relationship between the write sequence in FIG. 3 and the analysis circuit 12 is that an analysis circuit is attached to each command in accordance with the write sequence.

  First, when data write is instructed by a command supplied from the host system 5 (step 1), a write voltage is supplied from the outside (step 2).

  The supplied write voltage is supplied to the nonvolatile memory 14 through the analysis circuit 12, and is compared with the reference voltage in the analysis circuit 12 (step 3).

  As a result of this comparison, when the supplied voltage is lower than the reference voltage (NG), the write voltage has not been reached, so that even if the write sequence is executed thereafter, the nonvolatile memory 14 is not written. (Step 15).

Further, the number of times of writing in the register 9 is not counted (step 14).
On the other hand, when the voltage is equal to or higher than the reference voltage (OK), it waits for the next command from the command register to be supplied.

  Subsequently, a command for selecting the nonvolatile memory 14 is supplied (step 4).

  Since a bit for selecting the nonvolatile memory 14 is provided in this command, the selection bit is compared with a reference value (step 5).

  As a result of this comparison, when the value of the selected bit is different from the reference value (NG), the nonvolatile memory 14 is not selected, so that even if the subsequent write sequence is executed, the nonvolatile memory 14 is written. Is not performed (step 15).

  Further, the number of times of writing in the register 9 is not counted (step 14).

  On the other hand, if it is equal to the reference value (OK), it waits for the next command to be supplied.

  Subsequently, a value to be written is supplied from the host system 5 (step 6). The written value is compared with the past value (step 7).

  As a result of this comparison, when the value to be written is equal to the past value (OK), since the value has already been written, even if the subsequent writing sequence is executed, writing to the nonvolatile memory 14 is not performed (step 15).

  Further, the number of times of writing in the register 9 is not counted (step 14).

  On the other hand, when the value to be written is different from the past value (NG), it waits for the next command to be supplied because of the new value.

  Subsequently, a write instruction command is supplied from the host system 5 (step 8). This write instruction command is compared with the reference value (step 9).

  As a result of this comparison, if the command and the reference value are different (NG), no write instruction has been received, so even if the subsequent write sequence is executed, no write is performed in the nonvolatile memory 14 (step 15). .

  Further, the number of times of writing in the register 9 is not counted (step 14).

  On the other hand, if the command and the reference value are the same (OK), a write instruction is received, so that the next command is supplied.

  Subsequently, the elapse of the writing standby time is waited. After receiving the above write instruction, the time from when the reset signal supplied from the host system 5 is supplied is confirmed (step 10). In this embodiment, the standby time is 20 ms, but this is not a limitation. This 20 ms is compared with the time until the reset signal is supplied (step 11).

  As a result of this comparison, if it is shorter than 20 ms (NG), since the waiting time has not been reached, writing to the nonvolatile memory 14 is not performed even if the subsequent writing sequence is executed (step 15).

Further, the number of times of writing in the register 9 is not counted (step 14).
On the other hand, if it is longer than 20 ms (OK), since the standby time is satisfied, the writing to the nonvolatile memory 14 is terminated (step 13). Further, the value of the number of times of writing is counted (step 13).

  In the same manner, the operation of the command is sequentially checked by comparing with the reference value by the command supplied from the host system 5.

  FIG. 4 is a block diagram of the analysis circuit 12 that analyzes a command based on the write sequence shown in FIG. The analysis circuit 12 inputs the result of the comparison circuit for each command to the OR circuit, and outputs a signal to the control circuit 13 indicating whether or not to write to the nonvolatile memory 14 or to count the count register 10.

  In the present invention, since writing to the nonvolatile memory 14 and permission to count the count register 10 are set to the logical value “0”, the outputs of the respective comparison circuits are set to be “0”.

  5 to 9 are a block diagram and an explanatory diagram showing comparison circuits 21 to 25 for each command executed in the write sequence.

  The comparison circuit 21 shown in FIG. 5A includes a comparator circuit that compares a write voltage input from the outside with a reference voltage Vref. Based on the output signal of the comparator circuit, it is determined whether or not it is within the set range of the write voltage.

  The signal output from the comparator circuit is input to the OR circuit in the analysis circuit 12. A signal output from the OR circuit becomes a write permission signal and a count signal of the count register 10 via the control circuit 13.

  When the output of the OR circuit is “0”, it means that writing and counting are performed. On the contrary, when “1”, it means that writing and counting are not performed.

  Further, the operation waveform in FIG. 5B shows that when the write voltage falls below the reference voltage Vref, the Vout output changes from “0” to “1”, and thereafter the write voltage is not sufficient.

  The comparison circuit 22 shown in FIG. 6A is configured by a NAND circuit that receives a selection bit for selecting the nonvolatile memory 14 in the command input from the host system 5 and a reference value as input signals. Here, the selection bit is transmitted in the form of being included in advance as a signal in an 8-bit command from the host system or the register, or is determined as fixed data at the time of circuit design and set in advance in the comparison circuit. Is determined.

  In the present invention, since the selection bit is “1”, the circuit configuration is such that the reference value is “1”.

  Based on the output signal of the NAND circuit, it is determined whether or not the nonvolatile memory 14 has been selected.

  The signal output from the NAND circuit is input to the OR circuit in the analysis circuit 12. A signal output from the OR circuit becomes a write permission signal and a count permission signal of the count register 10 via the control circuit 13.

  Further, the operation waveform in FIG. 6B indicates that after the selection bit changes from “0” to “1”, the output Vout of the NAND circuit becomes “0” and the nonvolatile memory 14 is selected.

  The comparison circuit 23 shown in FIG. 7A has data (setting information) (X0-7) written to the nonvolatile memory 14 input from the host system 5 and data (setting information) (Y0) written in the past to the nonvolatile memory 14. -7) and an exclusive OR circuit having the input signals as input signals.

  In the present invention, since the data width is 8 bits, the circuit configuration is such that 8 bits are compared for each bit. The output of each comparison circuit is input to the AND circuit. Based on the output signal of the AND circuit, it is determined whether the data to be written has the same value as the data written in the past. If the value is different, a write operation is performed. If the values are the same, the write operation is not performed, and unnecessary load on the nonvolatile memory 14 is reduced.

  The signal output from the AND circuit is input to the OR circuit in the analysis circuit 12. A signal output from the OR circuit becomes a write permission signal and a count permission signal of the count register 10 via the control circuit 13.

  According to the truth table of FIG. 7C, a 1-bit comparator is shown. When the two inputs X0 and Y0 have the same value, the output Z0 outputs “1”, and when the two inputs X0 and Y0 have different values, the output Z0 outputs “0”. This logical sum is generally called a negative exclusive logical sum, and is represented by a circuit diagram of FIG. Similarly, the 8-bit output Z0-7 is connected to the 8-input terminal of the AND circuit, and the output Vout is input to the OR circuit in the analysis circuit 12.

  In addition, when the operation waveform of FIG. 7B is the same value by inputting the previous value X0-7 (8 bits) and the new value Y0-7 (8 bits) to the exclusive OR, the output Vout is “ When 1 is output and the value is different, the output Vout indicates that “0” is output.

  The comparison circuit 24 shown in FIG. 8A is configured by an exclusive OR circuit that receives a write instruction command input from the host system 5 and a reference value as input signals. Here, the reference value is transmitted in a form preliminarily included as a signal in an 8-bit command from the host system or the register, or is determined as fixed data at the time of circuit design and set in advance in the comparison circuit. Is determined.

  In the present invention, since the data width of the command is 8 bits, a circuit configuration for comparing 8 bits is used.

  Since the data width of the command is 8 bits, the comparison circuit 24 includes eight exclusive OR circuits excluding the negative circuit of the negative exclusive OR circuit described with reference to FIG. 7D. As shown in FIG. 8C, the output of each exclusive logic circuit is connected to the input terminal of the OR circuit, and the output Vout of the OR circuit is connected to the OR circuit in the analysis circuit 12. A signal output from the OR circuit in the analysis circuit 12 becomes a write permission signal and a count permission signal of the count register 10 via the control circuit 13.

  For example, if the write instruction command is “EE” h (h represents a hexadecimal number), “EE” h is set as the reference value. Thereby, the input terminals Y0 to Y7 of each exclusive OR circuit have Y0 = “0”, Y1 = “1”, Y2 = “1”, Y3 = “1”, Y4 = “0”, Y5 = Logical values such as “1”, Y6 = “1”, Y7 = “1” are set. In the operation waveform of FIG. 8B, if the value of each input terminal is the same value, the outputs of the exclusive OR circuit all output “0”, so the output of the OR circuit becomes “0”, and the analysis circuit 12 The output of the OR circuit indicates that “0” is output.

  If the value is different, the output of the exclusive OR circuit is all “1”, so the output of the OR circuit is “1”, and the output of the OR circuit in the analysis circuit 12 is “1”. Is done.

  Based on the output signal of the OR circuit in the comparison circuit 24, it is determined whether or not it is a write instruction command. When the output is 0, the write operation is performed, and when the output is 1, the write operation is not performed.

The comparison circuit 25 shown in FIG. 9A is composed of a flip-flop circuit in which the nonvolatile raw memory receives a standby time required for a write operation and a reference value as input signals.
In the case of the present invention, the standby time is set to 20 ms as the time from when a write instruction command is input until the next reset signal is input. The comparison circuit 25 includes a flip-flop circuit that uses as input signals a timer output signal that counts 20 ms and an output signal that counts from the input of a write instruction command to the input of a reset signal.

  The comparison circuit 25 starts an internal timer operation simultaneously with receiving the write instruction command described with reference to FIG. The timer outputs a logical value “1” to “0” when 20 ms elapses. The output signal is input to the data input terminal of the flip-flop and the OR circuit.

  Also, the comparison circuit 25 counts the time until receiving the reset signal from the host system 5 after receiving the write instruction command, and outputs “0” to “1” immediately after receiving the reset signal. . The output signal is input to the clock input terminal of the flip-flop, and outputs the value input to the data input when “0” changes to “1”.

  For example, in the operation waveform of FIG. 9B, when the reset signal is received for less than 20 ms, the timer output is “1”, so the data input of the flip-flop circuit is “1”, and the flip-flop circuit These output terminals indicate that “1” is output. In the operation waveform of FIG. 9C, when the reset signal is received for longer than 20 ms, the timer output is “0”, so the data input of the flip-flop circuit is “0”, and the flip-flop circuit These output terminals indicate that “0” is output.

  Based on an output signal from the flip-flop circuit, it is determined whether or not a predetermined standby time is satisfied. If the standby time is satisfied (output is 0), the write operation is performed. If the standby time is not satisfied (output is 1), the write operation is not performed.

The signal output from the flip-flop circuit is input to the OR circuit in the analysis circuit 12. A signal output from the OR circuit becomes a write permission signal and a count permission signal of the count register 10 via the control circuit 13.
In the embodiments, the case where the display device is a liquid crystal display device has been described. However, the present invention can be applied to other display devices such as a plasma display and an EL display. Further, although EPROM is assumed as the nonvolatile memory, it can be applied to EEPROM, flash memory, MRAM, and ferroelectric memory.

  It can be used for a semiconductor integrated circuit having a built-in nonvolatile memory used for a display driving circuit of a display device such as liquid crystal or plasma.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Semiconductor integrated circuit 3 Liquid crystal display panel 4 Flexible board 5 Host system 6 Signal processing circuit 7 I / F circuit 8 LCD drive circuit 9 Register 10 Count register 11 Command register 12 Analysis circuit 13 Control circuit 14 Non-volatile memory 21 Comparison circuit 1 22 Comparison circuit 2
23 Comparison circuit 3 24 Comparison circuit 4
25 Comparison circuit 5

Claims (9)

Signal processing circuit for processing pixel data and synchronization signal necessary for display, register for recording display setting information of display device, nonvolatile memory for storing part or all of display setting information of the register, and host system A control circuit that controls a write sequence of the nonvolatile memory that is executed by a command supplied from the analyzer, and an analysis circuit that analyzes whether or not the command is correctly executed for each command,
The register includes a command register that receives the command supplied from the host system, and a count register that holds the number of times of writing to the nonvolatile memory, and the analysis circuit uses the analysis result to calculate the nonvolatile memory. A display semiconductor integrated circuit having a function of counting the number of times of writing simultaneously with writing of setting information to 2. The display semiconductor according to claim 1, wherein the analysis circuit reads a value of the count register according to an instruction from the host system, and allows a user to recognize the number of times of writing that can be written to the nonvolatile memory. Integrated circuit. The display semiconductor integrated circuit according to claim 1, wherein the analysis circuit performs an operation check of the command. 4. The display semiconductor integrated circuit according to claim 3, wherein the analysis circuit determines whether correct command processing has been performed based on a result of checking the operation of the command. 5. The display semiconductor integrated circuit according to claim 4, wherein when the correct command processing is performed, the analysis circuit performs a count operation of the number of times of writing simultaneously with writing the setting information in the nonvolatile memory. 2. The writing circuit according to claim 1, wherein when the setting information is written, if the setting information already held in the nonvolatile memory is the same value as the setting information to be written, the analysis circuit does not perform a writing operation. A semiconductor integrated circuit for display according to 1.   2. The display according to claim 1, wherein the comparison circuit includes a NAND circuit having a selection bit for selecting the nonvolatile memory in a command input from the host system and a reference value as input signals. Semiconductor integrated circuit.   2. The display semiconductor integrated circuit according to claim 1, wherein the comparison circuit includes a flip-flop circuit that uses as input signals a standby time required for the non-volatile raw memory for a write operation and a reference value of an internal timer. . A display device comprising: a display panel; and the display semiconductor integrated circuit according to claim 1.

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