JP2016143377A - Parallelization compilation method, parallelization compiler, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the quality maintenance and management of parallelization programs.SOLUTION: A sequential program, which is executed by a single processor system and contains conditional descriptions comprising a series of descriptions consisting of a plurality of parts to be individually selected or unselected as compiling targets in accordance with input information by means of conditional compiling, is divided into a plurality of macro tasks regardless of the input information. All or some of parallelly executable macro tasks are then assigned to different processor units to produce a parallelization program to be executed by a multi-processor system, where multiple macro tasks corresponding to a process associated with one conditional description are assigned to the same processor unit (S110).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a parallel compilation method, a parallel compiler, and an electronic apparatus.

  In an in-vehicle device in which a multi-core processor is mounted, it is known that throughput is improved by distributing functions to each core (Non-Patent Document 1). A parallel compiler that generates a parallel program that can be processed in parallel by a multi-core processor from a program (sequential program) for a single core processor is known.

K Seo, J Yoon, J Kim, T Chung, K Yi, N Chang, “Coordinated implementation and processing of a unified chassis control algorithm with multi-central processing unit”, JAUTO1346 IMechE, 2009, Vol.224 Part D

  Here, in a sequential program, there are cases where a description to be compiled is selected according to a destination by a conditional compilation switch (conditional compilation). When a parallelized program is generated from such a sequential program using a parallelizing compiler, generally, a part to be compiled is first identified from the sequential program based on a conditional compilation switch, and then the parallel program is determined from the part. A generalized program is generated.

  However, if the part to be compiled is changed, there is a possibility that the data dependency and control dependency between the macro tasks constituting the sequential program may change. As a result, a plurality of processes based on a series of descriptions provided with conditional compilation switches may be assigned to different processor cores.

  In such a case, a plurality of parallel programs with different destinations generated from the same sequential program are generated from the same sequential program and assigned to each processor core even though they have equivalent functions. The contents may vary greatly. As a result, it becomes difficult to maintain quality and manage parallelized programs.

  An object of the present invention is to facilitate the maintenance and management of the quality of a parallelized program.

  A parallelized compiling method according to one aspect of the present invention is a program executed by a single processor system, and includes a plurality of portions that are switched depending on input information by conditional compilation. A division procedure for dividing a process described in a sequential program including a conditional description as a series of descriptions into a plurality of macro tasks regardless of input information (S210), and data dependency between macro tasks An extraction procedure for extracting macrotasks that can be executed in parallel by a plurality of processor units constituting the multiprocessor system (S220), and a process for assigning each macrotask to any one of the processor units, which can be executed in parallel All or some of the macro tasks can be transferred to different processor units. And a scheduling procedure for generating a parallelized program executed by the multiprocessor system (S110). In the scheduling procedure, a plurality of macro tasks corresponding to processing based on one conditional description are assigned to the same processor Assign to a unit.

  According to such a configuration, the parallelized program is generated from the sequential program in a state in which all conditional descriptions are included by the scheduling procedure. Then, by setting the input information, it is possible to remove a part that is not subject to compilation from the conditional description in the parallelized program and generate a type of parallelized program corresponding to the input information.

  In the parallelized program at the stage generated by the scheduling procedure, each process based on one conditional description is assigned to the same processor unit. For this reason, even when multiple types of parallelized programs with different destinations are generated by setting input information, the commonality of various parallelized programs can be further enhanced. As a result, it is easy to maintain and manage the quality of the parallelized program.

  In addition, the code | symbol in the parenthesis described in this column and a claim shows the correspondence with the specific means as described in embodiment mentioned later as one aspect, Comprising: The technical scope of this invention is shown. It is not limited.

It is a block diagram which shows the structure of PC in which the automatic parallelizing compiler was installed. It is a flowchart of an automatic parallelization process. It is a flowchart of a soft structure analysis process. It is a block diagram which shows the structure of a vehicle-mounted apparatus. It is explanatory drawing of the sequential program and allocation information in a specific example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment of the present invention is not limited to the following embodiment, and can take various forms as long as they belong to the technical scope of the present invention.

[About this embodiment]
1. About the automatic parallelizing compiler The automatic parallelizing compiler of this embodiment has a function of generating a parallel processing program for a multiprocessor system for an embedded system from a source program (sequential program) for a single processor system for an embedded system. doing.

1-1. Design concept of automatic parallelizing compiler The automatic parallelizing compiler of this embodiment has the following functions.
(1) Multigrain parallel processing (2) Static scheduling code insertion at compile time (3) Dynamic scheduling code generation at runtime (4) Realization of hierarchical macro data flow (5) Split / fusion of macro tasks, Loop Extraction of parallelism such as distribution / interchange (6) Improvement of data transfer efficiency by data localization (7) Power reduction by compiler 1-2. Internal processing of automatic parallelizing compiler The automatic parallelizing compiler has three stages of Front End (FE), Middle Path (MP), and Back End (BE). Each stage is independent as an execution form, and code is exchanged by an intermediate language generated from FE and MP.

  Note that FE is a part that generates an intermediate language that can be parsed in MP by performing lexical analysis and syntax analysis on the source code of the sequential program. The intermediate language generated by the FE is basically expressed by a parse tree having four operands, forms one block as a whole, and is not structured.

MP is a part that performs control dependency analysis, data dependency analysis, optimization, and the like, and performs coarse grain, medium grain, and near fine grain parallel processing using the data.
The BE is a part that reads the parallelized intermediate language generated by the MP and generates an actual machine code. This part has BE that generates parallel Fortran code for OpenMP and C code in addition to BE that generates assembler code of the target multi-core architecture. Furthermore, the part has a BE that outputs codes corresponding to various architectures, such as a BE that generates a parallelized code including memory allocation and data transfer by a parallelized API described later.

1-3. Parallelism analysis of automatic parallelizing compiler The automatic parallelizing compiler converts sequential programs into three types of coarse-grained tasks (macrotasks (MT)): basic blocks (BB), repetitive blocks (RB), and subroutine blocks (SB). Performs macro data flow processing to be divided.

However, the macro data flow processing has a problem that the utilization efficiency of the processor does not increase depending on the shape of the program, and sufficient coarse grain parallelism cannot be extracted.
Therefore, the automatic parallelizing compiler expands the conventional single-layer macro data flow processing method and employs hierarchical macro data flow processing that hierarchically uses the macro data flow processing inside the MT. In hierarchical macro data flow processing, MT is defined hierarchically and parallelism between macro tasks is analyzed for macro tasks in each hierarchy.

<Generation of macro flow graph (MFG)>
The automatic parallelizing compiler first analyzes the control dependency and the data dependency between macrotasks for the generated macrotasks of each layer. The analysis result is represented as a macro flow graph (MFG).

<Generation of macro task graph (MTG)>
MFG expresses control dependency and data dependency between macro tasks, but does not express parallelism. In order to extract parallelism, it is necessary to perform the earliest feasible condition analysis considering both control dependency and data dependency for each macro task. The earliest executable condition is a condition in which the MT can be executed at the earliest time, and is obtained from the following execution condition.

(1) If MTi is data-dependent on MTj, MTi cannot be executed until MTj has been executed.
(2) If the conditional branch destination of MTj is determined, MTi that is dependent on MTj can be executed even if execution of MTj is not completed.

Therefore, the general form of the earliest feasible condition is as follows.
(MTj on which MTi depends on control branches to MTi)
AND
((MTk where MTi is data-dependent (0 ≦ k ≦ | N |) ends) OR (determines that MTk is not executed))
The earliest executable condition of the macro task is represented by a macro task graph (MTG).

1-4. Multi-grain parallel processing In addition to the conventional loop parallelization, the automatic parallelizing compiler uses coarse-grained task parallelism that uses parallelism between coarse-grained tasks between loops and subroutines, and near-parallel processing that uses parallelism between statements. Multi-grain parallel processing that effectively combines fine-grain parallel processing (Reference 1 (Hiroki Honda, Masahiko Iwata, Hironori Kasahara, “Parallelity detection method between Fortran coarse-grained tasks”, IEICE Transactions, 1990))).

<Coarse grain task parallel processing>
The automatic parallelizing compiler generates a macro flow graph (MFG) that expresses the control dependency and data dependency between MTs such as BB, RB, SB, etc., and further, between MTs extracted from MFG by the earliest executable condition analysis Is expressed as a macrotask graph (MTG) (Reference 1, Reference 2 (Kasahara, Goda, Yoshida, Okamoto, Honda, “Macro Task Generation Method for Fortran Macro Data Flow Processing”), Science Theory 1992, Vol. J75-DI, No. 8, pp. 511-525)).

Thereafter, the automatic parallelizing compiler assigns the MT on the MTG to a processor group (PG) in which one or more processor elements (PE) are grouped.
<Medium-grain parallel processing>
If the MT assigned to the PG can be processed in parallel at the DOALL loop or iteration level, the MT is subjected to medium-grain parallel processing by the processors in the processor cluster. This medium-grain parallel processing is parallel processing using parallelism between DO loop iterations, and is the most common parallel processing in a multiprocessor.

<Near Fine Grain Parallel Processing>
Parallel processing for statement-level near-fine-grain tasks is called near-fine-grain parallel processing. As a result, statements that do not depend on can be executed in parallel, and the execution time is shortened.

1-5. Macrotask scheduling In coarse-grained task parallel processing, macrotasks generated at each level are assigned to PGs and executed. There are the following dynamic scheduling and static scheduling as scheduling methods for determining which PG a macro task is assigned to, and these are selected based on the shape of the macro task graph, non-determinism during execution, and the like.

<Dynamic scheduling>
When there is execution-time uncertainty such as conditional branching, a macrotask is assigned to a PG at the time of execution by dynamic scheduling. The dynamic scheduling routine operates the macro task execution management table according to the end of the macro task or the determination of the branch direction, and checks the earliest executable condition of each macro task.

  If the macro task can be executed, the macro task is put into the ready queue. The macrotasks in the ready queue are sorted according to their priorities, and the first macrotask in the ready queue is assigned to an idle processor cluster.

  Also, when generating dynamic scheduling code, a centralized scheduling method in which one dedicated processor performs scheduling and a distributed scheduling method in which the scheduling function is distributed to each processor can be used according to the number of processors used and the synchronization overhead of the system. it can.

<Static scheduling>
On the other hand, static scheduling is used when the macrotask graph has only data-dependent edges, and the automatic parallelizing compiler determines the assignment of macrotasks to PGs during compilation.

  Static scheduling can be effectively used for scheduling fine-grained tasks because it eliminates runtime scheduling overhead and minimizes data transmission and synchronization overhead.

  In the case of static scheduling, the task cost estimate value of the automatic parallelizing compiler is applied to the task cost. However, it is also possible to perform task scheduling at the actual cost by using the automatic profile parallel feedback function of the automatic parallelizing compiler. It is.

  When the profile automatic feedback function is used, as a first phase, the sequential program is decomposed into MTs, and a profiler function is inserted for each MT to generate a sequential program. This profiler function measures the task execution cost (clock cycle) and the number of task executions. By executing the sequential program in which the profiler function is inserted once on the target machine, a file having information on the task execution cost and the task execution number on the target machine is output.

Then, in the second phase, the parallelized program scheduled based on the actual cost is generated using the output file and the sequential program as input.
1-6. Data localization An automatic parallelizing compiler can perform cache optimization over the entire program. After analyzing the parallelism between loops, etc., if the automatic parallelizing compiler finds that there is data dependence between the loops, it tries to optimize the cache globally between the loops with dependence (Reference 3 (Patent No. 3). No. 4,177,681)).

  Specifically, the array accessed in each loop is investigated, and the same divided loop is allocated to the same processor by adjusting so as to access the same array portion. As a result, in the same divided loop, all the array data is reused on the cache.

In addition, this localization technology
(1) When a local memory or a distributed shared memory of an arbitrary size is provided, a local memory close to the processor is accessed before being accessed using DMA (DTU) (see Reference 4 (Japanese Patent No. 4476267)). Alternatively, it is preloaded into the distributed shared memory and reused throughout the program.

  (2) When the destination memory is full, when the DTU of the destination processor is informed by the synchronization flag that the data has been flushed to the shared memory or the like according to the flushing priority from the memory, it is automatically freed Transfer data to memory.

  (3) Data that will be reused in the future, but will not be used for a while, and if the memory area needs to be opened, the DTU saves the data to the centralized shared memory behind the task execution by the CPU. Reload by use.

It has evolved to local memory management and data transfer technology (Reference 5 (UK Patent No. 2478874)).
1-7. Generation of a parallelized program Parallelized programs are generated by an automatic parallelizing compiler using an automatic parallelizing API (see Reference 7 (Waseda University, "Optimally Scheduled Advanced Multiprocessor Application Program Interface", 2008)). Alternatively, parallelization can be done with source-to-source, such as parallelized Fortran.

  In this case, the automatic parallelizing compiler can execute the parallelized program on various platforms, so that the C or Fortran directive part for each processor is executed at runtime using the automatic parallelizing API standard interpretation system described later. Convert to library call. Thereafter, the automatic parallelizing compiler compiles the code for each processor with a sequential compiler to generate a binary, and when this binary is linked, the parallelized program can be executed on the target multiprocessor.

2. Next, features of the sequential program for the embedded system will be described, and a parallelization method by the automatic parallelizing compiler of this embodiment will be described. Note that the embedded system may be, for example, an in-vehicle device or an electronic device other than the in-vehicle device. The sequential program may be automatically generated by model-based design (as an example, automatically generated by MatWork (registered trademark) or Simulink (registered trademark) of MathWork).

  The automatic parallelizing compiler is composed of conditional branches and assignment statements, and performs inline expansion and renaming on sequential programs with fine processing to extract parallelism. In addition, task scheduling for conditional branch concealment is performed in order to comply with real-time characteristics, and static scheduling is performed so as to reduce overhead. Further, an automatic profile feedback function may be applied to perform static scheduling at an actual cost.

  In a sequential program, conditional compilation (selection to the preprocessor) performs conditional compilation to select a description to be compiled according to various types of embedded systems with different destinations, functions, hardware configurations, etc. May be. In such a case, by setting information corresponding to one of the types (information indicating the destination) as an argument of each conditional compilation switch of the sequential program, the binary code corresponding to the type can be obtained from the sequential program. Generated. A series of descriptions composed of a plurality of portions that are switched to be compiled according to the argument of the conditional compilation switch are referred to as conditional descriptions.

  On the other hand, the automatic parallelizing compiler of this embodiment ignores the selection of the compilation target by conditional compilation, performs macro task division, parallelism extraction, static scheduling, etc. for all parts of the sequential program. Generate a parallelized program. Thereafter, a description that is not subject to compilation is identified from the parallelized program by conditional compilation, and binary data for operating the multi-core processor is generated without the description. Further, the automatic parallelizing compiler assigns all macro tasks corresponding to all processes based on one conditional description to the same PG in static scheduling.

2-1. Operating Environment of Automatic Parallelizing Compiler The automatic parallelizing compiler 1 is a storage medium configured as, for example, an optical disk such as a DVD, CD-ROM, USB memory, or memory card (registered trademark), a magnetic disk, a semiconductor memory, or the like. 18 is provided to the user in the state stored in 18 (see FIG. 1). Of course, it may be provided to the user via the network.

  The personal computer (PC) 10 in which the automatic parallelizing compiler 1 is installed operates as an automatic parallelizing compiling device. The PC 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like.

The display 11 displays the video signal received from the CPU 13 as a video to the user.
The input device 16 includes a keyboard and a mouse, and outputs a signal corresponding to the operation to the CPU 13 when operated by the user.

The reading unit 17 is a part that reads data from the storage medium 18 in which the automatic parallelizing compiler 1 or the like is stored.
The RAM 15 is a readable / writable volatile memory, the ROM 14 is a read-only nonvolatile memory, and the HDD 12 is a readable / writable nonvolatile memory. In the ROM 14 and the HDD 12, programs that are read and executed by the CPU 13 are stored in advance.

  The RAM 15 is a storage area for temporarily storing the program when the CPU 13 executes the program stored in the ROM 14 or the HDD 12 or a storage area for temporarily storing work data. Used.

  Further, the CPU 13 reads the OS from the HDD 12 and executes it, and executes various programs recorded on the HDD 12 as processes on the OS. In this process, the CPU 13 receives an input of a signal from the input device 16 as necessary, outputs a video signal to the display 11, and controls data read / write to the RAM 15 and the HDD 12.

  In addition, the automatic parallelizing compiler 1 read from the storage medium 18 via the reading unit 17 is installed in the PC 10, and the automatic parallelizing compiler 1 is stored in the HDD 12 and executed as a process on the OS. One of the applications.

  This automatic parallel compilation device is used for developing a parallel program for an embedded system such as an in-vehicle device. However, the present invention is not limited to this, and can be used, for example, for developing parallel programs for embedded systems for various uses such as information appliances, and for developing parallel programs for other uses other than embedded systems.

2-2. Automatic Parallelization Processing Next, automatic parallelization processing for generating a parallelized program based on a sequential program that is subjected to conditional compilation will be described with reference to the flowchart of FIG. By the conditional compilation, binary data mounted on the embedded system of the type corresponding to the argument value referenced by the conditional compilation switch is generated from the sequential program. Further, this process is started in response to an instruction from the user by the automatic parallelizing compiler 1 operating on the PC 10.

  In S100, the automatic parallelizing compiler 1 identifies the conditional description from the sequential program based on the conditional compilation switch described in the sequential program, and shifts the processing to S105.

In S105, the automatic parallelizing compiler 1 executes a software structure analysis process (see FIG. 3), generates an MTG, and shifts the process to S110.
In S110, the automatic parallelizing compiler 1 performs static scheduling based on the MTG generated by the software structure analysis process. As a result, all or part of the macro tasks that can be executed in parallel are assigned to different PGs (information indicating the result of the assignment is assigned information), and a parallelized program is generated. At this time, all macrotasks corresponding to processing based on one conditional description are assigned to the same PG.

  In the parallelized program, a conditional compilation switch having the same content as the conditional compilation switch set in the conditional description in the sequential program is set for the description corresponding to each conditional description. For this reason, when the argument of the conditional compilation switch of the parallelized program is set to a value corresponding to any type, a parallelized program corresponding to the type is obtained.

  Further, the automatic parallelizing compiler 1 may specify the actual cost (processing time as an example) when executing each macrotask by the profile automatic feedback function in the static scheduling. Then, macro tasks that can be executed in parallel may be assigned to each PG so that the processing loads of the PGs are approximately the same while assigning the macro tasks corresponding to the processing based on the conditional descriptions to the same PG.

  At this time, since the automatic parallelizing compiler 1 operates the parallelized program on various platforms, the runtime library uses the automatic parallelizing API standard interpretation system to execute the parallelized program to which the automatic parallelizing API is added. It may be converted into an implemented parallelized program.

  In S115, the automatic parallelizing compiler 1 specifies a macro task corresponding to the processing based on each conditional description, and for each conditional description, the corresponding macro for each conditional description based on the MTG generated by the software structure analysis processing. Determine whether a task can be parallelized. Then, the conditional description for which it is determined that the macrotask can be parallelized is specified, and the process proceeds to S120.

  In S120, the automatic parallelizing compiler 1 verifies the performance of the parallelized program. Specifically, for example, the automatic parallelizing compiler 1 may specify the processing time of each macro task and calculate the sum of the processing times of all the macro tasks assigned to the PG for each PG. At this time, for a PG that needs to wait for the end of processing in another PG (for example, when processing corresponding to a macro task having data dependency is performed in another PG), the waiting time is calculated, The waiting time is added to the total processing time of PG. Then, the maximum value (parallel execution time) of the total processing time of each PG may be specified and used as the verification result.

  In addition to this, for example, the parallel execution time is calculated in the same manner, and the total processing time (maximum processing time) of all macro tasks is calculated as the processing time when the single core processor executes the sequential program. Also good. Then, a value obtained by dividing the parallel execution time by the maximum processing time is calculated as a reduction rate (a value indicating how much the processing speed is improved by parallelization), and this may be used as a verification result.

Note that the automatic parallelizing compiler 1 may notify the verification result of the performance of the generated parallelized program.
In S125, the automatic parallelizing compiler 1 determines whether or not the performance of the parallelized program has reached a certain level based on the verification result of the performance of the parallelized program. Specifically, for example, when the parallel execution time is less than or equal to a predetermined threshold, or when the reduction rate is less than or equal to a predetermined threshold, the performance of the parallelized program reaches a certain level. You may consider it. In addition, for example, when both the parallel execution time and the reduction rate are equal to or less than the threshold value, it may be considered that the performance of the parallelized program has reached a certain level. If an affirmative determination is obtained (S125: Yes), the process proceeds to S130, and if a negative determination is obtained (S125: No), the process proceeds to S135.

  In S130, the automatic parallelizing compiler 1 generates a report indicating the conditional description specified in S115 (conditional description in which each corresponding macrotask can be parallelized), and stores the report in the HDD 12. Note that a report indicating a plurality of parallelizable macro tasks corresponding to processing based on one conditional description may be generated, or both or one of the conditional description and the macro task may be displayed on the display 11. May be.

  In S135, the automatic parallelizing compiler 1 analyzes the compiler switch described in the parallelized program, and executes pre-pro processing that performs processing according to the analysis result. At this time, based on the conditional compilation switch, the description to be compiled is specified from the parallelized program by the type corresponding to the argument, and the process proceeds to S140.

  In S140, the automatic parallelizing compiler 1 generates binary data for operating the multi-core processor from the description to be compiled in the parallelized program, and ends this processing.

2-3. Software Structure Analysis Processing Next, software structure analysis processing for generating MTG from a sequential program will be described using the flowchart of FIG. This processing is executed by automatic parallelization processing.

  In S200, the automatic parallelizing compiler 1 performs inline expansion (replaces the description for calling the subroutine with the description of the process defined in the subroutine) for the sequential program, and proceeds to S205. A sequential program for an embedded system is generally finely processed and difficult to parallelize with a coarse granularity. However, by performing inline expansion, the parallelism within the subroutine can be effectively utilized.

  In S205, the automatic parallelizing compiler 1 renames the local variable. For example, in a sequential program automatically generated from a Simulink model, the same local variable may be used repeatedly in many places to reduce ROM usage. As a result, the parallelism cannot be extracted sufficiently. Therefore, the local variables being reused are renamed.

  Specifically, the automatic parallelizing compiler 1 specifies a plurality of processing blocks in which local variables with the same name are used in each function of the sequential program, and each local block with a unique name in each specified processing block. Modify the sequential program so that variables are used.

  The processing block may be, for example, a collection of descriptions including a loop processing, a branch processing statement such as an if statement or a switch-case statement, and an assignment statement accompanying the statement. In addition, for example, a collection of descriptions corresponding to each block in the Simulink model that generated the sequential program may be used as a processing block.

  In S210, the automatic parallelizing compiler 1 divides the sequential program that has been subjected to these processes into macro tasks. Then, an MFG is generated by analyzing data dependency and control dependency between the macro tasks, and the process proceeds to S215.

  In S215, the automatic parallelizing compiler 1 identifies a macro task that branches to a different macro task as a start task based on the control dependency indicated by the MFG. Further, the automatic parallelizing compiler 1 identifies the macro task that is executed first among the macro tasks that are executed in common among all of the series of processes that are sequentially executed starting from the start task as the end task. .

  Then, the automatic parallelizing compiler 1 executes the specified start task, the end task in the process starting from the start task, and all the processes executed after the start task and before the end task is executed. The macro task is merged into one macro task (task fusion), and the process proceeds to S220.

  In order to make the granularity of the macro task fine, among the macro tasks that are commonly executed in all of a plurality of series of processes that are sequentially executed starting from the start task as in the process in S215, It is preferable to specify a macro task to be executed as a termination task. However, the present invention is not limited to this, and any one of these macrotasks executed after the second may be specified as a termination task.

  Sequential programs for embedded systems (especially in-vehicle devices) have few loop structures, so it may be possible to apply near fine-grain parallelism or coarse-grained task parallelism. 1 applies coarse-grained task parallelization.

  In the sequential program, the cost of each macrotask is about several tens of clocks. However, when dynamic scheduling is performed by the automatic parallelizing compiler 1, an overhead of several tens to several hundreds of clocks is usually generated. For this reason, dynamic scheduling is not suitable for sequential programs.

  However, since a macrotask having a conditional branch is dynamically determined at the time of execution of the macrotask, static scheduling that assigns a processor core at the time of compilation cannot be applied as it is.

  Therefore, the automatic parallelizing compiler 1 performs task fusion by fusing a macro task having a conditional branch and a macro task at the branch destination into one coarse-grained task (Block task) by a task fusion algorithm. By performing task fusion, the MFG has no control dependency, and static scheduling is possible.

  In S220, the automatic parallelizing compiler 1 analyzes the earliest executable condition of each macro task based on the MFG subjected to task fusion, and generates an MTG. Then, this process ends.

3. Next, the configuration of the in-vehicle device 20 that operates according to the parallelized program generated by the automatic parallelizing compiler 1 of the present embodiment will be described (see FIG. 4). Of course, the automatic parallelizing compiler 1 is capable of generating parallelized programs that operate not only the in-vehicle device 20 but also various electronic devices having the same configuration.

The in-vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, an input / output port 24, and the like.
The multi-core processor 21 includes a ROM 21a, a RAM 21b, and a plurality of PEs 21c, 21d, etc.

  The ROM 21a stores a parallelized program 21a-1 (binary data) generated by the automatic parallelizing compiler 1. The multi-core processor 21 operates according to the parallelized program 21a-1 and performs overall control of the in-vehicle device 20.

The RAM 21b is a part accessed by the PEs 21c, 21d, etc.
The communication unit 22 is a part that communicates with another ECU connected via an in-vehicle LAN or the like.

Moreover, the sensor part 23 is a site | part comprised from the various sensors for detecting states, such as a control object.
The input / output port 24 is a part that transmits and receives various signals for controlling the control target.

[Specific examples]
Next, a specific example of processing for generating a parallelized program by the automatic parallelizing compiler 1 of the present embodiment will be described. In the following description, description such as process A is made, which means a description of a series of processes including various operations, assignments, branch processes, function calls, and the like.

  In this specific example, a parallelized program is generated based on a sequential program 300 that is subjected to conditional compilation that refers to two types of arguments (“CSW1, 2”) (see FIG. 5). The parallelized program is executed by a multi-core processor having two PEs (first and second cores), and each macrotask is assigned to these cores. In the figure, the sequential program 300 includes the processes of “Processes A to E”, but other processes may be included.

  In the sequential program 300, “Processing B and C” and “Processing D and E” are conditional descriptions. One of “Process B” and “Process C” is selected as a compilation target by the conditional compilation switch 301, and one of “Process D” and “Process E” is the compilation target by the conditional compilation switch 302. Selected as. Specifically, when “CSW1 = A”, “Process B” is selected as a target for compilation, and when “CSW1 ≠ A”, Process C is selected as a target for compilation. In addition, when “CSW2 = B”, “Process D” is selected as a target for compilation, and when “CSW2 ≠ B”, Process E is selected as a target for compilation.

The automatic parallelizing compiler 1 specifies each of “Processing B and C” and “Processing D and E” of the sequential program 300 as a conditional description in S100 of the automatic parallelization processing.
In S105 (software structure analysis process), the automatic parallelizing compiler 1 divides each of the “processes A to E” into different macro tasks (“A” to “E”) to generate an MTG. The macro tasks “A” to “E” correspond to “processes A to E”, respectively.

  In S110, the automatic parallelizing compiler 1 performs static scheduling based on the generated MTG. A to D patterns 310 to 313 indicate allocation information that may be generated by the static scheduling.

  By static scheduling, “B, C”, “D, E” as macro tasks are assigned to the same core. In the A pattern 310, “B, C” is assigned to the first core, and “D, E” is assigned to the second core. In the B pattern 311, “B, C” is assigned to the second core, “D, E”. Is assigned to the first core. In the C pattern 312, “B, C” and “D, E” are assigned to the first core, and in the D pattern 313, “B, C” and “D, E” are assigned to the second core.

  Here, by task fusion, a part of the macro task corresponding to processing based on one conditional description and the macro task corresponding to processing based on descriptions before and after the conditional description are merged into one macro task. It is also assumed that In such a case, the automatic parallelizing compiler 1 assigns the merged macrotask and the remaining macrotask corresponding to the conditional description to one core in static scheduling.

  More specifically, in the above specific example, as a result of task fusion, “A” and “B” may be merged into one macro task (macro task A + B). In such a case, “C” and macrotask A + B are assigned to the same core.

  Also, by task fusion, a part of the macrotask corresponding to the process based on one conditional description and a part (or all) of the macrotask corresponding to the process based on the conditional description before and after the conditional description A case where it is merged into one macro task is also assumed. Even in such a case, the automatic parallelizing compiler 1 assigns the merged macrotask and the remaining macrotask corresponding to the conditional description to one core in the static scheduling.

  More specifically, in the above specific example, as a result of task fusion, “C” and “D” may be merged into one macro task (macro task C + D). In such a case, “B”, “E”, and macrotask C + D are assigned to the same core. In the above specific example, as a result of task fusion, “C” to “E” may be merged into one macro task (macro task C + D + E). In such a case, “B” and macrotask C + D + E are assigned to the same core.

  Note that the conditional description (“process B, C” or “process D, E”) in this specific example can be switched between two types depending on whether a conditional compilation switch refers to one argument or not. It is structured as a series of descriptions consisting of parts. However, the present invention is not limited to this, and the conditional description may be configured by a conditional compile switch that refers to two or more arguments, or is configured by three or more parts that can be switched to be compiled. May be.

[effect]
The automatic parallelizing compiler 1 according to the present embodiment performs static scheduling and the like based on a sequential program including all conditional descriptions, and generates a parallelized program. Then, according to the argument of the conditional compilation switch, a part of the conditional description that is not subject to compilation is removed from the parallelized program, and a type of parallelized program corresponding to the input information is generated.

  In the parallelized program at the stage where static scheduling is performed, each process based on one conditional description is assigned to the same PG. For this reason, even when multiple types of parallelized programs with different destinations are generated by setting an argument of the conditional compilation switch, the commonality of various types of parallelized programs can be further enhanced. As a result, it becomes easy to maintain and manage the quality of the parallelized program.

  Here, if each process corresponding to one conditional description can be assigned to different PGs (can be parallelized), the performance of the parallelized program is reduced by assigning these processes to the same PG. End up.

  On the other hand, the automatic parallelizing compiler 1 specifies a conditional description that can parallelize a plurality of corresponding macro tasks and verifies the performance of the parallelized program. If the performance of the parallelized program does not reach a certain level, a report indicating the conditional description that can parallelize the corresponding macrotask is generated to notify the user of the conditional description.

  Thereby, as a result of performing the automatic parallel processing of the present embodiment, when a parallel program with sufficient performance cannot be obtained, the user can improve the performance of the parallel program based on the above report. Measures can be taken.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, this invention can take a various form, without being limited to the said embodiment.

  (1) In the automatic parallelization processing of this embodiment, a conditional description that can be parallelized is specified (S115), and the performance of the generated parallelized program is verified (S120), and the performance is kept at a certain level. If not, a report indicating a conditional description that can be parallelized is generated (S130).

  However, a report indicating a conditional description that can be parallelized may be generated regardless of the performance of the generated parallelized program. Even in such a case, the user can take measures for further improving the performance of the parallelized program based on the report.

  Further, the verification result of the performance of the generated parallelized program may be notified without specifying a conditional description that can be parallelized. By doing so, it is possible to grasp how much of the parallelized program has been obtained by the automatic parallelization processing of the present embodiment, and the convenience of the automatic parallelizing compiler 1 can be improved.

  (2) The automatic parallelizing compiler 1 of the present embodiment performs inline expansion of the sequential program in S200 of the software structure analysis process and renames local variables in S205. Both or one of these processes is performed. It is good also as a structure which does not perform. Even in such a case, the same effect can be obtained depending on the structure of the sequential program.

  (3) The functions of one constituent element in the above embodiment may be distributed as a plurality of constituent elements, or the functions of a plurality of constituent elements may be integrated into one constituent element. Further, at least a part of the configuration of the above embodiment may be replaced with a known configuration having the same function. Moreover, you may abbreviate | omit a part of structure of the said embodiment. In addition, at least a part of the configuration of the above embodiment may be added to or replaced with the configuration of the other embodiment. In addition, all the aspects included in the technical idea specified only by the wording described in the claim are embodiment of this invention.

  (4) In addition to the above-described automatic parallelizing compiler and automatic parallelizing compiling device, the present invention is realized in various forms such as a medium storing the automatic parallelizing compiler and a method corresponding to processing performed by the automatic parallelizing compiler. You can also

[Correspondence with Claims]
The correspondence between the terms used in the description of the above embodiment and the terms used in the description of the claims is shown.

The automatic parallelizing compiler 1 corresponds to an example of a parallelizing compiler, and the in-vehicle device 20 corresponds to an example of an electronic device.
PG and PE (first and second cores) in the specific example correspond to an example of a processor unit.

  Further, S110 of the automatic parallel processing corresponds to an example of a scheduling procedure and a scheduling unit, S120 corresponds to an example of a verification procedure and a verification unit, and S130 corresponds to an example of a notification procedure and a notification unit.

Further, S210 of the software structure analysis process corresponds to an example of a dividing procedure and dividing means, and S220 corresponds to an example of an extracting procedure and extracting means.
The value of the argument of the conditional compilation switch corresponds to an example of input information.

  DESCRIPTION OF SYMBOLS 1 ... Automatic parallelizing compiler, 10 ... PC, 11 ... Display, 12 ... HDD, 13 ... CPU, 14 ... ROM, 15 ... RAM, 16 ... Input device, 17 ... Reading part, 18 ... Storage medium, 20 ... In-vehicle device 21 ... multi-core processor, 21a ... ROM, 21b ... RAM, 21c, 21d ... processor element (PE), 22 ... communication unit, 23 ... sensor unit, 24 ... input / output port.

Claims (6)

A program that is executed by a single processor system and includes a conditional description that is a series of descriptions composed of a plurality of parts that are switched depending on input information by conditional compilation. A division procedure for dividing the process described in the sequential program into a plurality of macro tasks regardless of the input information (S210);
An extraction procedure for extracting the macrotasks that can be executed in parallel by a plurality of processor units constituting a multiprocessor system based on the data dependency between the macrotasks (S220);
A process of assigning each of the macrotasks to any one of the processor units, wherein all or part of the macrotasks that can be executed in parallel are assigned to different processor units and executed by the multiprocessor system. A scheduling procedure for generating a parallelized program (S110),
Assigning a plurality of macrotasks corresponding to processing based on one conditional description to the same processor unit in the scheduling procedure;
Parallelizing compilation method characterized by In the parallel compilation method according to claim 1,
A notification procedure (S130) for performing notification regarding the conditional description relating to processing corresponding to the plurality of macro tasks that can be allocated to the different processor units;
Parallelizing compilation method characterized by In the parallel compilation method according to claim 1 or 2,
A verification procedure (S120) for verifying the performance of the parallelized program;
Parallelizing compilation method characterized by In the parallel compilation method according to any one of claims 1 to 3,
A verification procedure (S120) for verifying the performance of the parallelized program;
When the performance of the parallelized program does not reach a certain level from the verification result in the verification procedure, notification regarding the conditional description related to the processing corresponding to the plurality of macrotasks that can be allocated to the different processor units A notification procedure (S130) for performing
A parallel compilation method, further comprising: A program that is executed by a single processor system and includes a conditional description that is a series of descriptions composed of a plurality of parts that are switched depending on input information by conditional compilation. Dividing means for dividing the processing described in the sequential program into a plurality of macro tasks regardless of the input information (S210);
Extraction means for extracting the macrotask that can be executed in parallel by a plurality of processor units constituting a multiprocessor system based on data dependency between the macrotasks (S220);
A process of assigning each of the macrotasks to any one of the processor units, wherein all or part of the macrotasks that can be executed in parallel are assigned to different processor units and executed by the multiprocessor system. As a scheduling means for generating a parallelized program (S110), the computer is operated,
The scheduling means allocates a plurality of the macrotasks corresponding to processing based on the one conditional description to the same processor unit;
Parallelizing compiler (1) characterized by A program that is executed by a single processor system and includes a conditional description that is a series of descriptions composed of a plurality of parts that are switched depending on input information by conditional compilation. A division procedure for dividing the process described in the sequential program into a plurality of macro tasks regardless of the input information (S210);
An extraction procedure for extracting the macrotasks that can be executed in parallel by a plurality of processor units constituting a multiprocessor system based on the data dependency between the macrotasks (S220);
A process of assigning each of the macrotasks to any one of the processor units, wherein all or part of the macrotasks that can be executed in parallel are assigned to different processor units and executed by the multiprocessor system. A scheduling procedure for generating a parallelized program (S110),
Assigning a plurality of macrotasks corresponding to processing based on one conditional description to the same processor unit in the scheduling procedure;
An electronic device (20) comprising the multiprocessor system that operates according to the parallelized program generated by the parallelized compiling method.

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