JP2016118934A - Random number creation device and random number creation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a random number creation device capable of creating a random number having high genuine property, by controlling properly a sampling timing.SOLUTION: A random number creation device 1 comprises: an oscillation circuit 2 for outputting an output value D1 in which, 0 and 1 of binary logic are alternately repeated; a control part 4 for, based on the output value D1 of the oscillation circuit 2, creating data in which a value is irregularly varied, thereby determining a sampling timing; and a shift register 3 for, sampling the output value D1 of the oscillation circuit 2 by the sampling timing determined by the control part 4, for creating a random number.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a random number generation device and a random number generation method, and more particularly to a true random number generation device and a generation method.

  With the development of information technology in recent years, crimes such as eavesdropping, falsification, and impersonation by third parties tend to increase. Therefore, information security by encryption has become important, and the use of random numbers is indispensable for encryption.

  Previously, many pseudo-random numbers generated by operations using formulas based on combinations of functions were used. However, the risk of artificially leaking functions and initial settings, and random number generation patterns predicted by third parties There was a possibility that could be done. Therefore, instead of pseudo-random numbers, true random numbers having high reproducibility and unpredictability have been demanded.

  In a general true random number generator, an output value in which binary logic “0” and “1” are repeated alternately is output from a ring oscillator, and the output value is sampled by a shift register using a predetermined sampling clock. By doing so, a true random number is generated.

  In Patent Document 1 below, a random number output from a random number output register is used to generate a sampling clock that is an integral multiple of the system clock, and the output value of the oscillator is sampled using the sampling clock, thereby generating a random number. An intrinsic random number generator that generates a random number with an output register is disclosed.

JP-A-2005-174206

  As described above, in the general true random number generator, the true random number is generated by sampling the output value from the ring oscillator by the shift register. Here, the authenticity (non-reproducibility and unpredictability) of the generated random number depends on the accuracy of sampling. If the sampling is simply performed using a sampling clock with a fixed period, the authenticity is high. Unable to generate random numbers.

  The present invention has been made in view of such circumstances, and an object thereof is to obtain a random number generation device and a random number generation method capable of generating a highly authentic random number by appropriately controlling the sampling timing. To do.

  The random number generation device according to the first aspect of the present invention is based on an oscillation circuit that outputs an output value in which binary logic “0” and “1” are alternately repeated, and an output value of the oscillation circuit, A random number is generated by sampling the output value of the oscillation circuit at the sampling timing determined by the control unit that determines the sampling timing by generating data whose value changes irregularly and the control unit And a random number generation unit.

  According to the random number generation device according to the first aspect, the control unit determines the sampling timing by generating data whose value changes irregularly based on the output value of the oscillation circuit. Accordingly, the sampling timing can be irregularly changed by the control unit, and as a result, the authenticity (non-reproducibility and unpredictability) of the random number generated by the random number generation unit can be increased. In addition, since the output value of the oscillation circuit fluctuates due to environmental factors such as ambient temperature and humidity, the sampling timing determined by the control unit also fluctuates accordingly.As a result, the authenticity of the random number can be further increased. Become. Furthermore, compared to the case where the sampling clock is generated by dividing the system clock, the circuit design can be facilitated by unifying the clock, and the sampling timing can be set finely, not limited to an integer multiple of the system clock. It becomes possible to further increase the authenticity of.

  The random number generation device according to a second aspect of the present invention is the random number generation device according to the first aspect, in particular, the control unit generates a pseudo random number using the output value of the oscillation circuit as a seed. It is characterized by having a vessel.

  According to the random number generation device according to the second aspect, the control unit has a pseudo-random number generator that generates a pseudo-random number using the output value of the oscillation circuit as a seed. Since the output value of the oscillation circuit changes every moment, the value of the pseudo random number generated by using it as a seed also changes every moment. As a result, it is possible to generate data whose value changes irregularly as the value of the pseudo random number.

  In the random number generation device according to the third aspect of the present invention, in particular, in the random number generation device according to the second aspect, the control unit further includes a counter that counts a system clock from a predetermined initial value. A control signal for causing the random number generator to sample the output value of the oscillation circuit is output when the count number of the system clock matches the value of the pseudo random number generated by the pseudo random number generator. To do.

  According to the random number generation device according to the third aspect, the control unit causes the random number generation unit to include the oscillation circuit when the count number of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator. A control signal for sampling the output value is output. When the control signal is input, the random number generation unit samples the output value of the oscillation circuit, so that the random number generation unit can generate a random number.

  The random number generation device according to a fourth aspect of the present invention is the random number generation device according to the second aspect, in particular, the control unit includes a counter that counts a system clock using an output value of the oscillation circuit as an initial value. And a control signal for causing the random number generator to sample the output value of the oscillation circuit when the count of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator. Is output.

  According to the random number generation device according to the fourth aspect, the control unit causes the random number generation unit to include the oscillation circuit when the count of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator. A control signal for sampling the output value is output. When the control signal is input, the random number generation unit samples the output value of the oscillation circuit, so that the random number generation unit can generate a random number. The output value of the oscillation circuit is used as the initial value of the counter. Since the output value of the oscillation circuit changes every moment, the initial value of the counter also changes every moment. Therefore, even if the values of the pseudo random numbers are the same, the count number until the count number of the system clock matches the value of the pseudo random number varies, so the timing at which the control unit outputs the control signal also varies. As a result, the authenticity of the random number can be further increased.

  The random number generation device according to a fifth aspect of the present invention is the random number generation device according to the second aspect, in particular, the control unit has a predetermined value in which the value of the pseudo random number generated by the pseudo random number generator is set in advance. A control signal for causing the random number generation unit to sample the output value of the oscillation circuit is output by matching the value.

  According to the random number generation device according to the fifth aspect, the control unit outputs the output of the oscillation circuit to the random number generation unit when the value of the pseudo random number generated by the pseudo random number generator matches a predetermined value set in advance. A control signal for sampling the value is output. When the control signal is input, the random number generation unit samples the output value of the oscillation circuit, so that the random number generation unit can generate a random number. Further, since the counter for counting the system clock can be omitted, the circuit configuration can be simplified.

  The random number generation device according to a sixth aspect of the present invention is the random number generation device according to any one of the second to fifth aspects, particularly in the period when the random number generation by the random number generation unit is not required. The operation of the circuit and the pseudo random number generator is stopped.

  According to the random number generation device according to the sixth aspect, the operations of the oscillation circuit and the pseudo-random number generator are stopped in a period in which generation of random numbers by the random number generation unit is not necessary. This makes it possible to reduce power consumption.

  The random number generation device according to a seventh aspect of the present invention is the random number generation device according to the first aspect, in particular, the control unit includes a counter that counts a system clock using an output value of the oscillation circuit as an initial value. It is characterized by having.

  According to the random number generation device according to the seventh aspect, the control unit has the counter that counts the system clock using the output value of the oscillation circuit as the initial value. Since the output value of the oscillation circuit changes every moment, the initial value of the counter also changes every moment. As a result, it is possible to generate data whose value irregularly changes as the count number of the system clock from the initial value to the target value by the counter.

  In the random number generation device according to the eighth aspect of the present invention, in particular, in the random number generation device according to the seventh aspect, the control unit further includes a pseudorandom number generator that generates a pseudorandom number using a predetermined value as a seed. And a control signal for causing the random number generator to sample the output value of the oscillation circuit when the count number of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator. It is characterized by doing.

  According to the random number generation device according to the eighth aspect, the control unit causes the random number generation unit to include the oscillation circuit when the count number of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator. A control signal for sampling the output value is output. When the control signal is input, the random number generation unit samples the output value of the oscillation circuit, so that the random number generation unit can generate a random number. In addition, since the value of the pseudo random number generated by the pseudo random number generator (that is, the target value of the counter) changes every moment, even if the initial value of the counter is the same, the system clock count is equal to the pseudo random number. Since the number of counts until it matches the value varies, the timing at which the control unit outputs the control signal also varies, and as a result, the authenticity of the random number can be further increased.

  The random number generation device according to the ninth aspect of the present invention is the random number generation device according to the seventh aspect, in particular, the control unit is configured such that the number of system clocks counted by the counter matches a predetermined value set in advance. Thus, a control signal for causing the random number generation unit to sample the output value of the oscillation circuit is output.

  According to the random number generation device according to the ninth aspect, the control unit causes the random number generation unit to sample the output value of the oscillation circuit when the count number of the system clock by the counter matches a predetermined value set in advance. Control signal for output. When the control signal is input, the random number generation unit samples the output value of the oscillation circuit, so that the random number generation unit can generate a random number. Further, the target value of the counter is fixed to a predetermined value, and the pseudo random number generator for generating the target value can be omitted, so that the circuit configuration can be simplified.

  The random number generation device according to the tenth aspect of the present invention is the random number generation device according to any one of the seventh to ninth aspects, particularly in the period when the random number generation by the random number generation unit is not required. The operation of the circuit and the counter is stopped.

  According to the random number generation device according to the tenth aspect, the operations of the oscillation circuit and the counter are stopped in a period in which generation of random numbers by the random number generation unit is not necessary. This makes it possible to reduce power consumption.

  The random number generation method according to the eleventh aspect of the present invention includes (A) generating an output value in which “0” and “1” of binary logic are alternately repeated, and (B) the step (A). A step of determining sampling timing by generating data whose value changes irregularly based on the output value generated by step (C), and (C) outputting the output value generated by step (A). Generating random numbers by sampling at the sampling timing determined in (B).

  According to the random number generation method according to the eleventh aspect, in step (B), the sampling timing is set by generating data whose value changes irregularly based on the output value generated in step (A). It is determined. Therefore, the sampling timing can be irregularly varied in step (B), and as a result, the authenticity (non-reproducibility and unpredictability) of the random numbers generated in step (C) can be increased. It becomes. Compared with the case where the sampling clock is generated by dividing the system clock, the circuit design can be facilitated by unifying the clock, and the sampling timing can be set finely, not limited to an integer multiple of the system clock. It becomes possible to further increase the authenticity of.

  According to the present invention, it is possible to generate a highly authentic random number by appropriately controlling the sampling timing.

It is a figure which shows the structure of the random number generator which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of an oscillation circuit. It is a figure which shows the structure of one ring oscillator. It is a figure which shows the structure of a shift register. It is a figure which shows the structure of the random number generator which concerns on Embodiment 2 of this invention. It is a figure which shows the structure of the random number generator which concerns on Embodiment 3 of this invention. It is a figure which shows the structure of the random number generator which concerns on Embodiment 4 of this invention. It is a figure which shows the structure of the random number generator which concerns on Embodiment 5 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

<Embodiment 1>
FIG. 1 is a diagram showing a configuration of a random number generation device 1 according to Embodiment 1 of the present invention. As shown in the connection relationship of FIG. 1, the random number generation device 1 includes an oscillation circuit 2, a shift register 3, and a control unit 4. The control unit 4 includes a pseudo random number generator 11, a counter 12, and a comparator 13. Note that a plurality of sets of pseudorandom number generators 11 and counters 12 may be mounted for backup at the time of failure or failure.

  The oscillation circuit 2 outputs an N-bit output value D1 in which binary logic “0” and “1” are alternately repeated in each bit. The control unit 4 determines sampling timing based on the control signal S3 by generating data whose value changes irregularly based on the output value D1 of the oscillation circuit 2. The shift register 3 functions as a random number generation unit, and generates an intrinsic random number D4 by sampling the output value D1 of the oscillation circuit 2 at the sampling timing determined by the control unit 4.

  FIG. 2 is a diagram illustrating a configuration of the oscillation circuit 2. The oscillation circuit 2 has a configuration in which a plurality of N ring oscillators 5 (1) to 5 (N) are connected in parallel. An enable signal S1 for instructing the start of the operation of the oscillation circuit 2 is input to each ring oscillator 5 in common. Each ring oscillator 5 outputs a 1-bit output value in which binary logic “0” and “1” are alternately repeated, and N ring oscillators 5 (1) to 5 (N) are arranged in parallel. By being connected, a total N-bit output value D1 is output from the oscillation circuit 2.

  FIG. 3 is a diagram showing a configuration of one ring oscillator 5. The ring oscillator 5 has a configuration in which an odd number of NAND circuits are connected in series. In the example shown in FIG. 3, the ring oscillator 5 includes five NAND circuits 6 (1) to 6 (5). An enable signal S <b> 1 is input to one input terminal of each NAND circuit 6. The output of the final stage NAND circuit 6 (5) is input to the other input terminal of the first stage NAND circuit 6 (1). The outputs of the preceding NAND circuits 6 (1) to 6 (4) are input to the other input terminals of the second and subsequent NAND circuits 6 (2) to 6 (5).

  FIG. 4 is a diagram illustrating a configuration of the shift register 3. The shift register 3 has a configuration in which a plurality of M flip-flops 7 (1) to 7 (M) are connected in series. A control signal S3 is commonly input from the control unit 4 to each flip-flop 7. A system clock SC is commonly input to each flip-flop 7.

  An N-bit output value D1 is input from the oscillation circuit 2 to the D terminal of the first flip-flop 7 (1). Outputs from the Q terminals of the preceding flip-flops 7 (1) to 7 (M-1) are input to the D terminals of the second and subsequent flip-flops 7 (2) to 7 (M). M flip-flops 7 (1) to 7 (M) are connected in series, and N-bit outputs from the respective flip-flops 7 are arranged, so that a total N × M-bit intrinsic random number D4 is generated in the shift register 3 Is output from.

  Hereinafter, the operation of the random number generation device 1 according to the first embodiment will be described with reference to FIG.

  The enable signals S1 and S2 are negated during a period when the generation of the true random number D4 is not requested, and the operations of the oscillation circuit 2 and the control unit 4 are thereby stopped.

  When generation of the true random number D4 is requested, the enable signal S1 is first asserted. When the enable signal S1 is asserted, the oscillation circuit 2 starts an oscillation operation. As a result, the output value D1 is output from the oscillation circuit 2.

  Next, the pseudorandom number generator 11 performs initialization using the output value D1 input from the oscillation circuit 2 as a seed, and then generates a pseudorandom number D2 by a predetermined algorithm. The pseudo random number D <b> 2 generated by the pseudo random number generator 11 is input to one input terminal of the comparator 13.

  Next, when the enable signal S2 for instructing the operation start of the counter 12 is asserted, the counter 12 starts the count operation of the system clock SC from a predetermined initial value (for example, “0”). The counter 12 increments the count value every time the system clock SC is input, and the count value D3 is input to the other input terminal of the comparator 13.

  The comparator 13 sequentially compares the value of the pseudo random number D2 and the count value D3 of the counter 12. Then, when the count operation of the counter 12 proceeds and the count value D3 coincides with the value of the pseudo random number D2, a control signal S3 for causing the shift register 3 to perform sampling is output.

  Next, when the control signal S3 is input from the comparator 13, the shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time. Referring to FIG. 4, sampled output value D1 is input to first-stage flip-flop 7 (1) and held.

  The control signal S3 output from the comparator 13 is also input to the pseudorandom number generator 11 and the counter 12.

  The pseudo-random number generator 11 receives the control signal S3, performs initialization using the output value D1 input from the oscillation circuit 2 at that time as a seed, and then uses the second pseudo-random number D2 as a seed. Generate. When the control signal S3 is input, the counter 12 returns the count value to the initial value and starts the second count operation. When the count value D3 obtained by the second count operation matches the value of the second pseudo random number D2, the comparator 13 outputs the second control signal S3. The shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time when the second control signal S3 is input. Referring to FIG. 4, sampled output value D1 is input to first-stage flip-flop 7 (1) and held. Further, the output value D1 (the output value D1 sampled based on the first control signal S3) held by the first-stage flip-flop 7 (1) until then is obtained from the first-stage flip-flop 7 (1). Shifted to flip-flop 7 (2). By repeating the same operation M times as described above, the output value D1 is held in each of the M flip-flops 7 (1) to 7 (M). Then, N-bit output values D1 held by the flip-flops 7 (1) to 7 (M) are output from the respective Q terminals, and the M output values D1 are arranged so that a total of N × An M-bit intrinsic random number D4 is output from the shift register 3.

  As described above, according to the random number generation device 1 according to the first embodiment, the control unit 4 generates the sampling timing by generating the data whose value changes irregularly based on the output value D1 of the oscillation circuit 2. To decide. Therefore, the sampling timing can be irregularly changed by the control unit 4, and as a result, the authenticity (non-reproducibility and unpredictability) of the random number D4 generated by the shift register 3 can be increased. Become. Further, since the output value D1 of the oscillation circuit 2 varies depending on environmental factors such as ambient temperature and humidity, the sampling timing determined by the control unit 4 also varies accordingly. As a result, the authenticity of the random number D4 is further increased. It becomes possible. Furthermore, compared to the case where the sampling clock is generated by dividing the system clock, the circuit design can be facilitated by unifying the clock, and the sampling timing can be set finely, not limited to an integer multiple of the system clock. It becomes possible to further increase the authenticity of D4.

  In addition, according to the random number generation device 1 according to the first embodiment, the control unit 4 includes the pseudo random number generator 11 that generates the pseudo random number D2 using the output value D1 of the oscillation circuit 2 as a seed. Since the output value D1 of the oscillation circuit 2 changes every moment, the value of the pseudo random number D2 generated by using it as a seed also changes every moment. As a result, it is possible to generate data whose value changes irregularly as the value of the pseudo random number D2.

  In addition, according to the random number generation device 1 according to the first embodiment, the control unit 4 confirms that the count number of the system clock SC by the counter 12 matches the value of the pseudo random number D2 generated by the pseudo random number generator 11. Thus, the control signal S3 for causing the shift register 3 to sample the output value D1 of the oscillation circuit 2 is output. By inputting the control signal S3, the shift register 3 samples the output value D1 of the oscillation circuit 2, whereby the shift register 3 can generate the random number D4.

  In addition, according to the random number generation device 1 according to the first embodiment, the operations of the oscillation circuit 2 and the control unit 4 are stopped during a period in which the random number generation unit 4 does not need to generate the random number D4. This makes it possible to reduce power consumption.

<Embodiment 2>
FIG. 5 is a diagram showing a configuration of the random number generation device 1 according to Embodiment 2 of the present invention. As shown in the connection relationship of FIG. 5, the random number generation device 1 includes an oscillation circuit 2, a shift register 3, and a control unit 4. The control unit 4 includes a pseudo random number generator 11, a counter 12, and a comparator 13.

  Hereinafter, the operation of the random number generation device 1 according to the second embodiment will be described with reference to FIG.

  The enable signals S1 and S2 are negated during a period when the generation of the true random number D4 is not requested, and the operations of the oscillation circuit 2 and the control unit 4 are thereby stopped.

  When generation of the true random number D4 is requested, the enable signal S1 is first asserted. When the enable signal S1 is asserted, the oscillation circuit 2 starts an oscillation operation. As a result, the output value D1 is output from the oscillation circuit 2.

  Next, the pseudorandom number generator 11 performs initialization using the output value D1 input from the oscillation circuit 2 as a seed, and then generates a pseudorandom number D2 by a predetermined algorithm. The pseudo random number D <b> 2 generated by the pseudo random number generator 11 is input to one input terminal of the comparator 13.

  The output value D1 of the oscillation circuit 2 is also input to the counter 12, and the counter 12 sets the input output value D1 as the initial value of the count.

  Next, when the enable signal S2 for instructing the operation start of the counter 12 is asserted, the counter 12 starts the count operation of the system clock SC from the initial value set above. The counter 12 increments the count value every time the system clock SC is input, and the count value D3 is input to the other input terminal of the comparator 13.

  The comparator 13 sequentially compares the value of the pseudo random number D2 and the count value D3 of the counter 12. Then, when the count operation of the counter 12 proceeds and the count value D3 coincides with the value of the pseudo random number D2, a control signal S3 for causing the shift register 3 to perform sampling is output.

  Next, when the control signal S3 is input from the comparator 13, the shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time.

  The control signal S3 output from the comparator 13 is also input to the pseudorandom number generator 11 and the counter 12.

  The pseudo-random number generator 11 receives the control signal S3, performs initialization using the output value D1 input from the oscillation circuit 2 at that time as a seed, and then uses the second pseudo-random number D2 as a seed. Generate. When the control signal S3 is input, the counter 12 sets the output value D1 input from the oscillation circuit 2 at that time as a second initial value. Then, the second counting operation starts from the second initial value. When the count value D3 obtained by the second count operation matches the value of the second pseudo random number D2, the comparator 13 outputs the second control signal S3. The shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time when the second control signal S3 is input. By repeating the same operation M times as described above, the output value D1 is held in each of the M flip-flops 7 (1) to 7 (M). Then, N-bit output values D1 held by the flip-flops 7 (1) to 7 (M) are output from the respective Q terminals, and the M output values D1 are arranged so that a total of N × An M-bit intrinsic random number D4 is output from the shift register 3.

  As described above, according to the random number generation device 1 according to the second embodiment, the control unit 4 matches the count number of the system clock SC by the counter 12 with the value of the pseudo random number D2 generated by the pseudo random number generator 11. As a result, the control signal S3 for causing the shift register 3 to sample the output value D1 of the oscillation circuit 2 is output. By inputting the control signal S3, the shift register 3 samples the output value D1 of the oscillation circuit 2, whereby the shift register 3 can generate the random number D4. Further, as the initial value of the counter 12, the output value D1 of the oscillation circuit 2 is used. Since the output value D1 of the oscillation circuit 2 changes every moment, the initial value of the counter 12 also changes every moment. Therefore, even if the value of the pseudo random number D2 is the same, the count number until the count number of the system clock SC matches the value of the pseudo random number D2 varies, so the timing at which the control unit 4 outputs the control signal S3. As a result, the authenticity of the random number D4 can be further increased.

<Embodiment 3>
FIG. 6 is a diagram showing a configuration of the random number generation device 1 according to Embodiment 3 of the present invention. As shown by the connection relationship in FIG. 6, the random number generation device 1 includes an oscillation circuit 2, a shift register 3, and a control unit 4. The control unit 4 includes a pseudo random number generator 11, a register 14, and a comparator 13.

  Hereinafter, the operation of the random number generation device 1 according to the third embodiment will be described with reference to FIG.

  The enable signals S1 and S2 are negated during a period when the generation of the true random number D4 is not requested, and the operations of the oscillation circuit 2 and the control unit 4 are thereby stopped.

  When generation of the true random number D4 is requested, the enable signal S1 is first asserted. When the enable signal S1 is asserted, the oscillation circuit 2 starts an oscillation operation. As a result, the output value D1 is output from the oscillation circuit 2.

  Next, the pseudorandom number generator 11 performs initialization using the output value D1 input from the oscillation circuit 2 as a seed, and then generates a pseudorandom number D2 by a predetermined algorithm. The pseudo random number generator 11 receives the system clock SC, and the pseudo random number generator 11 generates a new pseudo random number D2 in synchronization with the system clock SC. The pseudo random number D <b> 2 generated by the pseudo random number generator 11 is input to one input terminal of the comparator 13.

  The register 14 stores one or more predetermined values V set in advance. The predetermined value V is input to the other input terminal of the comparator 13 as data D5.

  The comparator 13 sequentially compares the value of the pseudo random number D2 with the predetermined value V. Then, when the value of the pseudo random number D2 matches the predetermined value V, the control signal S3 for causing the shift register 3 to perform sampling is output.

  Next, when the control signal S3 is input from the comparator 13, the shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time.

  The control signal S3 output from the comparator 13 is also input to the pseudorandom number generator 11.

  The pseudo-random number generator 11 receives the control signal S3, performs initialization using the output value D1 input from the oscillation circuit 2 at that time as a seed, and then performs the system clock SC similarly to the above. The pseudo random number D2 is generated in synchronization with the above. The comparator 13 sequentially compares the value of the pseudo random number D2 with the predetermined value V. Then, when the value of the pseudo random number D2 matches the predetermined value V, the second control signal S3 is output. The shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time when the second control signal S3 is input. By repeating the same operation M times as described above, the output value D1 is held in each of the M flip-flops 7 (1) to 7 (M). Then, N-bit output values D1 held by the flip-flops 7 (1) to 7 (M) are output from the respective Q terminals, and the M output values D1 are arranged so that a total of N × An M-bit intrinsic random number D4 is output from the shift register 3.

  As described above, according to the random number generation device 1 according to the third embodiment, the control unit 4 determines that the value of the pseudo random number D2 generated by the pseudo random number generator 11 matches the predetermined value V set in advance. The control signal S3 for causing the shift register 3 to sample the output value D1 of the oscillation circuit 2 is output. By inputting the control signal S3, the shift register 3 samples the output value D1 of the oscillation circuit 2, whereby the shift register 3 can generate the random number D4. Further, since the counter 12 for counting the system clock SC can be omitted, the circuit configuration can be simplified.

<Embodiment 4>
FIG. 7 is a diagram showing a configuration of the random number generation device 1 according to Embodiment 4 of the present invention. As shown by the connection relationship in FIG. 7, the random number generation device 1 includes an oscillation circuit 2, a shift register 3, and a control unit 4. The control unit 4 includes a pseudo random number generator 11, a counter 12, and a comparator 13.

  Hereinafter, the operation of the random number generation device 1 according to the fourth embodiment will be described with reference to FIG.

  The enable signals S1 and S2 are negated during a period when the generation of the true random number D4 is not requested, and the operations of the oscillation circuit 2 and the control unit 4 are thereby stopped.

  When generation of the true random number D4 is requested, the enable signal S1 is first asserted. When the enable signal S1 is asserted, the oscillation circuit 2 starts an oscillation operation. As a result, the output value D1 is output from the oscillation circuit 2.

  Next, the pseudo random number generator 11 performs initialization using a predetermined value set in advance as a seed, and thereafter generates a pseudo random number D2 by a predetermined algorithm. The pseudo random number D <b> 2 generated by the pseudo random number generator 11 is input to one input terminal of the comparator 13.

  The output value D1 of the oscillation circuit 2 is input to the counter 12, and the counter 12 sets the input output value D1 as the initial value of the count.

  Next, when the enable signal S2 for instructing the operation start of the counter 12 is asserted, the counter 12 starts the count operation of the system clock SC from the initial value set above. The counter 12 increments the count value every time the system clock SC is input, and the count value D3 is input to the other input terminal of the comparator 13.

  The comparator 13 sequentially compares the value of the pseudo random number D2 and the count value D3 of the counter 12. Then, when the count operation of the counter 12 proceeds and the count value D3 coincides with the value of the pseudo random number D2, a control signal S3 for causing the shift register 3 to perform sampling is output.

  Next, when the control signal S3 is input from the comparator 13, the shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time.

  The control signal S3 output from the comparator 13 is also input to the pseudorandom number generator 11 and the counter 12.

  The pseudorandom number generator 11 receives the control signal S3 and generates the second pseudorandom number D2. When the control signal S3 is input, the counter 12 sets the output value D1 input from the oscillation circuit 2 at that time as a second initial value. Then, the second counting operation starts from the second initial value. When the count value D3 obtained by the second count operation matches the value of the second pseudo random number D2, the comparator 13 outputs the second control signal S3. The shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time when the second control signal S3 is input. By repeating the same operation M times as described above, the output value D1 is held in each of the M flip-flops 7 (1) to 7 (M). Then, N-bit output values D1 held by the flip-flops 7 (1) to 7 (M) are output from the respective Q terminals, and the M output values D1 are arranged so that a total of N × An M-bit intrinsic random number D4 is output from the shift register 3.

  As described above, according to the random number generation device 1 according to the fourth embodiment, the control unit 4 includes the counter 12 that counts the system clock SC using the output value D1 of the oscillation circuit 2 as an initial value. Since the output value D1 of the oscillation circuit 2 changes every moment, the initial value of the counter 12 also changes every moment. As a result, it is possible to generate data whose value irregularly changes as the count number of the system clock SC from the initial value by the counter 12 to the target value (the value of the pseudo random number D2).

  Further, the control unit 4 samples the output value D1 of the oscillation circuit 2 in the shift register 3 when the count number of the system clock SC by the counter 12 matches the value of the pseudo random number D2 generated by the pseudo random number generator 11. The control signal S3 for making it output is output. By inputting the control signal S3, the shift register 3 samples the output value D1 of the oscillation circuit 2, whereby the shift register 3 can generate the random number D4. Further, since the value of the pseudo random number D2 generated by the pseudo random number generator 11 (that is, the target value of the counter 12) changes every moment, even if the initial value of the counter 12 is the same, the count number of the system clock SC is the same. Since the number of counts until the value matches the value of the pseudo-random number D2 varies, the timing at which the control unit 4 outputs the control signal S3 also varies, and as a result, the authenticity of the random number D4 can be further increased.

<Embodiment 5>
FIG. 8 is a diagram showing a configuration of the random number generation device 1 according to the fifth embodiment of the present invention. As shown by the connection relationship in FIG. 8, the random number generation device 1 includes an oscillation circuit 2, a shift register 3, and a control unit 4. The control unit 4 includes a register 15, a counter 12, and a comparator 13.

  Hereinafter, the operation of the random number generation device 1 according to the fifth embodiment will be described with reference to FIG.

  The enable signals S1 and S2 are negated during a period when the generation of the true random number D4 is not requested, and the operations of the oscillation circuit 2 and the control unit 4 are thereby stopped.

  When generation of the true random number D4 is requested, the enable signal S1 is first asserted. When the enable signal S1 is asserted, the oscillation circuit 2 starts an oscillation operation. As a result, the output value D1 is output from the oscillation circuit 2.

  The register 15 stores one or more predetermined values W set in advance. The predetermined value W is input to the one input terminal of the comparator 13 as data D6.

  The output value D1 of the oscillation circuit 2 is input to the counter 12, and the counter 12 sets the input output value D1 as the initial value of the count.

  Next, when the enable signal S2 for instructing the operation start of the counter 12 is asserted, the counter 12 starts the count operation of the system clock SC from the initial value set above. The counter 12 increments the count value every time the system clock SC is input, and the count value D3 is input to the other input terminal of the comparator 13.

  The comparator 13 sequentially compares the predetermined value W with the count value D3 of the counter 12. Then, when the count operation of the counter 12 proceeds and the count value D3 coincides with the predetermined value W, the control signal S3 for causing the shift register 3 to perform sampling is output.

  Next, when the control signal S3 is input from the comparator 13, the shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time.

  The control signal S3 output from the comparator 13 is also input to the counter 12.

  When the control signal S3 is input, the counter 12 sets the output value D1 input from the oscillation circuit 2 at that time as a second initial value. Then, the second counting operation starts from the second initial value. When the count value D3 obtained by the second counting operation coincides with the predetermined value W, the comparator 13 outputs the second control signal S3. The shift register 3 samples the output value D1 output from the oscillation circuit 2 at that time when the second control signal S3 is input. By repeating the same operation M times as described above, the output value D1 is held in each of the M flip-flops 7 (1) to 7 (M). Then, N-bit output values D1 held by the flip-flops 7 (1) to 7 (M) are output from the respective Q terminals, and the M output values D1 are arranged so that a total of N × An M-bit intrinsic random number D4 is output from the shift register 3.

  As described above, according to the random number generation device 1 according to the fifth embodiment, the control unit 4 determines that the count number of the system clock SC by the counter 12 matches the predetermined value W set in advance. A control signal S3 for sampling the output value D1 of the oscillation circuit 2 is output. By inputting the control signal S3, the shift register 3 samples the output value D1 of the oscillation circuit 2, whereby the shift register 3 can generate the random number D4. Further, since the target value of the counter 12 is fixed to the predetermined value W, and the pseudo random number generator 11 for generating the target value can be omitted, the circuit configuration can be simplified.

DESCRIPTION OF SYMBOLS 1 Random number generator 2 Oscillator 3 Shift register 4 Control part 11 Pseudo random number generator 12 Counter 13 Comparator

Claims (11)

An oscillation circuit that outputs an output value in which binary logic "0" and "1" are alternately repeated;
Based on the output value of the oscillation circuit, by generating data whose value changes irregularly, a control unit that determines the sampling timing;
By sampling the output value of the oscillation circuit at the sampling timing determined by the control unit, a random number generation unit that generates a random number;
A random number generator.   The random number generation device according to claim 1, wherein the control unit includes a pseudo random number generator that generates a pseudo random number using an output value of the oscillation circuit as a seed. The controller is
A counter that counts the system clock from a predetermined initial value;
When the count number of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator, the control signal for causing the random number generator to sample the output value of the oscillation circuit is output. The random number generation device according to claim 2. The controller is
A counter that counts a system clock using an output value of the oscillation circuit as an initial value;
When the count number of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator, the control signal for causing the random number generator to sample the output value of the oscillation circuit is output. The random number generation device according to claim 2.   The control unit generates a control signal for causing the random number generation unit to sample the output value of the oscillation circuit when a value of the pseudo random number generated by the pseudo random number generator matches a predetermined value set in advance. The random number generation device according to claim 2, which outputs the random number.   6. The random number generation device according to claim 2, wherein operations of the oscillation circuit and the pseudo-random number generator are stopped during a period in which generation of a random number by the random number generation unit is not required.   The random number generation device according to claim 1, wherein the control unit includes a counter that counts a system clock by using an output value of the oscillation circuit as an initial value. The controller is
A pseudorandom number generator that generates a pseudorandom number using a predetermined value as a seed;
When the count number of the system clock by the counter matches the value of the pseudo random number generated by the pseudo random number generator, the control signal for causing the random number generator to sample the output value of the oscillation circuit is output. The random number generation device according to claim 6.   The control unit outputs a control signal for causing the random number generation unit to sample the output value of the oscillation circuit when a count number of the system clock by the counter matches a predetermined value set in advance. Item 8. The random number generation device according to Item 7.   10. The random number generation device according to claim 7, wherein operations of the oscillation circuit and the counter are stopped in a period in which generation of a random number by the random number generation unit is not required. (A) generating an output value in which binary logic “0” and “1” are alternately repeated;
(B) determining sampling timing by generating data whose value changes irregularly based on the output value generated in the step (A);
(C) generating a random number by sampling the output value generated in step (A) at the sampling timing determined in step (B);
A random number generation method comprising:

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