JP2016051815A - Semiconductor device, manufacturing method of semiconductor device, print head, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be more efficiently manufactured.SOLUTION: The present invention relates to a semiconductor device that includes a substrate having a driving circuit formed thereon and a semiconductor thin film attached onto the substrate and having a plurality of light emitting elements formed thereon. In the semiconductor device of the present invention, the semiconductor thin film is formed by using a semiconductor layer formed by epitaxial growth; impurity diffusion is performed in a part of an area of the surface of the semiconductor thin film; a light emitting area that can emit light with the light emitting elements is formed in the area where the impurity diffusion has been performed; and an impurity diffusion area of the semiconductor thin film where impurity diffusion is performed is larger than the light emitting area.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, a print head, and an image forming apparatus, and can be applied to an image forming apparatus such as an electrophotographic printer.

  Conventionally, this type of apparatus is disclosed in the second embodiment of Patent Document 1, and is epitaxially grown in the order of n-type, p-type, and n-type on a GaAs substrate serving as a growth substrate, and the surface n is grown after the growth. A pnpn structure was formed by diffusing p-type impurities into the mold layer. Further, the pnpn structure is peeled off from the growth substrate and bonded to a different substrate on which a drive circuit is formed.

  As a conventional semiconductor device corresponding to a light emitting function, there is one described in Patent Document 1. The semiconductor device described in Patent Document 1 has a thyristor structure of an n-type first layer, a p-type second layer, an n-type third layer, and a p-type fourth layer in order from the bottom.

JP 2009-260246 A

  However, in a semiconductor device corresponding to a light emitting function with a conventional thyristor structure, the p-type fourth layer (uppermost layer) is formed by impurity diffusion with respect to the n-type third layer. In the semiconductor device corresponding to the light emitting function described in Patent Document 1, the shape and size of the light emitting region are determined by the shape and size of the region of the p-type fourth layer (the uppermost layer). However, when the p-type fourth layer is formed on the n-type third layer by the diffusion of impurities, heating at a high temperature is required. Therefore, after bonding to another substrate such as a drive circuit of the semiconductor device, The above-described impurity diffusion process cannot be performed. Therefore, when the semiconductor device described in Patent Document 1 is bonded to the drive circuit, it is necessary to finish the step of forming the p-type fourth layer (impurity diffusion treatment) before the bonding. is there.

  However, in the conventional semiconductor device, since the region to emit light is determined at the time of impurity diffusion, positioning with high accuracy is performed when bonding to the drive circuit after the impurity diffusion step. There was a need to do. Therefore, when a conventional semiconductor device corresponding to a light emitting function is bonded to a different substrate such as a drive circuit, it is necessary to employ an expensive assembly device corresponding to high positioning accuracy, or positioning takes time. There was a problem that the throughput in mass production decreased.

  Therefore, a semiconductor device, a semiconductor device manufacturing method, a print head, and an image forming apparatus that can be manufactured more efficiently are desired.

  A first aspect of the present invention is a semiconductor device comprising: a substrate on which a drive circuit is formed; and a semiconductor thin film attached on the substrate and formed with a plurality of light emitting elements. (1) The semiconductor thin film includes: (2) Impurity diffusion is performed in a part of the surface of the semiconductor thin film, and (3) In the region in which the impurity diffusion is performed. In addition, a light emitting region capable of emitting light by the light emitting element is formed. (4) An impurity diffusion region in which impurities are diffused in the semiconductor thin film is wider than the light emitting region.

  According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a substrate on which a drive circuit is formed; and a semiconductor thin film formed on the substrate and formed with a plurality of light emitting elements. A first step of forming a semiconductor thin film having a semiconductor layer; (2) a second step of impurity diffusion in a partial region of the surface of the semiconductor thin film; and (3) a region where the impurity diffusion has been performed. And (3) forming a light emitting region capable of emitting light by the light emitting element, and (4) in the third step, an impurity diffusion region in which impurities are diffused in the semiconductor thin film is formed from the light emitting region. It is also characterized by widening.

  According to a third aspect of the present invention, there is provided a print head comprising a semiconductor device having a plurality of light emitting elements formed thereon, a mounting substrate for mounting the semiconductor device, and a lens array for converging light emitted from the plurality of light emitting elements. The semiconductor device of the first aspect of the present invention is applied as the semiconductor device.

  According to a fourth aspect of the present invention, there is provided an electrostatic latent image carrier that carries an electrostatic latent image, and exposing the surface of the electrostatic latent image carrier to form an electrostatic latent image on the surface of the electrostatic latent image carrier. A print head to be formed; developing means for developing the electrostatic latent image formed on the surface of the electrostatic latent image carrier; and transfer for transferring the image developed on the surface of the electrostatic latent image carrier to a medium In the image forming apparatus, the print head according to the third aspect of the present invention is applied as the print head.

  According to the present invention, it is possible to provide a semiconductor device, a print head, and an image forming apparatus that can be more efficiently manufactured.

It is a top view which expands and shows only the part of the anode layer of the 3 terminal light emitting element concerning 1st Embodiment. 1 is a schematic sectional view of an image forming apparatus according to a first embodiment. 1 is a schematic cross-sectional view of an optical print head according to a first embodiment. 1 is a perspective view of a light emitting element array chip according to a first embodiment. It is a top view (the 1) of the light emitting element array chip concerning a 1st embodiment. FIG. 6 is a cross-sectional view taken along line A-A ′ in FIG. 5. FIG. 7 is a cross-sectional view taken along line B-B ′ in FIG. 6. It is a schematic sectional drawing of the state in which the epitaxial layer was formed in the manufacture process of the light emitting element array chip concerning 1st Embodiment. FIG. 6 is a schematic view showing a state where p-type impurities are diffused in a gate layer in the manufacturing process of the light-emitting element array chip according to the first embodiment. FIG. 6 is a schematic cross-sectional view showing a state where a sacrificial layer is exposed and etched in the manufacturing process of the light-emitting element array chip according to the first embodiment. It is a top view (the 2 and a top view before performing an etching process etc.) of the light emitting element array chip concerning a 1st embodiment. It is explanatory drawing of the junction shift | offset | difference amount generate | occur | produced with the light emitting element array chip concerning 1st Embodiment. FIG. 6 is a plan view of the light emitting element array chip according to the first embodiment (part 3 is a plan view in a state where a bonding deviation amount is generated). It is a top view (the 1) of the light emitting element array chip concerning a 2nd embodiment. It is the C-C 'sectional view taken on the line in FIG. It is sectional drawing of the D-D 'line | wire in FIG. It is a top view shown about the state which diffused the p type impurity to the epitaxial layer in the manufacture process of the light emitting element array chip concerning a 2nd embodiment. It is a top view (the 2 and a top view before performing an etching process etc.) of the light emitting element array chip concerning a 2nd embodiment. It is a top view of the light emitting element array chip concerning a 2nd embodiment (the 3 and a top view in the state where the amount of junction gap occurred).

(A) First Embodiment Hereinafter, a semiconductor device, a method for manufacturing a semiconductor device, a print head, and an image forming apparatus according to a first embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, an example in which the semiconductor device and the print head of the present invention are applied to a light emitting element array chip and an optical print head will be described.

(A-1) Configuration of First Embodiment FIG. 2 is a schematic cross-sectional view of an image forming apparatus according to the first embodiment.

  The image forming apparatus 200 is an electrophotographic printer using an optical print head on which a light emitting element (for example, a light emitting thyristor which is a three-terminal light emitting element) and a light emitting element array chip as a semiconductor device having a driving circuit thereof are mounted.

  The image forming apparatus 200 includes four process units 201-1 to 201- that form images of each color of yellow, magenta, cyan, and black, which are sequentially arranged along the conveyance path of the recording medium 205, using an electrophotographic method. 4, a recording medium cassette 206 for storing the recording medium 205, a hopping roller 207 for separating and conveying the recording medium 205 one by one, and a pinch arranged downstream of the hopping roller 207 in the conveying direction of the recording medium 205. Roller 208, 209, pinch rollers 208, 209 and the recording medium 205 are sandwiched between the conveying roller 210 for conveying the recording medium 205, and the registration roller 211 for correcting the skew of the recording medium 205 and conveying it to the process units 201a to 201d. And facing the process units 201a to 201d A transfer roller 212 as transfer means for transferring the image (toner image, developer image) formed on the photosensitive drum 202 to the recording medium 205, and the recording roller 205 on the recording medium 205. The image forming apparatus includes a fixing device 213 that heats and pressurizes and fixes a toner image, discharge rollers 214 and 215, pinch rollers 216 and 217 serving as discharge portions, and a paper stacker portion 218.

  The process units 201-1 to 201-4 have the same configuration except for the color of the toner. Each process unit 201 includes a photosensitive drum 202 as an electrostatic latent image carrier that carries an electrostatic latent image, a charging device 203 that is disposed around the photosensitive drum 202 and charges the surface of the photosensitive drum 202, An optical print head 204 as an exposure unit that selectively irradiates light onto the surface of the charged photosensitive drum 202 to form an electrostatic latent image, and toner on the electrostatic latent image formed on the surface of the photosensitive drum 202 A developing device 220 as developing means for supplying (developer) and developing, and an image (toner image, developer image) developed on the photosensitive drum 202 are transferred to the recording medium 205 and then transferred to the photosensitive drum 202. A cleaning device 219 for removing the remaining toner is provided.

  FIG. 3 is a sectional view schematically showing the structure of the optical print head 204.

  As shown in FIG. 3, an optical print head 204 as a print head includes a base material 221, an optical print head substrate unit 230 fixed on the base material 221, and a rod lens in which a large number of columnar optical elements are arranged. An array 222, a holder 223 for fixing the rod lens array 222, and clamp members 224a and 224b for fixing the base material 221, the optical printhead substrate unit 230, and the holder 223 are provided. In the optical print head 204, the components other than the optical print head substrate unit 230 are not limited, and can be configured in the same manner as various optical print heads.

  FIG. 4 is a perspective view showing the optical print head substrate unit 230.

  The optical print head substrate unit 230 includes a printed wiring board 231 and a plurality of chip-like driver ICs 232 each having a drive circuit for a light emitting element. Each driver IC 232 is fixed on the printed wiring board 231 with a thermosetting resin or the like. Further, a thin film three-terminal light emitting element array 233 is bonded to the surface of each driver IC 232. Each terminal of the driver IC 232 and a terminal pad (not shown) of the printed wiring board 231 are electrically connected by a bonding wire 234.

  Hereinafter, the driver IC 232 to which the three-terminal light emitting element array 233 is attached is referred to as a light emitting element array chip 236. That is, in the optical print head substrate unit 230, a plurality of light emitting element array chips 236 are arranged in a line on the printed wiring board 231.

  FIG. 5 is a plan view of the light emitting element array chip 236 (semiconductor composite device including the driver IC 232 and the three-terminal light emitting element array 233). 6 and 7 are cross-sectional views taken along lines A-A 'and B-B' in FIG. In the following description, when the three-terminal light-emitting element array 233 (three-terminal light-emitting element 235) is illustrated and described, the horizontal direction (longitudinal direction of the three-terminal light-emitting element array 233) viewed from the direction of FIG. The up-down direction (short direction of the three-terminal light emitting element array 233) viewed from the direction of FIG. 5 is referred to as a Y direction.

  In the three-terminal light-emitting element array 233, three-terminal light-emitting elements 235 as a plurality of light-emitting elements are arranged in a line.

  In the three-terminal light emitting element array 233, a bonding layer 241, a cathode layer 242, a cathode contact layer 243, a lower cladding layer 244, an active layer 245, an upper cladding layer 246, and gate layers 247a, 248a, and 249a are formed in this order from the bottom. Yes.

  Anode layers 247b, 248b, and 249b are formed in a partial region of the gate layers 247a, 248a, and 249a to form p-type semiconductor layers by diffusing p-type impurities. The anode layers 247b, 248b, and 249b are portions where p-type impurities are diffused into partial regions of the gate layers 247a, 248a, and 249a of the n-type semiconductor layer to form p-type semiconductor layers, respectively.

  In each three-terminal light emitting device 235, an anode contact electrode 250, a cathode contact electrode 251 and a gate contact electrode 252 are formed on each of the anode layer 249b, the cathode contact layer 243, and the gate layer 249a. Each electrode is electrically connected to a terminal pad (not shown) of the driver IC 232 through a thin film wiring. Further, the three-terminal light emitting element array 233 is bonded to the driver IC 232 via the planarizing film 240.

  Next, the structure of the anode layers 248b and 249b will be described with reference to FIG.

  FIG. 1 is a plan view illustrating only exposed portions of anode layers 248b and 249b constituting one three-terminal light emitting element 235. FIG.

  The anode layer 249b is cut to a size smaller than the anode layer 248b. The shape and size of the anode layer 249b (the shape and size of the surface formed at the boundary between the anode layer 249b and the anode layer 248b) is not limited, but here is a square (rectangle) with Wa on one side. Will be described.

  Further, as shown in FIG. 1, in each three-terminal light emitting element 235, the area LA including the anode layer 249b effectively emits light on the function of the optical print head 204 (function of the exposure apparatus) (hereinafter referred to as “light emission effective area”). Is also called). Since the light emission effective region LA is formed around the anode layer 249b, the light emitting effective region LA is a region having a position, shape, and width corresponding to the position, shape, and width (size) of the anode layer 249b. Here, as shown in FIG. 1, the description will be made assuming that the light emission effective region LA has a substantially rectangular shape centered on the anode layer 249b (a shape similar to the shape of the anode layer 249b). Here, it is assumed that the light emission effective area LA is a square (rectangle) having a side length We.

  Further, in each of the three-terminal light emitting elements 235, the shape and size of the upper surface area exposed by the anode layer 248b (the area including the area where the anode layer 249b is formed and functioning effectively as the light emission effective area LA). However, it is assumed that one side is a square (rectangle) having a predetermined width (details will be described later).

  Hereinafter, for the anode layer 249b, the light emission effective region LA, and the anode layer 248b, the width in the left-right direction (X direction) is also expressed as X1, X2, and X3. In the following, the vertical width (Y direction) of each of the anode layer 249b, the light emission effective region LA, and the anode layer 248b is also expressed as Y1, Y2, and Y3.

  1 and 5 to 7 are schematic views and do not accurately represent shapes such as thicknesses of the respective semiconductor layers. In each drawing explaining the three-terminal light-emitting element array 233, each three-terminal light-emitting element 235 is in an exposed state, but it may naturally be covered with an inorganic or organic insulating film as necessary. is there.

  Next, a configuration example of a semiconductor material suitable for manufacturing a three-terminal light emitting element array will be described.

  As a semiconductor material constituting the three-terminal light emitting element array 233, a material such as GaAs, AlGaAs, AlAs, InGaP, AlInGaP, or InAlGaAs can be used. A configuration example of the epitaxial layer 264 is shown below.

The buffer layer 261 is n-type GaAs, the sacrificial layer 262 is n-type AlAs, the junction layer 241 is n-type GaAs, the cathode layer 242 is n-type Al _x Ga _1-x As, the cathode contact layer 243 is n-type GaAs, and the lower cladding layer 244 is n-type Al _y Ga _1-y As, the active layer 245 is n-type Al _z Ga _1-z As, and the upper cladding layer 246 is p-type Al _z Ga _1-y As on p-type Al _z Ga _{1 -y} As. The two-layer structure of _z As, the gate layer 247a is n-type Al _y Ga _1-y As, the gate layer 248a is n-type Al _w Ga _1-w As, and the gate layer 249a is n-type GaAs. Here, when the emission wavelength of the light emitting element is 760 nm, it is desirable that x = 0.2, y = 0.6, z = 0.15, and w = 0.4.

In addition to the semiconductor layer, as an etching stop layer for exposing the cathode contact layer 243 during electrode formation, for example, an n-type In _v Ga _{1 -v} P between the cathode contact layer 243 and the lower cladding layer 244 is used. Etc. can also be added. Here, it is desirable that v = 0.49 to 0.51. The metal constituting the anode contact electrode 250, the cathode contact electrode 251, and the gate contact electrode 252 is composed of Au, Ge, Ni, Ti, Pt, Pd, W, Al, or an alloy thereof. Furthermore, an oxide semiconductor such as ITO or ZnO may be used.

  Next, a manufacturing method of the light emitting element array chip 236 constituting the image forming apparatus 200 (optical print head 204) of the first embodiment will be described.

  First, a method for manufacturing the three-terminal light emitting element array 233 constituting the light emitting element array chip 236 will be described.

  First, as shown in FIG. 8, various organic metal chemical vapor deposition (hereinafter referred to as “MOCVD method”) or molecular beam epitaxy (hereinafter referred to as “MBE method”) is applied to the growth substrate 260. The epitaxial layer 264 is formed using the above.

  FIG. 8 is a schematic cross-sectional view showing a state in which the epitaxial layer 264 is formed in the manufacturing process of the light emitting element array chip 236 (three-terminal light emitting element array 233).

  The epitaxial layer 264 includes a buffer layer 261, a sacrificial layer 262, a bonding layer 241, a cathode layer 242, a cathode contact layer 243, a lower cladding layer 244, an active layer 245, an upper cladding layer 246, gate layers 247a, 248a, in order from the lower layer. 249a.

  Next, as shown in FIG. 9, p-type impurities are diffused in a band shape from the gate layer 249a to the middle of the gate layer 247a by selective diffusion.

  FIG. 9 is a schematic view showing a state in which p-type impurities are diffused in the gate layers 247a, 248a, and 249a in the manufacturing process of the light-emitting element array chip 236 (three-terminal light-emitting element array 233).

  In the first embodiment, as shown in FIG. 9, a p-type impurity is diffused in a band-shaped (rectangular) region (hereinafter referred to as “impurity diffusion region”) on the upper surface of the gate layer 249a. In FIG. 9, the width of the strip-shaped impurity diffusion region DA (the width in the short side direction, the width in the vertical direction (Y direction)) is shown as Wd. Note that the impurity diffusion region DA is a region that can function as the anode layer 249b and the anode layer 248b. Further, the width Wd of the band-shaped impurity diffusion region DA is wider than the width Y2 (= We) in the vertical direction (Y direction) of the light emission effective region LA required for the specifications of the three-terminal light emitting element 235.

  Next, after the sacrificial layer 262 is exposed by etching, as shown in FIG. 10, only the sacrificial layer is selectively etched to form a three-terminal light emitting element array 233 from the growth substrate 260. The epifilm 263 can be peeled off.

  FIG. 10 is a schematic cross-sectional view showing a state where the sacrificial layer 262 is exposed and etched in the manufacturing process of the light emitting element array chip 236 (three-terminal light emitting element array 233).

  Next, the epi film 263 is bonded to the driver IC 232 having the planarizing film 240 formed on the surface. A specific apparatus for bonding the epi film 263 to the driver IC 232 (the planarizing film 240) is not limited, but various semiconductor device assembly apparatuses can be applied.

  FIG. 11 is a plan view of a state where the epi film 263 is attached to the driver IC 232 (the light emitting element array chip 236) in the manufacturing process of the light emitting element array chip 236.

  By the way, when the epi film 263 is bonded to the surface of the driver IC 232 (flattening film 240), a deviation from a target position may occur depending on the performance of the assembly apparatus to be used.

  FIG. 12 is an explanatory diagram of the amount of misalignment that occurs in the light emitting element array chip 236.

  FIG. 12A shows a state where the epifilm 263 is bonded to the target position (a state where there is no deviation). FIG. 12B shows a state in which the epifilm 263 is joined while being displaced from the target position. FIG. 12B shows a state in which the position of the epifilm 263 is shifted from the target position by Xd in the left-right direction (X direction) and Yd in the up-down direction (Y direction). Hereinafter, the amount of deviation (Xd, Yd) that occurs when the epifilm 263 is joined with a deviation from the target position is referred to as a “joining deviation amount”.

  Next, regions other than the regions in contact with the electrodes (the anode contact electrode 250 and the gate contact electrode 252) are removed from the gate layer 249a and the anode layer 249b. That is, in the manufacturing process of the light emitting element array chip 236, after the epi film 263 is attached to the driver IC 232 (flattening film 240), the final shape of the anode layer 249b is shaped (the shape of FIG. Shaping). Here, the position of the driver IC 232 is used as a reference for the position remaining as the anode layer 249b and the position where the anode contact electrode 250 is disposed.

  That is, as shown in FIG. 12B described above, when the position where the epitaxial film 263 is attached to the driver IC 232 (flattening film 240) deviates from the target position, the anode layer 249b remains when focusing only on the epitaxial film 263. The position where the anode contact electrode 250 is arranged and the position where the anode contact electrode 250 is arranged are also shifted by the same amount. At this time, in each of the three-terminal light emitting element arrays 233, the light emission effective area LA (X2 * Y2 area, in this case, a square area with one side width We) having a target size is all within the area of the anode layer 248b ( X3 * Y3 area). This is because even if a part of the target light emitting effective area LA is missing, the function and performance of the light emitting element array chip 236 as an exposure apparatus will be affected.

  Therefore, in this embodiment, by adjusting the size (width) of the impurity diffusion region DA, it is assumed that the target light emission effective region LA is all within the region of the anode layer 248b (details will be described later).

  Then, the cathode contact surface (cathode contact layer 243) for each three-terminal light emitting element 235 is exposed by etching, and separation for each three-terminal light emitting element 235 is performed. In the manufacturing process of the light emitting element array chip 236, an inorganic or organic insulating film (not shown) is appropriately formed, and then an anode contact electrode 250, a cathode contact electrode 251, and a gate contact electrode 252 are formed, thereby forming the light emitting element array. A chip 236 can be created.

  The light emitting element array chip 236 can be manufactured through the processes as described above.

  Next, in this embodiment, details of the shape adjustment of the impurity diffusion region DA will be described.

  As described above, in each of the three-terminal light emitting element arrays 233, it is necessary that all the light emission effective areas LA having a target size are included in the area of the anode layer 248b. However, as described above, the position where the epifilm 263 is bonded to the driver IC 232 (flattening film 240) may be shifted from the target position, and bonding shift amounts Xd and Yd may occur. It is conceivable to use a highly accurate assembly device when bonding the epi film 263 to the driver IC 232 (flattening film 240). However, a highly accurate assembly device is expensive and the assembly speed is slow (positioning is performed). It takes a long time to do).

  Therefore, in the light emitting element array chip 236 of this embodiment, the size of the impurity diffusion region DA is taken into consideration in consideration of the maximum amount of junction deviation amounts Xd and Yd generated in the manufacturing process (hereinafter referred to as “maximum junction deviation amount”). It is assumed that settings such as (width) are made. In the following description, the maximum joining displacement amount of the light emitting element array chip 236 is represented as Xdmax and Ydmax. As the maximum joining deviation amounts Xdmax and Ydmax, values based on specifications or experiments of an assembling apparatus used in the light emitting element array chip 236 can be applied.

  In the first embodiment, as shown in FIGS. 9 and 11, the impurity diffusion region DA has a strip shape (rectangular shape) arranged so that the left-right direction (X direction) is the longitudinal direction. The influence of the deviation in the direction (X direction) on the light emission effective area LA of the entire three-terminal light emitting element array 233 is small. For this reason, in this embodiment, it is assumed that only the width Wd in the vertical direction (Y direction) of the impurity diffusion region DA is set to a width that considers the maximum junction deviation amount Ydmax.

  In the following description, when the epi film 263 is bonded to the driver IC 232 (flattening film 240), it is necessary to consider the inclination of the epi film 263. However, as shown in FIG. , The inclination appears almost as a deviation in the Y direction. Therefore, the following description will be made assuming that the maximum joining deviation amount is set as a width in consideration of the deviation in the Y direction due to the inclination.

  FIG. 13 is a plan view of the light emitting element array chip 236 in a state in which a bonding deviation amount Yd is generated in the vertical direction (Y direction).

  FIG. 13A shows a state in which the bonding displacement amount Yd is generated in the upward direction in the vertical direction (Y direction) in the light emitting element array chip 236. FIG. 13B shows a state in which the bonding displacement amount Yd is generated in the lower direction in the vertical direction (Y direction) in the light emitting element array chip 236.

  13 (a) and 13 (b), the amount of misalignment Yd occurs in the vertical direction (Y direction). In any case, the effective light emission area LA having a target size (with one side being Wd). All the square areas are within the area of the anode layer 248b. In a semiconductor device having a light-emitting thyristor structure such as the three-terminal light-emitting device 235 of the first embodiment, the current hardly spreads in the lateral direction (left and right direction and vertical direction of the same layer). The effective light emission area LA is determined by the position, shape, and size of the diffused anode layer 249b. Therefore, as long as the target effective light emission area LA is all within the anode layer 248b, the size and light emission pattern of the effective light emission area LA in the three-terminal light emitting element array 233 do not change.

  Next, with reference to FIG. 1, a description will be given of the maximum values of junction deviation amounts Xd and Yd that are allowable in the three-terminal light-emitting element array 233 (hereinafter referred to as “allowable maximum deviation amounts”). In the following, the allowable maximum deviation amounts in the left-right direction (X direction) and the up-down direction (Y direction) are represented as Xdp and Ydp, respectively.

  In FIG. 1, the widths of the anode layer 249b, the light emission effective region LA, and the anode layer 248b in the vertical direction (Y direction) are indicated as Y1, Y2, and Y3, respectively. FIG. 1 shows a state in which the amount of joining deviation is 0 (Xd = Yd = 0). That is, in the state of FIG. 1, the center point P1 of the anode layer 249b (anode contact electrode 250) and the center point P2 of the anode layer 248b are in a state of matching on the plan view. Here, the description will be made assuming that the center point of the light emission effective region LA also coincides with the center point P1 of the anode layer 249b.

  When the amount of junction deviation is 0, in the three-terminal light emitting element 235, as shown in FIG. 1, in the vertical direction (Y direction), from the end of the light emission effective region LA to the end of the anode layer 248b. The distance is (Y3-Y2) / 2 at both the upper and lower ends. Therefore, in the three-terminal light emitting device 235 shown in FIG. 1, the allowable maximum deviation amount Ydp can be expressed as the following equation (1).

Therefore, it is necessary to set the width Y3 in the vertical direction (Y direction) of the anode layer 248b so that the allowable maximum deviation amount Ydp is equal to or greater than the maximum junction deviation amount Ydmax (Ydp ≧ Ydmax). Specifically, by setting the width Y3 in the vertical direction (Y direction) of the anode layer 248b to satisfy the following expression (2), even when the junction deviation amount Yd becomes the allowable maximum deviation amount Ydp, A light emission effective area LA having a target size can be secured. Therefore, when the width in the vertical direction (Y direction) of the impurity diffusion region DA is Wd and the width in the vertical direction (Y direction) of the light emission effective region LA is We, the width Wd of the impurity diffusion region DA is (3 ) Must be set so as to satisfy the relationship.
Ydp = (Y3-Y2) / 2 (1)
Y3 ≧ Y2 + (2 * Ydmax) (2)
Wd ≧ We + (2 * Ydmax) (3)

  For example, when the optical print head 204 can be exposed at a resolution of 600 DPI (Dot Per Inchi), the interval at which the adjacent three-terminal light emitting elements 235 are arranged (the interval between the central points P1 of the anode layer 248b) is 42 μm. It will be about. In this case, the width Wd (X3, Y3) of the impurity diffusion region DA is about 20 μm, and the width We (X2, Y2) of the light emission effective region LA is about 10 μm. Therefore, in this case, based on the above equation (1), the allowable maximum deviation amount Ydp is 5 μm. Further, in the three-terminal light emitting element array 233, a deviation amount up to 5 μm in the vertical direction (Y direction) is allowed. Therefore, in this case, the maximum joining deviation amount Ydmax should be 5 μm or less. However, for example, when the maximum joining deviation amount Ydmax is 10 μm due to the specification of the assembling apparatus, the allowable maximum deviation amount Ydp needs to be 10 μm or more. In order to set the allowable maximum deviation amount Ydp to 10 μm or more, it is necessary to set the width Wd (Y3) of the impurity diffusion region DA to 30 μm or more based on the above equations (1) to (3).

(A-3) Effects of First Embodiment According to the first embodiment, the following effects can be achieved.

  In the first embodiment, an epitaxial film 263 (semiconductor thin film) provided with an impurity diffusion region DA in a band shape is bonded to a driver IC 232 (heterogeneous substrate, substrate), and a pattern on the bonded driver IC 232 side (for example, the driver IC 232) The width Wd of the band-shaped impurity diffusion region DA is made wider than the target light emission effective region LA when the light emission effective region LA is formed in accordance with a wiring pattern or a mark pattern for alignment). Yes (with a large size). In other words, in the first embodiment, in consideration of the junction shift amounts Xd and Yd generated in the manufacturing process of the light emitting element array chip 236, the region of the anode layer 248b (the impurity diffusion region DA of the impurity diffusion region DA) rather than the target light emission effective region LA. (Area) is widened (large size). Specifically, in the first embodiment, the anode layer 248b (impurity diffusion region) is more than the target light emission effective region LA by an amount corresponding to the maximum junction deviation amounts Xdmax and Ydmax generated in the manufacturing process of the light emitting element array chip 236. The area of DA) is widened. That is, in the first embodiment, the shape and size of the region of the anode layer 248b (region of the impurity diffusion region DA) are set so that the allowable maximum deviation amounts Xdp and Ydp are equal to or larger than the maximum junction deviation amounts Xdmax and Ydmax. ing.

  Thereby, in the optical print head 204 of the first embodiment, even if a shift occurs when the epi film 263 is bonded to the driver IC 232, each of the three-terminal light emitting elements 235 has the same shape and the same size of light emission effective region. Since LA is obtained, high alignment accuracy is not required for the assembly apparatus used for joining. Further, when the optical print head 204 of the first embodiment is manufactured, an increase in throughput can be expected because the alignment accuracy when the epifilm 263 is bonded to the driver IC 232 can be afforded.

(B) Second Embodiment Hereinafter, a semiconductor device, a method for manufacturing the semiconductor device, a print head, and an image forming apparatus according to a second embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, an example in which the semiconductor device and the print head of the present invention are applied to a light emitting element array chip and an optical print head will be described.

(B-1) Configuration of Second Embodiment In the image forming apparatus 200 of the second embodiment, the configuration and manufacturing method of a part of the light emitting element array chip 236 are different. Hereinafter, differences between the structure (configuration) and the manufacturing method of the light emitting element array chip 236 in the second embodiment from the first embodiment will be described.

  FIG. 14 is a plan view of the light-emitting element array chip 236 (driver IC 232 to which the three-terminal light-emitting element array 233 is attached) according to the second embodiment. 15 and 16 are cross-sectional views taken along lines C-C 'and D-D' in FIG. In each drawing according to the second embodiment, parts that are the same as or correspond to those in the first embodiment are denoted by the same or corresponding reference numerals.

  FIG. 17 is an explanatory diagram showing a state in which p-type impurities are diffused into the epitaxial layer 264 epitaxially grown on the growth substrate 260 in the second embodiment.

  FIG. 18 is a plan view of the light emitting element array chip 236 of the second embodiment (plan view before performing an etching process or the like).

  In the first embodiment, the impurity diffusion region DA is formed in a band shape (rectangular shape) as shown in FIG. 9 and the like, but in the second embodiment, as shown in FIGS. 17 and 18 described above. In addition, an impurity diffusion region DA is formed in a rectangular (square) region separated for each three-terminal light emitting element 235. Although the shape of each impurity diffusion region DA is not limited, in FIG. 17, each impurity diffusion region DA is illustrated as a square having a side width of Wd. In the second embodiment, each impurity diffusion region DA has the shape of the anode layer 248b of each three-terminal light emitting element 235. That is, in the second embodiment, the shape of the anode layer 248b is determined before the three-terminal light emitting element array 233 is bonded to the driver IC 232.

  If the impurity diffusion region DA (the pn junction interface between the anode layer 248b and the gate layer 247a) is not etched during the exposure of the cathode contact layer and the gate isolation etching, each impurity diffusion region DA is The shape may be rectangular, polygonal, or circular.

  FIG. 19 is a plan view of the light emitting element array chip 236 according to the second embodiment in a state where the amount of misalignment Yd has occurred.

  FIG. 19A shows a state in which a bonding deviation amount Yd is generated in the upward direction in the light emitting element array chip 236. FIG. 19B shows a state in which the bonding deviation amount Yd is generated in the downward direction and the bonding deviation amount Xd is generated in the right direction in the light emitting element array chip 236.

  Each impurity diffusion region DA needs to be sized in consideration of the maximum junction deviation amount, as in the first embodiment. However, in the second embodiment, since the impurity diffusion region DA separated for each of the three-terminal light emitting elements 235 is formed, only the vertical direction (Y direction) of each impurity diffusion region DA is shown in FIG. Not only in the horizontal direction (X direction) but also in consideration of the maximum junction deviation amount (Xdmax, Ydmax), the width of the impurity diffusion region DA in the horizontal direction (X direction) and the vertical direction (Y direction) (that is, X3 and Y3 width) needs to be set.

Therefore, in the second embodiment, the width Y3 in the vertical direction (Y direction) of the anode layer 248b needs to satisfy the above-described expression (2). In the second embodiment, the width X3 in the left-right direction (X direction) of the anode layer 248b needs to satisfy the following expression (4). Here, since each impurity diffusion region DA is a square having a width of Wd on one side, the width Wd needs to satisfy the relationship of the above formula (3) and the following formula (5). In the second embodiment, the allowable maximum deviation amount Xdp in the left-right direction (X direction) can be expressed by the following equation (6).
X3 ≧ X2 + (2 * Xdmax) (4)
Wd ≧ We + (2 * Xdmax) (5)
Xdp = (X3-X2) / 2 (6)

(B-3) Effects of Second Embodiment According to the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

  In the three-terminal light-emitting element array 233 constituting the optical print head 204 of the second embodiment, the impurity diffusion region DA is not etched. For this reason, in the three-terminal light emitting element array 233 of the second embodiment, the pn junction interface (boundary portion between the anode layer 248b and the gate layer 247a) formed by impurity diffusion is not exposed by etching. Current can be suppressed and stable operation is possible.

(C) Other Embodiments The present invention is not limited to the above-described embodiments, and may include modified embodiments as exemplified below.

  (C-1) In each of the above embodiments, the example in which the print head of the present invention is applied to an electrophotographic printer has been described. However, the present invention is applied to other image forming apparatuses such as a FAX, a multifunction peripheral, and a copying machine. May be.

  In each of the above embodiments, the example in which the semiconductor device of the present invention (driver IC with a three-terminal light-emitting element array) is applied to a print head has been described. However, the device to which the semiconductor device of the present invention is applied. Is not limited. For example, the semiconductor device of the present invention may be applied to a display device such as a display. As described above, the semiconductor device of the present invention can be applied to various devices that can be realized by using an array type LED.

  (C-2) In the first embodiment, the width of the band-shaped impurity diffusion region DA is adjusted only in the vertical direction (Y direction) in consideration of the maximum junction deviation amount Ydmax. In order to ensure the performance of the three-terminal light emitting element 235 formed at both ends of the diffusion region DA, the maximum junction deviation amount Xdmax is also taken into consideration in the left-right direction (X direction) as in the second embodiment. Thus, the width in the longitudinal direction of the strip-shaped impurity diffusion region DA may be determined.

  DESCRIPTION OF SYMBOLS 200 ... Image forming apparatus, 201-1 to 201-4 ... Process unit, 202 ... Photosensitive drum, 203 ... Charging device, 204 ... Optical print head, 205 ... Recording medium, 206 ... Recording medium cassette, 207 ... Hopping roller, 208 209 ... Pinch roller, 210 ... Conveying roller, 211 ... Registration roller, 212 ... Transfer roller, 213 ... Fixing device, 214,215 ... Discharging roller, 216,217 ... Pinch roller, 218 ... Paper stacker unit, 219 ... Cleaning device , 220 ... Developing device, 221 ... Base material, 222 ... Rod lens array, 223 ... Holder, 224a, 224b ... Clamp member, 230 ... Optical print head board unit, 231 ... Printed wiring board, 232 ... Driver IC, 233 ... 3 Terminal light emitting element array, 234 ... Bonding Wires, 235... Three-terminal light emitting elements, 236... Light emitting element array chips, 240... Planarization film, 241... Bonding layer, 242. ... upper cladding layer, 247a, 248a, 249a ... gate layer, 247b, 248b, 249b ... anode layer, 250 ... anode contact electrode, 251 ... cathode contact electrode, 252 ... gate contact electrode, 260 ... growth substrate, 261 ... buffer layer 262 ... Sacrificial layer, 263 ... Epi film, 264 ... Epitaxial layer.

Claims (7)

In a semiconductor device comprising: a substrate on which a drive circuit is formed; and a semiconductor thin film attached on the substrate and formed with a plurality of light emitting elements.
The semiconductor thin film is configured using a semiconductor layer formed by epitaxial growth,
Impurity diffusion is performed in a part of the surface of the semiconductor thin film,
A light emitting region capable of emitting light by the light emitting element is formed in the region where the impurity diffusion has been performed,
An impurity diffusion region in which impurities are diffused in the semiconductor thin film is wider than the light emitting region.   2. The semiconductor device according to claim 1, wherein the impurity diffusion region is widened in consideration of a maximum shift amount when the semiconductor thin film is attached on the substrate.   The light-emitting element is a light-emitting thyristor having a pnpn structure, the impurity diffused in the impurity diffusion region is a p-type impurity, and a portion that becomes a p-type semiconductor layer by the impurity diffusion region is an anode of the light-emitting element. The semiconductor device according to claim 1, wherein the semiconductor device functions as a layer.   4. The semiconductor device according to claim 3, wherein a junction between the anode layer and the n-type semiconductor layer therebelow is not exposed. In a method for manufacturing a semiconductor device, comprising: a substrate on which a drive circuit is formed; and a semiconductor thin film formed on the substrate and formed with a plurality of light emitting elements.
A first step of forming a semiconductor thin film having a semiconductor layer by epitaxial growth;
A second step of diffusing impurities in a partial region of the surface of the semiconductor thin film;
Forming a light emitting region capable of emitting light by the light emitting element in the region where the impurity diffusion has been performed, and
In the third step, an impurity diffusion region in which impurities are diffused in the semiconductor thin film is made wider than the light emitting region.   A semiconductor device in which a plurality of light emitting elements are formed, a mounting substrate on which the semiconductor device is mounted, and a lens array that converges light emitted from the plurality of light emitting elements. A print head, wherein the semiconductor device according to any one of 1 to 4 is applied.   An electrostatic latent image carrier that carries an electrostatic latent image; a print head that exposes a surface of the electrostatic latent image carrier to form an electrostatic latent image on the surface of the electrostatic latent image carrier; and An image forming apparatus comprising: a developing unit that develops an electrostatic latent image formed on a surface of an electrostatic latent image carrier; and a transfer unit that transfers an image developed on the surface of the electrostatic latent image carrier to a medium. An image forming apparatus, wherein the print head according to claim 6 is applied as the print head.

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