JP2015225918A - Semiconductor module and semiconductor switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor module in which heat dissipation performance is enhanced compared with prior art.SOLUTION: A drain surface side thermal diffusion member 41 has a conductor block 41a connected electrically with a drain electrode of a semiconductor element. A gate-source surface side thermal diffusion member 42 has a conductor block 42a connected electrically with a source electrode of the semiconductor element, and a conductor pin 42b insulated from the conductor block 42a and connected electrically with a gate electrode of the semiconductor element. A wiring board 20 arranged on one side of the semiconductor element has a drain wiring 22 connected electrically with the conductor block 41a of the drain surface side thermal diffusion member 41. A wiring board 60 arranged on the other side of the semiconductor element has an intermediate wiring 62 connected with the conductor block 42a of the gate-source surface side thermal diffusion member 42, and a gate wiring 63 connected with the conductor pin 42b.

Description

  The disclosed technology relates to a semiconductor module and a semiconductor switch.

  A power device such as a power transistor is suitably used for applications such as a power switch and an inverter driven with a high voltage and a large current. Since a power device usually generates a large amount of heat, it is important to efficiently release the heat generated from the power device to the outside.

  As a technique for improving the heat dissipation of a power device, a power semiconductor package including a double-sided heat sink that contacts upper and lower surfaces of a plurality of power devices is known.

JP 2013-58733 A JP 2001-156225 A JP 2012-33864 A

  Silicon carbide (SiC) has attracted attention as a material for next-generation power devices. SiC can reduce the power consumption of the device with higher breakdown voltage and lower loss than conventional silicon (Si). In addition, SiC has a feature that it has a wider band gap than Si and an electric field strength that leads to dielectric breakdown is about 10 times larger. Also, since SiC has a wide bandwidth, few carriers are excited by heat, and high temperature operation is possible. In addition, according to SiC, since the breakdown electric field strength is high, the withstand voltage portion can be thinned, so that the on-resistance can be reduced. Since SiC devices have the advantages as described above, they are expected to contribute to miniaturization of modules and reduction of power loss.

  The biggest problem in manufacturing SiC devices is defects. A SiC device fabricated in a portion of a SiC wafer where a defect is formed has a higher probability of being a defective product than a SiC device fabricated in a portion without a defect. For this reason, if a SiC device is manufactured using a SiC wafer with many defects, a yield will fall. In order to increase the current capacity of the SiC device, it is necessary to increase the area per device. However, if a device with a large area is manufactured on a SiC wafer having a large number of defects, the possibility that a defect exists in the device is higher than a device with a smaller area, and the yield is reduced. Under such circumstances, the size of the current SiC device is smaller than that of the Si device. Thereby, the calorific value per area in a SiC device tends to become large compared with a Si device, and it is desirable to improve the heat dissipation of a device package compared with the package in the conventional Si device.

  This invention is made | formed in view of an above-described point, and it aims at providing the semiconductor module which improved the thermal radiation performance rather than before.

  The semiconductor module according to the present invention includes a first electrode on a first surface, a second electrode and a control electrode on a second surface opposite to the first surface, and the control electrode. A semiconductor element that conducts between the first electrode and the second electrode in response to a control signal supplied to the first electrode, and is bonded to the first surface of the semiconductor element and electrically connected to the first electrode. A first heat diffusion member having an electrically connected conductor portion, a first conductor portion joined to the second surface of the semiconductor element and electrically connected to the second electrode, and the first A second heat diffusion member having a second conductor portion insulated from one conductor portion and electrically connected to the control electrode; and a bonding surface of the first heat diffusion member to the semiconductor element A wiring board of at least one layer bonded to the opposite surface, wherein the first heat diffusion member The first wiring board having the first wiring pattern including the first wiring electrically connected to the conductor portion, and the side opposite to the bonding surface between the second heat diffusion member and the semiconductor element A wiring board having at least one layer bonded to the surface of the second heat diffusion member, the second wiring electrically connected to the first conductor portion of the second heat diffusion member, and the second heat diffusion member. And a second wiring board having a second wiring pattern including a third wiring electrically connected to the second conductor portion.

  The semiconductor switch according to the present invention includes a plurality of the semiconductor modules, the plurality of semiconductor modules are stacked with a heat sink therebetween, and the semiconductor elements of each of the plurality of semiconductor modules are connected in series. Including serialized units.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor module which improved heat dissipation performance compared with the past can be provided.

1 is an equivalent circuit diagram of a semiconductor module according to an embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor module 10 which concerns on embodiment of this invention. FIG. 3 is a plan view of a cross section taken along line 3A-3A in FIG. FIG. 3 is a plan view of a cross section taken along line 3B-3B in FIG. It is a perspective view which shows the state before bonding of the two wiring boards arrange | positioned at the lower surface side of the semiconductor element which concerns on embodiment of this invention. It is a perspective view which shows the state after bonding of the two wiring boards arrange | positioned at the lower surface side of the semiconductor element which concerns on embodiment of this invention. It is a perspective view which shows the state before bonding of the two wiring boards arrange | positioned at the upper surface side of the semiconductor element which concerns on embodiment of this invention. It is a perspective view which shows the state after bonding of the two wiring boards arrange | positioned at the upper surface side of the semiconductor element which concerns on embodiment of this invention. It is a perspective view which shows the structure of the semiconductor element Q which concerns on embodiment of this invention. It is a perspective view which shows the semiconductor element which concerns on embodiment of this invention, the drain surface side thermal-diffusion member 41, and the gate-source surface side thermal-diffusion member. It is a top view which shows the structure of the gate-source-surface side thermal diffusion member which concerns on embodiment of this invention. It is sectional drawing which followed the 8B-8B line | wire in FIG. 8A. It is sectional drawing which shows the connection state among the semiconductor element which concerns on embodiment of this invention, a gate / source surface side thermal diffusion member, and a wiring pattern. It is a perspective view which shows the external appearance of the semiconductor module which concerns on embodiment of this invention. It is sectional drawing which shows the thermal radiation path | route in the semiconductor module which concerns on embodiment of this invention. It is sectional drawing which shows the direction of the electric current which flows into the semiconductor module which concerns on embodiment of this invention. It is a top view which shows the structural example in the case of using the semiconductor module which concerns on embodiment of this invention as an inverter. It is the side view which looked at the drain terminal and source terminal of the semiconductor module which concern on embodiment of this invention from the direction of the arrow X in FIG. It is sectional drawing which shows the structure of the semiconductor module which concerns on embodiment of this invention. It is a figure which shows the structure of the semiconductor switch which concerns on embodiment of this invention comprised including a several semiconductor module. 1 is a diagram showing a configuration of a semiconductor switch according to an embodiment of the present invention configured to include a plurality of semiconductor modules 10. It is an equivalent circuit diagram of the semiconductor switch concerning this embodiment.

  Hereinafter, an exemplary embodiment of the disclosed technology will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

[First embodiment]
FIG. 1 is an equivalent circuit diagram of a semiconductor module 10 according to the first embodiment of the present invention. The semiconductor module 10 includes four semiconductor elements Q11, Q12, Q21, and Q22. Hereinafter, when the four semiconductor elements Q11, Q12, Q21, and Q22 are not distinguished or collectively referred to, they are referred to as a semiconductor element Q.

  In the present embodiment, each semiconductor element Q is an N-channel field effect transistor (FET) having a large current capacity and a high breakdown voltage. However, the present invention is not limited to this, and each semiconductor element Q may be another device such as an IGBT or a bipolar transistor. In addition, it is assumed that a SiC device is used as the semiconductor element Q. However, the present invention is not limited to this, and a semiconductor device made of another material such as Si, Ge, or GaN can also be used. .

  In the semiconductor module 10, the semiconductor elements Q11 and Q12 are connected in parallel, and the semiconductor elements Q21 and Q22 are connected in parallel. The pair consisting of semiconductor elements Q11 and Q12 is connected in series with the pair consisting of semiconductor elements Q21 and Q22. That is, in the semiconductor module 10, the plurality of semiconductor elements Q have a so-called 2-in-1 configuration. By serially connecting pairs in which a plurality of semiconductor elements are connected in parallel, it is possible to increase the current capacity as compared with the case where single semiconductor elements are connected in series.

  The gates of the semiconductor elements Q11 and Q12 are connected to the gate terminal G1. The drains of the semiconductor elements Q11 and Q12 are connected to the drain terminal D1. The sources of the semiconductor elements Q11 and Q12 are connected to the intermediate terminal C, the control signal reference terminal SG1, and the drains of the semiconductor elements Q21 and Q22. The semiconductor elements Q11 and Q12 are turned on and off at the same timing according to a control signal supplied from the outside via the control signal reference terminal SG1 and the gate terminal G1.

  The gates of the semiconductor elements Q21 and Q22 are connected to the gate terminal G2. The sources of the semiconductor elements Q21 and Q22 are connected to the source terminal S2 and to the control signal reference terminal SG2. The semiconductor elements Q21 and Q22 are turned on and off at the same timing according to a control signal supplied from the outside via the control signal reference terminal SG2 and the gate terminal G2.

  For example, when the semiconductor module 10 is used for an inverter, a plurality of semiconductor modules 10 are used. Each drain terminal D1 of the plurality of semiconductor modules 10 is connected to the positive electrode of the power supply, each source terminal S2 is connected to the negative electrode of the power supply, and each intermediate terminal C is connected to the load. Then, in each semiconductor module 10, the pair consisting of the semiconductor elements Q11 and Q12 and the pair consisting of the semiconductor elements Q21 and Q22 are turned on and off at different timings.

  On the other hand, when the semiconductor module 10 is used as a semiconductor switch, the drain terminal D1 is connected to the high voltage side of the current path, the source terminal S2 is connected to the low voltage side of the current path, and a pair of semiconductor elements Q11 and Q12 is connected. The pair of semiconductor elements Q21 and Q22 is turned on / off simultaneously.

  FIG. 2 is a cross-sectional view showing the configuration of the semiconductor module 10. 3A is a plan view of a cross section taken along line 3A-3A in FIG. 3B is a plan view of a cross section taken along line 3B-3B in FIG.

  In the semiconductor module 10, a drain surface side heat diffusion member 41 or a gate / source surface side heat diffusion member 42 including a conductor is joined to the upper surface and the lower surface of each semiconductor element Q. Specifically, as shown in FIG. 2, a drain surface side thermal diffusion member 41 is joined to the lower surface (drain surface P2) of the semiconductor element Q11, and gate / source surface side thermal diffusion is performed to the upper surface (gate / source surface P2). The member 42 is joined. The gate / source surface side heat diffusion member 42 is bonded to the lower surface (gate / source surface P1) of the semiconductor element Q21, and the drain surface side heat diffusion member 41 is bonded to the upper surface (drain surface P2). The semiconductor elements Q12 and Q22 are not shown in FIG. 2, but as is apparent from FIGS. 3A and 3B, the drain surface side heat diffusion member 41 is joined to the lower surface (drain surface P2) of the semiconductor element Q12. The gate / source surface side thermal diffusion member 42 is joined to the upper surface (gate / source surface P1). The gate / source surface side heat diffusion member 42 is bonded to the lower surface (gate / source surface P1) of the semiconductor element Q22, and the drain surface side heat diffusion member 41 is bonded to the upper surface (drain surface P2).

  The surface of the drain surface side heat diffusion member 41 or the gate / source surface side heat diffusion member 42 bonded to the lower surface of the semiconductor element Q opposite to the bonding surface with the semiconductor element Q is bonded to the wiring substrate 20. Yes. The wiring board 20 includes an insulating substrate 21 and wirings formed on the front and back of the insulating substrate 21. A drain wiring 22, a source wiring 23 and a gate wiring 24 are provided on the surface of the insulating substrate 21 on the semiconductor element Q side. A back surface wiring 26 electrically connected to the source wiring 23 through a through hole 25 is provided on the surface of the insulating substrate 21 opposite to the surface on the semiconductor element Q side.

  The back surface wiring 26 of the wiring substrate 20 is bonded to the wiring substrate 30. The wiring substrate 30 includes an insulating substrate 31 and wirings formed on the front and back of the insulating substrate 31. A source wiring 32 is provided on the surface of the insulating substrate 31 on the semiconductor element Q side, and the source wiring 32 is connected to the back surface wiring 26. A dummy wiring 33 that is not electrically connected to any terminal of the semiconductor module 10 is provided on the surface of the insulating substrate 31 opposite to the surface on the semiconductor element Q side.

  On the other hand, the surface of the drain surface side heat diffusing member 41 or the gate / source surface side heat diffusing member 42 bonded to the upper surface of the semiconductor element Q is bonded to the wiring substrate 60 on the side opposite to the bonding surface with the semiconductor element Q. Has been. The wiring substrate 60 includes an insulating substrate 61 and wirings formed on the front and back surfaces of the insulating substrate 61. An intermediate wiring 62 and a gate wiring 63 are provided on the surface of the insulating substrate 61 on the semiconductor element Q side. A dummy wiring 64 that is not electrically connected to any terminal of the semiconductor module 10 is provided on the surface of the insulating substrate 61 opposite to the surface on the semiconductor element Q side.

  The dummy wiring 64 of the wiring board 60 is bonded to the wiring board 70. The wiring substrate 70 includes an insulating substrate 71 and wirings formed on the front and back of the insulating substrate 71. A dummy wiring 72 that is not electrically connected to any terminal of the semiconductor module 10 is provided on the surface of the insulating substrate 71 on the semiconductor element Q side. A dummy wiring 73 that is not electrically connected to any terminal of the semiconductor module 10 is provided on the surface of the insulating substrate 71 opposite to the surface on the semiconductor element Q side.

  As described above, in the semiconductor module 10, the two-layer wiring board is provided on each of the upper surface side and the lower surface side of each semiconductor element Q. The drain wiring 22, the source wiring 23, the back wiring 26 and the source wiring 32 disposed on the lower surface side of each semiconductor element Q and the intermediate wiring 62 disposed on the upper surface side of each semiconductor element Q are opposed in parallel. The wiring boards 20, 30, 60 and 70 are arranged in parallel to each other.

  An annular frame 80 surrounding the outer periphery of each semiconductor element Q is provided between the wiring board 20 and the wiring board 60 that face each other with each semiconductor element Q interposed therebetween. A space defined by the wiring boards 20 and 60 and the frame body 80 is filled with a gel-like insulating resin 82 containing solid particles 81 having both high thermal conductivity and high insulation. That is, each semiconductor element Q is embedded in a gel-like insulating resin 82 containing solid particles 81. For example, diamond powder can be suitably used as the solid particles 81. The solid particles 81 are preferably a mixture of at least two types of particles having different particle sizes. When the solid particles 81 include a plurality of different particle sizes, the gap between the solid particles 81 dispersed in the insulating resin 82 can be reduced, and the content rate of the solid particles 81 can be increased. Thereby, since the contact area of the solid particles 81 increases, the heat generated from each semiconductor element Q can be efficiently released to the outside.

  Below, the structure of the wiring boards 20 and 30 provided in the lower surface side of each semiconductor element Q is demonstrated. 4A is a perspective view showing a state before the wiring board 20 and the wiring board 30 are bonded together, and FIG. 4B is a perspective view showing a state after the wiring board 20 and the wiring board 30 are bonded together.

  As shown in FIGS. 3A, 4A, and 4B, the wiring substrate 20 includes an insulating substrate 21 made of an insulator such as ceramic. On the surface of the insulating substrate 21 (the surface on the semiconductor element Q side), a drain wiring 22, a source wiring 23 and a gate wiring 24 made of a conductor having a relatively high conductivity and thermal conductivity such as copper are formed. . A drain terminal D1 is formed by pulling out the drain wiring 22 to the outside of the wiring board 20. That is, the drain terminal D1 is formed integrally with the drain wiring 22. Further, the gate terminal G <b> 2 is formed by pulling out the gate wiring 24 to the outside of the wiring substrate 20. That is, the gate terminal G2 is formed integrally with the gate wiring 24. In the present embodiment, the drawing direction of the gate terminal G2 is configured to be opposite to the drawing direction of the drain terminal D1. As shown in FIG. 2, the source wiring 23 is connected to a back surface wiring 26 formed on the back surface (surface opposite to the semiconductor element Q side) of the insulating substrate 21 through a through hole 25 provided in the insulating substrate 21. It is connected. The back surface wiring 26 is composed of the same conductor as the drain wiring 22, the source wiring 23, and the gate wiring 24 provided on the front surface side of the insulating substrate 21, and is provided so as to cover substantially the entire back surface of the insulating substrate 21. Yes. The conductors constituting the wirings on the front and back surfaces of the insulating substrate 21 are configured to have substantially the same thickness and the same area on the front and back of the insulating substrate 21. Thereby, the curvature of the insulated substrate 21 by the thermal expansion coefficient difference between the insulated substrate 21 and the conductor which comprises each wiring can be suppressed.

  On the other hand, as shown in FIG. 4A, the wiring substrate 30 has an insulating substrate 31 made of an insulator such as ceramic. On the surface of the insulating substrate 31 (the surface on the semiconductor element Q side), a source wiring 32 made of a conductor having a relatively high conductivity and thermal conductivity such as copper and covering substantially the entire surface is formed. A source terminal S2 and a control signal reference terminal SG2 are formed by drawing the source wiring 32 to the outside of the wiring board 30. That is, the source terminal S2 and the control signal reference terminal SG2 are formed integrally with the source line 32. In the present embodiment, as shown in FIG. 3A, the source terminal S2 is drawn out from two places, a position corresponding to the mounting position of the semiconductor element Q21 and a position corresponding to the mounting position of the semiconductor element Q22.

  Dummy wirings 33 (see FIG. 2) that are not electrically connected to any terminal of the semiconductor module 10 are formed on the back surface (the surface opposite to the semiconductor element Q side) of the insulating substrate 31. The dummy wiring 33 is configured by the same conductor as the source wiring 32 provided on the front surface side of the insulating substrate 31, and is provided so as to cover substantially the entire back surface of the insulating substrate 31. The conductors constituting the wirings on the front and back surfaces of the insulating substrate 31 are configured to have substantially the same thickness and the same area on the front and back of the insulating substrate 31. Thereby, the curvature of the insulated substrate 31 by the thermal expansion coefficient difference between the insulated substrate 31 and the conductor which comprises each wiring can be suppressed.

  Further, the thickness of the conductor in the wiring board 20 disposed on the side closer to each semiconductor element Q is larger than the thickness of the conductor in the wiring board 30 disposed on the side far from each semiconductor element Q. Thus, by making the conductor of the wiring board 20 disposed on the side closer to the semiconductor element Q, which is a heat generation source, thicker than the conductor of the wiring board 30 disposed on the side far from the semiconductor element Q, the heat dissipation path Thermal diffusion at the upstream side is promoted, and heat dissipation is improved.

  As shown in FIGS. 4A and 4B, the wiring board 20 and the wiring board 30 are bonded together so that the back surface wiring 26 of the wiring board 20 and the source wiring 32 of the wiring board 30 are in contact with each other. As shown in FIG. 4B, when the wiring board 20 and the wiring board 30 are bonded together, these terminals are drawn out in the same direction so that the drain terminal D1 and each of the two source terminals S2 are parallel to each other. It is. Further, these terminals are drawn out in the same direction so that the gate terminal G2 and the control signal reference terminal GS2 are parallel to each other.

  Below, the structure of the wiring boards 60 and 70 provided on the upper surface side of each semiconductor element Q will be described. FIG. 5A is a perspective view showing a state before the wiring board 60 and the wiring board 70 are bonded together, and FIG. 5B is a perspective view showing a state after the wiring board 60 and the wiring board 70 are bonded together.

  As shown in FIGS. 3B, 5A, and 5B, the wiring substrate 60 provided on the semiconductor element Q side includes an insulating substrate 61 made of an insulator such as ceramic. On the surface of the insulating substrate 61 (the surface on the semiconductor element Q side), an intermediate wiring 62 and a gate wiring 63 made of a conductor having a relatively high conductivity and thermal conductivity such as copper are formed. An intermediate terminal C and a control signal reference terminal SG1 are formed by pulling out the intermediate wiring 62 to the outside of the wiring board 60. That is, the intermediate terminal C and the control signal reference terminal SG1 are formed integrally with the intermediate wiring 62. In the present embodiment, the intermediate terminal C is drawn from two different locations of the intermediate wiring 62 so that the drawing directions are opposite to each other.

  On the other hand, the gate terminal G1 is formed by drawing the gate wiring 63 to the outside of the wiring substrate 60 via the back surface of the insulating substrate 61 (the surface opposite to the semiconductor element Q side). These terminals are drawn out in the same direction so that the gate terminal G1 and the control signal reference terminal GS1 are parallel to each other. On the back surface of the insulating substrate 61, a dummy wiring 64 (see FIG. 2) that is not electrically connected to any terminal of the semiconductor module 10 is formed in addition to the lead wiring of the gate wiring 63. The dummy wiring 64 is configured by the same conductor as the intermediate wiring 62 and the gate wiring 63 provided on the front surface side of the insulating substrate 61, and is provided so as to cover substantially the entire back surface of the insulating substrate 61. The conductors constituting the wirings on the front and back surfaces of the insulating substrate 61 are configured to have substantially the same thickness and the same area on the front and back of the insulating substrate 61. Thereby, the curvature of the insulated substrate 61 by the thermal expansion coefficient difference between the insulated substrate 61 and the conductor which comprises wiring can be suppressed.

  On the other hand, the wiring board 70 has an insulating substrate 71 made of an insulator such as ceramic as shown in FIG. 5A. Dummy wiring that is formed on the surface of the insulating substrate 71 (the surface on the semiconductor element Q side) by a conductor having a relatively high conductivity and thermal conductivity such as copper and is not electrically connected to any terminal of the semiconductor module 10 72 is formed. The dummy wiring 72 is a notch formed by cutting a conductor so that the dummy wiring 72 does not contact the lead-out wiring of the gate wiring 63 provided on the wiring board 60 when the wiring board 60 and the wiring board 70 are bonded together. Part 72a.

  A dummy wiring 73 that is not electrically connected to any terminal of the semiconductor module 10 is formed on the back surface of the insulating substrate 71 (the surface opposite to the semiconductor element Q side). The dummy wiring 73 is configured by the same conductor as the dummy wiring 72 provided on the front surface side of the insulating substrate 71, and is provided so as to cover substantially the entire back surface of the insulating substrate 71. The conductors constituting the wirings on the front and back surfaces of the insulating substrate 71 are configured to have substantially the same thickness and the same area on the front and back of the insulating substrate 71. Thereby, the curvature of the insulated substrate 71 by the thermal expansion coefficient difference between the insulated substrate 71 and the conductor which comprises wiring can be suppressed.

  Further, the thickness of the conductor in the wiring board 60 arranged on the side closer to each semiconductor element Q is thicker than the thickness of the conductor in the wiring board 70 arranged on the side far from the semiconductor element Q. Thus, by making the conductor of the wiring board 60 disposed on the side closer to the semiconductor element Q that is the heat source thicker than the conductor of the wiring board 70 disposed on the side far from the semiconductor element Q, the heat dissipation path Thermal diffusion at the upstream side is promoted, and heat dissipation is improved.

  As shown in FIGS. 5A and 5B, the wiring board 60 and the wiring board 70 are bonded together so that the dummy wiring 64 and the dummy wiring 72 are in contact with each other.

FIG. 6 is a perspective view showing the configuration of the semiconductor element Q. Each semiconductor element Q is on one side and a source electrode E _S and the gate electrode E _G, a drain electrode E _D on the other surface. In the following, a surface source electrode E _S and the gate electrode E _G is provided in the semiconductor device Q is denoted as the gate-source surface P1, it denoted a surface drain electrode E _D is provided with a drain surface P2. Gate electrode E _G is disposed at the center of the gate-source plane P1, the source electrode E _S is provided so as to extend in substantially the entire region of and the gate-source plane P1 surrounds the gate electrode E _G . Drain electrode E _D is provided so as to extend in substantially the entire region of the drain surface P2.

  7 shows a semiconductor element Q11, a drain surface side heat diffusion member 41 bonded to the drain surface P2 of the semiconductor element Q11, and a gate / source surface side heat diffusion member 42 bonded to the gate / source surface P1 of the semiconductor element Q11. It is a perspective view shown. 8A is a plan view showing the configuration of the gate / source surface side thermal diffusion member 42, and FIG. 8B is a cross-sectional view taken along line 8B-8B in FIG. 8A.

The drain surface side heat diffusing member 41 includes a conductor block 41a made of a conductor such as copper having a relatively high electrical conductivity and thermal conductivity. Drain electrode E _D of the semiconductor element Q11 is electrically and thermally connected to the conductor block 41a of the drain side heat diffusion member 41.

The gate / source surface side heat diffusing member 42 includes a conductor block 42a including a conductor such as copper having a relatively high conductivity and a relatively high heat conductivity, and a conductor pin 42b.
A through-hole 42d is provided in the central portion of the conductor block 42a so as to penetrate between the bonding surface with the semiconductor element Q and the bonding surface with the wiring substrate 60. The conductor pin 42b is a columnar body having a prismatic or columnar shape, and is inserted into the through hole 42d. One end of the conductor pin 42 b is exposed on the bonding surface with the semiconductor element, and the other end is exposed on the bonding surface with the wiring substrate 60. An insulating resin 42c is filled between the conductor pin 42b and the conductor block 42a, and the conductor pin 42b is insulated from the conductor block 42a. The source electrode E _S of the semiconductor element Q11 is electrically and thermally connected to the conductor block 42a of the gate-source side heat diffusion member 42. Gate electrode E _G of the semiconductor element Q11 is electrically and thermally connected to the conductive pin 42b of the gate-source side heat diffusion member 42. A recess 42e for avoiding contact between the gate wiring 63 of the wiring substrate 60 and the conductor block 42a is provided on the joint surface of the conductor block 42a with the wiring substrate 60.

  Similarly, in the semiconductor elements Q12, Q21, and Q22, the drain surface side heat diffusion member 41 is bonded to the drain surface P2, and the gate / source surface side heat diffusion member 42 is bonded to the gate / source surface P1.

As shown in FIG. 3A, the other surface of the drain surface side heat diffusing member 41 having one surface bonded to the drain surface P2 of the semiconductor elements Q11 and Q12 is electrically and thermally connected to the drain wiring 22 of the wiring board 20. It is connected to the. That is, the drain electrode E _D of the semiconductor element Q11 and Q12 are electrically and thermally connected to the drain wiring 22 of the wiring board 20 via a conductor block 41a of the drain side heat diffusion member 41.

  The other surface of the gate / source surface side thermal diffusion member 42 joined to the gate / source surface P1 of the semiconductor elements Q21 and Q22 is electrically and thermally connected to the source wiring 23 and the gate wiring 24 of the wiring substrate 20. Connected.

FIG. 9 is a cross-sectional view showing a connection state among the semiconductor element Q21 (Q22), the gate / source surface side thermal diffusion member 42, and the wiring board 20. The source electrode E _S of the semiconductor element Q21 (Q22) is electrically and thermally connected to the conductor block 42a of the gate-source side heat diffusion member 42, the gate electrode E _G is the gate-source side heat diffusion member It is electrically and thermally connected to 42 conductor pins 42b. The conductor block 42 a is electrically and thermally connected to the source wiring 23 of the wiring board 20, and the conductor pin 42 b is electrically and thermally connected to the gate wiring 24 of the wiring board 20. That is, the source electrode _{E S} of the semiconductor element Q21 (Q22) is electrically and thermally connected to the source line 23 via the conductor block 42a, the gate electrode _{E G} of the semiconductor element Q21 (Q22) is conductive pin 42b Is electrically and thermally connected to the gate wiring 24 via

  As shown in FIG. 3B, the other surface of the gate / source surface side thermal diffusion member 42, one surface of which is joined to the gate / source surface P1 of the semiconductor elements Q11 and Q12, is the intermediate wiring 62 and the gate of the wiring substrate 60. The wiring 63 is electrically and thermally connected.

The connection state among the semiconductor elements Q11 and Q12, the gate / source surface side thermal diffusion member 42, and the wiring board 60 is the same as that shown in FIG. That is, the source electrode E _S of the semiconductor elements Q11 and Q12 are electrically and thermally connected to the intermediate wire 62 of the wiring board 60 via a conductor block 42a of the gate-source side heat diffusion member 42, the semiconductor element Q11 and the gate electrode E _G of Q12 is electrically and thermally connected to the gate wiring 63 of the wiring board 60 through the conductive pin 42b of the gate-source side heat diffusion member 42.

The other surface of the drain surface side heat diffusing member 41 whose one surface is joined to the drain surface P2 of the semiconductor elements Q21 and Q22 is electrically and thermally connected to the intermediate wiring 62 of the wiring substrate 60. That is, the drain electrode E _D of the semiconductor element Q21 and Q22 are electrically and thermally connected to the intermediate wire 62 of the wiring board 60 via a conductor block 41a of the drain side heat diffusion member 41.

The semiconductor elements Q11 and Q12 are connected in parallel by the drain wiring 22 of the wiring board 20 and the intermediate wiring 62 of the wiring board 60, and the semiconductor elements Q21 and Q22 are the source wiring 23 of the wiring board 20 and the intermediate wiring of the wiring board 60. 62 are connected in parallel. The source electrode _{E S} of the semiconductor elements Q11 and Q12 has a drain electrode _{E D} of the semiconductor element Q21 and Q22, are electrically connected by the intermediate wiring 62.

  As shown in FIGS. 3A and 3B, the outer shape of the wiring substrate 20 (insulating substrate 21) and the wiring substrate 60 (insulating substrate 61) is substantially square, and the semiconductor elements Q11, Q12, Q21, and Q22 Between the board | substrate 20 and the wiring board 60, it arrange | positions so that it may become point symmetrical with respect to the center point of these wiring boards. Thus, by arranging the semiconductor elements Q11, Q12, Q21, and Q22 so as to be point-symmetric with respect to the center points of the wiring boards 20 and 60, the pressing force that acts to press each semiconductor element Q from both sides is provided. Can be made uniform among the semiconductor elements, and the reliability of the semiconductor module 10 can be improved.

  FIG. 10 is a perspective view showing the appearance of the semiconductor module 10. The semiconductor module 10 is obtained by joining a drain surface side heat diffusion member 41 or a gate / source surface side heat diffusion member 42 to the upper surface and the lower surface of each semiconductor element Q, and a wiring substrate 60 and a wiring substrate 60 composed of the wiring substrates 20 and 30. And 70 are sandwiched between the laminated substrates.

  FIG. 11 is a cross-sectional view showing a heat dissipation path in the semiconductor module 10. In FIG. 11, the main direction of heat release is indicated by arrows. As shown in FIG. 11, the semiconductor module 10 can be used with the heat sink 110 attached to the upper surface side and the lower surface side. The heat generated from each semiconductor element Q is transferred to the upper surface side through the drain surface side heat diffusion member 41 or the gate / source surface side heat diffusion member 42 bonded to the upper surface of each semiconductor element Q and the wiring substrates 60 and 70. The heat sink 110 is discharged to the heat sink 110 and is also transferred to the heat sink 110 on the lower surface side through the drain surface side heat diffusion member 41 or the gate / source surface side heat diffusion member 42 bonded to the lower surface of each semiconductor element Q and the wiring substrates 20 and 30. Released. As described above, according to the semiconductor module 10 according to the present embodiment, since each of the semiconductor elements Q has the heat dissipation path on the upper surface side and the lower surface side, the heat dissipation performance as compared with the conventional package having the heat dissipation path only on one side. Can be improved.

In the semiconductor module 10 according to this embodiment, the gate-source side heat diffusion member 42 which is joined to the gate-source surface P1 of the semiconductor device Q is in contact with the gate electrode E _G of the semiconductor device Q having a conductive pin 42b which is insulated from the conductor block 42a which is brought into contact with the source electrode E _S of the semiconductor elements Q moiety. In this way, by providing the gate / source surface side thermal diffusion member 42 with the gate connection conductor pin 42b, wire bonding to each semiconductor element Q becomes unnecessary, and the manufacturing process can be simplified. Further, since wire bonding is not necessary, the entire gate / source surface P1 of the semiconductor element Q can be bonded to the thermal diffusion member 42. That is, if in the case where wire bonding for gate electrode E _G is required, can not be brought into contact with the heat diffusion member around the wire bonding portion of the gate-source surface P1 of the semiconductor device Q. As a result, the bonding area between the semiconductor element Q and the heat diffusing member is limited, and heat dissipation is reduced. According to the semiconductor module 10 according to this embodiment, by providing the conductive pin 42b for gate connected to the gate-source side heat diffusion member 42, the wire bonding for gate electrode E _G becomes unnecessary, the semiconductor element It is possible to join the entire gate / source surface P1 of Q to the gate / source surface side thermal diffusion member 42. Thus, according to the semiconductor module according to the present embodiment, higher heat dissipation performance can be obtained than the conventional package having the double-sided heat sink structure.

  In the semiconductor module 10 according to the present embodiment, the thickness of the conductor in the wiring board 20 disposed on the side closer to the semiconductor element Q on the lower surface side of the semiconductor element Q is disposed on the side far from the semiconductor element Q. The wiring board 30 is thicker than the conductor. Similarly, on the upper surface side of the semiconductor element Q, the thickness of the conductor in the wiring board 60 arranged on the side closer to the semiconductor element Q is larger than the thickness of the conductor in the wiring board 70 arranged on the side far from the semiconductor element Q. It is thick. In this way, by making the conductors of the wiring boards 20 and 60 arranged on the side closer to the semiconductor element Q, which is a heat source, thicker than the conductors of the wiring boards 30 and 70 arranged on the side far from the semiconductor element Q, The heat diffusion on the upstream side of the heat dissipation path is promoted, and the heat dissipation is improved.

FIG. 12 is a cross-sectional view showing the direction of the current I flowing through the semiconductor module 10 when each semiconductor element Q is in a conducting state according to the control signal. In the semiconductor module 10, for example, the positive terminal of the power source is connected to the drain terminal D 1 connected to the drain wiring 22, and the negative terminal of the power source is connected to the source terminal S 2 connected to the source wiring 23 on the wiring substrate 20. In this case, when the semiconductor elements Q is turned on, current I flows from the drain terminal D1 to the drain wiring 22, an input to the drain electrode E _D of the semiconductor element Q11 and Q12 through the drain side heat diffusion member 41 Is done. Current I is output from the source electrode E _S of the semiconductor elements Q11 and Q12, it flows into the intermediate wiring 62 of the wiring board 60 via a gate-source side heat diffusion member 42. Then, current I is input to the drain electrode E _D of the semiconductor element Q21 and Q22 through the drain side heat diffusion member 41, is output from the source electrode E _S. The current I output from the semiconductor elements Q21 and Q22 is output from the source terminal S2 via the source wiring 23 of the wiring board 20, the through hole 25, and the source wiring 32 of the wiring board 30.

  When the semiconductor module 10 is used for an inverter, each semiconductor element Q is repeatedly turned on and off at high speed. Therefore, if the wiring inductance on the current path is large, an overvoltage due to overshoot occurs. Therefore, it is preferable to reduce the wiring inductance and suppress the occurrence of overvoltage.

  According to the configuration of the semiconductor module 10 according to the present embodiment, as shown in FIG. 12, the current flowing through the upper surface side of each semiconductor element Q and the current flowing through the lower surface side of each semiconductor element Q flow in opposite directions. That is, the direction of the current flowing through the intermediate wiring 62 provided on the upper surface side of the semiconductor element Q is opposite to the direction of the current flowing through the source wirings 23 and 32 disposed opposite to the intermediate wiring 62. Thus, the magnetic field generated by the current flowing through the intermediate wiring 62 and the magnetic field generated by the current flowing through the source wirings 23 and 32 act so as to cancel each other, so that the drain terminal D1 and the current output terminal, which are current input terminals. The wiring inductance inside the package viewed from the source terminal S2 can be reduced. Thereby, it is possible to suppress overvoltage due to overshoot when each semiconductor element Q is turned on and off at high speed.

  FIG. 13 is a plan view showing a configuration example when the semiconductor module 10 is used as an inverter. When the semiconductor module 10 is used as an inverter, the number of semiconductor modules 10 corresponding to the load configuration is used. FIG. 13 illustrates the case where two semiconductor modules 10 are used. The two semiconductor modules 10 are juxtaposed in the plane direction as shown in FIG. A P bus 121 connected to the positive electrode of a DC power source (not shown) is connected to the drain terminal D1 of each semiconductor module 10, and an N bus 122 connected to the negative electrode of the DC power source is a source terminal S2 of each semiconductor module 10. Connected to. The gate terminals G 1 and G 2 and the control signal reference terminals GS 1 and GS 2 are connected to a gate substrate 123 provided for each semiconductor module 10. A control signal is supplied via the gate substrate 123 between the gate terminal G1 and the control signal reference terminal GS1, and between the gate terminal G2 and the control signal reference terminal GS2, thereby controlling on / off of each semiconductor element Q. Is done.

  Load wires 124 and 125 connected to a load (not shown) such as a motor are connected to the intermediate terminal C of each semiconductor module 10. For example, a load line 124 corresponding to the U phase is connected to the intermediate terminal C of the semiconductor module 10 on the left side in the figure, and a load line 125 corresponding to the V phase is connected to the intermediate terminal C of the semiconductor module 10 on the right side in the figure. Has been. In the semiconductor module 10 according to the present embodiment, since the intermediate terminal C is drawn in the opposite direction from the two opposite sides of the wiring board 60, the load lines 124 and 125 are collected between the two semiconductor modules 10. Can be made. This facilitates routing of the load lines 124 and 125.

  FIG. 14 is a side view of the drain terminal D1 and the source terminal S2 of the semiconductor module as seen from the direction of the arrow X in FIG. The source terminal S2 and the drain terminal D1 are drawn from the same side of the semiconductor module 10 in the same direction. Further, the lead length of the source terminal S2 is longer than the lead length of the drain terminal D1. Furthermore, the drain terminal D1 and the source terminal S2 are bent upward in a direction perpendicular to the main surface of the wiring boards 20 and 30 from a drawing direction parallel to the main surfaces of the wiring boards 20 and 30, respectively. The bending direction of the drain terminal D1 and the source terminal S2 may be downward in the vertical direction with respect to the main surfaces of the wiring boards 20 and 30. Further, the bending angle may not be strictly perpendicular, and may be approximately upward or downward with respect to the main surfaces of the wiring boards 20 and 30. By configuring the drain terminal D1 and the source terminal S2 in this way, as shown in FIG. 13, the P bus 121 and the N bus 122 can be arranged linearly, and the P bus 121 and the N bus 122 are arranged. Is easy to route. Further, the P bus 121 and the N bus 122 can be arranged in parallel and close to each other. Thereby, the direction of the current flowing in the P bus 121 and the direction of the current flowing in the N bus 122 can be reversed, and the magnetic field generated by the current flowing in the P bus 121 and the magnetic field generated by the current flowing in the N bus 122 Can be made to cancel each other. Thereby, the wiring inductance of the P bus 121 and the N bus 122 viewed from the drain terminal D1 and the source terminal S2 can be reduced, and overvoltage due to overshoot when the semiconductor element Q is turned on / off at high speed can be suppressed. .

  In the present embodiment, a case where a so-called 2-in-1 configuration is formed using four semiconductor elements Q11, Q12, Q21, and Q22 is illustrated, but a 2-in-1 configuration using two semiconductor elements connected in series may be used.

  In this embodiment, two wiring boards are provided on the upper surface side and the lower surface side of each semiconductor element Q. However, one wiring board may be provided on the upper surface side and the lower surface side of each semiconductor element Q. . In this case, the source terminal S2 is pulled out from the back surface wiring 26 of the wiring board 20, and the wiring board 30 is abolished. Since only the dummy wirings 72 and 73 are provided on the wiring board 70, the wiring board 70 can be omitted. The patterning of the wiring is easier if the source terminal S2 is drawn from a wiring board 30 different from the wiring board 20, rather than the source terminal S2 is drawn from the back surface wiring 26 of the wiring board 20. For this reason, in this embodiment, the wiring board on the lower surface side of the semiconductor element Q has a two-layer structure. The reason why the wiring substrate on the upper surface side of the semiconductor element Q has a two-layer configuration is to match the configuration of the wiring substrate on the lower surface side. Thereby, the heat dissipation performance on the upper surface side and the lower surface side of the semiconductor element Q can be made uniform.

The semiconductor element Q is an example of the semiconductor element and other semiconductor elements in the present invention. Drain electrode E _D is an example of a first electrode in the present invention. The source electrode E _S is an example of a second electrode in the present invention. Gate electrode E _G is an example of a control electrode in the present invention. The drain surface side heat diffusion member 41 is an example of the first heat diffusion member in the present invention. The gate / source surface side thermal diffusion member 42 is an example of a second thermal diffusion member in the present invention. The conductor block 42a is an example of the first conductor portion of the second heat diffusing member in the present invention. The conductor pin 42b is an example of the first conductor portion of the second heat diffusing member in the present invention. The wiring boards 20 and 30 are examples of the first wiring board in the present invention. The drain wiring 22 is an example of a first wiring in the present invention. The wiring boards 60 and 70 are examples of the second wiring board in the present invention. The intermediate wiring 62 is an example of a second wiring in the present invention. The gate wiring 63 is an example of a third wiring in the present invention. The drain terminal D1 is an example of the first terminal in the present invention. The source terminal S2 is an example of a second terminal in the present invention.

[Second Embodiment]
FIG. 15 is a cross-sectional view showing the configuration of the semiconductor module 11 according to the second embodiment of the present invention. In FIG. 15, the same or corresponding components as those of the semiconductor module 10 according to the first embodiment described above are denoted by the same reference numerals, and redundant description is omitted.

  In the semiconductor module 10 according to the first embodiment described above, four semiconductor elements Q11, Q12, Q21, and Q22 are provided in a package to form a series circuit. On the other hand, the semiconductor module 11 according to the second embodiment is configured to include a single semiconductor element Q11. In the semiconductor module 10 according to the first embodiment, two wiring boards are provided on each of the upper surface side and the lower surface side of the semiconductor element Q. However, in the semiconductor module 11 according to the second embodiment, the semiconductor element Q is provided. One wiring board is provided on the upper surface side and the lower surface side.

Drain surface P2 of the semiconductor element Q11 is joined to the drain side heat diffusion member 41, electricity to the drain wiring 22 of the wiring board 20 drain electrode E _D via the conductor block 41a of the drain side heat diffusion member 41 Connected. A drain terminal D <b> 1 that is a current input terminal is drawn from the drain wiring 22. The gate-source surface P1 of the semiconductor element Q11 is joined to the gate-source side heat diffusion member 42 is electrically connected to the source wiring 66 of the wiring board 60 source electrode E _S via the conductor block 42a and has a gate electrode E _G is electrically connected to the gate wiring 63 of the wiring board 60 through the conductive pin 42b. A source terminal S 1 that is a current output terminal is connected to the source wiring 66. The drain terminal D1 and the source terminal S1 are drawn from the same side of the semiconductor module 11 in the same direction.

  Dummy wirings 27 and 67 are provided on the back side of the insulating substrate 21 and the insulating substrate 61 (on the side opposite to the semiconductor element Q11 side), respectively. The conductors constituting the wirings on the front and back surfaces of the insulating substrate 21 are configured to have substantially the same thickness and the same area on the front and back of the insulating substrate 21. Thereby, the curvature of the insulated substrate 21 by the thermal expansion coefficient difference between the insulated substrate 21 and a conductor can be suppressed. Similarly, the conductors constituting the respective wirings on the front and back surfaces of the insulating substrate 61 are configured to have substantially the same thickness and substantially the same area on the front and back of the insulating substrate 61. Thereby, the curvature of the insulated substrate 61 by the thermal expansion coefficient difference between the insulated substrate 61 and a conductor can be suppressed.

  FIG. 15 shows the direction of the current I flowing through the semiconductor module 11 when the semiconductor element Q11 is in a conducting state according to the control signal. According to the semiconductor module 11 according to the second embodiment, the current flowing through the source wiring 66 on the upper surface side of the semiconductor element Q11 and the drain wiring 22 on the lower surface side of the semiconductor element Q11 are the same as in the first embodiment. The flowing current is opposite and flows in the opposite direction. As a result, the magnetic field generated by the current flowing through the source wiring 66 and the magnetic field generated by the current flowing through the drain wiring 22 act so as to cancel each other, thereby reducing the wiring inductance inside the package as viewed from the drain terminal D1 and the source terminal S1. can do. Thereby, overvoltage due to overshoot when the semiconductor element Q11 is turned on and off at high speed can be suppressed.

  Further, the drain surface side heat diffusion member 41 is joined to the drain surface P2 of the semiconductor element Q11, and the gate / source surface side heat diffusion member 42 is joined to the gate / source surface P1 of the semiconductor element Q11. As a result, as in the case of the first embodiment, heat generated from the semiconductor element Q11 can be released from both sides of the semiconductor element Q11.

[Third Embodiment]
FIG. 16 is a diagram showing a configuration of a semiconductor switch 200 according to the third embodiment of the present invention configured to include a plurality of semiconductor modules 10. The plurality of semiconductor modules 10 are stacked along a direction perpendicular to the gate / source surface P1 and the drain surface P2 of the semiconductor element Q with the heat sink 210 interposed therebetween. That is, the plurality of semiconductor modules 10 are stacked along the direction of the heat dissipation path formed inside (the direction of the arrow shown in FIG. 11). In addition, it is preferable to attach the heat sink 210 also to the upper surface of the uppermost semiconductor module. For example, an air-cooled or water-cooled heater can be used as the heat sink 210. The lower surface of the lowermost semiconductor module 10 is in contact with the surface of a base 220 made of a member having high thermal conductivity.

  Each of the plurality of semiconductor modules 10 is arranged such that the drain terminal D1 and the source terminal S2 face the same direction. In this case, the gate terminals G1 and G2 and the control signal reference terminals GS1 and GS2 of the plurality of semiconductor modules 10 face in the opposite direction to the drain terminal D1 and the source terminal S2.

  In the semiconductor switch 200, the plurality of semiconductor modules 10 are connected in series. That is, the drain terminal D1 of the semiconductor module 10 arranged at the uppermost stage is connected to the high-voltage line HV of the current path, and the source terminal S2 is connected to the drain terminal D1 of the second-stage semiconductor module. Similarly, the source terminal S2 of each semiconductor module 10 is connected to the drain terminal D1 of the semiconductor module 10 one level lower. The source terminal S2 of the lowermost semiconductor module 10 is connected to the low-voltage line LV of the current path via the return conductor 230.

  The gate terminals G1 and G2 and the control signal reference terminals GS1 and GS2 of the plurality of semiconductor modules 10 are connected to separate control circuits 241 to 246 provided corresponding to each of the semiconductor modules 10. Each semiconductor element Q of the plurality of semiconductor modules 10 is turned on / off in accordance with a control signal supplied from the control circuits 241 to 246 corresponding to the semiconductor element Q. When a plurality of semiconductor modules 10 are used as semiconductor switches, all the semiconductor elements Q in the plurality of semiconductor modules 10 are normally turned on / off at the same timing. By connecting a plurality of semiconductor modules 10 in series, the voltage applied to each semiconductor element Q is reduced, so that a high-breakdown-voltage semiconductor switch can be configured. FIG. 16 shows an example in which six semiconductor modules 10 are connected in series, but the number of semiconductor modules 10 constituting the semiconductor switch 200 may be appropriately increased or decreased according to the required withstand voltage. Is possible. In the present embodiment, the semiconductor switch 200 is configured using the semiconductor module 10 according to the first embodiment, but the semiconductor module 11 according to the second embodiment can also be used.

  According to the semiconductor switch 200 according to the present embodiment, the plurality of semiconductor modules 10 are stacked along the direction of the heat dissipation path formed inside the semiconductor module 10 with the heat sink 210 interposed therebetween, which is efficient. It is possible to achieve heat dissipation and increase the breakdown voltage of the semiconductor switch. Further, by stacking a plurality of semiconductor modules 10, the size in the surface direction of the device can be reduced.

  In addition, since the drain terminal D1 and the source terminal S2 are drawn out to the same side of the semiconductor module 10 and these terminals are arranged in the stacking direction of the semiconductor module 10, wiring for connecting the stacked semiconductor modules in series is provided. Is easy to route. That is, as shown in FIG. 16, when a plurality of semiconductor modules 10 are stacked, the source terminal S2 of the upper semiconductor module 10 and the drain terminal D1 of the lower semiconductor module 10 are disposed adjacent to each other. These wiring connections are easy.

[Fourth Embodiment]
FIG. 17 is a diagram showing a configuration of a semiconductor switch 201 according to the fourth embodiment of the present invention configured to include a plurality of semiconductor modules 10. In FIG. 17, the same reference numerals are given to the same or corresponding components as those of the semiconductor switch 200 shown in FIG. In FIG. 17, the control circuits 241 to 246 in FIG. 16 are not shown.

  In the semiconductor switch 201 according to the fourth embodiment, a plurality of series units 251, 252, and 253 are configured. The configuration of each of the series units 251, 252, 253 is equivalent to the semiconductor switch 200 according to the third embodiment described above. That is, each of the series units 251, 252, and 253 is configured by stacking a plurality of semiconductor modules 10 with the heat sink 210 interposed therebetween and connecting the semiconductor elements Q of the plurality of semiconductor modules in series. Yes.

  Each stage of the semiconductor module 10 constituting the series units 251, 252, and 253 is connected in parallel to each of the corresponding stages of the semiconductor modules 10 constituting the other series units. For example, the uppermost semiconductor module 10 of the series unit 251 is connected in parallel to the uppermost semiconductor module 10 of the series unit 252 and is connected in parallel to the uppermost semiconductor module 10 of the series unit 253. Similarly, the second-stage semiconductor module 10 of the series unit 251 is connected in parallel to the second-stage semiconductor module 10 of the series unit 252 and connected in parallel to the second-stage semiconductor module 10 of the series unit 253. Yes.

  FIG. 18 is an equivalent circuit diagram of the semiconductor switch 201 according to the present embodiment. In the semiconductor switch 201 according to the present embodiment, the plurality of semiconductor modules form a matrix array. Thus, by forming a matrix array, a semiconductor switch having a high breakdown voltage and a large current capacity can be realized. In the present embodiment, a case where a 6 × 3 matrix array is configured is illustrated, but the present invention is not limited to this, and can be appropriately changed according to required withstand voltage and current capacity. It is. In the present embodiment, the semiconductor switch 201 is configured using the semiconductor module 10 according to the first embodiment, but the semiconductor module 11 according to the second embodiment can also be used.

10, 11 Semiconductor module 20, 30, 60, 70 Wiring board 22 Drain wiring 23 Source wiring 41 Drain surface side heat diffusion member 42 Gate / source surface side heat diffusion member 42a Conductor block 42b Conductor pin 62 Intermediate wiring 63 Gate wiring 63
81 solid particles 82 insulating resin 200, 201 semiconductor switch C intermediate terminals D1 drain terminal S2 source terminal Q11, Q12, Q21, Q22 semiconductor element _{E D} drain electrode _{E S} source electrode _{E G} gate electrode _{P 1} gate-source surface _{P 2} drain surface

Claims (15)

The first surface has a first electrode, the second surface opposite to the first surface has a second electrode and a control electrode, and corresponds to a control signal supplied to the control electrode A semiconductor element that conducts between the first electrode and the second electrode;
A first heat diffusion member having a conductor portion joined to the first surface of the semiconductor element and electrically connected to the first electrode;
A first conductor portion joined to the second surface of the semiconductor element and electrically connected to the second electrode and insulated from the first conductor portion and electrically connected to the control electrode A second heat diffusion member having a second conductor portion;
A wiring board having at least one layer bonded to a surface of the first heat diffusing member opposite to a surface to be bonded to the semiconductor element, and electrically connected to the conductor portion of the first heat diffusing member; A first wiring board having a connected first wiring;
A wiring board having at least one layer bonded to a surface of the second heat diffusing member opposite to a surface to be bonded to the semiconductor element, wherein the second heat diffusing member is formed on the first conductor portion of the second heat diffusing member; A second wiring board having a second wiring electrically connected and a third wiring electrically connected to the second conductor portion of the second heat diffusion member;
Including semiconductor modules. The first conductor portion of the second heat diffusing member has a through-hole penetrating between a bonding surface with the semiconductor element and a bonding surface with the second wiring board,
The second conductor portion of the second heat diffusing member is provided in the through-hole, one end portion is exposed on the joint surface with the semiconductor element, and the other end portion is the second wiring. The semiconductor module according to claim 1, wherein the semiconductor module is a columnar body exposed on a joint surface with a substrate. The first wiring board includes a wiring portion that faces the second wiring and through which a current in a direction opposite to a direction of a current flowing through the second wiring flows when the semiconductor element is conducted. Or the semiconductor module of Claim 2. Including at least one other semiconductor element provided between the first wiring board and the second wiring board and electrically connected to the semiconductor element;
The other semiconductor element includes the heat diffusion member bonded to one surface and the heat diffusion member bonded to the other surface, and the wiring portion of the first wiring substrate and the second wiring substrate. The semiconductor module according to claim 3, wherein the semiconductor module is electrically connected to the second wiring. The semiconductor element is a transistor,
The semiconductor module according to claim 4, wherein the other semiconductor element includes a transistor connected in series to the semiconductor element via the second wiring. The semiconductor module according to claim 5, wherein two terminals connected to the second wiring are led out in opposite directions from the second wiring board. The plurality of semiconductor elements including the semiconductor element and the other semiconductor elements are arranged so as to be point-symmetric with respect to the center points of the first wiring board and the second wiring board. 7. The semiconductor module according to any one of items 6. 8. The semiconductor according to claim 1, wherein each of the first wiring board and the second wiring board has a wiring made of a conductor having substantially the same thickness and the same area on both surfaces. module. Each of the first wiring board and the second wiring board is constituted by a two-layer wiring board, and the wiring of the wiring board disposed on the side closer to the semiconductor element of the two-layer wiring board The thickness of the conductor to form is thicker than the thickness of the conductor which forms the wiring of the wiring board arrange | positioned in the side far from the said semiconductor element among the said two layers of wiring boards. 2. The semiconductor module according to item 1. 10. The gel-like resin containing solid particles having thermal conductivity and insulating properties is filled between the first wiring board and the second wiring board. The semiconductor module according to item. The semiconductor module according to claim 10, wherein the solid particles are diamond powder. The semiconductor module according to claim 10 or 11, wherein the solid particles include at least two types of particles having different particle sizes. A first terminal and a second terminal for supplying power to a plurality of semiconductor elements including the semiconductor element and the at least one other semiconductor element;
The first terminal and the second terminal are drawn out from the first wiring board or the second wiring board in different directions in the same direction, and the first wiring board and the second terminal The semiconductor module according to claim 5, wherein the semiconductor module is bent in a direction intersecting with a main surface of the wiring board. A plurality of the semiconductor modules according to any one of claims 1 to 13, wherein the plurality of semiconductor modules are stacked with a heat sink interposed therebetween, and the semiconductor elements of each of the plurality of semiconductor modules are connected in series. A semiconductor switch that includes a series unit configured to be connected. Corresponding to each of the plurality of semiconductor modules constituting each series unit, comprising the plurality of series units, and each of the plurality of semiconductor modules constituting each series unit corresponding to another series unit so that the plurality of semiconductor modules constituting the plurality of series units form a matrix array. The semiconductor switch according to claim 14, wherein the semiconductor switch is configured to be connected in parallel to each of the semiconductor modules.