JP2015225474A - Information processing device and timer setting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the execution speed of an application program from decreasing due to processing for setting a hardware timer.SOLUTION: An information processing device 1 includes: a first processor 12 that executes an application program 11; a second processor 14; a memory 13; and a hardware timer 15 that generates an interrupt at a set time. The first processor stores information on a first received from a process of the application program, to the memory; and changes identification information that is stored in the memory, to information indicating that hardware setting is required. The second processor monitors the identification information and, if the identification information is changed to the information indicating that the hardware timer setting is required, reads the information on the first time from the memory; and performs setting of the hardware timer on the basis of the information on the first time.

Description

  The present invention relates to a hardware timer setting technique for generating an interrupt at a set time.

  Hardware that generates an interrupt at a set time is called a hardware timer. The time setting for the hardware timer is performed by, for example, issuing a system call for the application program process to use the timer function, and the OS (Operating System) setting the comparator value of the hardware timer.

  The process of setting the hardware timer takes time because it includes a process in which a CPU (Central Processing Unit) accesses a low-speed I / O (Input / Output) chipset. If it takes time to set the hardware timer, the timing at which the CPU executing the application program returns from the system call is delayed, and the execution speed of the application program decreases. This becomes a problem particularly when the application program should be executed at high speed. The prior art does not pay attention to such a problem.

JP 2012-48379 A

  Accordingly, an object of the present invention, in one aspect, is to provide a technique for suppressing a decrease in the execution speed of an application program due to processing for setting a hardware timer.

  An information processing apparatus according to the present invention includes a first processor that executes an application program, a second processor, a memory, and hardware that generates an interrupt at a set time. The first processor stores information on the first time received from the process of the application program in the memory, and changes the identification information stored in the memory to information indicating that a hardware timer setting is required. The second processor monitors the identification information. When the identification information is changed to information indicating that the hardware timer setting is required, the second processor reads the first time information from the memory. Set the hardware timer based on the information.

  In one aspect, it is possible to suppress a decrease in the execution speed of the application program due to the process of setting the hardware timer.

FIG. 1 is a diagram showing a system outline of the present embodiment. FIG. 2 is a diagram illustrating a structure of data stored in the queue. FIG. 3 is a diagram illustrating a processing flow of processing executed by the reception unit. FIG. 4 is a diagram illustrating a processing flow of processing executed by the setting thread. FIG. 5 is a diagram illustrating a processing flow of processing executed by the interrupt handler. FIG. 6 is a diagram for comparing the present embodiment with the case where a single CPU is used.

  FIG. 1 shows the configuration of the information processing apparatus 1 in the present embodiment. The information processing apparatus 1 includes a CPU 12, a memory 13, a CPU 14, and a hardware timer 15.

  For example, the CPU 12 executes an application program stored in a hard disk drive (HDD) or the like and a program of the OS 10 to realize a process 11 of the application program and a receiving unit 101 (for example, a thread) in the OS 10. . The memory 13 includes an area for storing the flag 131 and an area for the queue 132. The CPU 14 implements a setting thread 102 and an interrupt handler 103 in the OS 10 by executing a program of the OS 10 stored in, for example, a hard disk drive. The hardware timer 15 is, for example, a hardware timer (for example, a high precision event timer (HPET)) having a microsecond precision. For example, the hardware timer 15 is incorporated in a low-speed I / O chip set as compared with the CPUs 12 and 14.

  The process 11 of the application program issues a system call for using the timer function. The accepting unit 101 performs processing based on the accepted system call, stores the processing result in the queue 132, and updates the flag 131. When the flag 131 is updated, the setting thread 102 sets the hardware timer 15 based on the data stored in the queue 132 (that is, sets the timer). The hardware timer 15 generates an interrupt at a set time (in the present embodiment, when the comparator value and the counter value match). When called by an interrupt from the hardware timer 15, the interrupt handler 103 executes processing based on the data stored in the queue 132.

  FIG. 2 shows the structure of data stored in the queue 132. The data stored in the queue 132 has a linked data structure. The pointer 201 points to data to be processed first (data 202 in the example of FIG. 2). Each data includes expiration time information and expiration processing information. Each data is added with a pointer indicating data to be processed next. The expiration time is a timeout time of the hardware timer 15, and the expiration process is a process to be executed by the interrupt handler 103 when the expiration time is reached. Data with an earlier expiration time is processed earlier. Therefore, in the example of FIG. 2, the expiration time A is earlier than the expiration time B, and the expiration time B is earlier than the expiration time C.

  Next, the operation of the information processing apparatus 1 will be described with reference to FIGS. First, processing executed by the receiving unit 101 will be described with reference to FIG.

  First, the process 11 of the application program issues a system call for using the timer function. The accepting unit 101 accepts a system call from the process 11 of the application program (FIG. 3: step S1).

  The receiving unit 101 generates data including expiration time information and expiration processing information based on the system call received from the application program process 11 (step S3).

  The receiving unit 101 stores the data generated in step S3 in the queue 132 according to the expiration time information included in the data (step S5). In step S5, the pointer is reset for the data stored in the queue 132 so that data with an earlier expiration time is processed earlier.

  The accepting unit 101 determines whether the earliest expiration time among the expiration times for the data stored in the queue 132 has been changed by the process of step S5 (step S7). That is, it is determined whether the expiration time for the data stored in step S5 is the earliest expiration time.

  If the earliest expiration time has not changed (step S7: No route), the hardware timer 15 need not be set, and the process is terminated. On the other hand, when the earliest expiration time changes (step S7: Yes route), the hardware timer 15 should be set. Accordingly, the accepting unit 101 updates the flag 131 stored in the memory 13 (step S9). In step S9, for example, the value of the flag (0 or 1) is inverted. Then, the process ends. Here, the CPU 12 returns from the system call.

  By updating the flag as described above, it is possible to notify the CPU 14 that the hardware timer 15 should be set. When the above processing is completed, the CPU 12 returns from the system call and can execute the application program. Therefore, it becomes possible to eliminate the bottleneck and prevent the execution speed of the application program from decreasing.

  Next, processing executed by the setting thread 102 will be described with reference to FIG.

  First, the setting thread 102 determines whether or not the flag 131 in the memory 13 has been updated (FIG. 4: step S11). If the flag 131 has not been updated (step S11: No route), the hardware timer 15 need not be set, and the process proceeds to step S23.

  On the other hand, when the flag 131 is updated (step S11: Yes route), the setting thread 102 sets the hardware timer 15, so that the setting thread 102 determines the first data in the queue 132 (that is, the data with the earliest expiration time). The remaining time until the expiration time is calculated (step S13). In step S13, the remaining time is the time from the current time acquired from the system clock or the like to the expiration time.

  The setting thread 102 converts the remaining time calculated in step S13 into a value to be added to the counter value of the hardware timer 15 (step S15).

  The setting thread 102 acquires the counter value of the hardware timer 15 from the hardware timer 15 (step S17). Then, the setting thread 102 calculates the value to be set as the comparator value of the hardware timer 15 by adding the value after the conversion in the process of step S15 to the counter value acquired from the hardware timer 15 (step S19). ).

  The setting thread 102 sets the value calculated in step S19 as the comparator value of the hardware timer 15 (step S21).

  The setting thread 102 issues a monitoring command (step S23) and registers the address of the flag 131 in the memory 13. The monitoring instruction is, for example, a monitoring instruction in the Intel 64 architecture.

  The setting thread 102 checks with the process scheduler whether there is a reschedule request (step S25). A reschedule request is a request issued when another thread or the like is in a state to operate. The process scheduler assigns CPU usage rights.

  When there is a reschedule request (step S25: Yes route), the setting thread 102 transfers the usage right of the CPU 14 from the setting thread 102 to another thread or the like to the process scheduler (step S27). This prevents the setting thread 102 from occupying the CPU 14.

  When the use of the CPU 14 by another thread or the like is completed, the setting thread 102 acquires the right to use the CPU 14 (step S29). Then, the process returns to step S11.

  On the other hand, when there is no reschedule request (step S25: No route), the setting thread 102 issues a CPU standby instruction (step S31). The CPU wait instruction is, for example, an mwait instruction in the Intel 64 architecture. In response to the CPU standby instruction, the setting thread 102 waits until there is any access to the registered address (that is, the setting thread 102 transitions to a sleep state while monitoring the flag 131).

  The setting thread 102 returns from the CPU standby instruction when the flag 131 is updated or interrupted (step S33). This ends the monitoring of the flag 131. Then, the process returns to step S11.

  By executing the processing as described above, the CPU 14 entrusted with the processing for setting the hardware timer 15 from the CPU 12 can appropriately set the processing. In addition, by confirming with the process scheduler, the setting thread 102 can be prevented from occupying the CPU 14. The right to use the CPU 14 is transferred for the following reason. Specifically, the state in which the setting thread 102 directly issues a CPU standby instruction and is on standby is recognized by the OS 10 as a state in which the setting thread 102 continues to run. For this reason, other threads of the OS 10 cannot operate (that is, the setting thread 102 monopolizes the CPU 14).

  Next, processing executed by the interrupt handler 103 will be described with reference to FIG.

  The hardware timer 15 generates an interrupt when the comparator value of the hardware timer 15 matches the counter value. When the CPU 14 detects an interrupt, the interrupt handler 103 is called. The interrupt handler 103 determines whether unprocessed data exists in the queue 132 (FIG. 5: step S41).

  If there is no unprocessed data in the queue 132 (step S41: No route), the process is terminated. On the other hand, when there is unprocessed data in the queue 132 (step S41: Yes route), the interrupt handler 103 specifies data having the earliest expiration time among the unprocessed data (step S43).

  The interrupt handler 103 determines whether the current time has passed the expiration time for the data specified in step S43 (step S45). When the current time has passed the expiration time (step S45: Yes route), the interrupt handler 103 executes the expiration process based on the expiration process information included in the data identified in step S43 (step S47). Then, the process returns to step S41.

  On the other hand, when the current time has not passed the expiration time (step S45: Yes route), the interrupt handler 103 calculates the remaining time until the expiration time for the data specified in step S43 (step S49). In step S49, the remaining time is the time from the current time acquired from the system clock or the like to the expiration time.

  The interrupt handler 103 converts the remaining time calculated in step S49 into a value to be added to the counter value of the hardware timer 15 (step S51).

  The interrupt handler 103 acquires the counter value of the hardware timer 15 from the hardware timer 15 (step S53). Then, the interrupt handler 103 calculates the value to be set as the comparator value of the hardware timer 15 by adding the value after the conversion in the process of step S51 to the counter value acquired from the hardware timer 15 (step S55). ).

  The interrupt handler 103 sets the value calculated in step S55 as the comparator value of the hardware timer 15 (step S57). Then, the process ends.

  By executing the processing as described above, the interrupt handler 103 can appropriately execute the expiration processing when an interrupt occurs.

  The effect of this embodiment will be described with reference to FIG. In the present embodiment, the CPU 12 entrusts the processing for setting the hardware timer 15 to the CPU 14 using a flag. Therefore, since the CPU 12 returns from the system call at an early stage, the time during which the application program is stopped can be shortened. In addition, since the CPU 12 can update the process to the CPU 14 by updating the flag (that is, once accessing the memory 13), entrusting the process to the CPU 14 does not decrease the execution speed of the application program.

  On the other hand, when a single CPU is used, the system call cannot be restored until the processing for setting the hardware timer 15 is completed. Of the processes for setting the hardware timer 15, the process for accessing the hardware timer 15 (for example, the processes in steps S17 and S21) is a particularly time-consuming process.

  In view of the fact that it takes time to access the hardware timer 15, it is also conceivable to use an interrupt mechanism (for example, Local APIC Timer in the Intel 64 architecture) of the CPU. For example, it is conceivable to prepare one CPU having an interrupt mechanism and generate an interrupt to the CPU. However, since an interrupt cannot be generated in another CPU, the CPU that executes the application program is forced to execute an interrupt process (for example, an expiration process and a setting process for the next interrupt). The speed drops.

  It is also conceivable that a CPU having an interrupt mechanism is prepared separately from a CPU that executes an application program and an interrupt is generated in the CPU. However, in communication (for example, IPI (Inter-Processor Interrupt), etc.) between the CPU that executes the application program and the CPU that generates an interrupt, various pre-processing (for example, setting of the interrupt destination CPU, It takes time because the function to be executed and the setting of arguments, etc., are performed.

  Similarly to the present embodiment, a thread is newly started, and the thread is monitored by a spin loop without using a CPU standby instruction. When the flag is updated, the setting to the hardware timer 15 is performed. It is possible to have However, in this case, the process of monitoring the flag occupies the CPU, so that other kernel threads may not be able to operate, and the power consumption is higher than that of the present embodiment.

  Although one embodiment of the present invention has been described above, the present invention is not limited to this. For example, the functional block configuration of the information processing apparatus 1 described above may not match the actual program module configuration.

  In addition, the data holding configuration described above is an example, and the above configuration is not necessarily required. Further, in the processing flow, the processing order can be changed if the processing result does not change. Further, it may be executed in parallel.

  Further, the processing entrusted to the CPU 14 via the flag 131 on the memory 13 is not limited to the setting of the hardware timer 15 and may be other processing.

  Further, the CPUs 12 and 14 may be the core of a multi-core processor. The processing load related to the timer setting can be distributed among a plurality of cores in the multi-core processor.

  The embodiment of the present invention described above is summarized as follows.

  An information processing apparatus according to a first aspect of the present embodiment includes (A) a first processor that executes an application program, (B) a second processor, (C) a memory that stores a flag, D) Hardware that generates an interrupt at a set time. (B1) the second processor monitors the flag; (a1) the first processor stores the first time information received from the process of the application program in the memory and updates the flag; (B2) When the flag is updated, the second processor reads the first time information from the memory, and sets the hardware based on the first time information.

  In this way, the processing for setting the hardware can be executed by the second processor, so that the first processor can immediately resume the execution of the application program and can suppress the decrease in the execution speed of the application program. It becomes like this. In addition, since the flag stored in the memory is used, communication between processors can be accelerated.

  (B3) When there is another process to be executed, the second processor may transfer the right to use the second processor from the process for monitoring the flag to another process to be executed. In this way, it is possible to suppress the process of monitoring the flag from occupying the second processor.

  Further, (a2) the first processor receives information on processing to be executed when the first time comes from the process of the application program, stores it in the memory, and (d1) is set by the second processor. When the first time is reached, the hardware generates an interrupt. (B4) When the interrupt is generated, the second processor performs processing to be executed when the first time is reached. This information may be extracted from the memory, and a process to be executed when the first time is reached may be executed. In this way, processing to be executed when an interrupt is generated can be appropriately performed.

  In the hardware setting process described above, (b21) the time to the first time is calculated, and (b22) the time to the first time is added to the hardware counter value. (B23) The hardware counter value is acquired from the hardware. (B24) The setting value is calculated by adding the value to be added to the hardware counter value to the hardware counter value. (B24) The set value may be set to a hardware comparator value. In this way, the hardware can be set appropriately.

  Further, the hardware described above may be (d2) a high-precision event timer. Even when a high-precision event timer is used, it becomes possible to cope with it.

  A timer setting method according to a second aspect of the present embodiment includes a first processor that executes an application program, a second processor, a memory that stores a flag, and a hardware that generates an interrupt at a set time. Executed by an information processing apparatus having hardware. In this timer setting method, (E) the second processor monitors the flag, and (F) the first processor stores information on the first time received from the process of the application program in the memory. When the flag is updated, (G) when the flag is updated, the second processor reads the first time information from the memory, and performs hardware setting based on the first time information. Including.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1)
A first processor for executing an application program;
A second processor;
Memory,
Hardware that generates an interrupt at a set time;
Have
The first processor stores information on the first time received from the process of the application program in the memory, and information indicating that the hardware timer setting is required for the identification information stored in the memory. To
The second processor monitors the identification information, and when the identification information is changed to information indicating that the hardware timer setting is required, reads the information of the first time from the memory, An information processing apparatus configured to set a timer of the hardware based on the information of the first time.

(Appendix 2)
The second processor transfers the right to use the second processor from the process of monitoring the identification information to the other process to be executed when there is another process to be executed. Information processing device.

(Appendix 3)
The first processor receives information on processing to be executed when the first time comes from the process of the first application program, stores the information in the memory,
The hardware generates an interrupt when the first time is reached,
When the interrupt is generated, the second processor extracts information on processing to be executed when the first time is reached from the memory and executes the information when the first time is reached. The information processing apparatus according to appendix 1, which executes power processing.

(Appendix 4)
In the process of setting the hardware timer,
Calculating the time to the first time;
Converting the time until the first time to a value to be added to the counter value of the hardware;
Obtaining the counter value of the hardware from the hardware;
A setting value that is a value obtained by adding a value to be added to the hardware counter value to the hardware counter value;
The information processing apparatus according to any one of supplementary notes 1 to 3, wherein the setting value is set to a comparator value of the hardware.

(Appendix 5)
The information processing apparatus according to any one of appendices 1 to 4, wherein the hardware is a high-precision event timer.

(Appendix 6)
A timer setting method executed by an information processing apparatus having a first processor that executes an application program, a second processor, a memory, and hardware that generates an interrupt at a set time,
The first processor stores information on the first time received from the process of the application program in the memory, and information indicating that the hardware timer setting is required for the identification information stored in the memory. To
The second processor monitors the identification information, and when the identification information is changed to information indicating that the hardware timer setting is required, reads the information of the first time from the memory, A timer setting method including a process of setting a timer of the hardware based on the information of the first time.

1 Information processing device 10 OS
DESCRIPTION OF SYMBOLS 101 Reception part 102 Setting thread 103 Interrupt handler 11 Application program process 12 CPU 13 Memory 131 Flag 132 Queue 14 CPU 15 Hardware timer

Claims (5)

A first processor for executing an application program;
A second processor;
Memory,
Hardware that generates an interrupt at a set time;
Have
The first processor stores information on the first time received from the process of the application program in the memory, and information indicating that the hardware timer setting is required for the identification information stored in the memory. To
The second processor monitors the identification information, and when the identification information is changed to information indicating that the hardware timer setting is required, reads the information of the first time from the memory, An information processing apparatus configured to set a timer of the hardware based on the information of the first time. The second processor transfers the usage right of the second processor from the process of monitoring the identification information to the other process to be executed when there is another process to be executed. Information processing device. The first processor receives information on processing to be executed when the first time comes from the process of the first application program, stores the information in the memory,
The hardware generates an interrupt when the first time is reached,
When the interrupt is generated, the second processor extracts information on processing to be executed when the first time is reached from the memory and executes the information when the first time is reached. The information processing apparatus according to claim 1, which executes power processing. In the process of setting the hardware timer,
Calculating the time to the first time;
Converting the time until the first time to a value to be added to the counter value of the hardware;
Obtaining the counter value of the hardware from the hardware;
A setting value that is a value obtained by adding a value to be added to the hardware counter value to the hardware counter value;
The information processing apparatus according to claim 1, wherein the setting value is set to a comparator value of the hardware. A timer setting method executed by an information processing apparatus having a first processor that executes an application program, a second processor, a memory, and hardware that generates an interrupt at a set time,
The first processor stores information on the first time received from the process of the application program in the memory, and information indicating that the hardware timer setting is required for the identification information stored in the memory. To
The second processor monitors the identification information, and when the identification information is changed to information indicating that the hardware timer setting is required, reads the information of the first time from the memory, A timer setting method including a process of setting a timer of the hardware based on the information of the first time.

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