JP2015225458A - Information processing device and arbitration method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently access a memory from a plurality of processes.SOLUTION: When a controller 6 is in context with a series of consecutive accesses to a memory 2, the controller 6 limits masters 1-i which are allowed to have a bus use right among a plurality of masters 1-1 to 1-4 such that the total context number of the masters 1-i which are allowed to have a bus use right of a bus 3 is equal to or less than a prescribed number based on the configuration of a memory 2.

Description

  The present invention relates to an information processing apparatus and an arbitration method.

  In recent years, DRAM (Dynamic Random Access Memory) data transfer used as a large-capacity main memory of a microprocessor has evolved and speeded up to SDR (Single Data Rate), DDR (Double Data Rate), DDR2, and DDR3. .

  Further, as methods for improving the efficiency of memory access related to command issuance, there are a command order change (reorder), a technique (outstanding) for issuing the next command without waiting for the completion of the command (for example, Patent Documents 1 and 2). reference).

JP 2008-204487 A Special table 2008-541217 gazette

  FIG. 6 is a block diagram illustrating a configuration example of an information processing apparatus in which a plurality of masters access a single memory via a bus. In the apparatus shown in FIG. 6, the masters 101-1 to 101-4 are connected to the bus 102, and the masters 101-1 to 101-4 to which the bus use right is given by the arbiter 103 are the buses. A command is sent to the memory controller 104 via 102 to access the memory 105. FIG. 7 is a diagram showing an example of granting a bus use right by the arbiter 103 in FIG. As illustrated in FIG. 7, the arbiter 103 receives use requests from the masters 101-1 to 101-4 and, based on a predetermined arbitration method, the one or more masters 101-i that have issued use requests. The bus usage rights are given in order. The masters 101-1 to 101-4 proceed with the processing while accessing the memory 105 when the bus use right is given.

  When the memory 105 has a plurality of banks, when one or more pages in a certain bank are continuously accessed, the page is not opened / closed except at the page boundary. Can be accessed continuously. Such a continuous series of accesses is hereinafter referred to as a context.

  Even if a plurality of processes by the masters 101-1 to 101-4 request access to the memory 105, if a plurality of accesses to a page in the same bank do not occur, a page open / close process is performed. Instead, the memory 105 is continuously accessed.

  However, when the number of contexts for accessing the memory 105 from a plurality of processes increases, page open / close processes frequently occur, making it difficult to efficiently access the memory.

  In such a device, it may be possible to increase the efficiency of memory access by the above-mentioned reordering, standing-out, etc., but it is necessary to refer to a command string for a long period of time when trying to increase the efficiency of memory access by reordering Thus, the latency from issuing the read command to receiving the data increases. In addition, in order to increase the throughput against the increase in latency, when the standing is introduced, the circuit scale becomes large.

  The present invention has been made in view of the above problems, and an object thereof is to obtain an information processing apparatus and an arbitration method that efficiently access a memory from a plurality of processes.

  The information processing apparatus according to the present invention includes a plurality of masters that execute a plurality of processes, a memory shared by the plurality of masters, a bus, and a command supplied from the plurality of masters via the bus. The total number of contexts of the memory controller that executes access to the memory, the arbiter that gives the bus use right of the bus, and the master that is allowed to grant the bus use right, with a continuous series of accesses to the memory as contexts And a controller that restricts a master that is permitted to be given the bus use right among the plurality of masters so that the number of masters is less than a predetermined number based on the configuration of the memory.

  In the arbitration method according to the present invention, when the memory controller performs access to the memory in accordance with a command supplied via a bus from a plurality of masters that execute a plurality of processes, the arbitration method performs any of the plurality of masters. A bus use right is granted, and a continuous series of accesses to the memory is a context, and the total number of contexts of the master permitted to be granted the bus use right is less than a predetermined number based on the configuration of the memory. As described above, among the plurality of masters, the masters permitted to be given the bus use right are limited.

  According to the present invention, memory access from a plurality of processes is efficiently performed.

FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining the context in the processing in the master 1-i in FIG. FIG. 3 is a diagram for explaining assignment of a bus use right by the arbiter 5 in the information processing apparatus according to the first embodiment. FIG. 4 is a diagram illustrating an example of a set of masters according to the second embodiment. FIG. 5 is a block diagram showing the configuration of the information processing apparatus according to Embodiment 3 of the present invention. FIG. 6 is a block diagram illustrating a configuration example of an information processing apparatus in which a plurality of masters access a single memory via a bus. FIG. 7 is a diagram showing an example of granting a bus use right by the arbiter 103 in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

  FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to Embodiment 1 of the present invention.

  The apparatus shown in FIG. 1 includes a plurality of masters 1-1 to 1-4, a memory 2, a bus 3, a memory controller 4, an arbiter 5, a controller 6, and a selector 7.

  Each of the plurality of masters 1-1 to 1-4 is a processing circuit that performs a plurality of processes while reading and / or writing data to / from the memory 2 by a DMA (Direct Memory Access) circuit 11.

  The memory 2 is a memory shared by a plurality of masters 1-1 to 1-4, and is, for example, a DRAM.

  In the first embodiment, the memory 2 has a plurality of banks, and each bank has a plurality of pages.

  The bus 3 is a memory bus for the memory 2.

  The memory controller 4 executes access to the memory 2 in accordance with a command supplied from the plurality of masters 1-1 to 1-4 via the bus 3.

  The arbiter 5 exclusively gives the bus use right of the bus 3 by a predetermined arbitration method in response to the use request of the bus 3.

  Here, the context in the process in the master 1-i will be described. FIG. 2 is a diagram for explaining the context in the processing in the master 1-i in FIG. For example, a series of accesses that are continuously performed on addresses that are continuous or close to each other within the same page or across consecutive pages constitute one context.

  For example, as shown in FIG. 2, in the processing of the master 1-1, continuous reading from page # 0 in bank # 0 and continuous access to page # 5 in bank # 1 and page # 6 in bank # 2 When a simple write is executed, the continuous read becomes one context, the continuous write becomes one context, and the total number of contexts in the processing of the master 1-1 is 2. For example, in the processing of the master 1-1, when a continuous read from another page is separately executed in parallel with the continuous read, the number of contexts increases by one.

  The controller 6 includes a plurality of masters 1-1 to 1-4 such that the total number of contexts of the master 1-i that is permitted to grant the bus use right is equal to or less than a predetermined number based on the configuration of the memory 2. The master 1-i permitted to grant the bus use right is restricted.

  In the first embodiment, the controller 6 uses the selector 7 to connect only the master 1-i permitted to be granted the right to use the bus to the bus 3.

  Further, in the first embodiment, the controller 6 uses the bus so that the total used bandwidth of the master 1-i permitted to be granted the right to use the bus is maximized under a condition that does not exceed the bandwidth of the memory 2. The master 1-i that is permitted to grant the right is selected.

  Furthermore, in the first embodiment, the controller 6 uses the bus so that the total number of contexts of the master 1-i permitted to be granted the right to use the bus is equal to or less than the allowable number of contexts specified based on the configuration of the memory 2. The master 1-i that is permitted to grant the right is selected.

  Here, the allowable number of contexts is the number of banks of the memory 2.

  When the memory 2 has a plurality of ranks, the allowable number of contexts is a product of the number of banks of the memory 2 and the number of ranks.

  Next, the operation of the information processing apparatus according to the first embodiment will be described.

  FIG. 3 is a diagram for explaining assignment of a bus use right by the arbiter 5 in the information processing apparatus according to the first embodiment.

  Based on the number of contexts of each of the masters 1-1 to 1-4, the controller 6 first selects two masters 1-1 and 1-4 as masters that are permitted to be granted bus use rights. Notify the arbiter 5. In the first embodiment, the controller 6 stores data of the number of contexts of each of the masters 1-1 to 1-4 in advance.

  And the process of the master 1-1 is started (time T1), the process of the master 1-4 is started (time T2), and when the use request from the masters 1-1 and 1-4 is received, the arbiter 5 The master 1-1 and 1-4 are given the right to use the bus as appropriate.

  After that, when the processing of the master 1-1 is completed (time T3), the controller 6 becomes a master that is permitted to grant the bus use right based on the number of contexts of the masters 1-2, 1-3, and 1-4. Then, it is determined whether or not any of the remaining masters 1-2 and 1-3 can be added. Here, the controller 4 determines that the master 1-2 can be added, additionally selects the master 1-2, and notifies the arbiter 5 of the master 1-2. Then, the arbiter 5 gives the right to use the bus to the masters 1-2 and 1-4 as appropriate.

  The controller 6 may detect the end of the process of the master 1-1 based on an explicit signal from the master 1-1, or when there is no memory access from the master 1-1 for a predetermined time. You may determine with the process of the master 1-1 having been complete | finished.

  At this time, if the controller 6 determines that neither of the remaining masters 1-2 and 1-3 can be added as a master permitted to be granted the bus use right, at least the master 1-4. Neither of the remaining masters 1-2 and 1-3 until the end of the process is a master that is permitted to be granted bus use rights.

  After that, when the processing of the master 1-4 is completed (time T4), the controller 6 determines the remaining masters as masters that are permitted to grant the bus use right based on the number of contexts of the masters 1-2 and 1-3. It is determined whether or not 1-3 can be added. Here, the controller 4 determines that the master 1-3 can be added, additionally selects the master 1-3, and notifies the arbiter 5 of the master 1-3. Then, the arbiter 5 gives the right to use the bus to the masters 1-2 and 1-3 as appropriate.

  As described above, according to the first embodiment, when the controller 6 uses a series of continuous accesses to the memory 2 as a context, the controller 6 is permitted to grant the bus use right of the bus 3. Among the plurality of masters 1-1 to 1-4, the master 1-i that is granted the right to use the bus is selected so that the total number of contexts 1-i is not more than a predetermined number based on the configuration of the memory 2. Restrict.

  Thereby, access to the memory 2 from a plurality of processes is efficiently performed. In other words, when viewed from the memory 2, the number of contexts of memory access executed in parallel by a plurality of masters 1-i is kept low, so the frequency of executing page open / close is reduced, and memory access is efficiently performed. Executed.

Embodiment 2. FIG.

  In the information processing apparatus according to the second embodiment, the controller 6 allocates a plurality of masters 1-1 to 1-4 in advance to a plurality of sets, and the arbiter 5 is a master 1-permitted to grant bus use rights. i is switched collectively for each set.

  Specifically, the controller 6 sets the plurality of masters 1-1 to 1-4 so that the total number of contexts of the masters that are permitted to grant the bus use right in each set is equal to or less than the predetermined number described above. Assign to multiple sets in advance.

  Then, the controller 6 grants the master 1-j of another set to the bus use right when the processing of all the masters 1-i in the set that is currently granted the right to use the bus is completed. And the arbitrator 5 is notified.

  FIG. 4 is a diagram illustrating an example of a set of masters according to the second embodiment. For example, as shown in FIG. 4, the set # 1 includes masters 1-1 and 1-4, and the set # 2 includes masters 1-2 and 1-3. In this case, first, the masters 1-1 and 1-4 of the set # 1 are selected as masters to which the bus use right is granted, and the processing (time of both) of the masters 1-1 and 1-4 is completed. At T11), the master permitted to be given the bus use right is switched to the masters 1-2 and 1-3 of the set # 2.

  Note that other configurations and operations of the information processing apparatus according to the second embodiment are the same as those of the first embodiment, and thus description thereof is omitted.

  As described above, according to the second embodiment, for example, when there is data dependence between processes of a plurality of masters 1-i (for example, when the data after one process is processed by the other), By making the master 1-i into one set, the occurrence of deadlock and delay is reduced.

Embodiment 3 FIG.

  FIG. 5 is a block diagram showing the configuration of the information processing apparatus according to Embodiment 3 of the present invention.

  In the third embodiment, the controller 6 limits the masters that are permitted to be given the right to use the bus among a plurality of masters 21-1 to 21-4 to a predetermined fixed number or less. This fixed number is determined from the number of known masters 21-1 to 21-4 and the configuration of the memory 2, and is selected at the same time as described above. Is the maximum number of.

  In other words, this fixed number is the upper limit value of the number of masters that are selected at the same time and that are permitted to be given the right to use the bus.

  The masters 21-1 to 21-4 are the same as the masters 1-1 to 1-4, but do not have the DMA circuit 11. Instead, the same number of DMA circuits 22-1 and 22-2 as the above-mentioned fixed number (here 2) is less than the number of masters 21-1 to 21-4 (here 4). Acting as a proxy for memory access in the master 21-i that is permitted to be granted

  The DMA circuits 22-1 and 22-2 are connected to the bus 3, and the masters 21-1 to 21-4 are connected to the DMA circuits 22-1 and 22-2 via the selector 7.

  Then, the controller 6 selects the master 21-i permitted to be given the current bus use right by the selector 7, and connects it to the DAM circuits 22-1 and 22-2.

  The arbiter 5 gives the right to use the bus 3 to either the DMA circuit 22-1 or 22-2 based on a predetermined arbitration method.

  Note that other configurations and operations of the information processing apparatus according to the third embodiment are the same as those in the first embodiment, and thus the description thereof is omitted.

  As described above, according to the third embodiment, since only the fixed number of DMA circuits 22-1 and 22-2 are mounted, the circuit scale can be reduced.

  Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

  For example, in the information processing apparatuses according to the first and second embodiments, the plurality of masters 1 to 1 to 1-4 dynamically notify the controller 6 of the number of contexts of processing performed by the masters 1 to 1 to 4. Calculates the total number of contexts notified from the plurality of masters 1-1 to 1-4, and grants the right to use the bus so that the total number of contexts is equal to or less than a predetermined number based on the configuration of the memory 2. You may make it select the master permitted.

  Furthermore, in this case, when the masters 1-1 to 1-4 dynamically notify the controller 6 of the number of contexts, when one context crosses a bank boundary (that is, a page boundary that is a bank boundary). Alternatively, the banks may be regarded as different contexts, and the number of contexts for the context may be set to 2 (that is, increased by 1).

  Furthermore, in this case, when the total number of contexts notified dynamically exceeds the allowable number of contexts for the memory 2, at least one master is selected from the masters that are permitted to grant the current bus use right. You may make it exclude.

  In this case, when the total number of dynamically notified contexts is smaller than the allowable number of contexts for the memory 2, a master other than the master that is currently permitted to grant the bus use right is assigned to the bus use right. If the total number of contexts does not exceed the allowable number of contexts even if they are added to the masters that are allowed to be granted, the masters other than the masters that are currently allowed to grant bus usage rights are allowed to grant bus usage rights. May be added to the master.

  In the second embodiment, the set of masters to which the current bus use right can be granted may be forcibly switched every predetermined time (for example, 10 milliseconds).

  Furthermore, in the first to third embodiments, the memory controller 4 may have a reorder function and an standing function. That is, the arbitration method according to the first to third embodiments can be used in combination with the reorder function, the standing function, and the like, so that the memory access efficiency can be further increased.

  The present invention can be applied to, for example, an image processing apparatus including a plurality of image processing circuits as a master.

1-1 to 1-4, 21-1 to 21-4 Master 2 Memory 3 Bus 4 Memory controller 5 Arbiter 6 Controller 22-1 and 22-2 DMA circuit (an example of a memory access circuit)

Claims (9)

With multiple masters performing multiple processes,
Memory shared by the plurality of masters;
With bus,
A memory controller that executes access to the memory according to a command supplied from the plurality of masters via the bus;
An arbiter that gives the right to use the bus;
Among the plurality of masters, a series of continuous accesses to the memory is used as a context, and the total number of masters allowed to be granted the bus use right is equal to or less than a predetermined number based on the configuration of the memory. , A controller that restricts masters that are allowed to grant the bus use right,
An information processing apparatus comprising:   The controller determines a master that is permitted to grant the bus usage right so that the total usage bandwidth of the master that is permitted to grant the bus usage right is maximized under a condition that does not exceed the bandwidth of the memory. The information processing apparatus according to claim 1, wherein the information processing apparatus is selected.   The controller determines a master that is permitted to grant the bus usage right so that a total number of contexts of the master that is permitted to grant the bus usage right is equal to or less than an allowable number of contexts specified based on the configuration of the memory. The information processing apparatus according to claim 1, wherein the information processing apparatus is selected.   4. The information processing apparatus according to claim 3, wherein the allowable number of contexts is the number of banks of the memory.   4. The information processing apparatus according to claim 3, wherein the allowable number of contexts is a product of the number of banks of the memory and the number of ranks. Each of the plurality of masters notifies the controller of the number of contexts of the processing to be executed by the master,
The controller calculates the total number of contexts notified from the plurality of masters, and grants the right to use the bus so that the total number of contexts is equal to or less than a predetermined number based on the configuration of the memory. Selecting a master to be played,
The information processing apparatus according to any one of claims 1 to 5, wherein The controller distributes the plurality of masters to a plurality of sets so that the total number of contexts of the masters permitted to grant the bus use right in each set is equal to or less than a predetermined number based on the configuration of the memory. Switching masters that are allowed to grant bus usage rights together for each set,
The information processing apparatus according to claim 1. A plurality of memory access circuits acting on behalf of memory access in the master permitted to grant the bus use right;
The controller restricts a master permitted to be given the bus use right from the plurality of masters to a predetermined fixed number or less,
The number of the memory access circuits is less than the number of the plurality of masters and is the same as the fixed number;
The arbiter gives a bus use right of the bus to any of the plurality of memory access circuits;
The information processing apparatus according to claim 1. Arbitration that grants the bus use right of the bus to one of the plurality of masters when the memory controller executes access to the memory in accordance with a command supplied from the plurality of masters that executes a plurality of processes via the bus A method,
Among the plurality of masters, a series of continuous accesses to the memory is used as a context, and the total number of masters allowed to be granted the bus use right is equal to or less than a predetermined number based on the configuration of the memory. Limiting the masters allowed to grant the bus use right,
An arbitration method characterized by:

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