JP2015172849A - Communication control circuit, data communication system, and power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit data among a plurality of communication circuits, and to reduce a circuit scale.SOLUTION: A communication control circuit allows at least three communication circuits having an output port and an input port to transmit and receive data mutually. The communication circuit fixes the logic level of the output port to a first logic level during a period when the output port does not output data, includes a set of communication circuits, an output end connected to the input port of the communication circuit that does not belong to the set, and a plurality of input ends connected to the output port of each communication circuit belong to the set, and includes a logic gate where the logic level of the output end becomes the first logic level when the logic level of the plurality of input ends is the first logic level, and the logic level of the output end becomes a second logic level when the logic level of at least one input end is the second logic level opposite to the first logic level.

Description

  The present invention relates to a communication control circuit, a data communication system, and a power supply device, and more particularly to a communication control circuit, a data communication system, and a power supply device that allow three or more communication circuits to transmit / receive data to / from each other.

  The UART (Universal Asynchronous Receiver Transmitter) is an integrated circuit for converting a serial signal in an asynchronous manner into a parallel signal or converting in the opposite direction. There are a case where only a UART circuit is supplied by a packaged IC and a case where a UART circuit is built in as a part of a microprocessor peripheral. The UART is generally used as an interface with an external device in combination with, for example, an IC that converts to a signal level conforming to the RS-232C, RS-422, and RS-485 standards.

“Wikipedia”, [online], [November 19, 2013 search], Internet <URL: http: // ja. wikipedia. org / wiki / UART>

  For example, in order to perform one-to-many communication in a plurality of devices including a UART, an RS-485 driver IC may be mounted for each device, and communication may be performed via the mounted RS-485 driver IC. In this case, a space for mounting the RS-485 driver IC on the substrate is required, and the cost of the RS-485 driver IC is required.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a communication control circuit and a data communication capable of transmitting data between a plurality of communication circuits and reducing the circuit scale. A system and a power supply device are provided.

  (1) In order to solve the above problems, a communication control circuit according to an aspect of the present invention includes three or more output ports for outputting data to the outside and three or more input ports for inputting data from the outside. The communication control circuit in the data communication system capable of transmitting / receiving data to / from each other, wherein the communication circuit sets a logic level of the output port to a first level during a period in which data is not output from the output port. Fixed at a logic level, a set of communication circuits, an output terminal connected to the input port of the communication circuit not belonging to the set, and a plurality connected to the output ports of the communication circuits belonging to the set And when the logic level of the plurality of input terminals is the first logic level, the logic level of the output terminal is the first logic level. A logic gate in which the logic level of the output terminal is the second logic level when the logic level of at least one of the input terminals is a second logic level opposite to the first logic level. Prepare.

  (4) In order to solve the above-described problem, a data communication system according to an aspect of the present invention has an output port for outputting data to the outside and an input port for inputting data from the outside. Three or more communication circuits are provided, and the communication circuit fixes the logic level of the output port to a first logic level during a period in which data is not output from the output port, and further corresponds to the set of communication circuits. An output terminal connected to the input port of the communication circuit not belonging to the corresponding set, and a plurality of input terminals connected to the output port of each communication circuit belonging to the corresponding set. And when the logic level of the plurality of input terminals is the first logic level, the logic level of the output terminal is the first logic level, and at least one of The logic level of the entry power end comprises a plurality of logic gates logic level of the output terminal when a second logic level opposite to the first logic level is the second logic level.

  The present invention can be realized not only as a communication control circuit or a data communication system including such a characteristic processing unit, but also as a communication device including such a characteristic processing unit, or to perform such characteristic processing as a step. Or a program for causing a computer to execute such steps. Further, it can be realized as a semiconductor integrated circuit that realizes part or all of the communication control circuit or the data communication system.

  According to the present invention, it is possible to transmit data between a plurality of communication circuits and to reduce the circuit scale.

FIG. 1 is a diagram showing a configuration of a data communication system according to the first embodiment of the present invention. FIG. 2 is a time chart showing the operation of each communication control circuit in the data communication system according to the first embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a power supply system according to the second embodiment of the present invention. FIG. 4 is a diagram illustrating a configuration of a data communication system as a comparative example. FIG. 5 is a diagram showing details of the configuration of the control information communication system according to the second embodiment of the present invention. FIG. 6 is a diagram showing a configuration of a driver in the control information communication system according to the second embodiment of the present invention. FIG. 7 is a time chart showing the operation of each communication control circuit in the control information communication system according to the second embodiment of the present invention.

  First, the contents of the embodiment of the present invention will be listed and described.

  (1) In the communication control circuit according to the embodiment of the present invention, three or more communication circuits having an output port for outputting data to the outside and an input port for inputting data from the outside transmit data to each other. A communication control circuit in a data communication system capable of transmitting and receiving, wherein the communication circuit fixes a logic level of the output port to a first logic level in a period in which data is not output from the output port. A set of communication circuits; an output end connected to the input port of the communication circuit not belonging to the set; and a plurality of input ends connected to the output ports of the communication circuits belonging to the set. When the logic level of the plurality of input terminals is the first logic level, the logic level of the output terminal becomes the first logic level, and at least one of The logic level of the entry power end and a logic gate logic level of the output terminal becomes the second logic level when the second logic level opposite to the first logic level.

  With such a configuration, for example, in a period in which one communication circuit belonging to the set outputs data from its own output port, the logic level of the output port via the logic gate and the output end, that is, does not belong to the set Since the logic level of the input port in the communication circuit is the same, a communication circuit that does not belong to the set can receive data transmitted by the one communication circuit during the period. Therefore, data can be transmitted from the one communication circuit to a communication circuit not belonging to the set with a simple configuration using the logic gate.

  Therefore, in the communication control circuit according to the embodiment of the present invention, data transmission can be performed between a plurality of communication circuits, and the circuit scale can be reduced.

  (2) Preferably, the communication control circuit further includes an input port connected to the output terminal of the logic gate, an output port connected to the input port of each communication circuit belonging to the set, and the set A first buffer that has a bidirectional port connected to the input port and the output port of the communication circuit that does not belong to the communication circuit, and outputs data received from the input port to the bidirectional port; A relay circuit including one buffer and a second buffer that outputs data received from the bidirectional port from its own output port, and each of the communication circuits belonging to the set receives data from its own output port. The first buffer outputs a control signal indicating an output period for outputting the output terminal to the relay circuit. And dance state.

  With such a configuration, in the output period, one communication circuit belonging to the group can transmit data to a communication circuit that does not belong to the group while sharing the relay circuit. The number of relay circuits can be reduced as compared with the configuration in which is provided. Thereby, the space for mounting the relay circuit can be saved, and the manufacturing cost can be reduced.

  (3) More preferably, in the output period, the second buffer sets its output terminal to the first logic level, and the communication control circuit is further connected to the output terminal of the second buffer. A first input terminal connected to the output port of one of the communication circuits belonging to the set, and a second input terminal connected to the output port of the other communication circuit belonging to the set. When the logic level of the first input terminal and the second input terminal is the first logic level, the logic level of the output terminal becomes the first logic level, and the first input terminal And a logic gate in which the logic level of the output terminal becomes the second logic level when the logic level of at least one of the second input terminals is the second logic level.

  With such a configuration, for example, in a period in which the other communication circuit outputs data from its own output port, the logic level of the output port and the logic level of the output port, that is, the input port in the one communication circuit are the same. Therefore, the one communication circuit can receive data transmitted by the other communication circuit in the period. Therefore, with the simple configuration using the logic gate, the other communication circuit can transmit data to the one communication circuit.

  The other communication circuit transmits data to a communication circuit that does not belong to the set via a relay circuit during a period in which data is output from its own output port. Since the circuit can receive data transmitted by a communication circuit that does not belong to the set via the relay circuit, data is transmitted and received between the other communication circuit and a communication circuit that does not belong to the set. Can do.

  Similarly, the one communication circuit transmits data to a communication circuit that does not belong to the set via a relay circuit during a period in which data is output from its own output port. Since the communication circuit can receive data transmitted by the communication circuit that does not belong to the set via the relay circuit, the data is transmitted and received between the one communication circuit and the communication circuit that does not belong to the set. be able to.

  (4) The data communication system according to the embodiment of the present invention includes three or more communication circuits each having an output port for outputting data to the outside and an input port for inputting data from the outside. And the communication circuit fixes the logic level of the output port to a first logic level during a period when data is not output from the output port, and is provided corresponding to the set of communication circuits. An output terminal connected to the input port of the communication circuit not belonging to the set; and a plurality of input terminals connected to the output port of each of the communication circuits belonging to the corresponding set; When the logic level of the input terminal is the first logic level, the logic level of the output terminal is the first logic level, and the logic level of at least one of the input terminals is the above-described logic level. First logic level opposite to the second logic level of the output terminal when a logic level comprises a plurality of logic gates to be the second logic level.

  With such a configuration, for example, in a period in which one communication circuit belonging to the set outputs data from its own output port, the logic level of the output port via the logic gate and the output end, that is, does not belong to the set Since the logic level of the input port in the communication circuit is the same, a communication circuit that does not belong to the set can receive data transmitted by the one communication circuit during the period. Therefore, data can be transmitted from the one communication circuit to a communication circuit not belonging to the set with a simple configuration using the logic gate.

  In addition, with a configuration in which a plurality of logic gates are provided corresponding to the above groups, the expandability of the communication path in the data communication system can be ensured.

  Therefore, in the data communication system according to the embodiment of the present invention, data transmission can be performed between a plurality of communication circuits, and the circuit scale can be reduced.

  (5) In order to solve the above problem, a power supply apparatus according to an aspect of the present invention includes the communication control circuit according to (1).

  With such a configuration, in the communication control circuit in the power supply device, for example, during the period in which one communication circuit belonging to the set outputs data from its own output port, the logic level of the output port via the logic gate And the output port, that is, the logic level of the input port in the communication circuit that does not belong to the above set is the same, so that the communication circuit that does not belong to the above set receives the data transmitted by the one communication circuit during the period Can do. Therefore, data can be transmitted from the one communication circuit to a communication circuit not belonging to the set with a simple configuration using the logic gate.

  Therefore, in the power supply apparatus according to the embodiment of the present invention, data transmission can be performed between a plurality of communication circuits, and the circuit scale can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Moreover, you may combine arbitrarily at least one part of embodiment described below.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of a data communication system according to the first embodiment of the present invention.

  Referring to FIG. 1, a data communication system 301 includes microcomputers (communication circuits) MC1, MC2, and MC3, and AND gates (logic gates) G1, G2, and G3.

  Hereinafter, each of the microcomputers MC1, MC2, and MC3 is also referred to as a microcomputer MC. Each of the AND gates G1, G2, and G3 is also referred to as an AND gate G.

  Note that the data communication system 301 may include, for example, two or less, or four or more AND gates G. Further, the data communication system 301 may include, for example, four or more microcomputers MC.

  The data communication system 301 is mounted on, for example, the control board CB1. In the data communication system 301, for example, three or more microcomputers MC can transmit / receive data to / from each other.

  The communication control circuit in the data communication system 301 includes a set of microcomputers MC (hereinafter also referred to as a target set) and an AND gate G. Specifically, the communication control circuit CC11 includes microcomputers MC1 and MC2 and an AND gate G1. Communication control circuit CC12 includes microcomputers MC2 and MC3 and AND gate G2. Communication control circuit CC13 includes microcomputers MC3 and MC1 and AND gate G3.

  For example, the microcomputer MC can control other circuits. Specifically, the microcomputers MC1 and MC3 are control microcomputers for controlling, for example, an inverter circuit and a converter circuit. The microcomputer MC can control one or a plurality of other microcomputers MC. Specifically, the microcomputer MC2 is, for example, a centralized control microcomputer for controlling the microcomputers MC1 and MC3.

  The microcomputer MC includes, for example, a UART. In general, when UART is used, only one-to-one communication can be performed between a plurality of devices including UART, for example, microcomputers. On the other hand, between the microcomputers MC, for example, using UART, it is possible to perform one-to-many communication according to a bidirectional asynchronous serial communication method and transmit / receive data to / from each other.

  The microcomputer MC1 has an output port Tx1 for outputting data to the outside and an input port Rx1 for inputting data from the outside. The microcomputer MC2 has an output port Tx2 for outputting data to the outside and an input port Rx2 for inputting data from the outside. The microcomputer MC3 has an output port Tx3 for outputting data to the outside and an input port Rx3 for inputting data from the outside.

  Here, the output ports Tx1, Tx2, Tx3 and the input ports Rx1, Rx2, Rx3 may be specifically terminals of the microcomputer MC or nodes on the wiring.

  For example, when one microcomputer MC outputs data from its own output port, that is, when it becomes a talker, the other microcomputer MC receives data from its own input port without outputting data from its own output port. Become a listener. Therefore, for example, when one microcomputer MC becomes a talker, the remaining microcomputers MC become listeners.

  For example, the microcomputer MC fixes the logic level of the output port at a high level in a period in which data is not output from its own output port, that is, a period of being a listener.

  The AND gate G has an output terminal connected to the input port of the microcomputer MC that does not belong to the target group, and a plurality of input terminals connected to the output port of the microcomputer MC that belongs to the target group.

  Specifically, for example, in the communication control circuit CC11 in which the microcomputers MC1 and MC2 are the target group, the AND gate G1 includes an output terminal G1c connected to the input port Rx3 of the microcomputer MC3 and an output port Tx1 of the microcomputers MC1 and MC2. , Tx2 are connected to input terminals G1a, G1b, respectively.

  Further, for example, in the communication control circuit CC12 in which the microcomputers MC2 and MC3 are the target group, the AND gate G2 is connected to the output terminal G2c connected to the input port Rx1 of the microcomputer MC1 and the output ports Tx2 and Tx3 of the microcomputers MC2 and MC3. Input terminals G2a and G2b are connected to each other.

  Further, for example, in the communication control circuit CC13 in which the microcomputers MC3 and MC1 are the target group, the AND gate G3 is connected to the output terminal G3c connected to the input port Rx2 of the microcomputer MC2 and the output ports Tx3 and Tx1 of the microcomputers MC3 and MC1. Input terminals G3b and G3a are connected to each other.

  In the AND gate G, for example, when the logic levels of a plurality of input terminals are high, the logic level of the output terminal is high, and the logic level of at least one of the input terminals is low level opposite to the high level. In some cases, the logic level at the output end is low.

  Specifically, in the AND gate G1, for example, when the logic levels of the input terminals G1a and G1b are high, the logic level of the output terminal G1c becomes high, and at least one of the logic levels of the input terminals G1a and G1b When the level is the low level, the logic level of the output terminal G1c becomes the low level.

  Further, the AND gate G2, for example, when the logic levels of the input terminals G2a and G2b are high, the logic level of the output terminal G2c is high, and at least one of the logic levels of the input terminals G2a and G2b is low. In the case of the level, the logic level of the output terminal G2c becomes a low level.

  The AND gate G3 has, for example, a high logic level at the output terminal G3c when the logic levels of the input terminals G3a and G3b are high, and at least one of the logic levels of the input terminals G3a and G3b is low. In the case of the level, the logic level of the output terminal G3c becomes a low level.

  FIG. 2 is a time chart showing the operation of each communication control circuit in the data communication system according to the first embodiment of the present invention.

  Referring to FIG. 2, microcomputers MC1, MC2, MC3, for example, set the logic levels of output ports Tx1, Tx2, Tx3 in a break period Tb1 during which data is not output from its own output port and until timing td1s. Fix at high level.

  In the AND gates G1, G2, and G3, since the logic levels of the input terminals G1a, G1b, G2a, G2b, G3a, and G3b are high during the break period Tb1, the logic levels of the output terminals G1c, G2c, and G3c are high. It becomes.

  Next, the microcomputer MC1 transmits 10-bit data including a start bit and a stop bit by switching the logic level of the output port Tx1 according to the data to be transmitted, for example, in the data period Td1 of timing td1s to td1e. To do.

  For example, in the data period Td1, the microcomputers MC2 and MC3 keep the logic levels of the output ports Tx2 and Tx3 fixed at a high level.

  In the AND gate G1, since the logic level of the input terminal G1b is high in the data period Td1, when the logic level of the input terminal G1a is high, the logic level of the output terminal G1c is high, and the input terminal G1a When the logic level is low, the logic level of the output terminal G1c is low.

  With such a configuration, the logic level of the output port Tx1 and the logic level of the output terminal G1c, that is, the input port Rx3 in the microcomputer MC3 can be made the same, so that the microcomputer MC3 transmits the data in the data period Td1. 10-bit data can be received.

  Similarly, in the AND gate G3, since the logic level of the input terminal G3b is high in the data period Td1, when the logic level of the input terminal G3a is high, the logic level of the output terminal G3c is high. When the logic level of the input terminal G3a is low, the logic level of the output terminal G3c is low.

  With such a configuration, the logic level of the output port Tx1 and the logic level of the output port G3c, that is, the input port Rx2 in the microcomputer MC2, can be made the same, so that the microcomputer MC2 transmits the microcomputer MC1 in the data period Td1. 10-bit data can be received.

  Next, the microcomputers MC1, MC2, and MC3, for example, fix the logic levels of the output ports Tx1, Tx2, and Tx3 to a high level in the break period Tb2 of the timing td1e to td2s when no data is output from its own output port. In the AND gates G1, G2, and G3, the logic levels of the output terminals G1c, G2c, and G3c are high during the break period Tb2.

  Next, the microcomputer MC2 transmits, for example, 10-bit data in the data period Td2 from timing td2s to td2e.

  For example, in the data period Td2, the microcomputers MC3 and MC1 keep the logic levels of the output ports Tx3 and Tx1 fixed at a high level.

  In the AND gate G2, since the logic level of the input terminal G2b is high in the data period Td2, the logic level of the output terminal G2c is high when the logic level of the input terminal G2a is high, and the input terminal G2a When the logic level is low, the logic level of the output terminal G2c is low.

  With such a configuration, the logic level of the output port Tx2 and the logic level of the output terminal G2c, that is, the input port Rx1 in the microcomputer MC1, can be made the same, so that the microcomputer MC1 transmits the data in the data period Td2. 10-bit data can be received.

  Similarly, in the AND gate G1, since the logic level of the input terminal G1a is high in the data period Td2, when the logic level of the input terminal G1b is high, the logic level of the output terminal G1c is high. When the logic level of the input terminal G1b is low, the logic level of the output terminal G1c is low.

  With such a configuration, the logic level of the output port Tx2 and the output port G1c, that is, the logic level of the input port Rx3 in the microcomputer MC3 can be made the same, so that the microcomputer MC3 transmits the data in the data period Td2. 10-bit data can be received.

  Next, the microcomputers MC1, MC2, and MC3, for example, fix the logic levels of the output ports Tx1, Tx2, and Tx3 to a high level in the break period Tb3 of the timing td2e to td3s when data is not output from its own output port. In the AND gates G1, G2, and G3, the logic levels of the output terminals G1c, G2c, and G3c are high during the break period Tb3.

  Next, the microcomputer MC3 transmits, for example, 10-bit data in the data period Td3 from the timing td3s to td3e.

  For example, in the data period Td3, the microcomputers MC1 and MC2 keep the logic levels of the output ports Tx1 and Tx2 fixed at a high level.

  In the AND gate G3, since the logic level of the input terminal G3a is high in the data period Td3, the logic level of the output terminal G3c is high when the logic level of the input terminal G3b is high, and the input terminal G3b When the logic level is low, the logic level of the output terminal G3c is low.

  With such a configuration, the logic level of the output port Tx3 and the logic level of the output port G3c, that is, the input port Rx2 in the microcomputer MC2, can be made the same, so that the microcomputer MC2 transmits the data in the data period Td3. 10-bit data can be received.

  Similarly, in the AND gate G2, the logic level of the input terminal G2a is high in the data period Td3. Therefore, when the logic level of the input terminal G2b is high, the logic level of the output terminal G2c is high. When the logic level of the input terminal G2b is low, the logic level of the output terminal G2c is low.

  With such a configuration, the logic level of the output port Tx3 and the logic level of the output port G2c, that is, the input port Rx1 in the microcomputer MC1, can be made the same, so that the microcomputer MC1 transmits the data in the data period Td3. 10-bit data can be received.

  Note that the microcomputer MC according to the first embodiment of the present invention is configured to fix the logic level of the output port to a high level during a period in which data is not output from its own output port. It is not limited. For example, the microcomputer MC may be configured to fix the logic level of the output port at a low level during the period. In this case, an operation equivalent to the above operation can be realized by replacing the AND gate G in the data communication system 301 with an OR gate.

  Each device in the data communication system 301 includes a computer, and an arithmetic processing unit such as a CPU in the computer reads a program obtained by stepping part or all of the above processing from a memory (not shown) and executes the program. Each of the programs of the plurality of apparatuses can be installed from the outside. The programs of the plurality of apparatuses are distributed while being stored in a recording medium.

  By the way, for example, in order to perform one-to-many communication in a plurality of devices including the UART, an RS-485 driver IC may be mounted for each device, and communication may be performed via the mounted RS-485 driver IC. . In this case, a space for mounting the RS-485 driver IC on the substrate is required, and the cost of the RS-485 driver IC is required.

  On the other hand, in the data communication system according to the first embodiment of the present invention, the microcomputers MC1, MC2, and MC3 are respectively output ports Tx1, Tx1, Tx2, and Tx3 during a period in which data is not output from the output ports Tx1, Tx2, and Tx3. The logic levels of Tx2 and Tx3 are fixed to a high level. For example, the communication control circuit CC11 includes microcomputers MC1 and MC2 belonging to the target group, and an AND gate G1. The AND gate G1 has an output terminal G1c connected to the input port Tx3 of the microcomputer MC3 not belonging to the target group, and input terminals G1a and G1b connected to the output ports Tx1 and Tx2 of the microcomputers MC1 and MC2, respectively. In the AND gate G1, when the logic levels of the input terminals G1a and G1b are high, the logic level of the output terminal G1c is high, and the logic level of at least one of the input terminals G1a and G1b is opposite to the high level. When it is at the low level, the logic level of the output terminal G1c becomes the low level.

  With such a configuration, for example, during the period in which the microcomputer MC1 outputs data from the output port Tx1, the logic level of the output port Tx1 of the microcomputer MC1 and the logic of the output terminal G1c, that is, the input port Rx3 in the microcomputer MC3, are output via the AND gate G1. Since the level is the same, the microcomputer MC3 can receive data transmitted by the microcomputer MC1 during the period.

  Also, for example, during the period in which the microcomputer MC2 outputs data from the output port Tx2, the logic level of the output port Tx2 of the microcomputer MC2 and the logic level of the input port Rx3 in the output terminal G1c, that is, the microcomputer MC3, are the same via the AND gate G1. Therefore, the microcomputer MC3 can receive data transmitted by the microcomputer MC2 during the period. Therefore, data can be transmitted from the microcomputer MC1 or the microcomputer MC2 to the microcomputer MC3 with a simple configuration using the AND gate G1.

  Therefore, in the communication control circuit CC11 according to the first embodiment of the present invention, data transmission can be performed between a plurality of communication circuits, and the circuit scale can be reduced.

  Although the data communication system according to the first embodiment of the present invention is configured to include the communication control circuits CC1, CC2, and CC3, the present invention is not limited to this. The data communication system may be configured to include at least one communication control circuit.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a communication control circuit that performs communication between communication circuits via a balanced cable as compared to the communication control circuit according to the first embodiment. The contents other than those described below are the same as those of the communication control circuit according to the first embodiment.

[Power supply system]
FIG. 3 is a diagram showing a configuration of a power supply system according to the second embodiment of the present invention.

  With reference to FIG. 3, the power supply system 501 includes a power supply apparatus 101, power generation apparatuses 511 </ b> A, 511 </ b> B, and 511 </ b> C, a household power supply 512, a system power supply 513, and a battery panel 514. The power supply apparatus 101 includes circuit units 10A, 10B, and 10C. The circuit unit 10A includes a control board CB4, a converter circuit 31A, and an inverter circuit 33A. Circuit unit 10B includes a control board CB5 and converter circuits 31B and 31C. The circuit unit 10C includes a control board CB6, a converter circuit 31D, and an inverter circuit 33B.

  Hereinafter, each of the power generation devices 511A, 511B, and 511C is also referred to as a power generation device 511. Each of the circuit units 10A, 10B, and 10C is also referred to as a circuit unit 10. Each of the control boards CB4, CB5, and CB6 is also referred to as a control board CB. Each of converter circuits 31A, 31B, 31C, and 31D is also referred to as converter circuit 31. Each of the inverter circuits 33A and 33B is also referred to as an inverter circuit 33.

  The power generation device 511 and the battery panel 514 and the converter circuit 31 are connected by a power line. The household power supply 512 and the system power supply 13 and the inverter circuit 33 are connected by a power line. Each converter circuit 31 and each inverter circuit 33 are connected by a power line.

  In FIG. 1, three control boards CB are representatively shown, but two or less or four or more control boards CB may be provided.

  The power supply system 501 is used, for example, for buffers of energy output from solar power generation, wind power generation, and the like in which generated power fluctuates, power failure countermeasures, and power sales to commercial systems.

  More specifically, the power generation devices 511A, 511B, and 511C in the power supply system 501 are specifically a solar power generation device and a wind power generation device, respectively. For example, when the power generation devices 511 </ b> A and 511 </ b> B receive sunlight, the power generation devices 511 </ b> A and 511 </ b> B convert the received solar energy into DC power and output the converted DC power to the power supply device 101. The power generation device 511C converts, for example, kinetic energy generated from a windmill that receives wind force into DC power, and outputs the converted DC power to the power supply device 101.

  For example, the power supply device 101 converts the DC power received from the power generation device 511 and outputs the converted power to the system power supply 513, the household power supply 512, and the battery panel 514. The power supply apparatus 101 converts, for example, power received from the battery panel 514 and the system power supply 513 and outputs the converted power to the household power supply 512.

  In the power supply apparatus 101, the control board CB is provided corresponding to the circuit unit 10. For example, the control board CB controls the converter circuit 31 based on the power generation amount of the power generation device 511 or the power storage amount of the battery panel 514 connected to the converter circuit 31 included in the corresponding circuit unit 10. The control board CB controls the inverter circuit 33 based on the state of the system power supply 513 or the household power supply 512 connected to the inverter circuit 33 included in the corresponding circuit unit 10, for example.

[Control board as a comparative example]
FIG. 4 is a diagram illustrating a configuration of a data communication system as a comparative example.

  Referring to FIG. 4, a data communication system 901 as a comparative example includes control boards CB94, CB95, CB96 and balanced cables Bp, Bn. The control board CB94 includes a microcomputer MC94 and a driver D94. Control board CB95 includes microcomputer MC95 and driver D95. Control board CB96 includes microcomputers MC96 and MC97 and drivers D96 and D97.

  Drivers D94 to D97 are provided corresponding to microcomputers MC94 to MC97, for example. Therefore, the control board CB96 on which two microcomputers are mounted requires a space for mounting two drivers, and is expensive because two drivers are mounted.

  Therefore, the communication control circuit according to the second embodiment of the present invention solves such a problem by the following configuration and operation.

  FIG. 5 is a diagram showing a configuration of a control information communication system according to the second embodiment of the present invention.

  Referring to FIG. 5, a control information communication system (data communication system) 401 includes control boards CB4, CB5, CB6 and balanced cables Bp, Bn. The control board CB4 includes a microcomputer (communication circuit) MC4 and a driver (relay circuit) D4. The control board CB5 includes a microcomputer (communication circuit) MC5 and a driver (relay circuit) D5. The control board CB6 includes microcomputers (communication circuits) MC6 and MC7, AND gates (logic gates) G4, G5 and G6, an OR gate G7, a driver (relay circuit) D6, a resistor R1, and a high level node Nh. including.

  The control boards CB4, CB5, and CB6 correspond to the control boards CB4, CB5, and CB6 included in the circuit units 10A, 10B, and 10C shown in FIG.

  Hereinafter, each of the microcomputers MC4 to MC7 is also referred to as a microcomputer MCd. Each of the drivers D4 to D7 is also referred to as a driver D. Each of the AND gates G4, G5, and G6 is also referred to as an AND gate G.

  The microcomputers MC4 to MC7 have the following functions in addition to the functions of the microcomputers MC1 to MC3 described in FIG.

  That is, the microcomputers MC can communicate with each other. Each microcomputer MC mounted on a different control board CB can perform communication via balanced cables Bp and Bn, for example, in order to increase resistance to noise during communication.

  For example, as shown in FIG. 3, the microcomputer MC4 is a control microcomputer for controlling the converter circuit 31A and the inverter circuit 33A included in the circuit unit 10A. The microcomputer MC5 is a control microcomputer for controlling the converter circuits 31B and 31C included in the circuit unit 10B, for example. The microcomputer MC6 is a control microcomputer for controlling the converter circuit 31D and the inverter circuit 33B included in the circuit unit 10C, for example.

  For example, the microcomputer MC7 acquires information such as the power generation amount of the power generation device 511, the power storage amount of the battery panel 514, and the load in the household power supply 512 from each converter circuit 33 and each inverter circuit 31 via the microcomputers MC4 to MC6. It is a centralized control microcomputer for controlling the microcomputers MC4 to MC6 based on the information.

  Microcomputers MC4 to MC7 have an output port for outputting data to the outside, an input port for inputting data from the outside, and a control port for outputting a control signal indicating a period for outputting data from the output port. .

  Specifically, the microcomputer MC6 has an output port Tx6, an input port Rx6, and a control port De6. The microcomputer MC7 has an output port Tx7, an input port Rx7, and a control port De7. The control signal is, for example, high active. The control signal may be low active.

  When the microcomputers MC4 to MC7 are talkers that output data from their own output ports, the logic levels of their own control ports are set to a high level. In addition, when the microcomputers MC4 to MC7 are listeners that do not output data from their own output ports, the logic levels of their own control ports are set to a low level.

  Specifically, for example, when the microcomputer MC6 becomes a talker, the logic level of the control port De6 is set to a high level. The remaining microcomputers MC4, MC5 and MC7 are listeners. In this case, for example, a set including the microcomputer MC6 and the microcomputer MC7 serving as a talker is a target group.

  Similarly, for example, when the microcomputer MC7 becomes a talker, the logic level of the control port De7 is set to a high level. The remaining microcomputers MC4, MC5, MC6 are listeners. In this case, for example, a set including the microcomputer MC7 and the microcomputer MC6 serving as a talker is a target group.

  The communication control circuit in the control information communication system 401 includes a set of microcomputers MC, two AND gates G, and a driver. Specifically, the communication control circuit CC21 includes microcomputers MC6 and MC7, an AND gate G4, a driver D6, and an AND gate G5. Communication control circuit CC22 includes microcomputer MC7, microcomputer MC6, AND gate G4, driver D6, and AND gate G6.

  AND gates G4 to G6 have the same functions as AND gates G1 to G3 shown in FIG.

  The AND gate G4 has an output terminal connected to the input port of the microcomputer MCd not belonging to the target group, and a plurality of input terminals connected to the output port of the microcomputer MCd belonging to the target group.

  The driver D6 does not belong to the input port Txd connected to the output terminal of the AND gate G4, the output port Rxd connected to the input port of each microcomputer MCd belonging to the target group via the AND gates G5 and G6, and the target group Bidirectional ports IPp and IPn connected to the input port and output port of the microcomputer MCd via a driver D, and a control port Ded are provided.

  AND gates G5 and G6 have a first input terminal connected to output port Rxd of driver D6, an output terminal connected to the input port of one microcomputer MCd belonging to the target group, and the other microcomputer MCd belonging to the target group. And a second input terminal connected to the output port.

  Specifically, for example, in the communication control circuits CC21 and CC22, the AND gate G4 is connected to the output terminal G4c connected to the input port Txd of the driver D6 and the output ports Tx6 and Tx7 of the microcomputers MC6 and MC7, respectively. It has input terminals G4a and G4b. That is, the output terminal G4c is connected from the input port Txd of the driver D6 to the microcomputer MC4 via the drivers D6 and D4, and is connected from the input port Txd of the driver D6 to the microcomputer MC5 via the drivers D6 and D5.

  For example, in the communication control circuit CC21, the AND gate G5 is connected to the input terminal G5b connected to the output port Rxd of the driver D6, the output terminal G5c connected to the input port Rx6 of the microcomputer MC6, and the output port Tx7 of the microcomputer MC7. And an input terminal G5a to be connected.

  For example, in the communication control circuit CC22, the AND gate G6 is connected to the input terminal G6b connected to the output port Rxd of the driver D6, the output terminal G6c connected to the input port Rx7 of the microcomputer MC7, and the output port Tx6 of the microcomputer MC6. And an input terminal G6a to be connected.

  In the AND gate G4, for example, when the logic levels of the input terminals G4a and G4b are high, the logic level of the output terminal G4c is high, and at least one of the logic levels of the input terminals G4a and G4b is low. In some cases, the logic level of the output terminal G4c becomes a low level.

  In addition, for example, when the logic levels of the input terminals G5a and G5b are high, the AND gate G5 has a logic level of the output terminal G5c and a logic level of at least one of the input terminals G5a and G5b is low. In the case of the level, the logic level of the output terminal G5c becomes a low level.

  In addition, for example, when the logic levels of the input terminals G6a and G6b are high, the AND gate G6 has a logic level of the output terminal G6c and a logic level of at least one of the input terminals G6a and G6b is low. In the case of the level, the logic level of the output terminal G6c becomes a low level.

  A voltage having a high logic level is supplied to the high level node Nh. The resistor R1 has a first end connected to the input end G6b of the AND gate G6 and a second end connected to the high level node Nh.

  The OR gate G7 has an output terminal G7c connected to the control port Ded of the driver D6, an input terminal G7a connected to the control port De7 of the microcomputer MC7, and an input terminal G7b connected to the control port De6 of the microcomputer MC6. Have.

  In the OR gate G7, for example, when the logic levels of the input terminals G7a and G7b are low, the logic level of the output terminal G7c is low, and at least one of the logic levels of the input terminals G7a and G7b is high. In some cases, the logic level of the output terminal G7c becomes a high level.

  FIG. 6 is a diagram showing a configuration of a driver in the control information communication system according to the second embodiment of the present invention.

  The driver D is specifically an RS-485 driver IC. The bidirectional ports IPp and IPn in the driver D are balancedly connected to the bidirectional ports IPp and IPn in the other driver D via balanced cables Bp and Bn, respectively.

  FIG. 6 shows the driver D6 as a representative. The following description can be similarly applied to the drivers D4 and D5.

  Referring to FIG. 6, driver D6 includes buffers B1 and B2. The buffer B1 has an input terminal B1a connected to the input port Txd, a control terminal B1c connected to the control port Ded, and bidirectional output terminals B1p and B1n connected to the bidirectional ports IPp and IPn, respectively.

  The buffer B2 has an output terminal B2a connected to the output port Rxd, a control terminal B2c connected to the control port Ded, and bidirectional input terminals B2p and B2n connected to the bidirectional ports IPp and IPn, respectively.

  For example, when the logical level of the control port Ded is high, the buffer B1 outputs data received from the input port Txd to the bidirectional ports IPp and IPn. Specifically, the buffer B1 converts the single-ended signal received from the input port Txd into a differential signal, and outputs the converted differential signal to the bidirectional ports IPp and IPn.

  For example, when the logic level of the control port Ded is low, the buffer B1 electrically disconnects the bidirectional output terminals B1p and B1n from itself and puts the bidirectional output terminals B1p and B1n into a high impedance state.

  For example, when the logical level of the control port Ded is low, the buffer B2 outputs the data received from the buffer B1 and the bidirectional ports IPp and IPn to the output port Rxd. Specifically, the buffer B2 converts the differential signal received from the buffer B1 and the bidirectional ports IPp and IPn into a single end signal, and outputs the converted single end signal to the output port Rxd.

  For example, when the logic level of the control port Ded is high, the buffer B2 electrically disconnects the output terminal B2a from itself and sets the output terminal B2a to a high impedance state. As shown in FIG. 5, the output terminal B2a is connected to the first terminal of the resistor R1 via the output port Rxd. Therefore, for example, when the logic level of the control port Ded is high, the logic level of the output terminal B2a of the buffer B2 is high.

  FIG. 7 is a time chart showing the operation of each communication control circuit in the control information communication system according to the second embodiment of the present invention.

  Referring to FIG. 7, microcomputers MC4 to MC7, for example, fix the logic level of the output port to a high level in the break period Tb5 until the timing td6s when data is not output from its own output port, and the control port Fix the logic level to low level.

  In the OR gate G7, in the break period Tb5, the logic levels of the input terminals G7a and G7b are low, so the logic level of the output terminal G7c is low.

  In the driver D6, since the logic level of the control port Ded is low in the break period Tb5, the state Sb1 of the buffer B1 is in a cut-off state in which the bidirectional output terminals B1p and B1n are in a high impedance state, and the buffer B2 The state Sb2 is a through state in which data received from the buffer B1 and the bidirectional ports IPp and IPn is output to the output port Rxd.

  In the driver D6, in the break period Tb5, the logic level of the output ports of the microcomputers MC4 and MC5 is high, and the state Sb2 of the buffer B2 is in the through state, so that the logic level of the output port Rxd is high.

  In the AND gate G4, since the logic levels of the input terminals G4a and G4b are high during the break period Tb5, the logic level of the output terminal G4c is high.

  In the AND gates G5 and G6, the logic levels of the input terminals G5a, G5b, G6a, and G6b become a high level during the break period Tb5, so that the logic levels of the output terminals G5c and G6c become a high level.

  Next, for example, the microcomputer MC6 sets the logic level of the control port De6 to the high level in the data period Td6 from the timing td6s at which data transmission is started to the timing td6e at which data transmission is ended.

  In the OR gate G7, the logic levels of the input terminals G7a and G7b are low level and high level, respectively, in the data period Td6, so that the logic level of the output terminal G7c is high level.

  In the driver D6, since the logic level of the control port Ded becomes high in the data period Td6, the state Sb1 of the buffer B1 is in a through state in which data received from the input port Txd is output to the bidirectional ports IPp and IPn. Further, the state Sb2 of the buffer B2 is a cut-off state in which the output terminal B2a is in a high impedance state, that is, the logic level of the output terminal B2a is high.

  For example, in the data period Td6, the microcomputer MC6 transmits 10-bit data including the start bit and the stop bit by switching the logic level of the output port Tx6 according to the data to be transmitted.

  In the AND gate G6, since the logic level of the input terminal G6b is high in the data period Td6, the logic level of the output terminal G6c is high when the logic level of the input terminal G6a is high, and the input terminal G6a When the logic level is low, the logic level of the output terminal G6c is low.

  With such a configuration, the logic level of the output port Tx6 and the logic level of the output port G6c, that is, the input port Rx7 in the microcomputer MC7 can be made the same, so that the microcomputer MC7 transmits the data in the data period Td6. 10-bit data can be received.

  In the AND gate G4, since the logic level of the input terminal G4b is high in the data period Td6, when the logic level of the input terminal G4a is high, the logic level of the output terminal G4c is high, and the input terminal G4a When the logic level is low, the logic level of the output terminal G4c is low.

  In the driver D6, since the state Sb1 of the buffer B1 is in the through state in the data period Td6, the logic level of the input port Txd, that is, the output port Tx6, and the logic level based on the differential signal in the balanced cables Bp and Bn are the same. can do. Thereby, the microcomputers MC4 and MC5 can receive the 10-bit data transmitted by the microcomputer MC6 in the data period Td6.

  Next, the microcomputers MC4 to MC7, for example, fix the logic level of the output port to the high level and set the logic level of the control port in the break period Tb6 from the timing td6e to td7s when data is not output from its own output port. Fix at low level.

  In break period Tb6, the states of OR gate G7, driver D6, and AND gates G4, G5, and G6 are the same as those described in break period Tb5, and therefore detailed description will not be repeated.

  Next, for example, in the data period Td7 from the timing td7s at which data transmission is started to the timing td7e at which data transmission is ended, the microcomputer MC7 sets the logic level of the control port De7 to a high level.

  In the OR gate G7, the logic levels of the input terminals G7a and G7b become high level and low level, respectively, in the data period Td7, so that the logic level of the output terminal G7c becomes high level.

  In the driver D6, since the logic level of the control port Ded becomes a high level in the data period Td7, the state Sb1 of the buffer B1 is in the through state, and the state Sb2 of the buffer B2 is in the cutoff state.

  For example, in the data period Td7, the microcomputer MC7 transmits 10-bit data including the start bit and the stop bit by switching the logic level of the output port Tx7 according to the data to be transmitted.

  In the AND gate G5, since the logic level of the input terminal G5b is high in the data period Td7, the logic level of the output terminal G5c is high when the logic level of the input terminal G5a is high, and the input terminal G5a When the logic level is low, the logic level of the output terminal G5c is low.

  With such a configuration, the logic level of the output port Tx7 and the logic level of the output terminal G5c, that is, the input port Rx6 in the microcomputer MC6 can be made the same, so that the microcomputer MC6 transmits the data in the data period Td7. 10-bit data can be received.

  In the AND gate G4, since the logic level of the input terminal G4a is high in the data period Td7, when the logic level of the input terminal G4b is high, the logic level of the output terminal G4c is high, and the input terminal G4b When the logic level is low, the logic level of the output terminal G4c is low.

  In the driver D6, since the state Sb1 of the buffer B1 is in the through state in the data period Td7, the logic level of the input port Txd, that is, the output port Tx7, and the logic level based on the differential signal in the balanced cables Bp and Bn are the same. can do. Thereby, the microcomputers MC4 and MC5 can receive the 10-bit data transmitted by the microcomputer MC7 in the data period Td7.

  The microcomputers MC4 to MC7, for example, fix the logic level of the output port to the high level and set the logic level of the control port to the low level in the break period Tb7 from the timing td7e to td8s when the data is not output from its own output port. Fix it.

  In break period Tb7, the states of OR gate G7, driver D6, and AND gates G4, G5, and G6 are the same as those described in break period Tb5, and therefore detailed description will not be repeated.

  Next, the driver D6 receives, for example, 10-bit data transmitted from the microcomputer MC4 or MC5 via the balanced cables Bp and Bn in the data period Td8 from timing td8s to td8e.

  For example, in the data period Td8, the microcomputers MC6 and MC7 fix the logic levels Tx6 and Tx7 of the output ports to the high level and the logic levels of the control ports De6 and De7 to the low level as in the break period Tb7. .

  In the driver D6, in the data period Td8, as in the break period Tb7, the logic level of the control port Ded is low, so that the state Sb1 of the buffer B1 is cut off and the state Sb2 of the buffer B2 is in the through state. Become.

  Therefore, in the driver D6, in the data period Td8, the logic level of the output port Rxd becomes the same as the logic level based on the differential signals in the balanced cables Bp and Bn.

  In the AND gate G5, since the logic level of the input terminal G5a is high in the data period Td8, when the logic level of the input terminal G5b, that is, the output port Rxd is high, the logic level of the output terminal G5c is high. When the logic level of the output port Rxd is low, the logic level of the output terminal G5c is low.

  In the AND gate G6, since the logic level of the input terminal G6a is high in the data period Td8, when the logic level of the input terminal G6b, that is, the output port Rxd is high, the logic level of the output terminal G6c is high. When the logic level of the output port Rxd is low, the logic level of the output terminal G6c is low.

  With this configuration, the logic level of the output port Rxd and the output terminals G5c and G6c, that is, the logic levels of the input ports Rx6 and Rx7 in the microcomputers MC6 and MC7 can be made the same. At Td8, 10-bit data transmitted from the microcomputer MC4 or MC5 can be received.

  Note that the microcomputer MCd according to the second embodiment of the present invention is configured to fix the logic level of the output port to a high level during a period in which data is not output from its own output port. It is not limited. For example, the microcomputer MCd may be configured to fix the logic level of the output port to a low level during the period. In this case, an operation equivalent to the above operation can be realized by replacing the AND gates G4 to G6 with an OR gate.

  The control information communication system 401 according to the second embodiment of the present invention is configured to include AND gates G5 and G6, but is not limited thereto. In the control board CB6, for example, when the microcomputer MC6 does not need to receive data transmitted by the microcomputer MC7, the AND gate G5 is not necessary. In this case, the output port Rxd of the driver D6 and the input port Rx6 of the microcomputer MC6 are directly connected. For example, when the microcomputer MC7 does not need to receive data transmitted by the microcomputer MC6, the AND gate G6 is not necessary. In this case, the output port Rxd of the driver D6 and the input port Rx7 of the microcomputer MC7 are directly connected.

  In the control information communication system 401 according to the second embodiment of the present invention, the microcomputers MC6 and MC7, the driver D6, the AND gates G4 to G6, and the OR gate are mounted on one control board CB. However, the present invention is not limited to this. The microcomputers MC6 and MC7, the driver D6, the AND gates G4 to G6, and the OR gate may be separately mounted on two or more control boards CB.

  As described above, in the control information communication system according to the second embodiment of the present invention, the microcomputers MC4 to MC7 fix the logic level of the output port to a high level during a period in which data is not output from the output port. For example, the communication control circuit CC22 includes microcomputers MC6 and MC7 belonging to the target group, and an AND gate G4. The AND gate G4 is connected to the input port of the microcomputer MC4 that does not belong to the target group via the drivers D6 and D4, and is connected to the input port of the microcomputer MC5 that does not belong to the target group via the drivers D6 and D5. G4c and input terminals G4a and G4b connected to the output ports Tx6 and Tx7 of the microcomputers MC6 and MC7, respectively. In the AND gate G4, when the logic levels of the input terminals G4a and G4b are high, the logic level of the output terminal G4c is high, and the logic level of at least one of the input terminals G4a and G4b is opposite to the high level. When it is at a low level, the logic level of the output terminal G4c becomes a low level.

  With such a configuration, for example, during the period in which the microcomputer MC6 outputs data from the output port Tx6, the logic level of the output port Tx6 of the microcomputer MC6 and the output terminal G4c, that is, the input ports of the microcomputers MC4 and MC5, via the AND gate G4. Since the logic levels are the same, the microcomputers MC4 and MC5 can receive data transmitted by the microcomputer MC6 during the period.

  Further, for example, during the period in which the microcomputer MC7 outputs data from the output port Tx7, the logic level of the output port Tx7 of the microcomputer MC7 and the logic level of the output port G4c, that is, the input ports of the microcomputers MC4 and M5, via the AND gate G4. Therefore, the microcomputers MC4 and MC5 can receive data transmitted by the microcomputer MC7 during the period. Therefore, data can be transmitted from the microcomputer MC6 or the microcomputer MC7 to the microcomputers MC4 and MC5 with a simple configuration using the AND gate G4.

  Therefore, in the communication control circuit CC22 according to the second embodiment of the present invention, data transmission can be performed between a plurality of communication circuits, and the circuit scale can be reduced.

  In the control information communication system according to the second embodiment of the present invention, the communication control circuit CC22 further includes a driver D6. The driver D6 has an input port Txd connected to the output terminal G4c of the AND gate G4, an output port Rxd connected to the input ports Rx6 and Rx7 of the microcomputers MC6 and MC7 via the AND gates G5 and G6, respectively, and the microcomputer MC4. Bidirectional ports IPp and IPn are connected to the input port and the output port via the driver D4, and are connected to the input port and the output port of the microcomputer MC5 via the driver D5. The driver D6 outputs a buffer B1 that outputs data received from its own input port Txd to the bidirectional ports IPp and IPn, and a buffer that outputs data received from the buffer B1 and bidirectional ports IPp and IPn from its own output port Rxd. And B2. The microcomputers MC6 and MC7 output to the driver D6 a control signal indicating an output period for outputting data from its own output ports Tx6 and Tx7. The buffer B1 sets its own output terminals B1p and B1n to a high impedance state outside the output period.

  With such a configuration, in the output period, the microcomputer MC6 or the microcomputer MC7 can transmit data to the microcomputer MC4 and the microcomputer MC5 while sharing the driver D6. Therefore, the driver D is provided for each microcomputer MCd. In comparison, the number of drivers D can be reduced. Thereby, the space for mounting the driver D can be saved, and the manufacturing cost can be reduced.

  In the control information communication system according to the second embodiment of the present invention, the buffer B2 sets its own output terminal B2a to the high level during the output period. Communication control circuit CC22 further includes an AND gate G6. The AND gate G6 has an input terminal G6b connected to the output terminal B2a of the buffer B2, an output terminal G6c connected to the input port Rx7 of the microcomputer MC7, and an input terminal G6a connected to the output port Tx6 of the microcomputer MC6. Have. In the AND gate G6, when the logic levels of the input terminals G6b and G6a are high, the logic level of the output terminal G6c is high, and at least one of the logic levels of the input terminals G6b and G6c is low. At the same time, the logic level of the output terminal G6c becomes a low level.

  With such a configuration, for example, during the period when the microcomputer MC6 outputs data from the output port Tx6, the logic level of the output port Tx6 of the microcomputer MC6 and the logic level of the output terminal G6c, that is, the input port Rx7 of the microcomputer MC7 are the same. Therefore, the microcomputer MC7 can receive data transmitted by the microcomputer MC6 during the period. Accordingly, the microcomputer MC6 can transmit data to the microcomputer MC7 belonging to the target group with a simple configuration using the AND gate G6.

  In addition, the microcomputer MC6 transmits data to the microcomputer MC4 and the microcomputer MC5 via the drivers D6 and D4 and the drivers D6 and D5, respectively, during a period in which data is output from the output port Tx6. Can receive data transmitted by the microcomputer MC4 and the microcomputer MC5 via the drivers D4 and D6 and the drivers D5 and D6, respectively, so that data is transmitted and received between the microcomputer MC6 and the microcomputer MC4 and the microcomputer MC5. Can do.

  Similarly, the microcomputer MC7 transmits data to the microcomputer MC4 and the microcomputer MC5 via the drivers D6 and D4 and the drivers D6 and D5, respectively, during the period in which data is output from the output port Tx7. Since MC7 can receive data transmitted by microcomputer MC4 and microcomputer MC5 via drivers D4 and D6 and drivers D5 and D6, respectively, data is transmitted and received between microcomputer MC7 and microcomputer MC4 and microcomputer MC5. be able to.

  Since other configurations and operations are the same as those of the data communication system according to the first embodiment, detailed description thereof will not be repeated here.

  The above embodiment should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The above description includes the following features.

[Appendix 1]
A communication control circuit in a data communication system in which three or more communication circuits having an output port for outputting data to the outside and an input port for inputting data from the outside can transmit / receive data to / from each other ,
The communication circuit fixes the logic level of the output port to a first logic level during a period in which data is not output from the output port.
A set of the communication circuits;
An output end connected to the input port of the communication circuit not belonging to the set; and a plurality of input ends connected to the output port of the communication circuit belonging to the set; When the logic level of the output terminal is the first logic level, the logic level of the output terminal becomes the first logic level, and the logic level of at least one of the input terminals is opposite to the first logic level. A logic gate whose logic level at the output end is the second logic level when it is at the second logic level;
The communication circuit is a microcomputer,
The first logic level and the second logic level are a high level and a low level, respectively.
The communication control circuit, wherein the logic gate is an AND gate.

DESCRIPTION OF SYMBOLS 10 Circuit unit 31 Converter 33 Inverter 101 Power supply apparatus 301 Data communication system 401 Control information communication system (data communication system)
501 Power supply system 511 Power generation device 512 Household power supply 513 System power supply 514 Battery panel B1, B2 Buffer Bp, Bn Balanced cable CC11, CC12, CC13, CC21, CC22 Communication control circuit CB1, CB4, CB5, CB6 Control board D4, D5 , D6 driver (relay circuit)
G1, G2, G3, G4, G5, G6 AND gate (logic gate)
G7 OR gate MC1, MC2, MC3, MC4, MC5, MC6, MC7 Microcomputer (communication circuit)
Nh High level node R1 Resistance

Claims (5)

A communication control circuit in a data communication system in which three or more communication circuits having an output port for outputting data to the outside and an input port for inputting data from the outside can transmit / receive data to / from each other ,
The communication circuit fixes the logic level of the output port to a first logic level during a period in which data is not output from the output port.
A set of the communication circuits;
An output end connected to the input port of the communication circuit not belonging to the set; and a plurality of input ends connected to the output port of the communication circuit belonging to the set; When the logic level of the output terminal is the first logic level, the logic level of the output terminal becomes the first logic level, and the logic level of at least one of the input terminals is opposite to the first logic level. A communication control circuit comprising: a logic gate having a logic level of the output terminal that is the second logic level when the output logic level is the second logic level. The communication control circuit further includes:
An input port connected to the output terminal of the logic gate, an output port connected to the input port of each communication circuit belonging to the set, and the input port and the output port of the communication circuit not belonging to the set A first buffer for outputting data received from the input port to the bidirectional port, and data received from the first buffer and the bidirectional port. A relay circuit including a second buffer that outputs from the output port,
Each of the communication circuits belonging to the set outputs a control signal indicating an output period for outputting data from its output port to the relay circuit,
2. The communication control circuit according to claim 1, wherein the first buffer puts its output terminal in a high impedance state outside the output period. In the output period, the second buffer sets its output terminal to the first logic level,
The communication control circuit further includes:
A first input terminal connected to an output terminal of the second buffer; an output terminal connected to the input port of one of the communication circuits belonging to the set; and the other communication circuit belonging to the group. And when the logic levels of the first input terminal and the second input terminal are the first logic level, the logic level of the output terminal is the first input terminal. When the logic level of at least one of the first input terminal and the second input terminal is the second logic level, the logic level of the output terminal is the second logic level. The communication control circuit according to claim 2, comprising a logic gate. Each comprising three or more communication circuits having an output port for outputting data to the outside and an input port for inputting data from the outside;
The communication circuit fixes the logic level of the output port to a first logic level during a period in which data is not output from the output port.
further,
Provided corresponding to the set of communication circuits, connected to the input port of the communication circuit not belonging to the corresponding set, and connected to the output port of each communication circuit belonging to the corresponding set And when the logic level of the plurality of input terminals is the first logic level, the logic level of the output terminal is the first logic level, and at least one of A data communication system comprising a plurality of logic gates, wherein the logic level of the output terminal is the second logic level when the logic level of the input terminal is a second logic level opposite to the first logic level .   A power supply apparatus comprising the communication control circuit according to claim 1.

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