JP2015155872A - Histogram generation device and laser radar device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a histogram to be created while simplifying a configuration and eliminating a dead time.

SOLUTION: By a multiphase clock generation circuit 22, N clock signals having the same clock cycles and phase differences are generated. N counters 30 are provided in correspondence with the clock signals, have the same count-up cycle, a measured signal and the corresponding clock signal are inputted to the counters, is counted up for each of a prescribed number of clocks of the corresponding clock signals, and a count rate is outputted. N memories 36 are provided in accordance with the N counters, and frequency is stored to each address. A histogram generation circuit 32 is provided in accordance with the N counters, and the signal level of the measured signal is sampled for each of the prescribed number of clocks. When the sampled signal level is a prescribed level, frequency stored to a corresponding memory address is read with respect to the count rate outputted by the counter, a specified value is added up, and stored.

COPYRIGHT: (C)2015,JPO&INPIT

Description

  The present invention relates to a histogram creation device and a laser radar device, and more particularly to a histogram creation device and a laser radar device for obtaining a flight time of laser light to an object with high reliability even when there is disturbance light.

  Conventionally, as shown in FIG. 16, the time measurement circuit and the histogram creation circuit are configured as separate circuits. The time measurement circuit measures the elapsed time from the start time (start signal) to the event occurrence time (stop signal), and transmits the measurement result to the histogram creation circuit. The histogram creation circuit creates a histogram representing the event occurrence frequency for each time in the memory based on the measurement result output from the time measurement circuit. The process waiting buffer is interposed between the time measurement circuit and the histogram creation circuit, and temporarily buffers the measurement result when the next event occurs during the histogram creation process associated with a certain event.

  The time measuring circuit measures the time from the start signal to the stop signal and outputs the result. If the time resolution can be low, the number of clocks can be counted with a simple counter. However, if high time resolution is required, multiple counters can be operated at different phases, and the average value of the results is obtained. Need to be devised. Examples thereof are shown in FIGS. 17 and 18 (Patent Document 1).

  Also, the histogram creation process is a process of designating an address of the histogram memory, reading the contents, adding +1 (+ w when integrating weights), and writing back. In the configuration shown in FIG. 16, the histogram creation circuit executes a sequence for updating the contents of the histogram memory, and a histogram is created in the histogram memory. FIG. 19 shows this in a timing diagram. FIG. 20 shows the relationship between the histogram memory address and the time measurement value. The created histogram is read from the histogram memory and output under the control of the histogram reading circuit.

  As a conventional technique for improving the throughput (processing capacity per unit time) of the histogram memory, there is a method called interleaving in which the configuration is shown in FIG. 21 and the operation is shown in FIG. In this method, the memory is divided into a plurality of banks, and the operation timing of each bank is shifted to operate in parallel, thereby improving the throughput. In the example of FIG. 22, each of the memories A and B is divided into four banks, banks a, b, c, and d, and the memory update process can be started for each clock by shifting the operation timing by one clock. The memory A and the memory B constitute a so-called double buffer, and while the histogram is being created in the memory A, the histogram of the memory B is read and the creation of the histogram in the memory A is completed. Later, the memory A and the memory B are switched. If interleaving is not used, the memory update process can be started only every four clocks, so the throughput is quadrupled by using the interleaving method.

JP2013-205092A

  However, in the time measurement circuit, when it is desired to increase the time resolution, there is a problem that not only the time resolution of the time measurement circuit but also the throughput of the histogram memory needs to be improved accordingly. Further, even if a process waiting buffer is interposed, it is difficult to process without missing an event (output of the time measuring circuit), and there is a problem that some dead time occurs.

  An object of the present invention is to provide a histogram creation device and a laser radar device that can simplify the configuration and create a histogram while eliminating dead time.

  In order to achieve the above object, a histogram creation device according to a first aspect of the present invention is a multiphase clock generation unit that generates and outputs N clock signals having the same clock period and having a phase difference; N counters provided corresponding to N clock signals and having the same count-up period and receiving the corresponding clock signals, and for each predetermined number of clocks by the corresponding clock signals N counters for counting up and outputting count values, N memories for storing the frequency at each address, N counters for storing the frequency at each address, and N counters N histogram generators provided to receive a signal under measurement and a corresponding clock signal, and receive the signal under measurement for each of the predetermined number of clocks by the corresponding clock signal. When the sampled signal level is a predetermined level, the frequency stored in the corresponding memory address, which is predetermined for the count value output from the counter, is read. And N histogram generating units that add and store predetermined values.

  According to the first invention, the multi-phase clock generation unit generates and outputs N clock signals, is provided corresponding to the N clock signals, and has the same count-up cycle. The N counters to which the corresponding clock signals are input counts up every predetermined number of clocks according to the corresponding clock signals, outputs the count value, and N histograms provided corresponding to the N counters When the signal to be measured and the corresponding clock signal are input by the creation unit, the signal level of the signal to be measured is sampled for each predetermined number of clocks by the corresponding clock signal, and the sampled signal level is a predetermined level, With respect to the count value output from the counter, the address of the corresponding memory among the N memories provided corresponding to the N counters It reads the frequency being paid, and stores by adding a predetermined value.

  In this way, N counters provided corresponding to the N clock signals, N memories, and N histogram creating units provided corresponding to the N counters are used. By storing the frequency at each address of each memory, the configuration can be simplified and a histogram can be created while eliminating dead time.

  In the first aspect of the invention, the multi-phase clock generation unit has N clocks having the same clock period and having a phase difference of 1 / N of the count-up period with any of the other clock signals. A signal may be generated and output.

  In the first invention, the count-up cycle may be a time longer than a time required for the histogram creation unit to read out the frequency from the memory and add and store a predetermined value.

  In the first invention, each of the N memories may have a double buffer configuration having two memories.

  A laser radar device according to a second aspect of the invention receives a light emitting unit that emits laser light a plurality of times and laser light reflected by an object, and outputs the signal under measurement corresponding to reception of light including the laser light. The maximum frequency is searched from the frequency stored in each address of the N memories of the histogram generating device and the histogram generating device of the first invention, and the searched maximum frequency is stored. A maximum value search unit for obtaining a flight time of the laser beam to the object based on the address, and the counter of the histogram creation device is configured so that each time the laser beam is emitted by the light emitting unit. Start counting.

  According to the second invention, the light emitting unit emits the laser beam a plurality of times, and the light receiving unit outputs the signal under measurement corresponding to the light including the laser beam reflected by the received object, and searches for the maximum value. The maximum frequency is searched from the frequency stored in each address of the N memories of the histogram creation device by the unit, and the flight time of the laser light to the object is determined based on the address where the searched maximum frequency is stored. Ask for. If the flight time of the laser beam to the object is obtained, it can be converted into the distance to the object.

  In this way, by searching for the maximum frequency stored in each address of the N memories of the histogram creation device, the configuration is simplified, and the flight time of the laser beam to the object is reduced while eliminating the dead time. Can be determined appropriately.

  In the second aspect of the invention, the light receiving unit includes a plurality of light receiving elements, and outputs the signal under measurement representing the number of reactions of the light receiving elements. And the corresponding clock signal is input, the signal level of the signal under measurement is sampled every predetermined number of clocks by the corresponding clock signal, and the sampled signal level is a predetermined level, the count output from the counter The frequency stored in the corresponding memory address, which is predetermined for the value, may be read, and a numerical value corresponding to the number of reactions represented by the signal under measurement may be added and stored.

  According to a third aspect of the present invention, there is provided a multi-phase clock generator for generating and outputting N clock signals having the same clock period and having a phase difference, and outputting the N clock signals to the N clock signals. N histogram generating units provided correspondingly and having the same count-up period and to which a signal under measurement and a corresponding clock signal are input, from the first register to the last register for storing the frequency Up to M registers, and in the clock cycle of the corresponding clock signal, the frequency stored in each register is stored in the previous register so as to circulate, and stored in the head register. When the signal level of the signal under measurement is a predetermined level when the frequency is stored in the last register, the frequency stored in the head register is set to a predetermined value. It is configured to include the N-number of the histogram creating unit to be stored in the last register by adding a.

  According to the third invention, the multi-phase clock generation unit generates N clock signals having the same clock period and having a phase difference, provided corresponding to the N clock signals, and , Having N registers from the first register to the last register for storing the frequency by N histogram generators having the same count-up period and receiving the signal under measurement and the corresponding clock signal The frequency stored in each register is stored in the previous register so as to circulate in the clock cycle of the corresponding clock signal, and the frequency stored in the first register is stored in the last register. When the signal level of the signal under measurement is a predetermined level, a predetermined value is added to the frequency stored in the head register and stored in the tail register.

  As described above, the multi-phase clock generation unit that generates N clock signals and M registers, and the number of N clocks that circulate the frequency stored in each register in the clock cycle of the corresponding clock signal. By using this histogram creation unit, it is possible to simplify the configuration and create a histogram while eliminating dead time.

  Further, in the third invention, the clock period is set to a time equal to or more than a time from when a predetermined value is added to the frequency at which the histogram creation unit is stored in the register to determine the added value to be stored in the register It is good.

  According to a fourth aspect of the present invention, there is provided a laser radar device according to a fourth aspect of the present invention, wherein a light emitting unit that emits laser light a plurality of times and a laser beam reflected by an object are received, and the signal under measurement corresponding to light reception including the laser light. A maximum frequency from the frequencies stored in the M registers of each of the N histogram generating units of the histogram generating apparatus, A maximum value search unit for obtaining a flight time of laser light to the object based on the register in which the searched maximum frequency is stored, and the histogram creation unit of the histogram creation device includes: Each time the laser beam is emitted by the light emitting unit, the circulation of the frequency stored in each register in the clock cycle is started.

  According to the fourth invention, the light emitting unit emits the laser light a plurality of times, the light receiving unit outputs the signal under measurement corresponding to the laser light reflected by the received object, and the maximum value searching unit The maximum frequency is searched from the frequencies stored in each of the M registers of the N histogram generating units of the histogram generating device, and the laser beam to the object is determined based on the register in which the searched maximum frequency is stored. Find the flight time.

  In this way, by searching for the maximum frequency stored in the M registers of each of the N histogram generating units of the histogram generating apparatus, the configuration is simplified, and dead time is eliminated, and the object is detected. The flight time of the laser beam can be obtained appropriately.

  In the fourth invention, the light receiving section includes a plurality of light receiving elements, and outputs the signal to be measured representing the number of reactions of the light receiving elements. The histogram generating section of the histogram generating apparatus includes the head register When the signal level of the signal under measurement is a predetermined level when the frequency stored in the last register is stored in the last register, the number of reactions represented by the signal under measurement in the frequency stored in the head register It is also possible to add a numerical value corresponding to and store it in the last register.

  As described above, according to the histogram creation device and the laser radar device of the present invention, it is possible to create a histogram while simplifying the configuration and eliminating the dead time.

It is a block diagram which shows the functional structure of the laser radar apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the functional structure of the histogram creation apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the multiphase clock generation part which concerns on the 1st Embodiment of this invention. It is a figure which shows the timing chart which illustrates operation | movement of the histogram preparation apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the functional structure of the laser radar apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the functional structure of the histogram creation apparatus which concerns on the 2nd Embodiment of this invention. It is a timing chart which illustrates operation of a histogram creation device concerning a 2nd embodiment of the present invention. It is a block diagram which shows the functional structure of the laser radar apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the functional structure of the histogram creation apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the functional structure of the laser radar apparatus which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the functional structure of the histogram creation apparatus which concerns on the 4th Embodiment of this invention. It is a figure which shows the structure of the multiphase clock generation part which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the functional structure of the laser radar apparatus which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the functional structure of the histogram creation apparatus which concerns on the 5th Embodiment of this invention. It is a figure which shows the timing chart which illustrates operation | movement of the histogram creation apparatus which concerns on the 5th Embodiment of this invention. It is a figure which shows the example which comprised the time measurement circuit and the histogram preparation circuit as a separate circuit. It is a figure which shows the example which calculates | requires the average value of a result by operating a some counter with a different phase. It is a figure which shows the example which calculates | requires the average value of a result by operating a some counter with a different phase. It is a figure which shows the example which a histogram preparation circuit performs the sequence which updates the content of a histogram memory, and produces a histogram in a histogram memory. It is a figure which shows the example of the relationship between the address of a histogram memory, and a time measurement value. It is a figure which shows the example of the prior art which improves the throughput of a histogram memory. It is a figure which shows the example of interleaving.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, substantially the same or equivalent components or parts are denoted by the same reference numerals.

<Principle of the invention>
Here, the timing at which the laser beam is emitted is set as the starting time, and the timing at which the laser beam reflected by the object is detected is set as the event occurrence time. Since this time is a round-trip flight time until the laser beam reaches the object and returns, the distance to the object can be calculated using the speed of light.

  At this time, in order to reduce the influence of disturbance light such as sunlight, a histogram is created from a plurality of time measurement results, and a frequently measured time is employed as a measurement value. To achieve a distance resolution of 15 centimeters (the required distance resolution varies depending on the system requirements, 15 centimeters is an example), the time resolution needs to be 1 ns, and the histogram needs to be created with that time resolution. There is.

  However, since the histogram creation process is a process of adding weights to the bins of the histogram corresponding to the event occurrence time, that is, the flight time, the designated memory contents are read, added, and written back. Considering a memory that can be actually used, it is very difficult to complete a series of processes in 1 ns. Therefore, assuming that the actual values are 4 ns for reading the memory contents, 4 ns for the addition, and 8 ns for the write back, it takes 16 ns to process one memory cycle.

  Therefore, if the histogram memory is divided into N (for example, 16) banks and the operation timing of each bank is shifted by 1 ns, the time resolution of 1 ns can be realized as a whole. In the present embodiment, the operation timing of each bank is supplied from a multiphase clock generation circuit.

<First Embodiment>
A laser radar device according to a first embodiment of the present invention will be described. As shown in FIG. 1, a laser radar device 100 according to a first embodiment of the present invention includes a light receiving element 10, a pulse shaping unit 12, a laser control unit 14, a laser light emitting element 16, and a histogram creation device. 20 and an output unit 90.

  The light receiving element 10 receives the laser light reflected by the laser light emitted from the laser light emitting element 16. The light receiving element 10 outputs a voltage pulse to the pulse shaping unit 12 in response to light.

  The pulse shaping unit 12 shapes the voltage pulse input from the light receiving element 10 and outputs the waveform to the histogram creating apparatus 20 as a stop signal.

  The laser control unit 14 instructs the laser light emitting element 16 to emit laser light, and simultaneously outputs a start signal to the histogram creating device 20. Further, the laser control unit 14 instructs the laser light emitting element 16 to emit laser light a plurality of times.

  The laser light emitting element 16 emits laser light to the object in accordance with a light emission instruction input from the laser control unit 14.

  Each time the laser light emitting element 16 emits laser light, the histogram creating device 20 measures the time from the time when the laser light is emitted until the light receiving element 10 receives the laser light, and displays a histogram representing the frequency for each time. Create and output to the output unit 90. Since the light receiving element 10 also reacts to sunlight or the like, the histogram creation device 20 statistically processes the measurement results of a plurality of times in order to more appropriately separate the target laser light from other disturbance light.

  As shown in FIG. 2, the histogram creation device 20 includes a multiphase clock generation circuit 22, 16 histogram creation units 29 </ b> A to 29 </ b> P, and a maximum value search circuit 42.

  As shown in FIG. 3C, the multi-phase clock generation circuit 22 sets φG as the original clock 1 GHz (cycle 1 ns) and outputs clock signals φ1 and φ2 of 250 MHz (cycle 4 ns) to 1 ns with a two-stage Johnson counter. Generate by shifting. Further, using the flip-flop, the clock signal φ2 is delayed by 1 ns to generate the clock signals φ3 to φ16, and the generated clock signals φ1 to φ16 are respectively converted into the counters 30A to 30P and the histogram generating circuits 32A to 32P. And each of the histogram memories 36A to 36P. Apparently, {φ1, φ5, φ9, φ13}, {φ2, φ6, φ10, φ14}, {φ3, φ7, φ11, φ15}, {φ4, φ8, φ12, φ16} have the same waveform.

  In addition, as shown in FIG. 3B, the multiphase clock generation circuit 22 generates clock signals φA and φB using another two-stage Johnson counter. Further, the generated clock signals φA and φB are set to φA1 and φB1, and each of the clock signals φA1 and φB1 is delayed by 1 ns by using flip-flops (not shown) one by one, and the clock signals φA2 to φA16, and φB2 φB16 is generated, and the generated clock signals φA1 to φA16 and φB1 to φB16 are output to the counters 30A to 30P, the histogram creation circuits 32A to 32P, and the histogram memories 36A to 36P, respectively. The Johnson counter shown in FIG. 3B is configured using a D-type flip-flop with an enable terminal so that it operates only when φ1 and φ2 are zero. Therefore, the period of φA and φB is a time corresponding to four periods of φ1. Timing for memory update is generated from the clock signals φA and φB. For example, memory reading is performed when φA = 1 and φB = 0, addition is performed when φA = 1 and φB = 1, and writing back is performed when φA = 0.

  Further, as shown in FIG. 3A, the multiphase clock generation circuit 22 generates a count signal and outputs the count signal to the counters 30A to 30P.

  Specifically, a start signal input from the laser control unit 14 is input to generate a count signal, and the generated count signal is used as a reset terminal of a flip-flop (C) that generates clock signals φ1 to φ16, and a clock The signals φA and φB are output to the reset terminal of the flip-flop constituting the Johnson counter (B) that generates the signals φA and φB. Thus, the generation of each clock signal is started in accordance with the start signal input from the laser control unit 14. In the first embodiment, an example in which a multiphase clock is generated from φG has been described, but a multiphase clock may be generated using a PLL (Phase Locked Loop). In that case, various modifications are made according to the specifications of the PLL.

  The histogram creation device 20 includes histogram creation units 29A to 29P corresponding to each bank. Since the configurations of the histogram creation units 29A to 29P are the same, the histogram creation unit 29A will be described below as an example.

  The histogram creating unit 29A includes a counter 30A, a histogram creating circuit 32A, a memory switching circuit 34A, a histogram memory 36A, a histogram memory 38A, and a histogram reading circuit 40A.

  The counter 30A is arranged so as to correspond to the histogram creation circuit 32A, and receives the clock signals φ1, φA1, φB1 and the count signal input from the multiphase clock generation circuit 22 as input, and every four clocks by the clock signal φ1. Counting up is performed, and the count value is output to the histogram creating circuit 32A. In the present embodiment, the count-up is performed when φA1 and φB1 are 0 and the clock signal φ1 rises, and thus the count-up is performed every four clocks by the clock signal φ1. . The count value represents the address of the memory in the histogram memory 36A corresponding to the histogram bin created by the histogram creation circuit 32A. Note that 4 clocks is a count-up cycle and corresponds to the time required for the above-described processing of one memory cycle by the histogram creation unit 32A. Further, the count-up cycle may be longer than the time required for the processing of one memory cycle by the histogram creation unit 32A.

  The histogram generation circuit 32A receives the clock signals φ1, φA1, φB1, and the count signal input from the multiphase clock generation circuit 22 and the stop signal input from the pulse shaping unit 12, and receives four clocks based on the clock signal φ1. Each time, the signal level of the stop signal is sampled, and when the stop signal is 1, the frequency of the memory address in the histogram memory 36A indicated by the count value of the counter 30A is indicated by the address of the memory in the histogram memory 36A. Is added, and 1 is added and stored in the address of the memory. In this embodiment, when φA1 and φB1 are 0 and the clock signal φ1 rises, the signal level of the stop signal is sampled. As a result, the stop signal is sampled every four clocks by the clock signal φ1.

  The memory switching circuit 34A switches the access destination by the histogram creation circuit 32A to either the histogram memory 36A or the histogram memory 38A. Here, the histogram memory 36A and the histogram memory 38A constitute a so-called double buffer. That is, when the histogram creation circuit 32A creates a histogram for the histogram memory 36A, the histogram read circuit 40A reads the histogram stored in the histogram memory 38A, and the histogram creation process and histogram of the histogram creation circuit 32A. When the histogram reading process of the reading circuit 40A is completed, the memory switching circuit 34A switches the access destination by the histogram creating circuit 32A to the histogram memory 38A.

  The histogram reading circuit 40A reads a histogram stored in one of the histogram memory 36A and the histogram memory 38A that is not accessed by the histogram creating circuit 32A, and outputs it to the maximum value search circuit 42. The histogram reading circuit 40A initializes the memory contents after reading the histogram stored in either the histogram memory 36A or the histogram memory 38A.

  Note that the number of histogram bins and the bit width of data created by the histogram creation units 29A to 29P may be considered as design requirements.

  In addition, the histogram can be read with a high degree of freedom in design because it is sufficient to secure time in the operation cycle of the entire system. If time permits, the histograms may be read sequentially by sequentially operating the histogram reading circuits 40A to 40P, or the histograms may be read in parallel by operating the histogram reading circuits 40A to 40P in parallel. You may comprise so that time may be shortened.

  The maximum value search circuit 42 searches for the maximum value from all bins based on the histogram output from each of the histogram readout circuits 40A to 40P, and the flight time determined in advance for the bin of the maximum value. (That is, the distance) is output to the output unit 90. When there are a plurality of bins having the maximum value, the first bin may be adopted as the search result, or the center bin may be adopted as the search result. Further, the flight time corresponding to the bin with the second largest value may be output to the output unit 90 as the flight time corresponding to the bin with the third largest value. Thus, since the flight time of the laser can be obtained, the distance to the object can be measured.

  FIG. 4 is a timing chart illustrating the operation of the histogram creation device 20. The histogram generators 29B to 29P receive the clock signals φ2 to φ16, φA2 to φA16, and φB2 to φB16 obtained by shifting the clock signals φ1, φA1, and φB1 input to the histogram generator 29A by 1 ns, thereby generating a histogram. In order to perform the same operation as the unit 29A, first, the operation of the histogram creation unit 29A will be described.

  With the start signal input from the laser controller 14 as an input, the multiphase clock generation circuit 22 generates a count signal and also generates clock signals φ1, φA1, and φB1. The counter 30A starts counting when the input count signal becomes 1, and counts up in a count-up cycle based on the clock signals φ1, φA1, and φB1. The count value takes an integer value from 0 and is output to the histogram creation circuit 32A as a memory address in the histogram memory 36A corresponding to the histogram bin created by the histogram creation circuit 32A. In FIG. 4, serial numbers in the whole histogram created by the 16 histogram creating units 29 </ b> A to 29 </ b> P are shown in parentheses together with the count value. The serial number takes a value of 16 skips and corresponds to a bin in the entire histogram created by the 16 histogram creation units 29A to 29P. The initial value of the serial number in the histogram creation units 29B to 29P is 1 to 15.

  Next, the case where the stop signal becomes 1 will be described in detail. The histogram creation circuit 32A samples the stop signal at the count up (update) timing of the counter 30A (φA1 and φB1 are 0 and the clock signal φ1 rises). As an address in the histogram memory 36A corresponding to the histogram bin created by the histogram creation circuit 32A, the value stored in the memory at the address is updated.

  In the example of FIG. 4, in the counter 30A, the stop signal is 1 at the timing of counting up to the count values 3 and 4, and the values stored in the memory addresses 3 and 4 in the histogram memory 36A are updated. The In the counter 30B, the stop signal is 1 at the timing of counting up to the count values 3 and 4, and the values stored in the memory addresses 3 and 4 in the histogram memory 36B are updated. In the counter 30C, the stop signal is 0 at the timing of counting up to the count value 3, but the stop signal is 1 at the timing of counting up to the count value 4, and the memory in the histogram memory 36C The value stored in the address 4 is updated. In the counter 30P, the stop signal is 1 at the timing of counting up to the count value 3, and the value stored in the address 3 of the memory in the histogram memory 36P is updated. Since the stop signal is 0 at the timing of up, the value stored in the memory address 4 in the histogram memory 36P is not updated.

  Further, in the counter 30A, the stop signal is 1 in the vicinity of the timing of counting up to the count value 6, but since the stop signal is 0 at the timing of counting up to the count value 6, the memory in the histogram memory 36A The value stored in the address 6 is not updated. On the other hand, in the counter 30B, the stop signal is 1 at the timing of counting up to the count value 6, and the value stored in the memory address 6 in the histogram memory 36B is updated. Also in the counter 30C, the stop signal is 1 at the timing of counting up to the count value 6, and the value stored at the memory address 6 in the histogram memory 36C is updated.

  When updating the value stored in the histogram memory 36A, the histogram creating circuit 32A is based on the clock signals φA1 and φB1, and the histogram memory 36A acquired from the counter 30A when the clock signals φA = 1 and φB = 0. The value stored in the memory at the designated address is read from the histogram memory 36A based on the address in the memory, and 1 is added to the value read when the clock signal φA = 1 and φB = 1. The value added when φA = 0 is written back to the memory at the designated address.

  Each time laser light is emitted by the laser light emitting element 16, the counter 30A and the histogram creating circuit 32A operate as described above. The counters 30B to 30P and the histogram creation circuits 32B to 32P operate in the same manner for each set. Thus, a histogram representing the frequency for each flight time is created based on the frequency stored in each address of the histogram memories 36A to 36P.

  As described above, according to the laser radar device 100 according to the first embodiment, 16 counters provided corresponding to 16 clock signals, 16 histogram memories, and 16 The frequency is stored in each address of the 16 histogram memories using the 16 histogram generating units provided corresponding to the counters of the above, thereby simplifying the configuration and eliminating the dead time, A histogram representing the frequency for each of the time of flight can be created. Further, by searching for the maximum value of the frequency stored in each address of the 16 histogram memories of the histogram creation device 20, the flight time of the laser beam to the target can be appropriately obtained.

  In addition, the counter and the histogram memory are paired and operated with a cycle time that does not cause a dead time, and a plurality of the groups are operated at different timings, so that a dead time due to the memory cycle time does not occur. Necessary time resolution can be obtained.

  In addition, since the counter and the histogram memory are combined and operated at a cycle time that does not cause a dead time, a process waiting buffer between the counter and the histogram process is not required, and the configuration can be simplified.

  In addition, since it is not necessary to improve the accuracy of the counter alone, the configuration can be simplified by reducing the average value calculation circuit and the like for increasing the accuracy.

  Note that the present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the gist of the present invention.

  In the first embodiment, the case where the count value is an integer value from 0 has been described as an example, but the present invention is not limited to this. For example, a serial number may be used as the count value. In this case, a value of 16 skips is used as the count value, such as the value written together with the count value in FIG.

  In the first embodiment, the case where the clock signals φA2 to φA16 and φB2 to φB16 are generated by delaying the clock signals φA and φB by 1 ns has been described. However, the present invention is not limited to this. For example, as in the case of generating the clock signals φA and φB, the clock signals φ2 and φ3 are input, the clock signals φA2 and φB2 are input, the clock signals φ3 and φ4 are input, and the clock signals φA3 and φB are input. A circuit that generates φB3 and a circuit that generates clock signals φA4 and φB4 with clock signals φ4 and φ5 as inputs may be used.

  In the first embodiment, the case where the histogram creation device is used in the laser radar device has been described. However, the present invention is not limited to this. For example, the histogram creation device may be applied to a measuring instrument such as an oscilloscope and a scientific measurement field such as radiation physics.

<Second Embodiment>
Next, a second embodiment will be described. In addition, about the part which becomes the structure and effect | action similar to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The second embodiment is different from the first embodiment in that there are a plurality of light receiving elements.

  A laser radar apparatus according to the second embodiment of the present invention will be described. As shown in FIG. 5, a laser radar device 200 according to the second embodiment of the present invention includes a plurality of light receiving elements 10, a plurality of pulse shaping units 12, an adding unit 202, a laser control unit 14, The laser light emitting element 16, the histogram creation device 220, and the output unit 90 are provided.

  The plurality of light receiving elements 10 are realized by a photodiode array, and receive the laser light emitted from the laser light emitting element 16 and reflected by the object. Each of the light receiving elements 10 responds to light and outputs a voltage pulse to the pulse shaping unit 12 corresponding to each of the light receiving elements 10.

  The adder 202 identifies the number of reacted light receiving elements based on each of the waveform shaped voltage pulses input from each of the pulse shaping sections 12, and the number of reacted light receiving elements and a stop composed of voltage pulses. The signal is output to the histogram creation device 220.

  Each time the laser light emitting element 16 emits laser light, the histogram creating device 220 measures the time from the time when the laser light is emitted until the plurality of light receiving elements 10 receive the laser light, and receives light that reacts every time. A histogram representing the number of elements as a frequency is created and output to the output unit 90. As shown in FIG. 6, the histogram creation device 220 includes a multiphase clock generation circuit 22, 16 histogram creation units 292 </ b> A to 292 </ b> P, and a maximum value search circuit 42.

  The histogram creation device 220 includes histogram creation units 292A to 292P corresponding to each bank. Since the configurations of the histogram creation units 292A to 292P are the same, the histogram creation unit 292A will be described below as an example.

  The histogram creating unit 292A includes a counter 30A, a histogram creating circuit 232A, a memory switching circuit 34A, a histogram memory 36A, a histogram memory 38A, and a histogram reading circuit 40A. FIG. 7 is a timing chart illustrating the operation of the histogram creation device 220. The added value Wx shown in FIG. 7 is a value corresponding to the number of light receiving elements that have reacted to light.

  The histogram generation circuit 232A receives the clock signals φ1, φA1, φB1, and the count signal input from the multiphase clock generation circuit 22 and the stop signal input from the adder 202, and receives the clock signal φ1 every four clocks. Further, when the signal level of the stop signal is sampled and the stop signal is 1, the frequency of the address of the memory in the histogram memory 36A indicated by the count value of the counter 30A is indicated by the address of the memory in the histogram memory 36A. The value of the number of reacted light receiving elements input from the reading / adding unit 202 is added and stored in the address of the memory.

  Note that the other configuration and operation of the laser radar device 200 according to the second embodiment are the same as those of the first embodiment, and thus the description thereof is omitted.

  As described above, according to the laser radar device 200 according to the second embodiment, 16 counters provided corresponding to 16 clock signals, 16 histogram memories, and 16 The frequency of the light receiving element that has reacted to each address of the 16 histogram memories is stored using the 16 histogram creation units provided corresponding to the counters of the above, thereby simplifying the configuration and eliminating the dead time. However, it is possible to create a histogram representing the frequency for each flight time of the laser light. Further, by searching for the maximum value of the frequency of the light receiving element that has been reacted and stored in each address of the 16 histogram memories of the histogram creation device 220, it is possible to appropriately obtain the flight time of the laser light to the object. .

<Third Embodiment>
Next, a third embodiment will be described. In addition, about the part which becomes the structure and effect | action similar to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The third embodiment is different from the first embodiment in that it has a single memory configuration.

  A laser radar apparatus according to the third embodiment of the present invention will be described. As shown in FIG. 8, a laser radar device 300 according to the third embodiment of the present invention includes a light receiving element 10, a pulse shaping unit 12, a laser control unit 14, a laser light emitting element 16, and a histogram creation device. 320 and an output unit 90.

  Each time the laser light emitting element 16 emits laser light, the histogram creation device 320 measures the time from when the laser light is emitted until the light receiving element 10 receives the laser light, and displays a histogram representing the frequency for each time. Create and output to the output unit 90. As shown in FIG. 9, the histogram creation device 320 includes a multiphase clock generation circuit 22, 16 histogram creation units 294 </ b> A to 294 </ b> P, and a maximum value search circuit 42.

  The histogram creation device 320 includes histogram creation units 294A to 294P corresponding to each bank. Since the configurations of the histogram creation units 294A to 294P are the same, the following description will be given taking the histogram creation unit 294A as an example.

  The histogram creating unit 294A includes a counter 30A, a histogram creating circuit 32A, a histogram memory 36A, and a histogram reading circuit 340A.

  The histogram reading circuit 340A reads the histogram stored in the histogram memory 36A and outputs it to the maximum value search circuit 42. Note that the histogram reading circuit 340A initializes the memory contents after reading the histogram stored in the histogram memory 36A.

  In addition, about the other structure and effect | action of the laser radar apparatus 300 which concern on 3rd Embodiment, since it is the same as that of 1st Embodiment, description is abbreviate | omitted.

  As described above, according to the laser radar apparatus 300 according to the third embodiment, in the single memory configuration, the 16 counters provided corresponding to the 16 clock signals and the 16 histograms are provided. Using a memory and 16 histogram generators corresponding to 16 counters, the frequency is stored at each address of the 16 histogram memories, thereby simplifying the configuration and eliminating the dead time. However, it is possible to create a histogram representing the frequency for each flight time of the laser light. Further, by searching for the maximum value of the frequency stored in each address of the 16 histogram memories of the histogram creation device 320, the flight time of the laser beam to the target can be appropriately obtained.

<Fourth embodiment>
Next, a fourth embodiment will be described. In addition, about the part which becomes the structure and effect | action similar to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The fourth embodiment is different from the first embodiment in that a start signal is generated by a multiphase clock generation circuit.

  A laser radar apparatus according to the fourth embodiment of the present invention will be described. As shown in FIG. 10, a laser radar device 400 according to a fourth embodiment of the present invention includes a light receiving element 10, a pulse shaping unit 12, a laser control unit 414, a laser light emitting element 16, and a histogram creation device. 420 and an output unit 90 are provided.

  The laser control unit 414 receives a start signal from the histogram creation device 420 and simultaneously instructs the laser light emitting element 16 to emit laser light.

  Each time the laser light emitting element 16 emits laser light, the histogram creation device 420 measures the time from when the laser light is emitted until the light receiving element 10 receives the laser light, and displays a histogram representing the frequency for each time. Create and output to the output unit 90. As shown in FIG. 11, the histogram creation device 420 includes a multiphase clock generation circuit 422, 16 histogram creation units 296 </ b> A to 296 </ b> P, and a maximum value search circuit 42.

  As shown in FIG. 12F, the multi-phase clock generation circuit 422 uses φG as the original clock 1 GHz (cycle 1 ns) and outputs 250 MHz (cycle 4 ns) clock signals φ1 and φ2 by 1 ns using a two-stage Johnson counter. Create by staggering. Further, using a flip-flop, the clock signal φ2 is delayed by 1 ns to generate clock signals φ3 to φ16, and each of the generated clock signals φ1 to φ16 is output to each of the histogram creation circuits 32A to 32P.

  Further, as shown in FIG. 12E, the multiphase clock generation circuit 422 generates the clock signals φA1 and φB1 using another two-stage Johnson counter. Further, each of the generated clock signals φA1 and φB1 is delayed by 1 ns to generate clock signals φA2 to φA16 and φB2 to φB16, and each of the generated clock signals φA1 to φA16 and φB1 to φB16 is represented as a histogram. It outputs to each of the creation circuits 32A-32P. The Johnson counter shown in FIG. 12E is configured using a D-type flip-flop with an enable terminal so that it operates only when the clock signals φ1 and φ2 are zero.

  In addition, as shown in FIG. 12D, the multiphase clock generation circuit 422 receives a count-on signal (asynchronous to the multiphase clock) that is a signal for turning on the count signal as an input. The clock signal φA1, φB1, φ1, and φ2 are all simultaneously sampled at a timing of 0, and if the signal is 1, the count signal is raised and output to each of the counters 30A to 30P. The rising edge of the count signal is detected, a start signal is generated, and output to the laser controller 414. The start signal generation circuit shown in FIG. 12D is configured by using a D-type flip-flop with an enable terminal so that it operates only when all of the clock signals φA1, φB1, φ1, and φ2 are 0 at the same time.

  The histogram creation device 420 includes histogram creation units 296A to 296P corresponding to each bank. Since the configurations of the histogram creation units 296A to 296P are the same, the histogram creation unit 296A will be described below as an example.

  The histogram creating unit 296A includes a counter 30A, a histogram creating circuit 32A, a memory switching circuit 34A, a histogram memory 36A, a histogram memory 38A, and a histogram reading circuit 40A.

  As described above, according to the laser radar device 400 according to the fourth embodiment, the start signal is generated by the multiphase clock generation circuit, and the 16 signals provided corresponding to the 16 clock signals are generated. The configuration is simplified by storing the frequency at each address of the 16 histogram memories using the counter, the 16 histogram memories, and the 16 histogram creating sections provided corresponding to the 16 counters. Thus, it is possible to create a histogram indicating the frequency of each flight time of the laser light while eliminating the dead time. Further, by searching for the maximum value of the frequency stored in each address of the 16 histogram memories of the histogram creation device 420, the flight time of the laser light to the target can be appropriately obtained.

<Fifth embodiment>
Next, a fifth embodiment will be described. In addition, about the part which becomes the structure and effect | action similar to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the fifth embodiment, the histogram memory is composed of register groups that can be circulated in bin units, and the contents of the register groups are circulated one bin at a predetermined time (clock cycle) while the count signal is on. This is different from the first embodiment.

  A laser radar apparatus according to the fifth embodiment of the present invention will be described. As shown in FIG. 13, a laser radar device 500 according to a fifth embodiment of the present invention includes a light receiving element 10, a pulse shaping unit 12, a laser control unit 14, a laser light emitting element 16, and a histogram creation device. 520 and an output unit 90.

  Each time the laser light emitting element 16 emits laser light, the histogram creation device 520 measures the time from when the laser light is emitted until the light receiving element 10 receives the laser light, and displays a histogram representing the frequency for each hour. Create and output to the output unit 90. As shown in FIG. 14, the histogram creation device 520 includes a multiphase clock generation circuit 522, four histogram creation units 298 </ b> A to 298 </ b> D, and a maximum value search circuit 42.

  Similarly to FIG. 3C, the multi-phase clock generation circuit 522 sets φG as the original clock 1 GHz (cycle 1 ns) and outputs clock signals φ1 and φ2 of 250 MHz (cycle 4 ns) to 1 ns with a two-stage Johnson counter. Generate by shifting. Further, using the flip-flop, the clock signal φ2 is delayed by 1 ns to generate the clock signals φ3 and φ4, and the generated clock signals φ1 to φ4 are output to the adder circuits 532A to 532D, respectively. Note that the clock cycle of the clock signals φ1 to φ4 is a time longer than the time until an addition value stored in a register 530AM, which will be described later, is determined in the histogram creation unit 520.

  The multiphase clock generation circuit 522 generates a count signal and outputs the count signal to the registers 530A to 530D and the addition circuits 532A to 532D. It should be noted that the data stored in each of the registers 530A1 to 530AM, 530B1 to 530BM, 530C1 to 530CM, and 530D1 to 530DM provided in each of the histogram creation units 298A to 298D is the length of a unit that makes one round. The count signal is generated so that the count signal becomes 1. Further, for each of the histogram creation units 298A to 298D, a count signal input to the histogram creation units 298A to 298D is generated so that the circulation of each of the data stored in the register is delayed by 1 ns.

  The histogram creation device 520 includes histogram creation units 298A to 298D corresponding to each bank. Since the configurations of the histogram creation units 298A to 298D are the same, the histogram creation unit 298A will be described below as an example.

  The histogram creation unit 298A includes registers 530A1 to 530AM, an adder circuit 532A, and a histogram read circuit 540A.

  The registers 530A1 to 530AM store the frequencies corresponding to the histogram bins, respectively. In addition, the histogram creation unit 298A causes the previous registers 530A1 to 530A (M−1) to circulate the frequency stored in each of the registers 530A2 to 530AM in the clock cycle of the corresponding clock signal φ1. Store each one. Also, the histogram creation unit 298A inputs the frequency stored in the top register 530A1 to the adder circuit 532A. The output value of the adder circuit 532A is stored in the last register 530AM. At this time, the stop signal input to the adder circuit 532A is sampled, and when the stop signal is 1, the adder circuit 532A outputs a value obtained by adding 1 to the frequency stored in the register 530A1. Stored in the register 530AM.

  The histogram reading circuit 540 reads the histogram stored in the registers 530A1 to 530AM and outputs it to the maximum value search circuit 42. Note that the histogram reading circuit 540A initializes the memory contents after reading the histograms stored in the registers 530A to 530AM. When there are a plurality of light receiving elements as shown in the second embodiment, the number of reacted light receiving elements may be added.

  FIG. 15 is a timing chart illustrating the operation of the histogram creation device 520. The operations of the histogram creation units 298A to 298D are the same as the operation of the histogram creation unit 298A when the clock signal φ1 input to the histogram creation unit 298A, φ2 to φ4 obtained by shifting the clock signal φ1 by 1 ns, and the count signal are input. Hereinafter, the operation of the histogram creation unit 298A will be described.

  First, with the start signal input from the laser controller 14 as an input, the multiphase clock generation circuit 22 generates a count signal and a clock signal φ1. When the count signal is 1, the histogram creation unit 298A circulates the frequency corresponding to the histogram bins stored in the registers 530A1 to 530AM in the clock cycle based on the clock signal φ1.

  When the stop signal becomes 1, the histogram creation unit 298A samples the stop signal every clock cycle of the clock signal φ1, and if the stop signal is 1, the addition circuit 532A A value obtained by adding 1 to the frequency stored in the register 530A1 is stored in the last register 530AM.

  Each time laser light is emitted by the laser light emitting element 16, the histogram creating unit 298A operates as described above. Also, the histogram creation units 298B to 298D operate similarly. Accordingly, a histogram representing the frequency for each flight time is created based on the frequencies stored in the registers 530A1 to 530DM.

  As described above, according to the laser radar device 500 according to the fifth embodiment, M pieces of M histograms provided in each of the four histogram generation units provided corresponding to the four clock signals. By storing the frequencies in the M registers, it is possible to simplify the configuration and create a histogram representing the frequency for each flight time of the laser light while eliminating the dead time. Further, by searching for the maximum value of the frequency stored in the 4 × M registers of the histogram creation device 520, the flight time of the laser beam to the target can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Light receiving element 12 Pulse shaping part 14 Laser control part 16 Laser light emitting element 20 Histogram creation apparatus 22 Multiphase clock generation circuit 29 Histogram creation part 30 Counter 32 Histogram creation circuit 34 Memory switching circuit 36 Histogram memory 38 Histogram memory 40 Histogram reading circuit 42 Maximum value search circuit 90 Output unit 100 Laser radar device 200 Laser radar device 202 Addition unit 220 Histogram creation device 232 Histogram creation circuit 292 Histogram creation unit 294 Histogram creation unit 296 Histogram creation unit 298 Histogram creation unit 300 Laser radar device 320 Histogram creation device 340 Histogram reading circuit 400 Laser radar device 414 Laser control unit 420 Histogram creation device 422 Multiphase clock generation Generation circuit 500 Laser radar device 520 Histogram creation device 522 Multiphase clock generation circuit 530 Register 532 Addition circuit 540 Histogram readout circuit

Claims (10)

A multi-phase clock generator that generates and outputs N clock signals having the same clock period and having a phase difference;
N counters provided corresponding to the N clock signals and having the same count-up period and receiving the corresponding clock signals, each having a predetermined number of clocks corresponding to the corresponding clock signals N counters that count up and output count values,
N memories provided corresponding to the N counters for storing the frequency at each address;
N histogram generating units provided corresponding to the N counters, wherein a signal under measurement and a corresponding clock signal are input, and the signal under measurement for each predetermined number of clocks by the corresponding clock signal When the sampled signal level is a predetermined level, the frequency stored in the corresponding memory address, which is predetermined for the count value output from the counter, is read. N histogram creation units for adding and storing predetermined values;
Including a histogram creation device.   The multi-phase clock generation unit generates and outputs N clock signals having the same clock period and having a phase difference of 1 / N of any other clock signal and the count-up period. Item 2. The histogram creation device according to Item 1.   3. The histogram creation device according to claim 1, wherein the count-up cycle is set to a time equal to or longer than a time required for the histogram creation unit to read a frequency from the memory and add and store a predetermined value.   The histogram generating apparatus according to claim 1, wherein each of the N memories has a double buffer configuration having two memories. A light emitting unit that emits laser light multiple times;
A light receiving unit that receives the laser light reflected by the object and outputs the signal under measurement corresponding to the reception of the light including the laser light;
The histogram creation device according to any one of claims 1 to 4,
The maximum frequency is searched from the frequencies stored in the addresses of the N memories of the histogram generating device, and the flight time of the laser beam to the object is determined based on the address where the searched maximum frequency is stored. A maximum value search unit for obtaining
A laser radar device including:
The counter of the histogram creation device is a laser radar device that starts counting each time laser light is emitted by the light emitting unit. The light receiving unit includes a plurality of light receiving elements, and outputs the signal under measurement representing the number of reactions of the light receiving elements,
The histogram creation unit of the histogram creation device receives a signal to be measured and a corresponding clock signal, samples the signal level of the signal to be measured for each predetermined number of clocks by the corresponding clock signal, and the sampled signal level is When it is a predetermined level, the frequency stored in the corresponding memory address, which is predetermined with respect to the count value output from the counter, is read out, and the frequency according to the reaction number represented by the signal under measurement is read. 6. The laser radar device according to claim 5, wherein numerical values are added and stored. A multi-phase clock generator that generates and outputs N clock signals having the same clock period and having a phase difference;
N histogram generating units provided corresponding to the N clock signals and having the same count-up period and receiving the signal under measurement and the corresponding clock signal, for storing the frequency M registers from the first register to the last register, and in the clock cycle of the corresponding clock signal, the frequency stored in each register is stored in the previous register so as to circulate, If the signal level of the signal under measurement is a predetermined level when the frequency stored in the head register is stored in the tail register, a predetermined value is added to the frequency stored in the head register. N histogram generators stored in the tail register;
Including a histogram creation device.   The histogram according to claim 7, wherein the clock period is set to a time equal to or longer than a time until a sum value to be stored in the register is determined by adding a predetermined value to the frequency at which the histogram creation unit is stored in the register. Creation device. A light emitting unit that emits laser light multiple times;
A light receiving unit that receives the laser light reflected by the object and outputs the signal under measurement corresponding to the reception of the light including the laser light;
The histogram creation device according to claim 7,
A maximum frequency is searched from the frequencies stored in the M registers of each of the N histogram generating units of the histogram generating device, and the target is determined based on the register in which the searched maximum frequency is stored. A maximum value search unit for obtaining the flight time of laser light to an object,
A laser radar device comprising:
The histogram creation unit of the histogram creation device is a laser radar device that starts circulation of the frequency stored in each register in the clock cycle each time laser light is emitted by the light emitting unit. The light receiving unit includes a plurality of light receiving elements, and outputs the signal under measurement representing the number of reactions of the light receiving elements,
The histogram creation unit of the histogram creation device stores the frequency stored in the head register in the head register when the signal level of the signal under measurement is a predetermined level when storing the frequency in the tail register. The laser radar device according to claim 9, wherein a numerical value corresponding to the number of reactions represented by the signal under measurement is added to the frequency of the measurement and stored in the tail register.