JP2015133544A - Power measurement device and protection control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To omit the switching of a plurality of analog signals, and to improve the frequency characteristics of measurement data.SOLUTION: A power measurement device includes a plurality of conversion units for receiving a plurality of analog signals, and converting them into a plurality of measurement data, and a transmission unit for transmitting the plurality of measurement data to the outside. The plurality conversion units includes, respectively, a lowpass filter for passing the low band of analog input signals, a sample and hold section for sampling the output value of the lowpass filter every predetermined first period, and outputting the sampled values while holding over the period of next sample, an A/D conversion section performing A/D conversion of the output from the sample and hold section every second period shorter than the first period, before being outputted, and a calculation section for calculating the representative value of a plurality of values, subjected to A/D conversion in the period, as the measurement data every first period.

Description

  The present invention relates to a technique for measuring an analog signal.

  In Patent Document 1, a digital type protective relay that switches a plurality of analog input signals by a multiplexer, multiplexes the signals in a time division manner, converts them into a digital quantity by one A / D converter, and calculates them. An apparatus is described. This configuration is adopted in a protection device for a substation.

  Such a digital type protective relay device detects the presence or absence of a system fault by performing digital arithmetic processing on A / D converted data by a digital arithmetic means such as a microcomputer based on a predetermined program. Issue a trip command.

  Further, for example, a configuration has been proposed in which a high-speed sampling method is employed and an effective accuracy of 14 bits is ensured.

  In addition, it is known that an analog signal is sampled at a certain sampling frequency, and A / D conversion accuracy is improved by using a digital filter for error compression. As a result, it is known to share an input circuit for unifying the current full scale of the short-circuit / ground fault detection relay and unifying the voltage full scale regardless of the voltage class.

  In addition, it is proposed in IEC 61850 that is an international standard that an analog input signal input unit in a digital protection relay device is separated from a protection arithmetic unit and configured as a merging unit.

Japanese Patent No. 3186735

  However, when a plurality of analog signals are switched and input to one A / D converter using a multiplexer, it is necessary to wait until the transient state of the signal after switching the multiplexer is stabilized. The cause of the transient state is that the stray capacitance is generated in the signal line, and the waveform is dull due to the relation with the ON resistance of the multiplexer. Further, it takes time until the waveform becomes stable due to a switching time of the multiplexer and a ringing phenomenon which is a transient phenomenon at the time of switching the signal waveform. Because of these restrictions, high-speed switching cannot be performed, and there is a limit to speeding up sampling while maintaining A / D conversion accuracy.

  In order to solve the above problems, a power measurement device according to one embodiment of the present invention includes a plurality of conversion units that respectively receive a plurality of analog input signals and convert the plurality of measurement data into a plurality of measurement data, and a plurality of measurement data externally And a transmission unit for transmitting to. Each of the plurality of conversion units samples a low-pass filter that passes the low-pass of the analog input signal, and the output value of the low-pass filter for each predetermined first period. A sample-and-hold unit that holds and outputs over a period up to the first sample, an A / D converter that performs A / D conversion on the output of the sample-and-hold unit for each second period shorter than the first period, and a first A calculation unit that calculates, as measurement data, representative values of a plurality of values subjected to A / D conversion within a period for each period.

  According to one embodiment of the present invention, switching of a plurality of analog signals can be omitted and frequency characteristics of measurement data can be improved.

The structure of the merging unit of the Example of this invention is shown. It is a time chart which shows the operation timing of a merging unit. It is a flowchart which shows operation | movement of a merging unit. It is a time chart which shows the specific example of operation | movement of a merging unit. It is a time chart which shows the specific example of operation | movement of the modification of a merging unit. An example of a circuit structure of an error compression filter is shown. The frequency-gain characteristic of the analog input unit of a comparative example and the merging unit of an Example is shown. The frequency-phase characteristic of the analog input unit of a comparative example and the merging unit of an Example is shown. The structure of a protection control system is shown.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows the configuration of a merging unit according to an embodiment of the present invention.

  The merging unit 1000 converts, for each of a plurality of channels, a plurality of analog input signals 100a indicating temporal changes such as voltages and currents measured in the power system into analog voltage signals having a full scale of ± 10V, for example. The input converter 1a, the aliasing error prevention filter 1b which is an analog filter (FIL) for preventing the aliasing error due to the sample and hold in the subsequent stage, and the output signal of the aliasing error prevention filter 1b every predetermined period. A sample hold (S / H: Sample Hold) unit 1c that holds and analog signals output from the sample hold unit 1c are converted into digital signals by A / D conversion at intervals shorter than the sample hold unit 1c. A / D converter 1d and digital signal error are compressed as measurement data And a error press filter 1e is a digital filter that force (DF). The input converter 1a is an AUX PT (Auxiliary Potential Transformer) or an AUX CT (Auxiliary Current Transformer). The error compression filter 1e is configured by hardware, for example.

  The merging unit 1000 further includes a measurement data memory unit 1f that is a RAM for storing measurement data that is an output of the error compression filter 1e for a plurality of channels, a timing control unit 1g that supplies a control signal to each circuit, a CPU (Central A computing unit 1h such as a processing unit, a ROM 1i that stores programs and data used by the computing unit 1h, a work memory 1j that stores programs and data used by the computing unit 1h, and a LAN controller that controls communication with the outside ( LANCE) 1k and a physical chip (PHY controller) 1l connected to the outside for communication. Note that the LAN controller 1k and the physical chip 11 can be configured in two pairs to provide redundancy and improve communication reliability.

  The timing control unit 1g includes a sample hold command signal 100c indicating the sample hold timing of the sample hold unit 1c, an A / D conversion command signal 100d indicating the A / D conversion timing of the A / D converter 1d, and the error compression filter 1e. The reset signal 100e indicating the reset timing of the error, the operation clock signal 100j of the error compression filter 1e, the write signal 100f indicating the timing of writing to the measurement data memory unit 1f, and the operation start indicating the operation start timing of the arithmetic unit 1h The signal 100g is cyclically output at a predetermined cycle. Although not shown in the figure, the timing controller 1g is connected to a clock oscillator for supplying a clock signal as a reference for each signal.

  With this configuration, the merging unit 1000 takes an analog input signal from the power system, A / D converts it into quantization information, generates error measurement data by compressing the error, and outputs the output signal 100h to the communication network by the LAN controller 1k. It has a function of outputting as 100i. The merging unit 1000 is connected with devices for protection control calculation, measurement, and analysis calculation, which will be described later, via a communication network, and these constitute a function distribution system. That is, the merging unit 1000 provides measurement information obtained from an analog input signal in order to provide diversity applicable not only to protection control but also to functions such as measurement and signal analysis functions.

  FIG. 2 is a time chart showing the operation timing of the merging unit 1000.

  In this figure, (1) indicates the time of sample by the sample hold unit 1c. (2) shows the timing of the sample hold command signal 100c to the sample hold unit 1c. The sample hold period T1 of the sample hold unit 1c is, for example, an electrical angle of 3.75 °. The sample hold unit 1c samples an input with a certain sample hold command signal 100c and holds it until the next sample hold command signal 100c after T1. This hold period of length T1 is called a hold period. (3) shows the timing of the A / D conversion command signal 100d supplied to the A / D converter 1d. The A / D conversion cycle T2 of the A / D converter 1d is 1 / N of T1 (N is an integer of 2 or more), and the rising conditions of the signals (2) and (3) are synchronized. N is 16, for example. (4) shows the timing at which the A / D converter 1d outputs a digital signal.

  (5) shows the operation timing of the error compression filter 1e. The N digital signals t01 to t0N output from the A / D converter 1d during T1 are filtered, and an operation result is cyclically output every cycle T2.

  Here, as indicated by (5), the error compression filter 1e uses only the digital signals t01 to t0N that are A / D converted within the hold period, and the digital signal that is A / D converted outside the hold period. Are not used together with the digital signals t01 to t0N. Since the digital signal outside the hold period is not a signal sampled and held at the same time as the digital signals t01 to t0N, if the error compression filter 1e is the digital signal t01 to t0N within the hold period and the digital signal outside the hold period, When both of these are continuously filtered, a large difference is generated between the digital signals, and therefore a phase difference is generated between the measurement data output from the error compression filter 1e. In the error compression filter 1e of the present embodiment, since the plurality of digital signals within the hold period are signals sampled and held at the same time by the sample hold unit 1c, the difference between the data is small, and the error compression filter 1e. There is almost no phase difference between the measurement data output from. That is, the error compression filter 1e can handle a plurality of digital signals within the hold period as DC signals, and can statistically process the DC signals to compress errors included in the DC signals.

  (6) shows the timing for transferring the measurement data from the merging unit 1000 to the communication network. This measurement data is also output every T1.

  FIG. 3 is a flowchart showing the operation of the merging unit 1000.

  In step 3a, the sample hold unit 1c samples the analog signal output from the input converter 1a at the period T1, holds the sampled signal until the next sample, and outputs it. In step 3b, the A / D converter 1d performs A / D conversion on the output of the sample hold unit 1c at a period T2 and outputs the result as a digital signal. In step 3e, the calculation unit 1h determines whether or not A / D conversion of N samples has been completed. If it has been completed, the process proceeds to step 3f. If not, the process proceeds to step 3b. Let's get the next sample. In step 3f, the error compression filter 1e obtains representative data of N digital signals output from the A / D converter 1d as measurement data within the hold period. In step 3i, the timing control unit 1g stores the output of the error compression filter 1e in the measurement data memory unit 1f. In step 3b, the calculation unit 1h reads the measurement data stored in the measurement data memory unit 1f and transfers it to the outside by the LAN controller 1k. The merging unit 1000 repeats the above operation at a cycle T1.

  FIG. 4 is a time chart showing a specific example of the operation of the merging unit 1000.

  In this figure, (1) shows the waveform of the output of the input converter 1a. (2) shows a sample hold command signal 100c to the sample hold unit 1c. Here, it is shown that the sample hold command signal 100c is output at time t0 and at time t1 after T1. (3) shows the waveform of the output of the sample hold unit 1c. High-frequency noise is superimposed on this waveform. (4) shows an A / D conversion command signal 100d to the A / D converter 1d. The A / D conversion command signal 100d is output at a cycle of T2. (5) shows the waveform of the signal A / D converted at the timing of (4). Even in the hold period, the signal varies due to high frequency noise. (6) shows the timing of the digital signal output from the A / D converter 1d. A digital signal is output in accordance with the timing of (4). (7) shows the timing of error compression processing by the error compression filter 1e. The error compression filter 1e is reset and filtered by a reset signal 100e synchronized with the sample hold command signal 100c. As a result, the error compression filter 1e eliminates the digital signal input outside the target hold period, and calculates one measurement data based only on the digital signal within the target hold period. (8) shows the measurement data output from the error compression filter 1e in (7). The measurement data output in (7) is transmitted to the outside in synchronization with the next sample / hold command signal 100c. Thus, measurement data based on the analog input signal sampled and held at time t0 is transmitted at time t1.

  Here, a modified example of the merging unit 1000 will be described.

  The merging unit 1000 of the modified example includes a data selection unit between the A / D converter 1d and the error compression filter 1e.

  FIG. 5 is a time chart showing a specific example of the operation of the modified example of the merging unit 1000. This time chart is the same as the time chart when the data selection unit is not used, but the operation of (7) is different. (7) shows the operation of the data selection unit and the error compression filter 1e. The data selection unit stores N digital signals output from the A / D converter 1d within one hold period, deletes the maximum value and the minimum value from the n digital signals, and outputs N-2 pieces. Output a digital signal. Thereafter, the error compression filter 1e performs a filtering process on the N-2 digital signals output from the data selection unit. As a result, the error compression filter 1e obtains representative data within the hold period as measurement data from N-2 digital signals. Thereby, the error compression filter 1e can remove the influence of the largest noise from the digital signal within the hold period.

  FIG. 6 shows an example of the circuit configuration of the error compression filter 1e.

  The error compression filter 1e here is an FIR (Finite Impulse Response) type digital filter having no feedback loop. The error compression filter 1e includes sample delay units 5a, 5b, 5c, 5d, and 5e, multipliers 5l, 5m, 5n, 5o, 5p, 5q, and 5r, and adders 5f, 5g, 5h, 5i, 5j, and 5k. Including. The timing of the operation clocks of the sample delay devices 5a to 5e is the A / D conversion command signal 100d having the period T2. The reset timing of the sample delay devices 5a to 5e is the sample hold command signal 100c having the period T1. The sample delay units 5a to 5e store the digital signal Xin input from the A / D converter 1d at the period T2, and output it to the next sample delay unit at the next period. Multipliers 5l to 5r multiply Xin and sample delays 5a to 5e by coefficients, respectively. In the present embodiment, each coefficient of the multipliers 5l to 5r is 1.0. The adders 5f to 5k add the outputs of the multipliers 5l to 5r and output the measurement data. That is, the error compression filter 1e outputs the sum of the digital signals in the hold period as measurement data at the end of the hold period. Thereby, the representative value of the digital signal within the hold period can be calculated, and the influence of the noise of the digital signal on the representative value can be reduced. Further, by resetting the sample delay units 5a to 5e for each hold period and erasing the digital signals stored in the sample delay units 5a to 5e, only the digital signals within the hold period can be added. In addition, since the error compression filter 1e includes N-1 sample delay units and N-1 adders, it is possible to add all N digital signals that have been A / D converted within the hold period. it can.

  A modification of the error compression filter 1e will be described. The error compression filter 1e here is a circuit that adds the current sample and the past N-1 samples and calculates an average of N for each period T1. The calculation formula is shown by the following formula. The following equation represents the case where the multiplier coefficient is 1.0.

  The error compression filter 1e of the present embodiment resets all the sample delay devices to 0 at the period T1. As a result, the error compression filter 1e performs an operation using only the digital signal within one hold period. That is, the error compression filter 1e does not calculate the digital signal in one hold period and the digital signal in another hold period. Thereby, the error compression filter 1e can handle a digital signal within one hold period as a DC signal.

  A modification of the error compression filter 1e will be described.

  The error compression filter 1e of the modification may include a DFT (Discrete Fourier Transformer) processing unit. In this case, the DFT processing unit calculates the component Fk of each frequency k by performing the following calculation on the digital signal fn input from the A / D converter 1d at the period T2.

  Further, the error compression filter 1e according to the modified example obtains a DC component F0 represented by the following expression among Fk.

  Here, for simplicity, N is 8, and f0, f1,..., F7 indicate digital signals that are A / D converted at t (−7), t (−6),. As a result, the error compression filter 1e calculates the DC component of the digital signal of N samples within one hold period as measurement data.

  Hereinafter, the analog input unit of the comparative example and the merging unit 1000 of the present embodiment will be compared.

  The analog input unit of the comparative example converts a plurality of analog input signals into digital signals. The analog input unit of the comparative example includes a folding error prevention filter that is an analog filter and a sample hold unit for each of a plurality of channels of analog input signals. The analog input unit further includes a multiplexer, an A / D converter, and a digital filter. The aliasing error prevention filter filters the analog input signal, and the sample hold unit samples and holds the output of the aliasing error prevention filter at the period T1. Further, the multiplexer switches and outputs the outputs of the plurality of sample and hold units, the A / D converter converts the output of the multiplexer into a digital signal at a period T2, and the digital filter filters the output of the A / D converter. Harmonics for commercial power supply frequencies (50 Hz, 60 Hz, etc.) are removed. T2 is T1 / N. In this comparative example, N is 16. The sample hold unit of the comparative example is the same as the sample hold unit 1c of the example.

  FIG. 7A shows the frequency-gain characteristics of the analog input unit of the comparative example. In this figure, the horizontal axis indicates the frequency, and the vertical axis indicates the gain. f1 is a commercial power supply frequency. fs1 is the sample hold frequency of the sample hold unit of the comparative example. fs1 is 1 / T1. The gain characteristic 6a of the folding error prevention filter of the comparative example is a low-pass type, and prevents a folding error caused by the sample hold unit. That is, the aliasing error prevention filter of the comparative example passes the frequency component of fs / 2 or less. The gain characteristic 6b of the digital filter of the comparative example is a low-pass type that allows a frequency component equal to or less than f1 to pass, and removes a harmonic component with respect to f1. In other words, the digital filter of the comparative example passes the frequency component below the cutoff frequency. fc is a cut-off frequency fc of the digital filter, which is smaller than fs / N and about f1. Therefore, in the comparative example, the gain characteristic of the analog input unit including the aliasing error prevention filter and the digital filter is the same as the gain characteristic 6b of the digital filter. That is, in the comparative example, the pass band of the analog input unit is much narrower than the pass band of the gain characteristic 6a of the aliasing error prevention filter.

  Further, since the analog input unit of the comparative example requires time for switching the multiplexer, the sample hold period is limited to about 3.75 ° or 7.5 ° in electrical angle. Since the output of the A / D converter fluctuates greatly every sample and hold period T1, harmonic components are generated in the output of the A / D converter, and it is necessary to limit the band of the output of the A / D converter. is there. Therefore, it is difficult for the analog input unit to output a frequency component higher than the desired commercial power supply frequency. As a result, the data used for the protective relay device and the data used for measurement / analysis are acquired by separate A / D conversions.

  The gain characteristic of the aliasing error prevention filter 1b of the present embodiment is the same as the gain characteristic 6a of the aliasing error prevention filter of the comparative example. That is, the aliasing error prevention filter 1b of the present embodiment passes a frequency component equal to or less than fs / 2.

  FIG. 7B shows frequency-gain characteristics of the merging unit 1000 of the embodiment. The error compression filter 1e of the present embodiment can handle a digital signal within one hold period as a DC signal by performing computation using only the digital signal within one hold period. Do not narrow the bandwidth. Therefore, the gain characteristic 6c of the merging unit 1000 of the embodiment is not affected by the error compression filter 1e and is the same as the gain characteristic of the aliasing error prevention filter 1b. Therefore, the pass band of the merging unit 1000 of the embodiment is significantly wider than the pass band of the analog input unit of the comparative example. As a result, the output of the merging unit 1000 can be applied not only to a protective relay device using a frequency component near the fundamental wave of the commercial power supply frequency but also to measurement and signal analysis using broadband measurement data including harmonics. is there. This makes it possible to share the output of the merging unit 1000 between the protective relay device and measurement or signal analysis.

  FIG. 8 shows frequency-phase characteristics of the analog input unit of the comparative example and the merging unit of the example.

  In this figure, the horizontal axis indicates the frequency, and the vertical axis indicates the phase. In the phase characteristic 7a of the analog input unit of the comparative example, the phase difference between the frequencies f1−α and f1 + α is θ1. α is, for example, 10% of f1. Due to the characteristics of the digital filter of the comparative example, the phase delay increases as the frequency increases. On the other hand, in the phase characteristic 7b of the merging unit 1000 of the present embodiment, the phase difference between the frequencies f1−α and f1 + α is θ2. Since the input to the error compression filter 1e can be regarded as a DC signal, the error compression filter 1e has almost no phase change with respect to the frequency change, and the phase characteristic of the aliasing error prevention filter 1b is the phase characteristic of the merging unit 1000 of this embodiment. Appears as 7b. That is, θ2 is smaller than θ1.

  The merging unit 1000 can faithfully A / D convert an input analog input signal, and removes noise components generated during A / D conversion by the error compression filter 1e.

  Further, since the error compression filter 1e does not affect the transient delay of the merging unit 1000, the delay time of the merging unit 1000 is smaller than the delay time of the analog input unit of the comparative example.

  The merging unit 1000 of this embodiment has an A / D converter 1d for each channel, and since they operate synchronously and in parallel, the analog signal is not switched, so that broadband and highly accurate measurement data can be obtained. Can be output. Further, since the digital signal can be handled as a DC signal by calculating a digital signal that has been A / D converted within the hold period, the frequency characteristics of the measurement data can be improved. In addition, since the measurement data can be broadened in bandwidth and increased in accuracy, the aliasing error prevention filter 1b can be simplified, and the failure rate can be reduced and the characteristics can be stabilized.

  Hereinafter, a protection control system to which the present invention is applied will be described.

  FIG. 9 shows the configuration of the protection control system.

  This protection control system includes merging units (MU) 8a, 8b, 8c, protection units (P1, P2) IED (Intelligent Electronic Device) 8d, 8e, and a control unit (C1) IED 8f. (M1) IED8g for measurement, (OSC1) IED8h for oscilloscope, layer 2 switching hub (L2SW) 8i, supervisory control calculation unit (SCADA) 8j, human machine interface (HMI) unit 8k, external communication ( COM) part 8l.

  In this embodiment, the merging units 8a to 8c and the IEDs 8d to 8h are connected by a loop network 80a. This makes it possible to transfer measurement data from each of the merging units 8a to 8c to the IEDs 8d to 8h within a predetermined time. Further, each of the IEDs 8d to 8h is connected to the monitoring control calculation unit 8j, the HMI unit 8k, and the external communication unit 8l via the layer 2 switching hub 8i.

  Each of the merging units 8a to 8c corresponds to the merging unit 1000, generates measurement data based on an analog input signal taken from the power system, and transmits the measurement data to the network 80a at a predetermined cycle.

  Each of the IEDs 8d to 8h receives the measurement data from the merging unit and transmits the measurement data to other connected IEDs. The measurement data output from the merging units 8a to 8c can be shared not only in the protection units IED8d and 8e but also in a plurality of IEDs having different uses such as the control unit IED8f, measurement IED8g, and oscilloscope ID8h. The protection units IEDs 8d and 8e perform protection relay calculations based on measurement data from the merging unit. The control unit IED8f performs control calculations based on the measurement data from the merging unit. The measurement IED 8g performs measurement calculation based on measurement data from the merging unit. The oscilloscope ID 8h performs oscilloscope calculations based on measurement data from the merging unit. Thus, a protection control system to which the merging unit 1000 is applied can be constructed.

  In this embodiment, the loop configuration is used for explanation, but it goes without saying that the protection control system can be configured using a network topology such as a radial configuration other than the loop configuration.

  According to the present embodiment, since the band of the sampled and held signal is not narrowed, wideband measurement data can be acquired. Thereby, since measurement data can be used not only for the use of a protective relay device but also for measurement and analysis applications that handle a wide frequency band, unified measurement data can be shared.

  Terms in the expression of one embodiment of the present invention will be described. The power measuring device corresponds to the merging units 8a, 8b, 8c, 1000, and the like. The low-pass filter corresponds to the aliasing error prevention filter 1b and the like. The sample hold unit corresponds to the sample hold unit 1c and the like. The A / D converter corresponds to the A / D converter 1d and the like. The calculation unit corresponds to the error compression filter 1e and the like. The transmission unit corresponds to the LAN controller 1k, the physical chip 11 and the like. The first period corresponds to the sample hold period T1 and the like. The second period corresponds to the A / D conversion period T2. The first arithmetic unit corresponds to the protection units IED8d and 8e. The second arithmetic unit corresponds to the control unit IED8f, the measurement IED8g, the oscilloscope IED8h, and the like. The amount of alternating current electricity corresponds to voltage or current.

  The present invention is not limited to the above embodiments, and can be modified in various other forms without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1a: Input converter 1b: Folding error prevention filter 1c: Sample hold part 1d: A / D converter 1e: Error compression filter 1f: Measurement data memory part 1g: Timing control part 1h: Calculation part 1j: Work memory 1k: LAN Controller 11: physical chips 8a, 8b, 8c, 1000: merging units 8d, 8e: protection unit IED 8f: control unit IED 8g: measurement IED 8h: oscilloscope IED 8j: monitoring control calculation unit 8k: HMI unit 8l: external Communication unit 80a: network

Claims (7)

A plurality of analog input signals are respectively input, and a plurality of conversion units that respectively convert into a plurality of measurement data,
A transmitter for transmitting the plurality of measurement data to the outside;
With
Each of the plurality of conversion units is
A low pass filter that passes the low pass of the analog input signal, and
A sample-and-hold unit that samples the output value of the low-pass filter every predetermined first period, and holds and outputs the sampled value over a period until the next sample;
An A / D converter for A / D converting and outputting the output of the sample and hold unit every second period shorter than the first period;
For each of the first periods, a calculation unit that calculates representative values of a plurality of values that have been A / D converted within the period, as measurement data;
including,
Power measuring device. The calculation unit adds a plurality of values subjected to the A / D conversion within the period for each of the first periods, and calculates the representative value based on a result of the addition.
The power measuring device according to claim 1. The calculation unit initializes the addition for each first period.
The power measuring device according to claim 2. The first period is N (N is an integer of 2 or more) times the second period,
The calculation unit adds the A / D-converted N values within the period.
The power measuring device according to claim 3. The first period is N (N is an integer of 2 or more) times the second period,
The calculation unit adds N-2 values excluding the maximum value and the minimum value among the N values subjected to the A / D conversion within the period.
The power measuring device according to claim 3. A power measuring device that converts a plurality of analog input signals indicating the amount of alternating current electricity of the power system into a plurality of measurement data, and
Using any one of the plurality of measurement data, a first arithmetic device that performs the operation of the protective relay;
Using any one of the plurality of measurement data, a second arithmetic device that performs an operation different from that of the protective relay;
With
The power measuring device is
A plurality of converters that respectively input the plurality of analog input signals and convert the plurality of measurement data into the plurality of measurement data,
A transmission unit for transmitting the plurality of measurement data to either the first arithmetic device or the second arithmetic device;
With
Each of the plurality of conversion units is
A low pass filter that passes the low pass of the analog input signal, and
A sample-and-hold unit that samples the output value of the low-pass filter every predetermined first period, and holds and outputs the sampled value over a period until the next sample;
An A / D converter for A / D converting and outputting the output of the sample and hold unit every second period shorter than the first period;
For each of the first periods, a calculation unit that calculates representative values of a plurality of values that have been A / D converted within the period, as measurement data;
including,
Protection control system. The power measuring device, the first computing device, and the second computing device are connected by a loop network, and the power measuring device is connected in advance to the first computing device and the second computing device. Transferring the plurality of measurement data within a predetermined time;
The protection control system according to claim 6.

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