JP2015073002A - Compound semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device and a manufacturing method of the same, which can improve withstand voltage to a further degree.SOLUTION: A compound semiconductor device comprises: a channel layer 11; an electron supply layer 12 formed on the channel layer 11; a gate electrode 13, a source electrode 14 and a drain electrode 15. The drain electrode 15 includes a first part 15a which forms ohmic junction with the electron supply layer 12 and a second part 15b which extends on the side away from the gate electrode 13 across the first part 15a to reach a depth deeper than a top face of the channel layer 11 just below the first part 15a.

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  A nitride semiconductor has characteristics such as a high saturation electron velocity and a wide band gap. For this reason, various studies have been conducted on applying nitride semiconductors to high breakdown voltage and high output semiconductor devices using these characteristics. As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, GaN-based HEMTs using GaN as an electron transit layer and AlGaN as an electron supply layer have attracted attention.

  However, the conventional GaN-based HEMT has a problem of depletion below the drain electrode and a reduction in breakdown voltage associated therewith.

JP2013-21016A JP 2006-86354 A JP 2009-99678 A

  An object of the present invention is to provide a compound semiconductor device capable of further improving the breakdown voltage and a method for manufacturing the same.

  In one embodiment of the compound semiconductor device, a channel layer, an electron supply layer formed above the channel layer, and a gate electrode, a source electrode, and a drain electrode formed above the electron supply layer are provided. It has been. The drain electrode includes a first portion that is in ohmic contact with the electron supply layer and an upper surface immediately below the first portion of the channel layer on a side farther from the gate electrode than the first portion. And a second portion reaching a deep portion.

  In one embodiment of the method for manufacturing a compound semiconductor device, an electron supply layer is formed above the channel layer, and a gate electrode, a source electrode, and a drain electrode are formed above the electron supply layer. The drain electrode includes a first portion that is in ohmic contact with the electron supply layer and an upper surface immediately below the first portion of the channel layer on a side farther from the gate electrode than the first portion. And a second portion reaching a deep portion.

  According to the above compound semiconductor device or the like, the breakdown voltage can be improved while avoiding an increase in contact resistance.

It is a figure which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is a figure which shows the effect | action of the compound semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the method of manufacturing the compound semiconductor device which concerns on 2nd Embodiment to process order. FIG. 4B is a cross-sectional view illustrating a method of manufacturing the compound semiconductor device in the order of steps subsequent to FIG. 4A. FIG. 4B is a cross-sectional view illustrating a method of manufacturing the compound semiconductor device in the order of steps subsequent to FIG. 4B. It is sectional drawing which shows the modification of the compound semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the method of manufacturing the compound semiconductor device which concerns on 3rd Embodiment in process order. FIG. 7B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 7A. FIG. 7B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 7B. FIG. 7D is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 7C. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the method of manufacturing the compound semiconductor device which concerns on 4th Embodiment in process order. FIG. 9B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 9A. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 5th Embodiment. It is sectional drawing which shows the method of manufacturing the compound semiconductor device which concerns on 5th Embodiment in process order. FIG. 11B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 11A. It is sectional drawing which shows the outline | summary of the model of the 1st and 2nd simulation. It is a figure which shows the result of a 1st simulation. It is a figure which shows the result of a 2nd simulation. It is a figure which shows the result of a 3rd simulation.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a diagram illustrating a structure of a compound semiconductor device (GaN-based HEMT) according to the first embodiment. FIG. 1A is a cross-sectional view, and FIG. 1B is a layout diagram. FIG. 1A corresponds to a cross section taken along line I-I in FIG.

  In the first embodiment, as shown in FIG. 1, the electron supply layer 12 is formed above the channel layer 11, and the gate electrode 13, the source electrode 14, and the drain electrode 15 are formed above the electron supply layer 12. ing. The drain electrode 15 includes a first portion 15a that is in ohmic contact with the electron supply layer 12, and an upper surface immediately below the first portion 15a of the channel layer 11 on the side farther from the gate electrode 13 than the first portion 15a. And a second portion 15b reaching a deeper portion.

  In the first embodiment configured as described above, since the interface between the channel layer 11 and the electron supply layer 12 exists immediately below the first portion 15a, two-dimensional electrons are present in the vicinity of this interface of the channel layer 11. Gas (2DEG) is present. The first portion 15 a is in ohmic contact with the electron supply layer 12. Therefore, the resistance between the first portion 15a and the two-dimensional electron gas is low.

  Further, since the second portion 15b is formed so as to enter the channel layer 11, as compared with the reference example in which the second portion 15b shown in FIG. 2B is not formed, FIG. As shown, the potential gradient in the thickness direction of the channel layer 11 becomes gentle, and the potential gradient hardly changes even when the drain voltage increases. For this reason, depletion below the drain electrode 15 is sufficiently suppressed. That is, the depletion layer end 16 is unlikely to move down to the drain electrode 15. As a result, electric field concentration near the end of the drain electrode 15 on the gate electrode 13 side is suppressed, and avalanche breakdown is suppressed. Accordingly, the breakdown voltage can be further improved.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 3 is a sectional view showing the structure of a compound semiconductor device (GaN-based HEMT) according to the second embodiment.

In the second embodiment, as shown in FIG. 3, the buffer layer 27 is formed above the substrate 26, the channel layer 21 is formed above the buffer layer 27, and the electron supply layer 22 is formed above the channel layer 21. Is formed. The band gap of the electron supply layer 22 is larger than the band gap of the channel layer 21. As the substrate 26, for example, a p-type silicon substrate doped with B as an impurity or a silicon substrate not intentionally doped with an impurity is used. An example of a p-type silicon substrate is one having a thickness of 645 μm to 1 mm and doped with B at a concentration of 8 × 10 ¹⁹ ± 8 × 10 ¹⁸ cm ⁻³ . As the buffer layer 27, for example, an AlGaN layer having an Al composition of 20% to 100%, or a stacked body in which a plurality of AlN layers and GaN layers are alternately stacked is used. Even if an Al _x Ga _(1-x) N (0 <x ≦ 1) layer (AlN at the interface with the substrate 26) is used as the buffer layer 27, the Al composition decreases as the distance from the interface with the substrate 26 increases. Good. The thickness of the buffer layer 27 is, for example, 100 nm to 2 μm. As the channel layer 21, for example, a GaN (i-GaN) layer that is not intentionally doped with impurities is used. The thickness of the channel layer 21 is, for example, 100 nm to 1.2 μm. As the electron supply layer 22, for example, an AlGaN layer having an Al composition of 10% to 30% is used. The thickness of the electron supply layer 22 is, for example, 5 nm to 40 nm.

A protective film 28 is formed above the electron supply layer 22, and an opening 29 for a gate electrode is formed in the protective film 28. A gate insulating film 30 is formed so as to enter the opening 29, and a gate electrode 23 is formed above the gate insulating film 30. The conductive film 31 and the conductive film 32 are included in the gate electrode 23. As the protective film 28, for example, a silicon nitride film, a silicon oxide film, or a stacked body of a silicon nitride film and a silicon oxide film is used. The thickness of the protective film 28 is, for example, 20 nm to 500 nm. As the gate insulating film 30, for example, a film containing at least one selected from the group consisting of an Al ₂ O ₃ film, a SiO ₂ film, a SiN film, a HfO ₂ film, and an AlN film is used. The length of the opening 29 in the gate length direction is, for example, 0.5 μm to 4 μm. The thickness of the gate insulating film 30 is, for example, 40 nm ± 2 nm. For example, a TiN film is used as the conductive film 31, and an Al film is used as the conductive film 32, for example. The thickness of the conductive film 31 is, for example, 40 nm ± 10 nm, and the thickness of the conductive film 32 is, for example, 500 nm ± 100 nm.

An interlayer insulating film 33 that covers the gate electrode 23 is formed above the protective film 28. A source electrode opening 34 and a drain electrode opening 35 are formed in the interlayer insulating film 33 and the protective film 28. An opening 36 that penetrates the electron supply layer 22 and reaches the middle of the channel layer 21 is formed inside the opening 35 in plan view. The depth of the opening 36 with respect to the upper surface of the electron supply layer 22 is, for example, 0.3 μm to 0.7 μm. The distance between the end of the opening 35 on the gate electrode 23 side and the end of the opening 36 on the gate electrode 23 side is, for example, 0.1 μm to 0.8 μm. A source electrode 24 is formed in the opening 34, and a drain electrode 25 is formed in the opening 35 and the opening 36. A part of the source electrode 24 and a part of the drain electrode 25 are on the interlayer insulating film 33. The conductive film 37 and the conductive film 38 are included in both the source electrode 24 and the drain electrode 25. For example, a silicon oxide film is used as the interlayer insulating film 33. As the conductive film 37, for example, a film made of a material having a work function of less than 4.5 eV is used. Examples of the material having a work function of less than 4.5 eV include Al, Ti, TiN (metal rich), Ta, TaN (metal rich), Zr, TaC (metal rich), NiSi ₂ and Ag. The material having a low work function is used for the conductive film 37 in order to obtain a low contact resistance by reducing the barrier barrier with the semiconductor immediately below the source electrode 24 and the drain electrode 25. As the conductive film 38, for example, a film containing Al as a main material (for example, an Al film) is used. The conductive film 37 has a thickness of, for example, 1 nm to 100 nm, and the conductive film 38 has a thickness of, for example, 20 nm to 500 nm.

  The drain electrode 25 includes a first portion 25a that is ohmic-bonded to the electron supply layer 22 on the gate electrode 23 side with respect to the opening 36, and a channel layer 21 on the side farther from the gate electrode 23 than the first portion 25a. And a second portion 25b reaching a portion deeper than the upper surface immediately below the first portion 25a.

  In the second embodiment configured as described above, since the interface between the channel layer 21 and the electron supply layer 22 exists immediately below the first portion 25a, two-dimensional electrons are present in the vicinity of this interface of the channel layer 21. Gas is present. The first portion 25 a is in ohmic contact with the electron supply layer 22. Therefore, the resistance between the first portion 25a and the two-dimensional electron gas is low.

  Further, since the second portion 25 b is formed so as to enter the channel layer 21, depletion below the drain electrode 25 is sufficiently suppressed. As a result, electric field concentration near the end of the drain electrode 25 on the gate electrode 13 side is suppressed, and avalanche breakdown is suppressed. Accordingly, the breakdown voltage can be further improved.

  The depth of the opening 36, that is, the distance from the upper surface of the electron supply layer 22 at the lower end of the second portion 25b is preferably determined according to the breakdown voltage in the thickness direction required for the compound semiconductor device. .

  Next, a method for manufacturing the compound semiconductor device according to the second embodiment will be described. 4A to 4C are cross-sectional views illustrating a method of manufacturing the compound semiconductor device according to the second embodiment in the order of steps.

  First, as shown in FIG. 4A (a), a buffer layer 27, a channel layer 21, and an electron supply layer 22 are formed on a substrate 26 by, for example, metal organic vapor phase epitaxy (MOVPE). To do. Next, a protective film 28 is formed on the electron supply layer 22 by, for example, a plasma chemical vapor deposition (CVD) method. The protective film 28 may be formed by a thermal CVD method or an atomic layer deposition (ALD) method.

  Thereafter, an opening 29 is formed in the protective film 28 as shown in FIG. 4A (b). In the formation of the opening 29, a region where the opening 29 is to be formed is exposed, a resist pattern covering the other region is formed on the protective film 28, and a fluorine-based gas, for example, is used with this resist pattern as a mask. The protective film 28 is etched by a dry etching method. Then, this resist pattern is removed. After the opening 29 is formed, the gate insulating film 30 is formed on the protective film 28 by, for example, plasma CVD. The gate insulating film 30 is also formed inside the opening 29. Next, a conductive film 31 and a conductive film 32 are formed on the gate insulating film 30 by sputtering, for example.

  Thereafter, as shown in FIG. 4A (c), the conductive film 32, the conductive film 31, and the gate insulating film 30 are processed to form the gate electrode. In the formation of the gate electrode 23, a resist pattern that covers a region where the gate electrode 23 is to be formed and that exposes other regions is formed on the conductive film 32, and, for example, a chlorine-based gas is used using this resist pattern as a mask. The conductive film 32, the conductive film 31, and the gate insulating film 30 are etched until the protective film 28 is exposed by a dry etching method. Then, this resist pattern is removed.

  Subsequently, as shown in FIG. 4B (d), an interlayer insulating film 33 covering the gate electrode 23 and the gate insulating film 30 is formed on the protective film 28 by, eg, plasma CVD. As a material of the interlayer insulating film 33, for example, tetraethoxysilane (TEOS: tetraethylorthosilicate) is used. Next, a resist pattern 51 is formed on the interlayer insulating film 33 so as to expose a region where the source electrode opening 34 is to be formed and a region where the drain electrode opening 35 is to be formed, and cover the other regions. To do. Thereafter, using the resist pattern 51 as a mask, the interlayer insulating film 33 and the protective film 28 are etched by, for example, a dry etching method using a fluorine-based gas to expose the upper surface of the electron supply layer 22. As a result, the opening 34 and the opening 35 are formed.

Subsequently, as shown in FIG. 4B (e), the resist pattern 51 is removed, and a region where a drain electrode opening 36 is to be formed on the interlayer insulating film 33 and the electron supply layer 22 is exposed. A resist pattern 52 is formed to cover this area. Next, the opening 36 is formed by etching the electron supply layer 22 and the channel layer 21 using the resist pattern 52 as a mask. In this etching, for example, the power is 1200 ± 300 W, the pressure is 1.3 ± 0.3 mm Torr, the flow rate of Cl ₂ is 75 ± 10 sccm, and the time is 1 to 3 minutes.

  Thereafter, as shown in FIG. 4B (f), the resist pattern 52 is removed, and, for example, a physical vapor deposition (PVD) method is performed on the interlayer insulating film 33, the electron supply layer 22, and the channel layer 21. A conductive film 37 and a conductive film 38 are formed.

  Subsequently, as shown in FIG. 4C (g), a resist pattern 53 is formed on the conductive film 38 so as to cover a region where the source electrode 24 is to be formed and a region where the drain electrode 25 is to be formed, and expose other regions. Form.

  Next, as shown in FIG. 4C (h), using the resist pattern 53 as a mask, the conductive film 38 and the conductive film 37 are etched until the interlayer insulating film 33 is exposed, for example, by a dry etching method using a chlorine-based gas. As a result, the source electrode 24 and the drain electrode 25 are formed. At this time, the upper layer portion of the interlayer insulating film 33 may be etched by overetching. After the formation of the source electrode 24 and the drain electrode 25, the resist pattern 53 is removed and an annealing process is performed to change the conductive film 38 and the conductive film 37 into a conductive film having a lower contact resistance. For example, the atmosphere of this annealing treatment is an atmosphere containing one or more of rare gas, nitrogen, oxygen, ammonia and hydrogen, the time is 180 seconds or less, and the temperature is 550 ° C. to 650 ° C. In the case where Al is contained in the conductive film 38, this annealing treatment causes Al and the conductive film 37 to react with each other, and a slight Al spike is generated in the semiconductor portion (electron supply layer 22). As a result, the contact resistance decreases. At this time, the low work function of Al also contributes to the reduction in resistance.

  Then, a protective film, wiring, and the like are formed as necessary to complete the compound semiconductor device (GaN-based HEMT).

  As shown in FIG. 5, the electron supply layer 22 includes an AlGaN (i-AlGaN) layer 22a not intentionally doped with impurities, and an n-type AlGaN (n-AlGaN) doped with n-type impurities. The layer 22b and an n-type GaN (n-GaN) layer 22c doped with an n-type impurity may be included. The i-AlGaN layer 22a may be referred to as a spacer layer. The n-GaN layer 22c may be called a protective layer or a cap layer.

(Third embodiment)
Next, a third embodiment will be described. FIG. 6 is a cross-sectional view showing the structure of a compound semiconductor device (GaN-based HEMT) according to the third embodiment.

In the third embodiment, as shown in FIG. 6, the buffer layer 27 is formed above the substrate 26, the channel layer 21 is formed above the buffer layer 27, and the channel layer, as in the second embodiment. An electron supply layer 22 is formed above 21. A p-type compound semiconductor layer 41 is formed above the electron supply layer 22, and a conductive film 42 is formed thereon. As the p-type compound semiconductor layer 41, for example, a p-type GaN layer is used. The p-type GaN layer is doped with, for example, Mg at a concentration of 1 × 10 ¹⁹ cm ⁻³ to 4 × 10 ¹⁹ cm ⁻³ . The thickness of the p-type compound semiconductor layer 41 is, for example, 10 nm to 300 nm. As the conductive film 42, for example, a TiN film is used. The thickness of the conductive film 42 is, for example, 20 nm to 150 nm. The length of the p-type compound semiconductor layer 41 and the conductive film 42 in the gate length direction is, for example, 0.5 μm to 2 μm.

A protective film 43 covering the p-type compound semiconductor layer 41 and the conductive film 42 is formed above the electron supply layer 22, and an opening 44 exposing a part of the conductive film 42 is formed in the protective film 43. A conductive film 45 in contact with the conductive film 42 through the opening 44 is formed on the protective film 43. As the protective film 43, for example, the same film as the protective film 28 is used. As the conductive film 45, for example, a film made of a material having a work function of 4.5 eV or more is used. Examples of the material having a work function of 4.5 eV or more include Au, Ni, Co, TiN (nitrogen rich), TaN (nitrogen rich), TaC (carbon rich), Pt, W, Ru, Ni ₃ Si, Pd, and the like. It is done. The thickness of the conductive film 45 is, for example, 10 nm to 500 nm. The conductive film 42 and the conductive film 45 are included in the gate electrode 23.

  Other configurations are the same as those of the second embodiment.

  According to the third embodiment configured as described above, the same effect as that of the second embodiment can be obtained. Furthermore, according to the third embodiment, a normally-off operation can be realized.

  Next, a method for manufacturing the compound semiconductor device according to the third embodiment will be described. 7A to 7D are cross-sectional views showing a method of manufacturing the compound semiconductor device according to the third embodiment in the order of steps.

  First, as shown in FIG. 7A (a), the buffer layer 27, the channel layer 21, the electron supply layer 22, and the p-type compound semiconductor layer 41 are formed on the substrate 26 by, for example, the MOVPE method. Next, a conductive film 42 is formed on the p-type compound semiconductor layer 41 by, for example, a sputtering method.

Thereafter, as shown in FIG. 7A (b), a resist pattern 54 is formed on the conductive film 42 so as to cover the region where the conductive film 42 and the p-type compound semiconductor layer 41 remain and expose other regions. Subsequently, the resist pattern 54 as a mask, the electron supply layer 22 by dry etching using a chlorine-based gas or SF _x based gas to etch the conductive film 42 and the p-type compound semiconductor layer 41 to expose.

  Next, as shown in FIG. 7A (c), the resist pattern 54 is removed, and a protective film 43 covering the conductive film 42 and the p-type compound semiconductor layer 41 is formed by, for example, plasma CVD. The protective film 43 may be formed by a thermal CVD method or an ALD method.

  Thereafter, as shown in FIG. 7B (d), a resist pattern 55 is formed on the protective film 43 so as to expose a region where the opening 44 is to be formed and cover other regions. Subsequently, wet etching using, for example, a chemical solution containing hydrofluoric acid is performed using the resist pattern 55 as a mask. As a result, an opening 44 is formed.

  Next, as shown in FIG. 7B (e), the resist pattern 55 is removed, and a conductive film 45 is formed on the protective film 43 and the conductive film 42 by, for example, a PVD method.

  Thereafter, as shown in FIG. 7B (f), the conductive film 45 is processed to form the gate electrode 23. In the formation of the gate electrode 23, a resist pattern is formed on the conductive film 45 so as to cover the region where the conductive film 45 remains and expose other regions, and the protective film 43 is exposed by dry etching using this resist pattern as a mask. The conductive film 45 is etched until Then, this resist pattern is removed.

  Subsequently, as shown in FIG. 7C (g), an interlayer insulating film 33 covering the gate electrode 23 is formed on the protective film 43 by, for example, plasma CVD. Next, a resist pattern 51 is formed on the interlayer insulating film 33 so as to expose a region where the source electrode opening 34 is to be formed and a region where the drain electrode opening 35 is to be formed, and cover the other regions. To do. Then, the opening part 34 and the opening part 35 are formed similarly to 2nd Embodiment.

  Subsequently, as shown in FIG. 7C (h), a resist pattern 52 is formed and an opening 36 is formed in the same manner as in the second embodiment. Next, as shown in FIG. 7C (i), the resist pattern 52 is removed, and a conductive film 37 and a conductive film 38 are formed. Thereafter, as shown in FIG. 7D (j), a resist pattern 53 is formed. Subsequently, as shown in FIG. 7D (k), the conductive film 38 and the conductive film 37 are etched to form the source electrode 24 and the drain electrode 25. Next, the resist pattern 53 is removed, and an annealing process is performed to change the conductive film 38 and the conductive film 37 into a conductive film having a lower contact resistance.

  Then, a protective film, wiring, and the like are formed as necessary to complete the compound semiconductor device (GaN-based HEMT).

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 8 is a cross-sectional view showing the structure of a compound semiconductor device (GaN-based HEMT) according to the fourth embodiment.

  In the fourth embodiment, the opening 36 is not formed, and an impurity diffusion layer 47 that penetrates the electron supply layer 22 and reaches the middle of the channel layer 21 is formed inside the opening 35 in plan view. . The distance between the end of the opening 35 on the gate electrode 23 side and the end of the impurity diffusion layer 47 on the gate electrode 23 side is, for example, 0.1 μm to 0.8 μm. The impurity diffusion layer 47 is doped with Si as an n-type impurity, for example. A portion of the conductive film 37 and the conductive film 38 included in the drain electrode 25 is formed above the impurity diffusion layer 47. The impurity diffusion layer 47 is included in the second portion 25 b of the drain electrode 25. Other configurations are the same as those of the second embodiment.

  According to the fourth embodiment configured as described above, the same effect as in the second embodiment can be obtained. Furthermore, as will be described later, it can be manufactured with fewer steps compared to the second embodiment.

  The distance from the upper surface of the electron supply layer 22 at the lower end of the impurity diffusion layer 47 is preferably determined according to the breakdown voltage in the thickness direction required for the compound semiconductor device.

  Next, a method for manufacturing the compound semiconductor device according to the fourth embodiment will be described. 9A to 9B are cross-sectional views showing a method of manufacturing the compound semiconductor device according to the fourth embodiment in the order of steps.

First, as shown in FIG. 9A, processing up to the formation of the resist pattern 52 is performed in the same manner as in the second embodiment. Next, as shown in FIG. 9A (b), n-type impurity ions are implanted without etching the electron supply layer 22 and the channel layer 21, penetrate the electron supply layer 22, and reach the middle of the channel layer 21. The reaching impurity implantation region 46 is formed. In this ion implantation, for example, the implantation energy is set to 300 keV to 800 keV, the dose is set to 1 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ⁻² , and the tilt angle is set to 0 ° to 7 °.

  Thereafter, as shown in FIG. 9A (c), the resist pattern 52 is removed, and the n-type impurity in the impurity implantation region 46 is activated to form an impurity diffusion layer 47. In the activation of the n-type impurity, for example, heat treatment is performed at a temperature of 1000 ° C. to 1200 ° C.

  Subsequently, as shown in FIG. 9B (d), a conductive film 37 and a conductive film 38 are formed in the same manner as in the second embodiment. Next, as shown in FIG. 9B (e), the source electrode 24 and the drain electrode 25 are formed by processing the conductive film 38 and the conductive film 37. Thereafter, annealing is performed to change the conductive film 38 and the conductive film 37 into a conductive film having a lower contact resistance.

  Then, a protective film, wiring, and the like are formed as necessary to complete the compound semiconductor device (GaN-based HEMT).

  Thus, the compound semiconductor device according to the fourth embodiment can be manufactured with fewer steps compared to the second embodiment.

(Fifth embodiment)
Next, a fifth embodiment will be described. FIG. 10 is a cross-sectional view showing the structure of a compound semiconductor device (GaN-based HEMT) according to the fifth embodiment.

  In the fifth embodiment, as in the fourth embodiment, the opening 36 is not formed, and the impurity diffusion layer 47 that penetrates the electron supply layer 22 and reaches the middle of the channel layer 21 is opened in plan view. It is formed inside the portion 35. Other configurations are the same as those of the third embodiment.

  According to the fifth embodiment configured as described above, the same effect as in the third embodiment can be obtained. Furthermore, as will be described later, it can be manufactured with fewer steps compared to the third embodiment.

  Next, a method for manufacturing the compound semiconductor device according to the fifth embodiment will be described. 11A to 11B are cross-sectional views showing a method of manufacturing the compound semiconductor device according to the fifth embodiment in the order of steps.

  First, as shown in FIG. 11A, processing up to the formation of the resist pattern 52 is performed in the same manner as in the third embodiment. Next, as shown in FIG. 11A (b), an impurity implantation region 46 is formed in the same manner as in the fourth embodiment.

  Thereafter, as shown in FIG. 11A (c), the resist pattern 52 is removed and the n-type impurity in the impurity implantation region 46 is activated to form the impurity diffusion layer 47 as in the fourth embodiment. .

  Subsequently, as shown in FIG. 11B (d), a conductive film 37 and a conductive film 38 are formed in the same manner as in the second embodiment. Next, as illustrated in FIG. 11B (e), the source electrode 24 and the drain electrode 25 are formed by processing the conductive film 38 and the conductive film 37. Thereafter, annealing is performed to change the conductive film 38 and the conductive film 37 into a conductive film having a lower contact resistance.

  Then, a protective film, wiring, and the like are formed as necessary to complete the compound semiconductor device (GaN-based HEMT).

  As described above, the compound semiconductor device according to the fifth embodiment can be manufactured with fewer steps compared with the third embodiment.

  In addition, you may use the electron supply layer 22 like the modification shown in FIG. 5 by 3rd Embodiment, 4th Embodiment, and 5th Embodiment.

  Next, the first and second simulations performed by the inventor will be described. FIG. 12 is a cross-sectional view showing an outline of the first and second simulation models. In the first simulation, the change in the electric field strength when the depth with respect to the upper surface of the electron supply layer 22 of the second portion 25b is changed is verified, and in the second simulation, the first portion 25a is changed. The change in the electric field strength when the length L in the direction in which the current flows was changed was verified. That is, in the first simulation, the length L of the first portion 25a is fixed to 0.5 μm, the depth D of the second portion 25b is changed, and in the second simulation, the length of the second portion 25b is changed. The depth D was fixed to 0.4 μm, and the length L of the first portion 25a was changed. The drain voltage was 250 V and the gate voltage was -8.2 V (off). FIG. 13 shows the result of the first simulation, and FIG. 14 shows the result of the second simulation.

  As shown in FIG. 13, the deeper the second portion 25b, the more the electric field intensity was relaxed. Further, as shown in FIG. 14, the shorter the first portion 25a, the more the electric field intensity was relaxed. On the other hand, it is apparent that the shorter the second portion 25a, the higher the contact resistance because the ohmic junction area decreases. Therefore, the depth D of the second portion 25b is preferably as large as possible, and the length L of the first portion 25a is preferably determined according to the electric field strength and the contact resistance.

  Next, a third simulation performed by the inventor will be described. In the third simulation, the potential in the vicinity of the drain electrode in each of the first model similar to the second embodiment and the second model obtained by excluding the portion corresponding to the second portion from the first model. The distribution was verified. That is, as shown in FIG. 15, the potential in the vicinity of the drain electrode 125 in the model including the substrate 126, the buffer layer 127, the channel layer 121, the electron supply layer 122, the protective layer 128, the interlayer insulating film 133, and the drain electrode 125. The distribution was verified. FIG. 15A shows the simulation result of the first model, and FIG. 15B shows the simulation result of the second model.

  As shown in FIG. 15, in the second model, the equipotential lines in the channel layer 121 are relatively flat, and in the first model, the equipotential lines in the channel layer 121 are deep below the drain electrode 125. It was bent greatly towards the part. This means that the first model has a higher potential in the deep part of the channel layer 121 than the second model. For this reason, in the first model, it can be said that depletion near the end of the drain electrode can be suppressed as compared with the second model, and the electric field at the corner of the drain electrode can be relaxed.

  The material of the channel layer and the electron supply layer is not limited to a GaN-based semiconductor, and other nitride semiconductors such as an AlN-based semiconductor or an InN-based semiconductor may be used. For example, an InAlN layer may be used as the electron transit layer, and an AlN layer may be used as the electron supply layer.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A channel layer;
An electron supply layer formed above the channel layer;
A gate electrode, a source electrode, and a drain electrode formed above the electron supply layer;
Have
The drain electrode is
A first portion in ohmic contact with the electron supply layer;
A second portion reaching a portion deeper than an upper surface of the channel layer immediately below the first portion on a side farther from the gate electrode than the first portion;
A compound semiconductor device comprising:

(Appendix 2)
The compound semiconductor device according to appendix 1, further comprising a p-type compound semiconductor layer formed between the electron supply layer and the drain electrode.

(Appendix 3)
The compound semiconductor device according to appendix 1 or 2, wherein the second portion includes a metal film.

(Appendix 4)
The compound semiconductor device according to appendix 1 or 2, wherein the second portion includes an impurity diffusion layer.

(Appendix 5)
The compound semiconductor device according to any one of appendices 1 to 4, further comprising a protective film that covers the electron supply layer.

(Appendix 6)
6. The compound semiconductor device according to any one of appendices 1 to 5, wherein each of the channel layer and the electron supply layer is a compound semiconductor layer having a composition containing at least nitrogen and gallium.

(Appendix 7)
Forming an electron supply layer above the channel layer;
Forming a gate electrode, a source electrode, and a drain electrode above the electron supply layer;
Have
The drain electrode is
A first portion in ohmic contact with the electron supply layer;
A second portion reaching a portion deeper than an upper surface of the channel layer immediately below the first portion on a side farther from the gate electrode than the first portion;
A method for producing a compound semiconductor device, comprising:

(Appendix 8)
The method of manufacturing a compound semiconductor device according to appendix 7, further comprising a step of forming a p-type compound semiconductor layer between the electron supply layer and the drain electrode.

(Appendix 9)
The step of forming the drain electrode includes:
Forming an opening reaching a portion deeper than the upper surface of the channel layer in the electron supply layer and the channel layer;
Forming a metal film on the electron supply layer and in the opening;
The method for producing a compound semiconductor device according to appendix 7 or 8, characterized by comprising:

(Appendix 10)
The step of forming the drain electrode includes:
Forming an impurity diffusion layer reaching a portion deeper than the upper surface of the channel layer in the electron supply layer and the channel layer;
Forming a metal film on the electron supply layer and the impurity diffusion layer;
The method for producing a compound semiconductor device according to appendix 7 or 8, characterized by comprising:

(Appendix 11)
11. The method of manufacturing a compound semiconductor device according to any one of appendices 7 to 10, further comprising a step of forming a protective film that covers the electron supply layer.

(Appendix 12)
12. The method of manufacturing a compound semiconductor device according to any one of appendices 7 to 11, wherein the channel layer and the electron supply layer are each formed of a compound semiconductor layer having a composition containing at least nitrogen and gallium.

DESCRIPTION OF SYMBOLS 11, 21: Channel layer 12, 22: Electron supply layer 13, 23: Gate electrode 14, 24: Source electrode 15, 25: Drain electrode 15a, 25a: 1st part 15b, 25b: 2nd part 36: Opening Part 47: impurity diffusion layer

Claims (10)

A channel layer;
An electron supply layer formed above the channel layer;
A gate electrode, a source electrode, and a drain electrode formed above the electron supply layer;
Have
The drain electrode is
A first portion in ohmic contact with the electron supply layer;
A second portion reaching a portion deeper than an upper surface of the channel layer immediately below the first portion on a side farther from the gate electrode than the first portion;
A compound semiconductor device comprising:   The compound semiconductor device according to claim 1, further comprising a p-type compound semiconductor layer formed between the electron supply layer and the drain electrode.   The compound semiconductor device according to claim 1, wherein the second portion includes a metal film.   The compound semiconductor device according to claim 1, wherein the second portion includes an impurity diffusion layer.   5. The compound semiconductor device according to claim 1, wherein each of the channel layer and the electron supply layer is a compound semiconductor layer having a composition containing at least nitrogen and gallium. Forming an electron supply layer above the channel layer;
Forming a gate electrode, a source electrode, and a drain electrode above the electron supply layer;
Have
The drain electrode is
A first portion in ohmic contact with the electron supply layer;
A second portion reaching a portion deeper than an upper surface of the channel layer immediately below the first portion on a side farther from the gate electrode than the first portion;
A method for producing a compound semiconductor device, comprising:   The method of manufacturing a compound semiconductor device according to claim 6, further comprising a step of forming a p-type compound semiconductor layer between the electron supply layer and the drain electrode. The step of forming the drain electrode includes:
Forming an opening reaching a portion deeper than the upper surface of the channel layer in the electron supply layer and the channel layer;
Forming a metal film on the electron supply layer and in the opening;
The method of manufacturing a compound semiconductor device according to claim 6 or 7, wherein: The step of forming the drain electrode includes:
Forming an impurity diffusion layer reaching a portion deeper than the upper surface of the channel layer in the electron supply layer and the channel layer;
Forming a metal film on the electron supply layer and the impurity diffusion layer;
The method of manufacturing a compound semiconductor device according to claim 6 or 7, wherein:   10. The method of manufacturing a compound semiconductor device according to claim 6, wherein the channel layer and the electron supply layer are each formed of a compound semiconductor layer having a composition containing at least nitrogen and gallium.

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