JP2015046501A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which provides an improvement in ease of a heat radiation design.SOLUTION: A semiconductor device 10 has a so-called multi-chip structure including a first semiconductor chip 20 and a second semiconductor chip 30 which is mounted on the first semiconductor chip 20 in an overlapping manner. The second semiconductor chip 30 has a size in a plane direction which is smaller than that of the first semiconductor chip 20 and is flip-chip mounted on the first semiconductor chip 20 via a plurality of flip-chip bumps 32. In the first semiconductor chip 20, a first circuit 70 is formed. In the second semiconductor chip 30, a second circuit 80 is formed. An amount of heat generation of the second circuit 80 is larger than that of the first circuit 70 and the second circuit 80 is a circuit which requires heat dissipation performance higher than that of the first circuit 70. The first circuit 70 and the second circuit 80 are electrically connected via the flip-chip bumps 32.

Description

  The present invention relates to a semiconductor device.

  Conventionally, for example, as disclosed in Japanese Patent Application Laid-Open No. 2003-031768, a multi-chip type semiconductor device in which a first semiconductor chip (first LSI chip) and a second semiconductor chip (second LSI chip) are stacked is known. It has been.

JP 2003-031768 A Japanese Patent Laid-Open No. 2003-068907 JP 2003-10075A JP 2004-221568 A JP-A-11-003969 JP-T-2006-514438 JP 2000-299431 A JP 2002-033444 A JP 2007-115904 A JP 09-213877 A JP 2001-320013 A

  A circuit incorporated in a semiconductor device includes various active elements, passive elements, circuit blocks, and wirings. Further, a plurality of elements and circuit blocks having different calorific values may be incorporated in one semiconductor device. In this case, in order to keep the circuit characteristics good, it is required to avoid characteristic fluctuations due to heat of a semiconductor element or the like. Therefore, the heat radiation design of the semiconductor device is important.

  In the conventional multi-chip type semiconductor device, a part of the circuit may be formed on the first semiconductor chip and the remaining part of the circuit may be formed on the second semiconductor chip. In this case, the heat radiation design becomes complicated by stacking a plurality of semiconductor chips. If the heat dissipation design is performed so that the entire semiconductor device is uniformly cooled in accordance with a circuit that requires high heat dissipation, the same heat dissipation can be achieved for multiple elements and multiple circuit blocks with different heat generation amounts. Will be given. Then, not only a part of the circuits that require high heat dissipation, but also elements and other circuit blocks that do not require heat dissipation are designed to ensure heat dissipation, resulting in waste.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device that can easily design heat dissipation when a plurality of semiconductor chips are stacked.

The semiconductor device according to the present invention is
A first semiconductor chip on which a first circuit is formed;
A second semiconductor chip formed on the first semiconductor chip, the second circuit having a smaller size in the planar direction than the first semiconductor chip and a larger amount of heat generation than the first circuit;
It is characterized by providing.

  According to the present invention, circuits that require high heat dissipation can be integrated into a small second semiconductor chip, so that heat dissipation design is facilitated.

1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the semiconductor device concerning Embodiment 3 of this invention. It is a figure which shows the semiconductor device concerning Embodiment 4 of this invention. FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention. It is a figure which shows the semiconductor device concerning Embodiment 6 of this invention. It is a figure which shows the semiconductor device as a comparative example with respect to embodiment of this invention.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a semiconductor device 10 according to a first embodiment of the present invention. FIG. 1A is a bottom view of the semiconductor device 10, and FIG. 1B is a side view of the semiconductor device 10. FIG. 1A is a plan view when FIG. 1B is viewed in the direction of arrow A. FIG. The semiconductor device 10 is a power amplifier module used for mobile communication such as a mobile phone.

  The semiconductor device 10 has a so-called multi-chip structure including a first semiconductor chip 20 and a second semiconductor chip 30 mounted so as to overlap therewith. The second semiconductor chip 30 is smaller in size in the planar direction than the first semiconductor chip 20, and is flip-chip mounted on the first semiconductor chip 20 via a plurality of flip chip bumps 32.

  The first semiconductor chip 20 is formed with a first circuit 70 in a circuit diagram of FIG. 4 to be described later. In the second semiconductor chip 30, a second circuit 80 shown in a circuit diagram of FIG. 4 to be described later is formed. The second circuit 80 is a circuit that generates more heat than the first circuit 70 and requires higher heat dissipation than the first circuit 70. The first circuit 70 and the second circuit 80 are electrically connected via the flip chip bump 32.

  The semiconductor device 10 has a CSP (Chip Scale Package) structure. As shown in FIG. 1, the size of the first semiconductor chip 20 in the planar direction is larger than that of the second semiconductor chip 30, and the first semiconductor chip 20 forms a main part of the CSP structure of the semiconductor device 10. In other words, the first semiconductor chip 20 mainly forms the outer shape of the entire CSP structure.

  The first semiconductor chip 20 includes an active surface 20b on which an active layer (layer on which the first circuit 80 including active elements and the like are formed) is formed, and a facing surface 20a positioned opposite to the active surface 20b. On the active surface 20b, five copper posts 22 as electrodes are arranged on two opposite sides. The second semiconductor chip 30 is mounted on the active surface 20 b of the first semiconductor chip 20.

  The semiconductor device 10 further includes surface mount components 40a, 40b, and 40c (hereinafter collectively referred to as surface mount components 40). The surface mount component 40 is called SMD (Surface Mount Device), and is a circuit component capable of surface mounting of the first semiconductor chip 20. For example, chip components such as an inductor, a capacitor, and a resistor. In the first embodiment, the surface mounting component 40 is mounted by soldering on the active surface 20b and the opposing surface 20a on the surface on which the second semiconductor chip 30 is mounted, that is, the active surface 20b. The circuit 70 is electrically connected.

  The second semiconductor chip 30 includes a first main surface 30a facing the first semiconductor chip 20 side and a second main surface 30b opposite to the first main surface 30a. The resin sealing body 50 seals the periphery of the second semiconductor chip 30 while exposing part or all of the second main surface 30b. Further, the facing surface 20a and the side surface of the first semiconductor chip 20 are not provided with the resin sealing body 50 and are exposed.

  The metallized layer 34 is provided in the part exposed from the resin sealing body 50 in the 2nd main surface 30b. By providing the metallized layer 34 and exposing it, the heat radiation of the second semiconductor chip 30 can be performed on the entire second main surface 30b. The metallized layer 34 also serves as a ground electrode of a multi-stage power amplifier circuit MAMP described later.

  FIG. 2 is a diagram showing a semiconductor device 12 according to a modification of the first embodiment of the present invention. The semiconductor device 12 is obtained by flip-chip mounting the above-described semiconductor device 10 on a circuit board 60 (a motherboard in the first embodiment). In this structure, the metallized layer 34 of the second semiconductor chip 30 and the height of the copper post 22 are combined. As a result, the second main surface 30b of the second semiconductor chip 30 is connected to the circuit board 60 with solder.

  As a result, it is possible to efficiently transfer the heat generated by the second semiconductor chip 30 to the circuit board 60 during circuit operation. Further, by mounting the metallized layer 34 with an electrically conductive material such as solder directly on a ground electrode (not shown) provided on the surface of the circuit board 60, both heat dissipation and grounding can be realized. The connection between the metallized layer 34 of the second semiconductor chip 30 and the circuit board 60 may be a connection using other than solder. An adhesive made of a heat conductive material may be used.

  FIG. 3 is a diagram showing a semiconductor device 14 according to another modification of the first embodiment of the present invention. In the semiconductor device 14, the semiconductor device 10 includes a copper post 22 a instead of the copper post 22, and the height of the copper post 22 a is different from the height of the metallized layer 34 of the second semiconductor chip 30. As a result, there is a gap between the metallized layer 34 and the circuit board 60.

  The gap is filled with an underfill material 62 having high thermal conductivity. Thereby, the metallized layer 34 and the circuit board 60 can be thermally connected via the underfill material 62, and the heat generated by the second semiconductor chip 30 during the circuit operation can be efficiently transmitted to the circuit board 60. It becomes possible. In addition to the underfill material 62, the gap may be filled with a heat conductor.

  FIG. 4 is a circuit diagram for explaining a configuration of the semiconductor device 10 according to the first embodiment of the present invention. FIG. 4 shows a circuit diagram of a multi-stage power amplifier circuit MAMP built in the semiconductor device 10. The first circuit 70 included in the first semiconductor chip 20 is connected to the input terminal IN via the matching circuit MC1, and includes a first-stage amplifier transistor 72 in the multi-stage power amplifier circuit MAMP and a bias circuit 74 that supplies a bias thereto. Contains. The second circuit 80 provided in the second semiconductor chip 30 includes a final stage amplification transistor 82 in the multistage power amplification circuit MAMP.

  The output side of the first stage amplifying transistor 72 is connected to the input side of the last stage amplifying transistor 82 via the matching circuit MC2. The output side of the final stage amplification transistor 82 is connected to the output terminal OUT via the matching circuit MC3. The first circuit 70 includes a bias circuit 76, and the bias circuit 76 supplies a bias to the final stage amplification transistor 82 via the wiring 84. In terms of correspondence with FIG. 1, the wiring 84 includes the flip chip bump 32.

  FIG. 4 is a circuit block diagram of a two-stage power amplifier as an example of a multi-stage power amplifier module. In FIG. 4, during the module operation, the power input from the input terminal IN is amplified by the first stage amplifier transistor 72, further amplified by the final stage amplifier transistor 82, and output from the output terminal OUT.

  In general, the power output from the final stage amplification transistor is larger than that of the first stage amplification transistor. For this reason, when comparing the power consumed by the amplifying transistor, the final-stage amplifying transistor 82 consumes more power than the first-stage amplifying transistor 72, and accordingly, the amount of heat generated is also large.

  In order to obtain good characteristics of the power amplifier, it is important to secure a path for radiating heat generated from the amplification transistor. In particular, it is important to efficiently dissipate heat from the final stage amplification transistor 82. In this regard, in the semiconductor device 10 according to the first embodiment, as shown in FIG. 4, the second circuit 80 including the final stage amplification transistor 82 is arranged in the second semiconductor chip 30, and other circuit blocks, that is, the first circuit 70. Are arranged on the first semiconductor chip 20.

  As a result, the second circuit 80 including the final amplification transistor 82 that requires high heat dissipation can be integrated into the second semiconductor chip 20. As a result, compared with the case where a circuit block with a large amount of heat generation and a circuit block with a small amount of heat are mixed in the same semiconductor chip, the second semiconductor chip 20 has only to be dissipated preferentially. It is easy to suppress excessive heat dissipation.

  Specifically, according to the semiconductor device 10, by using the metallized layer 34 of the second semiconductor chip 20 as a heat transfer path, a circuit like the semiconductor device 12 shown in FIG. 2 or the semiconductor device 14 shown in FIG. Heat can be efficiently radiated to the substrate 60. Thereby, it is easy to improve the characteristics as a power amplifier without being influenced by the heat dissipation of the first semiconductor chip 20.

  In FIG. 4, the final stage amplification transistor 82 is arranged on the second semiconductor chip 20, but other peripheral matching circuits, bias circuits, and the like may be arranged on the second semiconductor chip 20. Although FIG. 4 shows an example of a two-stage power amplifier module, the present invention can also be applied to a multistage power amplifier composed of three or more stages. In this case as well, the same effect can be obtained by forming a circuit block having a high calorific value on the second semiconductor chip 20.

  According to the semiconductor device 10 according to the first embodiment, the second semiconductor chip 30 and the surface mounting component 40 are collectively mounted on the active surface 20b of the first semiconductor chip 20. For this reason, it is not necessary to provide circuit wiring in the opposing surface 20a.

  FIG. 10 is a diagram showing a semiconductor device 610 as a comparative example with respect to the embodiment of the present invention. In the semiconductor device 610 of FIG. 10, when a module is configured with a plurality of semiconductor chips 620 and 630, the plurality of semiconductor chips 620 and 630 are separately mounted on the package substrate 660. The semiconductor chips 620 and 630 and the package substrate 660 or the semiconductor chip 620 and the semiconductor chip 630 are connected by a wire 662. A chip component 640 such as an inductor, a capacitor, and a resistor is also mounted on the package substrate 660.

  In such a configuration, the package substrate 660 having a sufficient width for mounting the semiconductor chips 620 and 630 and the chip component 640 side by side in the plane direction is necessary. For this reason, the size and height of the semiconductor device 610 must be increased, which hinders downsizing / lowering the size of the device.

  In this regard, according to the semiconductor device 10 according to the first embodiment, the package substrate 660 is not necessary, and the planar size of the semiconductor device 10 can be reduced to the size of the first semiconductor chip 20 in the planar direction. Further, since the package substrate 660 is unnecessary, the height of the semiconductor device 10 can be reduced, and a small and low-profile multichip power amplifier can be realized.

  The material of the semiconductor chip will be described. The semiconductor material of the first semiconductor chip 20 may be silicon, and the semiconductor material of the second semiconductor chip 30 may be a different semiconductor material (compound semiconductor) other than silicon. The reason is that since the first semiconductor chip 20 requires a relatively large area, a relatively inexpensive silicon chip is used, and the second semiconductor chip 30 forms a second circuit 80 that requires high performance. Therefore, a high performance compound semiconductor chip is used. As a result, it is possible to achieve both good characteristics of the power amplifier and cost reduction of the entire semiconductor device while minimizing the use area of a semiconductor chip made of a relatively expensive compound semiconductor.

  However, the present invention is not limited to such a form, and the first semiconductor chip 20 may be other than silicon, and the second semiconductor chip 30 may be other than the compound semiconductor chip. For example, the semiconductor material of both the first semiconductor chip 20 and the second semiconductor chip 30 may be silicon. When high performance is not required for the power amplifier, it is possible to further reduce the cost by using a relatively inexpensive silicon chip for the second semiconductor chip 20.

  In the semiconductor device 10 according to the first embodiment, two semiconductor chips are used. However, the present invention is not limited to this. Three or more semiconductor chips may be used. For example, when three semiconductor chips are used, the first circuit 70 having a low calorific value is formed on the first semiconductor chip 20 having the largest size in the planar direction as in the first embodiment. The final amplification transistor 82 and other circuit blocks having a relatively high heat generation amount may be formed in the second semiconductor chip 30 and the added third semiconductor chip. In the case of a three-stage power amplifier, the second-stage amplification transistor and the final-stage amplification transistor may be formed in the second semiconductor chip 30 and the added third semiconductor chip.

  In the semiconductor device 10 according to the first embodiment, the surface mounting component 40 is mounted, but the present invention is not limited to this. The semiconductor device according to the present invention does not necessarily include a surface mount component.

  Note that the above-described mounting structure with the circuit board 60 and other various modifications can be similarly applied to each of the semiconductor devices according to the second and later embodiments described later.

Embodiment 2. FIG.
FIG. 5 is a diagram showing a semiconductor device 110 according to the second embodiment of the present invention. The semiconductor device 110 according to the second embodiment is similar to the semiconductor device according to the first embodiment except that the first semiconductor chip 20 is replaced with the first semiconductor chip 120 and the mounting position of the surface mount component 40 is changed. 10 has the same configuration. Therefore, in the following description, the same or corresponding components as those in the first embodiment will be described with the same reference numerals, and differences from the first embodiment will be mainly described, and common items will be briefly described. Or omitted.

  The first semiconductor chip 120 includes an active surface 120b and a facing surface 120a. However, wiring is also formed on the facing surface 120a, and this wiring is electrically connected to the surface-mounted component 40 mounted on the facing surface 120a. Further, in the semiconductor device 110, in addition to the resin sealing body 50, a resin sealing body 150 that is provided on the facing surface 120 a and covers the surface-mounted component 40 is also provided.

  According to the semiconductor device 110 according to the second embodiment, the height dimension of the device is larger than that of the semiconductor device 10 according to the first embodiment. On the other hand, the second semiconductor chip 30 and the surface-mounted component 40 are not mounted on the same plane, but mounted on the two main surfaces (opposing surface 120a and active surface 120b) of the first semiconductor chip 120, respectively. . Thereby, the second semiconductor chip 30 and the surface mount component 40 can be freely arranged on the two different main surfaces of the first semiconductor chip 120 without interfering with each other.

  For example, specifically, the second semiconductor chip 30 and the surface mounting component 40 are provided at the center positions of the opposing surface 120a and the active surface 120b, so that both components can be mounted so as to overlap in plan view. . For this reason, the planar dimension of the first semiconductor chip 120, and hence the planar dimension of the semiconductor device 110, can be reduced.

Embodiment 3 FIG.
FIG. 6 is a diagram showing a semiconductor device 210 according to the third embodiment of the present invention. FIG. 6A is a top view of the semiconductor device 210, and FIG. 6B is a side view of the semiconductor device 210. FIG. 6A is a plan view when FIG. 6B is viewed in the direction of arrow B, and the metal cap 250 is seen through.

  The semiconductor device 210 has a so-called multi-chip structure including a first semiconductor chip 220 and a second semiconductor chip 230 mounted on the first semiconductor chip 220. The second semiconductor chip 230 is smaller in size in the planar direction than the first semiconductor chip 220, and is flip-chip mounted on the first semiconductor chip 220 via a plurality of flip chip bumps 232.

  As in the first semiconductor chip 20 according to the first embodiment, the first circuit 70 is formed in the first semiconductor chip 220. Similar to the second semiconductor chip 30 according to the first embodiment, the second circuit 80 is formed in the second semiconductor chip 220.

  Similar to the semiconductor device 10 according to the first embodiment, the semiconductor device 210 has a CSP (Chip Scale Package) structure. As shown in FIG. 6, the size of the first semiconductor chip 220 in the planar direction is larger than that of the second semiconductor chip 230, and the first semiconductor chip 220 forms the main part of the CSP structure of the semiconductor device 210.

  The first semiconductor chip 220 includes an active surface 220b on which an active layer (layer on which the first circuit 80 including active elements and the like are formed) is formed, and a facing surface 220a positioned opposite to the active surface 220b. On the active surface 220b, copper posts 222 as electrodes are arranged on two opposite sides. Here, in the semiconductor device 210 according to the third embodiment, the height dimension of the copper post 222 is smaller than that of the semiconductor device 10 according to the first embodiment. This is because the distance between the active surface 220b and the circuit board on which the semiconductor device 210 is to be mounted (the circuit board 60 of the first embodiment) may be small due to the mounting position of the second semiconductor chip 230. The copper post 222 is lowered.

  The second semiconductor chip 230 is flip-chip mounted on the facing surface 220 a of the first semiconductor chip 220 via flip-chip bumps 232. This is in contrast to the first and second embodiments. Specifically, the second semiconductor chip 220 includes a first main surface 230a facing the first semiconductor chip 220 and a second main surface 230b opposite to the first main surface 230a, and the first main surface 230a. Flip chip bumps 232 are connected to each other.

  The first semiconductor chip 220 includes a plurality of vias 224 therein. The via 224 is a TSV (Through Si Via). The second circuit 80 formed in the second semiconductor chip 230 is electrically connected to the first circuit 70 formed in the first semiconductor chip 220 through the flip chip bump 232 and the via 224. .

  Further, surface mount components 240 a, 240 b, 240 c (hereinafter collectively referred to as surface mount components 240) are mounted on the facing surface 220 a of the first semiconductor chip 220. The surface mount component 240 is an SMD (Surface Mount Device) similar to the surface mount component 40 according to the first embodiment. The surface mount component 240 is also electrically connected to the first circuit 70 formed in the first semiconductor chip 220 through the via 224.

  A metallized layer 234 is provided on the entire surface of the second major surface 230b. The metallized layer 234 also serves as the ground electrode of the multistage power amplifier circuit MAMP. The semiconductor device 210 includes a metal cap 250 covered from the facing surface 220 a side of the first semiconductor chip 220. The metal cap 250 is in contact with the metallized layer 234 and is electrically and thermally connected to the metallized layer 234.

  The metal cap 250 may be solder-connected to the circuit board when the semiconductor device 210 is mounted on the circuit board or the like (for example, the circuit board 60 of the first embodiment). Thereby, it is possible to efficiently dissipate heat generated by the second semiconductor chip 230 to the circuit board during circuit operation. The connection between the metal cap 250 and the mother board may be a connection using a heat conductive material other than solder.

  Various modifications performed in the semiconductor device 10 according to the first embodiment may be applied to the semiconductor device 110 according to the second embodiment.

Embodiment 4 FIG.
FIG. 7 is a diagram showing a semiconductor device 310 according to the fourth embodiment of the present invention. FIG. 7A is a top view of the semiconductor device 310, and FIG. 7B is a side view of the semiconductor device 310. FIG. 7A is a plan view when FIG. 7B is viewed in the direction of arrow C, and the sealing resin body 350 is seen through.

  The semiconductor device 310 according to the fourth embodiment has a configuration similar to that of the semiconductor device 210 according to the third embodiment. Therefore, the same or corresponding components as those of the third embodiment are denoted by the same reference numerals, and descriptions of common matters are simplified or omitted.

  Next, differences between the semiconductor device 310 according to the fourth embodiment and the semiconductor device 210 according to the third embodiment will be described. The semiconductor device 310 according to the fourth embodiment includes a sealing resin body 350 provided on the facing surface 220a of the first semiconductor chip 220 instead of the metal cap 250 in the semiconductor device 210 according to the third embodiment. . The metallized layer 234 of the second semiconductor chip 230 is exposed from the sealing resin body 350. Thus, instead of the metal cap 250, the sealing resin body 350 may be provided.

Embodiment 5 FIG.
FIG. 8 is a diagram showing a semiconductor device 410 according to the fifth embodiment of the present invention. FIG. 8A is a top view of the semiconductor device 410, and FIG. 8B is a side view of the semiconductor device 410. FIG. 8A is a plan view when FIG. 8B is viewed in the direction of arrow D, and the metal cap is seen through.

  The semiconductor device 410 according to the fifth embodiment has a structure similar to that of the semiconductor device 210 according to the third embodiment. Therefore, the same or corresponding components as those of the third embodiment are denoted by the same reference numerals, and descriptions of common matters are simplified or omitted.

  Next, differences between the semiconductor device 410 according to the fifth embodiment and the semiconductor device 210 according to the third embodiment will be described. The first difference is that the first semiconductor chip 220 is replaced with the first semiconductor chip 420. The first semiconductor chip 420 is different from the first semiconductor chip 220 in the position and number of vias 424. This is provided with surface mount components 440 a and 440 b (hereinafter collectively referred to as surface mount components 440) instead of the surface mount components 240, and the surface mount components 440 are mounted on the active surface 420 b of the first semiconductor chip 420. Because.

  Further, in the semiconductor device 410, the copper post 422 has a height equal to or greater than the thickness of the surface mount component 440. Further, a sealing resin body 450 is provided on the active surface 420 b of the first semiconductor chip 420. These points are also different from the third embodiment. The sealing resin body 450 exposes a part of the surface of the copper post 422 while covering the surface mounting component 440.

  Also in the semiconductor device 410 according to the fifth embodiment, the second semiconductor chip 230 and the surface mounting component 440 are separately mounted on the facing surface 420a and the active surface 420b of the first semiconductor chip 420 as in the second embodiment. . Thereby, the planar dimension of the semiconductor device 410 can be reduced.

Embodiment 6 FIG.
FIG. 9 is a diagram showing a semiconductor device 510 according to the sixth embodiment of the present invention. FIG. 9A is a top view of the semiconductor device 510, and FIG. 9B is a side view of the semiconductor device 510. FIG. 9A is a plan view when FIG. 9B is viewed in the direction of arrow E, and the sealing resin body 550a is seen through.

  The semiconductor device 510 according to the sixth embodiment has a configuration similar to that of the semiconductor device 410 according to the fifth embodiment. Therefore, the same or corresponding components as those in the fifth embodiment are denoted by the same reference numerals, and descriptions of common matters are simplified or omitted.

  Next, differences between the semiconductor device 510 according to the sixth embodiment and the semiconductor device 410 according to the fifth embodiment will be described. The semiconductor device 510 does not include the metal cap 250. Instead, a sealing resin body 550 is provided. The sealing resin body 550 includes a sealing resin body 550a provided on the facing surface 420a of the first semiconductor chip 420 and a sealing resin body 550b provided on the active surface 420b.

  The sealing resin body 550a seals the side surface of the second semiconductor chip 230 and the first main surface 230a while exposing the metallized layer 234. The sealing resin body 550 b exposes a part of the surface of the copper post 422 while covering the surface mounting component 440.

  As in the second and fifth embodiments, the semiconductor device 510 according to the sixth embodiment can reduce the planar size of the semiconductor device 510.

DESCRIPTION OF SYMBOLS 10 Semiconductor device, 20 1st semiconductor chip, 20a Opposing surface, 20b Active surface, 22 Copper post, 30 2nd semiconductor chip, 30a 1st main surface, 30b 2nd main surface, 32 Flip chip bump, 34 Metallized layer, 40 40a, 40b, 40c Surface mount component, 50 Resin encapsulant, 60 Circuit board, 62 Underfill material, 70 First circuit, 72 First stage amplification transistor, 74 Bias circuit, 76 Bias circuit, 80 Second circuit, 82 End Stage amplification transistor, 84 wires, MAMP multi-stage power amplification circuit, MC1, MC2, MC3 matching circuit

Claims (12)

A first semiconductor chip on which a first circuit is formed;
A second semiconductor chip formed on the first semiconductor chip, the second circuit having a smaller size in the planar direction than the first semiconductor chip and a larger amount of heat generation than the first circuit;
A semiconductor device comprising: The first semiconductor chip includes an active surface on which an active layer is formed and an opposing surface located opposite to the active surface,
The semiconductor device according to claim 1, wherein the second semiconductor chip is mounted on the active surface of the first semiconductor chip. The first semiconductor chip includes an active surface on which an active layer is formed and an opposing surface located opposite to the active surface,
The semiconductor device according to claim 1, wherein the second semiconductor chip is mounted on the facing surface of the first semiconductor chip.   4. The device according to claim 2, further comprising a surface mounting component mounted on a surface of the first semiconductor chip on the side where the second semiconductor chip is mounted among the active surface and the facing surface. 5. Semiconductor device.   The surface mounting component mounted on the surface different from the surface where the said 2nd semiconductor chip was mounted among the said active surface and the said opposing surface of a said 1st semiconductor chip is further provided, or characterized by the above-mentioned. 3. The semiconductor device according to 3. The second semiconductor chip includes a first main surface facing the first semiconductor chip side, and a second main surface opposite to the first main surface,
A resin sealing body that seals the periphery of the second semiconductor chip while exposing part or all of the second main surface;
A metallized layer provided in a portion exposed from the resin sealing body in the second main surface;
The semiconductor device according to claim 1, comprising: The second semiconductor chip includes a first main surface facing the first semiconductor chip side, and a second main surface opposite to the first main surface,
A metallization layer provided on the second main surface;
A metal body connected to the metallization layer;
The semiconductor device according to claim 1, further comprising: The second semiconductor chip includes a first main surface facing the first semiconductor chip side, and a second main surface opposite to the first main surface,
A metallization layer provided on the second main surface;
A circuit board electrically connected to the first circuit and the second circuit and connected to the metallized layer directly or via a heat conductor;
The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 6, wherein the metallized layer also serves as a ground electrode of the second circuit. The semiconductor material of the first semiconductor chip is silicon,
The semiconductor device according to claim 1, wherein a semiconductor material of the second semiconductor chip is other than silicon.   The semiconductor device according to claim 1, wherein a semiconductor material of the first semiconductor chip and the second semiconductor chip is silicon. The first circuit includes a first stage amplification transistor in a multistage power amplification circuit,
12. The semiconductor device according to claim 1, wherein the second circuit includes second and subsequent amplification transistors in a multi-stage power amplification circuit.

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