JP2015014962A - Arithmetic device, arithmetic method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly adjust hash requests between a plurality of hash arithmetic units and a plurality of hosts outputting a hash arithmetic request.SOLUTION: Two or more hash arithmetic units and an arithmetic control module connected to a plurality of host devices are provided. In response to an arithmetic request from the host device, the arithmetic control module determines a hash arithmetic unit for execution, depending on the processing capacity of the hash arithmetic unit and the data size of the arithmetic request, and makes the determined hash arithmetic unit execute the hash arithmetic.

Description

  The present invention relates to a calculation device, a calculation method, and a program.

  It is already known that devices such as personal computers (MFPs) and multifunction peripherals (MFPs) detect tampering using hash values in order to prevent tampering with installed software and data during communication. ing.

  For example, when the device is activated, a hash value of the software is calculated and stored in advance in the secondary storage device of the device. When the device starts up, the software hash value is recalculated, and if it does not match the hash value stored in the secondary storage device in advance, it is determined that it has been tampered with, and abnormal processing is performed. ing.

The calculation of the hash value is obtained by using all the target data in the calculation in order to obtain the calculation result. For this reason, once the calculation is started, another data calculation is not normally performed until the calculation is completed.
Since the computation time increases in proportion to the size of the target data, the startup time can be increased by installing multiple hardware to perform the processing faster than performing processing with a CPU (central processing unit). It is already known to shorten the time.

Consider the case where there are a plurality of CPUs in the system in addition to the above-described configuration having a plurality of hardware, and each of them uses the hardware independently. In this case, when the CPU tries to perform control, it first checks whether or not arithmetic processing is being performed on one hardware module. After confirming the presence / absence of the arithmetic processing, when there is no arithmetic processing, that is, when it is free, the execution register can be hit after setting the parameter as the arithmetic request. When there is an arithmetic processing, that is, when it is not free, it is necessary to search for another module that is not performing processing and wait until the module can be used. In order to use hardware like this, the CPU has to perform extra control, and there is a problem that the processing load of the CPU increases.
Further, when it is necessary to wait until the module can be used, there is a problem that the execution time of the application is delayed if the calculation result is processing on the critical path.
Proposals for solving this type of problem have been made (for example, see Patent Document 1).

  Patent Document 1 discloses a contention arbitration device and a master / slave system for the purpose of performing the most efficient access request arbitration when a plurality of master devices have access requests to one slave device at the same time. And a competitive arbitration method is disclosed.

  In the invention described in Patent Document 1, an arbitration unit calculates an access priority for an access request to a slave device used by a CPU to optimize access arbitration. However, there are a plurality of slave devices, and the problem of how to optimize the slave device arbitration among them is not solved.

  Therefore, an object of the present invention is to arbitrate optimal calculation requests.

  In order to solve the above problem, the invention described in claim 1 determines two or more hash operation units and a hash operation unit to be executed in response to an operation request from a plurality of host devices, and the determined hash operation And a control unit that causes the unit to perform a hash operation.

  According to the present invention, it is possible to arbitrate optimal calculation requests.

1 is an explanatory diagram of an overall configuration of an image forming apparatus as one embodiment. FIG. It is a conceptual diagram of an arithmetic processing module. It is a flowchart which shows the control method of an arithmetic processing module. It is a figure which shows another example of a calculation control module. It is a figure which shows an example of the flow of a calculation process. It is a comparative example showing a difference between the arithmetic unit of the present embodiment and a calculation request access to the arithmetic modules A and B simply. FIG. 5 is a second embodiment illustrating a configuration in which functions are added to the arithmetic control module and the arithmetic processing module illustrated in FIG. 4. FIG. 6 is a diagram showing a third embodiment.

An embodiment of the present invention will be described.
The present invention has the following characteristics when a plurality of masters have a plurality of hardware.
<Overview>
Even if multiple CPUs use hardware independently at the same time, the control unit issues a calculation request to the calculation device, and power supply to the Ethernet (hereinafter, registered trademark) I / F connected to the calculation device is stopped. Sometimes, another device receives a processing request from the LAN as a proxy. After receiving the Ethernet I / F return signal via the external connection I / F with low standby power, the device that received the process on behalf of the proxy issues a request again to establish communication.

<Embodiment>
The present embodiment will be described in detail with reference to the following drawings.
[Constitution]
FIG. 1 is an explanatory diagram of an overall configuration of an image forming apparatus as an embodiment.
CPU A (16a) and CPU B (16b) are circuits that centrally control the image forming apparatus, execute software, request computations to the arithmetic processing modules A (13a) and B (13b), and operate the modules. Instructions are possible. The CPU A (16a) and the CPU B (16b) confirm the calculation result to the arithmetic processing modules A (13a) and B (13b) in order to compare the hash values by the notification of the interrupt signal. The processing speed of CPU A (16a) and CPU B (16b) is inferior to that of arithmetic module A (16a) and CPU B (16b), but the hash value can be calculated by itself. CPU A (16a) and CPU B (16b) operate independently of each other. In this embodiment, the number of CPUs A (16a) and CPUs B (16b) is two. However, the present invention is not limited to this, and three or more CPUs may be connected.

  The main storage device 12 serves as a development location for software and data. It has a function to read / write data in the memory by receiving access from the CPU A (16a), CPU B (16b) and the DMAC (Direct Memory Access Control) of each module.

  The nonvolatile memory 11 has an area for storing software and data while the power is off. Since the nonvolatile memory 11 has a slower transfer rate than the main storage device 12, the nonvolatile memory 11 develops data in the main storage device 12 as necessary after power-on. Direct access by CPU A (16a), CPU B (16b) and DMAC is also possible.

  The external connection I / F (15) is an I / F connected to an external network. A typical example is Ethernet I / F. The external connection I / F (15) may be connected to a storage storing data such as an SD memory card or a USB flash memory. The external connection I / F (15) needs to calculate a hash value.

The arithmetic processing module A (13a) and the arithmetic processing module B (13b) are modules that calculate hash values. All the software and data are used for calculation, and the hash value is calculated and the result is output.
The arithmetic processing modules A (13a) and B (13b) are connected to the bus line 17 in the same manner as the other modules, and have a configuration shown in detail in FIG.

FIG. 2 is a conceptual diagram of the arithmetic processing module.
The register unit 23 includes a register for setting an interrupt mask register processing parameter for determining an interrupt output destination, an interrupt clear register, an operation start register, an operation result register, an access start address of a DMAC, and a data size.
The calculation unit 22 is a data counter that counts data calculated by the hash calculation unit determined by the CPU A (16a) and CPU B (16b), and a first calculation unit that calculates an estimated processing time from the processing capability of the hash calculation unit. And a calculation circuit.

  Further, when the calculation unit 22 requests the hash calculation unit determined by the CPU A (16a) and CPU B (16b) to calculate, the calculation unit 22 calculates the data size of the calculation request content and the processing capability of the calculation unit. The calculation unit 22 includes a second calculation circuit that calculates the estimated time for completing the calculation request by adding up the estimated completion times of the plurality of hash calculation units and combining the estimated completion time with the shortest time. May be.

When the operation processing module stores the result in the operation result register after the operation is completed, the operation processing module sends an interrupt signal to the CPU. The interrupt signal line is connected to each CPU and sends an interrupt signal to the requested CPU.
Here, the computing device can set a threshold value, and when a plurality of computation requests are accumulated, the estimated time for completing the computation request is equal to or greater than the threshold value, and the data size of the computation request is equal to or less than the threshold value. In this case, a reject circuit for rejecting the calculation request may be provided.

In this embodiment, an arithmetic control module 22 is inserted between the CPU and the CPU.
The arithmetic processing module is equipped with a DMAC 21 and reads the data to be calculated without intervention of the CPU when the calculation is started. By setting an access start address and a data size in the register unit 23, the addresses to be accessed are sequentially counted up. Along with this count-up, there is a mechanism that can read the data in the set range when it becomes 0 by operating the down counter from the set size.
The arithmetic processing module is connected to the bus line between the register unit 23 and the DMAC 21. The register unit 23 performs access from the CPU, and the DMAC 21 performs read access to the storage area. In the present embodiment, there are two register units 23 and DMAC 21, but a larger number may be connected.

[Operation]
A control method of the arithmetic processing module is shown in the flowchart of FIG.
The arithmetic processing module first performs register setting, parameter setting, DMAC 21 setting, and interrupt destination setting (step S1).
When the register setting is completed, DMA is performed with the calculation start register setting, and hash value calculation is started (step S2).
When the calculation is completed and data is stored in the calculation result register, the interrupt signal is output to the set destination (step S3).
If the interrupt signal is cleared (step S4) and the operation result register is read, the operation result is obtained and the processing is completed (step S5).
In the present embodiment, the process from register setting to operation start register setting is referred to as an operation request, and interrupt clearing to operation result register reading is referred to as a result confirmation.

  The calculation control module 14-1 temporarily stores the calculation request from the CPU, issues the calculation request to an empty calculation processing module, and when the calculation result is output from the calculation processing module, the calculation result is displayed. Deposit and notify the CPU using an interrupt signal.

The details are as shown in FIG. 4 in order to realize the function.
FIG. 4 is a diagram illustrating another example of the arithmetic control module.
The calculation request management unit 32 temporarily stores the calculation request. Specifically, the CPU establishes register access to the arithmetic module and stores the register setting for the arithmetic request. Further, the received CPU (CPU A or CPU B) and the serial number of the calculation request are stored as ID information. Then, the calculation request arbitration unit 31 is notified that there has been a calculation request in the calculation request unit. When the calculation request arbitration unit 31 receives a calculation request notification, the stored setting is cleared. At this time, if one CPU issues multiple calculation requests, the CPU must not associate the calculation request with the calculation result. Therefore, when issuing multiple calculation requests, the CPU must write the serial number to the register. .
It is assumed that there are a plurality of storage areas for temporarily storing calculation requests.
The calculation request arbitration unit 31 determines whether the calculation process or calculation process is being processed or is in a standby state from the notification of execution and completion of the calculation request. When notified from the calculation management unit 33, the calculation request stored in the calculation management unit 33 to the standby module is set in the calculation module. When the setting is completed, the calculation request management unit is notified that the calculation request has been completed. At this time, the ID information is received from the calculation request management unit 32 and the module being processed is stored so that it can be interpreted what is being processed. When an interrupt is input from the module for which the calculation process is completed, the completed module and ID information is output to the calculation result management unit 33.

The calculation result management unit 33 confirms the result of the module coming from the calculation request management unit 32. The result is temporarily saved and an interrupt signal is output to the CPU in the ID information. When the result confirmation access from the CPU is completed, the temporarily saved calculation result and ID are deleted. At this time, the serial number in the ID information can be read from the register, and the CPU reads the corresponding register so that the result of which calculation request is known, and is used for identification when there are a plurality of calculation requests.
`` Make sure that the operation request result is known '' means that a serial number storage register * is prepared for each result storage area * (* = 1, 2), and the serial number is stored when the result storage area * is read. It is to know which operation request result is obtained by reading the storage register.
It is assumed that there are a plurality of storage areas for temporarily storing calculation requests.

FIG. 5 is an example of a flow in which arithmetic processing is performed.
In FIG. 5, the horizontal axis represents the transition of time, the state in which each part is being processed or record-holding is indicated by hatching, and the standby state and the storage possible time are indicated by white. Further, the CPU calculation request and the confirmation result indicate that the access is from the A or B CPU in the portion of Δ.
In the example in which this processing is performed, a case will be described where there are two storage areas for the calculation management unit and two storage areas for the calculation result management unit.

The calculation request arbitration unit performs processing arbitration to the calculation request management unit, the calculation modules A and B, and the calculation result management unit as a flow.
When the first request (request A-1) is received from CPU A for the first time, the arithmetic arbitration unit holds data in the arithmetic request storage area 1. Since the calculation module A is free as shown in (1), calculation processing (processing A-1) is performed in the calculation module A.

  Next, when calculation request No. 1 (request B-1) is input from CPU B, the data is stored in the calculation request storage area 1, and this time calculation module A is processing. Arithmetic processing (processing A-1) is performed. If calculation request number 2 (request B-1) is entered into CPU A during this process A-1, calculation request storage area 1 is retained, so it is temporarily stored in calculation request storage area 2, It will be in a standby state until the calculation module becomes free. At this time, even if both computation modules A and B are not available, the request storage area temporarily accepts the request, so that CPU A and CPU B can issue computation requests regardless of the usage status of computation modules A and B. Become.

  Next, when the calculation of the calculation module A is completed, the result is confirmed, and the result is moved to the calculation request storage area as shown in (3). An interrupt instruction is output to CPU A, CPU A finishes checking the result, and processing of request No. 1 (A-1) of CPU A is completed (result A-1). At this time, since the processing module A completes the processing, the processing request in the processing request storage area 2 (4) is started by the processing module A. During this time, if CPU A accesses the third calculation request (request A-3), the storage area of calculation request storage area 1 is free, so CPU A's third calculation request is held there. .

Next, as shown in (5), the processing ends from the operation module B, the operation result is transferred to the result operation request storage area, and the CPU B confirms the result. At this time, if the result confirmation of CPU B is not completed, the result confirmation area 2 is used to move the result of the computation module A to the result computation request storage area as shown in (6).
In the flow as described above, the calculation request arbitration unit can arbitrate calculation requests to efficiently perform calculation processing and reduce the load on the CPU.

<Comparative example>
FIG. 6 is a comparative example showing a difference between the arithmetic unit of the present embodiment and a calculation request access to the arithmetic modules A and B simply.
Since CPU A and CPU B use computation modules independently, CPU A must periodically check that computation module B can be used when CPUs A-2 and A-3 in Figure 6 are requested. As a result, the CPU load increases.
Also, if calculation modules A and B are dedicated to CPU A and CPU B respectively, the request access of CPU A and CPU B is the same as this actual brother pair because module A and B are performing their own calculation processing. It can be realized by the number of times. However, even if there is an operation request to be processed when the other is not using the operation processing module, it cannot be used and the efficiency is lowered.

<Embodiment 2>
FIG. 7 is Embodiment 2 which shows the structure which added the function to the arithmetic control module and arithmetic processing module which were shown in FIG.
The arithmetic processing modules A (13a) and B (13b) output the down counter value from the DMAC data size to the arithmetic control module.
The calculation control module 14-3 includes a calculation request management unit 32 and a processing time estimation unit 34. The calculation request management unit 32 outputs the calculation request ID and data size to the processing time estimation unit 34. If a calculation cancel request is received from the processing time estimation unit 34, the calculation request is canceled and deleted.
The processing time estimation unit 34 calculates the calculation completion estimated time of the arithmetic processing module from the down counter from the arithmetic processing module. In the calculation of the hash value, the processing capacity of the computing unit is fixed if the data is input to a fixed value. Therefore, the calculation completion estimated time is calculated by adding the fixed time for transferring the calculation request and storing the calculation result. I want.
“Estimated processing time of arithmetic processing modules A (13a) and B (13b)” = “fixed time” + “down counter (remaining data size)” ÷ “arithmetic processing capacity”.
Since this value assumes that data can be read without delay, the predicted value is the fastest value.
Based on the ID from the calculation request management unit 32 and the data size value, the calculation completion estimated time of the corresponding ID is calculated. In the calculation of the hash value, the processing capacity of the computing unit is fixed if the data is input to a fixed value. Therefore, the calculation completion estimated time is calculated by adding the fixed time for transferring the calculation request and storing the calculation result. I want.
"Estimated processing time for the corresponding ID" = "Fixed time" + "Data size value" ÷ "Calculation processing capacity"
Since this value assumes that data can be read without delay, the predicted value is the fastest value.

As described above, from the two calculation results, the calculation processing module schedule is predicted to calculate the predicted calculation completion time for completing the calculation request. Since the calculation is performed with the theoretically fastest value, the predicted completion time is the fastest value. This value is output to the calculation request cancellation determination unit.
The calculation request cancellation determination unit can read from the CPU by holding the predicted calculation completion time of each calculation request in a read accessible register. In addition, a calculation request cancel register can be provided to cancel the calculation request after setting the ID calculation serial number. When the calculation request is executed, the calculation request management unit cancels the corresponding calculation request.
Here, “cancel” is a function that prepares a request cancel register and cancels the request when the CPU accesses the register.

  The calculation processing time always takes a fixed time for transferring the calculation request and storing the calculation result. Therefore, when the data size is reduced, the fixed time becomes dominant, and the calculation processing capacity per time is reduced. Therefore, each CPU is equipped with an estimated calculation time threshold register, and when waiting for a turn occurs, the calculation request for the processing estimated time below the estimated calculation time threshold register is automatically canceled and canceled with an interrupt signal. Notify the target CPU of the event. The canceled CPU performs the hash calculation by itself. This is because the processing executed by the CPU itself is processed faster than the arithmetic processing module executes due to processing waiting or the like.

<Embodiment 3>
FIG. 8 is a diagram illustrating the third embodiment.
This figure is an explanatory diagram for predicting the schedule of the arithmetic processing module of the processing time estimation unit. There are arithmetic processing modules A and B, five arithmetic request storage areas, and five arithmetic waits. First, a request of waiting 1 is set to the shorter calculation completion estimated time in the module being calculated, and the estimated completion time of the calculation request A-1 is obtained.
Next, the calculation request B-1 is calculated by superimposing the estimated processing time on the shorter one between the calculation completion estimated time during calculation of the calculation processing module A and the A-1 calculation completion estimated time of the calculation processing module B. By repeating this, the calculation completion estimated time of the calculation request is calculated.

<Program>
The arithmetic device according to the present invention described above is realized by a program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this. Therefore, as an example, a case where the function of the present invention is realized by a program will be described below.

For example,
In a substantial computer of a computing device having two or more hash computing units,
A procedure for determining a hash calculation unit to be executed in response to calculation requests from a plurality of host devices;
The determined hash calculation unit performs a hash calculation procedure,
A program that executes

Thus, the arithmetic device according to the present invention can be realized anywhere as long as there is a computer environment capable of executing the program.
Such a program may be stored in a computer-readable storage medium.

<Storage medium>
Here, examples of the storage medium include a computer-readable storage medium such as a CD-ROM, a flexible disk (FD), and a CD-ROM, a semiconductor memory such as flash memory, RAM, ROM, and FeRAM, and an HDD.

  CE-ROM is an abbreviation for Compact Disc Read Only Memory. Flexible disk means Flexible Disk (FD). CD-R is an abbreviation for CD Recordable. RAM is an abbreviation for Random-Access Memory. ROM is an abbreviation for Read-Only Memory. FeRAM is an abbreviation for Ferroelectric RAM and means a ferroelectric memory. HDD is an abbreviation for Hard Disc Drive.

<Effect>
As described above, according to the present embodiment, by adding an arbitration module between a plurality of arithmetic processing modules and a plurality of CPUs, register settings from any one of the CPUs are temporarily stored in a buffer provided in the arbitration module. . Since the arithmetic module that has not been processed by the arbitration module performs the arithmetic operation, the control from the CPU can be realized with the same control as that of one arithmetic module.
As a result, when multiple CPU modules have the same function, the arbitration module manages multiple modules with the same function so that processing can be performed without being aware of which module's usage status, thereby reducing the CPU control load. Can do.

  In addition, it is possible to operate the computing unit with high efficiency by not performing computation on data with a small data size that decreases in processing capacity during computation processing. This is because the processing capacity per unit time decreases as the overhead ratio increases with respect to the data to be processed. Such data is referred to herein as small data.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

1, 2 Calculation request storage area 11 Non-volatile memory 12 Main storage device 13a Arithmetic processing module A
13b Arithmetic processing module B
14-1, 14-2, 14-3 Operation control module 15 External connection I / F
16a CPU A
16b CPU B
17 Bus line 21 DMAC
22 Calculation Unit 23 Register Unit 31 Calculation Request Arbitration Unit 32 Calculation Request Management Unit 33 Calculation Result Management Unit 34 Processing Time Estimation Unit

JP 2008-250419 A

Claims (8)

  Two or more hash calculation units, and a control unit that determines a hash calculation unit to be executed in response to a calculation request from a plurality of host devices, and causes the determined hash calculation unit to perform a hash calculation. An arithmetic unit. The arithmetic unit according to claim 1,
An arithmetic apparatus comprising: a data counter that counts data calculated by the determined hash calculation unit; and a first calculation circuit that calculates an estimated processing time based on the processing capability of the hash calculation unit. The arithmetic unit according to claim 2,
When an operation is requested to the determined hash calculation unit, the data size of the calculation request content and the processing capability of the hash calculation unit are calculated, and the estimation completion time of a plurality of hash calculation units is aggregated to estimate the shortest time An arithmetic apparatus comprising: a second calculation circuit that calculates an estimated time for completion of the calculation request by combining with a completion time. In the arithmetic unit according to claim 3,
If a threshold can be set and multiple calculation requests are accumulated, the calculation request is rejected if the estimated time to complete the calculation request is greater than or equal to the threshold and the data size of the calculation request is less than or equal to the threshold. An arithmetic unit comprising a rejection circuit. In the arithmetic unit according to claim 3,
A computing device having a function of notifying a host device of an estimated time for completion of a computation request. The arithmetic unit according to claim 5, wherein
A computing device having a function of canceling a computation request.   A determination unit of an arithmetic device having two or more hash operation units determines a hash operation unit to be executed in response to an operation request from a plurality of host devices, and the determined hash operation unit performs a hash operation An arithmetic method characterized by In a substantial computer of a computing device having two or more hash computing units,
A procedure for determining a hash calculation unit to be executed in response to calculation requests from a plurality of host devices;
The determined hash calculation unit performs a hash calculation,
A program characterized by having executed.

Images