JP2014232555A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer test read data to a data bus with a simple configuration.SOLUTION: A semiconductor device includes: a data amplifier 60 that transfers read data which is read from a memory cell array, to a data bus RWBS1; a BOC circuit 70 that switches a correspondence between the data bus RWBS1 and a data bus RWBS2, in response to a control signal S1; and a DBI circuit 80 that inverts the read data on the data bus RWBS2 in response to a control signal S2 and outputs it to a data bus RWBS3. The DBI circuit 80 includes a multiplexer for selecting inverted read data or non-inverted read data. When a control signal S3 is active, the multiplexer selects test read data TRD and transfers it to the data bus RWBS3. According to this invention, the test read data can be transferred to a data bus without increasing the number of signal wiring lines that constitute the data bus.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a multipurpose register for holding test read data.

  A DRAM (Dynamic Random Access Memory) which is a typical semiconductor device performs a read leveling operation in read training after an initialization period. The read leveling operation is a kind of training operation that measures the timing at which the test read data output from the DRAM reaches the memory controller, and adjusts the read data reception timing on the memory controller side based on the result (patent) Reference 1).

  Test read data used in the read leveling operation is held in a register circuit called a multi-purpose register. Here, in the DDR3 (Double Data Rate 3) type DRAM, since the data pattern of the test read data is defined by the standard, the function for transferring the test read data to the data bus is performed by a simple circuit. It is possible to realize.

JP 2012-194686 A

  However, in a recently proposed DDR4 (Double Data Rate 4) type DRAM, a standard is defined so that a data pattern of test read data can be arbitrarily designated on the user side. For this reason, depending on the circuit configuration of the circuit that transfers the test read data to the data bus and the connection position to the data bus, the transfer time of the read data on the data bus increases, and the number of signal wirings increases significantly. It is possible that this problem will occur.

  A semiconductor device according to the present invention includes a memory cell array having a plurality of memory cells, a data bus including a plurality of signal wirings, and a data amplifier for transferring read data including a plurality of bits read from the memory cell array to the data bus. An output circuit for outputting the read data transferred via the data bus to a data terminal; and, in response to a first control signal, the plurality of signal wirings constituting the data bus and the read data. A BOC circuit that switches a correspondence relationship with the plurality of bits that constitutes, a DBI circuit that inverts the logic level of the plurality of bits that constitutes the read data in response to a second control signal, and a test read consisting of a plurality of bits In response to a multipurpose register for holding data and a third control signal, the test read data A multiplexer for transferring the data to the data bus, and the BOC circuit and the DBI circuit are inserted in series in the data bus, and the multiplexer includes an output node of the data amplifier, the BOC circuit, and the The data bus is inserted between any one of the output nodes of the DBI circuit.

  According to the present invention, since the test read data is transferred to the data bus by arranging the multiplexer upstream from the output node of the BOC circuit or DBI circuit, the data bus in the portion connected to the output circuit is transferred. There is no need to increase the number. As a result, it is possible to transfer the test read data to the data bus without increasing the number of signal wirings constituting the data bus. For example, if test read data is supplied to the data bus using a multiplexer used in the DBI circuit, the transfer time of read data on the data bus does not increase.

1 is a block diagram showing an overall structure of a semiconductor device 10 according to a preferred embodiment of the present invention. 2 is a block diagram showing a configuration of a data controller 15. FIG. It is a figure for demonstrating the function of the BOC circuit 70, (a) shows the relationship between data bus RWBS1 and read data, (b) has shown an example of the relationship between data bus RWBS2 and read data. 4A and 4B are diagrams for explaining the function of a DBI circuit 80. FIG. 5A shows the value of read data on the data bus RWBS2, and FIG. 5B shows the value of read data on the data bus RWBS3. 2 is a block diagram showing configurations of a FIFO circuit 16 and a data input / output circuit 17. FIG. 2 is a schematic plan view showing a layout of a semiconductor device 10. FIG. FIG. 7 is a schematic plan view showing the layout of a region B shown in FIG. 6 in more detail. It is a block diagram for demonstrating the data bus structure by the prototype which the present inventors considered in the process leading to invention. 3 is a circuit diagram of a DBI circuit 80 according to the first embodiment of the present invention. FIG. It is a block diagram which shows the structure of the data controller 15 by the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the data controller 15 by the 3rd Embodiment of this invention. 3 is a circuit diagram showing a part of a BOC circuit 70. FIG. It is a block diagram which shows the structure of the data controller 15 by the 4th Embodiment of this invention. It is a block diagram which shows the structure of the data controller 15 by the 5th Embodiment of this invention. It is a block diagram which shows the structure of the data controller 15 by the 6th Embodiment of this invention. It is a block diagram which shows the structure of the data controller 15 by the 7th Embodiment of this invention. It is a block diagram which shows the structure of the data controller 15 by the 8th Embodiment of this invention. It is a block diagram which shows the structure of the data controller 15 by the 9th Embodiment of this invention. FIG. 10 is a schematic plan view showing a layout of a semiconductor device 10 according to a tenth embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM integrated on one semiconductor chip, and includes a memory cell array 11 divided into n + 1 banks as shown in FIG. A bank is a unit capable of executing commands individually, and basically non-exclusive operations are possible between banks.

  The memory cell array 11 is provided with a plurality of word lines WL and a plurality of bit lines BL intersecting with each other, and memory cells MC are arranged at the intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. Each bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 14, and the bit line BL selected by the column decoder 13 is connected to the data controller 15 via the sense amplifier SA. The data controller 15 is connected to the data input / output circuit 17 via the FIFO circuit 16. The data input / output circuit 17 is a circuit block that inputs and outputs data via the data terminal 21.

  In addition to the data terminal 21, the semiconductor device 10 includes strobe terminals 22 and 23, clock terminals 24 and 25, a clock enable terminal 26, an address terminal 27, a command terminal 28, an alert terminal 29, power supply terminals 30 and 31, as external terminals. 34, a data mask terminal 32, an ODT terminal 33, and the like are provided.

  The strobe terminals 22 and 23 are terminals for inputting / outputting external strobe signals DQST and DQSB, respectively. The external strobe signals DQST and DQSB are complementary signals and define the input / output timing of data input / output via the data terminal 21. Specifically, at the time of data input, that is, at the time of write operation, external strobe signals DQST and DQSB are supplied to the strobe circuit 18, and the strobe circuit 18 controls the operation timing of the data input / output circuit 17 based on them. . Thereby, the write data input via the data terminal 21 is taken into the data input / output circuit 17 in synchronization with the external strobe signals DQST and DQSB. On the other hand, at the time of data output, that is, at the time of read operation, the operation of the strobe circuit 18 is controlled by the strobe controller 19. As a result, the data input / output circuit 17 outputs read data in synchronization with the external strobe signals DQST and DQSB.

  The clock terminals 24 and 25 are terminals to which external clock signals CK and / CK are input, respectively. The input external clock signals CK and / CK are supplied to the clock generator 40. In this specification, a signal having “/” at the head of a signal name means a low active signal or an inverted signal of the corresponding signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generator 40 is activated based on the clock enable signal CKE input via the clock enable terminal 26, and generates the internal clock signal ICLK. The external clock signals CK and / CK supplied via the clock terminals 24 and 25 are also supplied to the DLL circuit 41. The DLL circuit 41 is a circuit that generates an output clock signal LCLK whose phase is controlled based on the external clock signals CK and / CK. The output clock signal LCLK is used as a timing signal that defines the output timing of read data by the data input / output circuit 17.

  The address terminal 27 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the row control circuit 51, the column control circuit 52, the mode register 42, the command decoder 43, the multipurpose register 53, and the like. The The row control circuit 51 is a circuit block including an address buffer and a refresh counter, and controls the row decoder 12 based on the row address. The column control circuit 52 is a circuit block including an address buffer and a burst counter, and controls the column decoder 13 based on the column address. If the entry is made in the mode register set, the address signal ADD is supplied to the mode register 42, whereby the contents of the mode register 42 are updated.

  The command terminal 28 is a terminal to which a chip select signal / CS, an act signal / ACT, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a parity signal PRTY, a reset signal RST, and the like are supplied. is there. These command signals CMD are supplied to the command decoder 43, and the command decoder 43 generates an internal command ICMD based on these command signals CMD. The internal command signal ICMD is supplied to the control logic circuit 44. The control logic circuit 44 controls operations of the row control circuit 51, the column control circuit 52, the data controller 15, the multipurpose register 53, and the like based on the internal command signal ICMD.

  The command decoder 43 includes a verification circuit (not shown). The verification circuit verifies the address signal ADD and the command signal CMD based on the parity signal PRTY. As a result, if there is an error in the address signal ADD or the command signal CMD, the verification circuit passes through the control logic circuit 44 and the output circuit 45. To output an alert signal ALRT. The alert signal ALRT is output to the outside via the alert terminal 29. This error information, that is, the CA parity error status is stored in the multipurpose register 53, and the stored information is output as the alert signal ALRT.

  The power supply terminals 30, 31, and 34 are terminals to which power supply potentials VDD, VSS, and VPP are supplied, respectively. The power supply potentials VDD, VSS, VPP supplied through the power supply terminals 30, 31, 34 are supplied to the power supply circuit 46. The power supply circuit 46 is a circuit block that generates various internal potentials based on the power supply potentials VDD, VSS, and VPP. The internal potential generated by the power supply circuit 46 includes an array potential VARY, a reference potential VREF, and the like. The array potential VARY and the reference potential VREF are generated by stepping down the external potential VDD.

  The external voltage VPP is a potential mainly used in the row decoder 12. The row decoder 12 drives the word line WL selected based on the address signal ADD to the VPP level, thereby turning on the cell transistor included in the memory cell MC. The internal potential VARY is a potential mainly used in the sense circuit 14. When the sense circuit 14 is activated, the read data read out is amplified by driving one of the bit line pairs to the VARY level and the other to the VSS level. The external potential VDD is used as an operating potential for most peripheral circuits such as the row control circuit 51 and the column control circuit 52. The reference potential VREF is a potential used in the data input / output circuit 17.

  The data mask terminal 32 and the ODT terminal 33 are terminals to which a data mask signal DM and a termination signal ODT are supplied, respectively. The data mask signal DM and the termination signal ODT are supplied to the data input / output circuit 17. The data mask signal DM is activated when masking part of the write data and read data, and the termination signal ODT is used when the output buffer included in the data input / output circuit 17 is used as a termination resistor. This is a signal to be activated. The data mask terminal 32 is also used as a DBI terminal. For example, when the value of the terminal 32 is at a low level, after the data is inverted in the semiconductor device 10, the inverted data is written into the memory cell array or output from the semiconductor device 10. When the value of the terminal 32 is at a high level, the non-inverted data is written into the memory cell array or output from the semiconductor device 10 without inverting the data in the semiconductor device 10. Whether the terminal 32 is used as a data mask terminal or a DBI terminal is specified by the mode register 42.

  FIG. 2 is a block diagram showing the configuration of the data controller 15.

  As shown in FIG. 2, the data controller 15 includes a data amplifier 60, a BOC circuit 70, and a DBI circuit 80. The data amplifier 60 is a circuit used in both the read operation and the write operation, and the DBI circuit 80 and the BOC circuit 70 are circuits that can be used in both the read operation and the write operation. For example, the BOC circuit 70 changes its control at the time of reading and writing, and is controlled by, for example, three control signals Y0, Y1, and Y2 at the time of reading, and is controlled by one control signal of Y2 at the time of writing. The

  In a read operation, data amplifier 60 amplifies read data supplied from column decoder 13 via input / output node 61 and outputs the amplified data from input / output node 62 to data bus RWBS1. In a write operation, the write data supplied from the data bus RWBS1 via the input / output node 62 is amplified and output from the input / output node 61 to the column decoder 13. The data bus RWBS1 includes a plurality of signal lines, and can transmit a plurality of bits of read data and write data in parallel. For example, when the data bus RWBS1 is composed of 64 signal wires, 64-bit read data and write data are transmitted in parallel. The same applies to data buses RWBS2 and RWBS3 described later. In this specification, the data buses RWBS1 to RWBS3 may be collectively referred to as “data bus RWBS”.

  The BOC circuit 70 is a circuit for switching the connection relationship between a plurality of signal wirings constituting the data bus RWBS1 and a plurality of signal wirings constituting the data bus RWBS2 in response to the control signal S1. As shown in FIG. 2, the BOC circuit 70 includes an input node 71 and an output node 72. The input node 71 is connected to the data bus RWBS1, and the output node 72 is connected to the data bus RWBS2.

  3A and 3B are diagrams for explaining the function of the BOC circuit 70. FIG. 3A shows the relationship between the data bus RWBS1 and the read data, and FIG. 3B shows an example of the relationship between the data bus RWBS2 and the read data. Show. Further, DQm (m = 0 to 7) shown in FIGS. 3A and 3B indicates the corresponding data terminal 21, and Dn (n = 0 to 7) indicates the read data burst output from the data terminal 21. The output order is shown. Therefore, FIGS. 3A and 3B show an example in which 8-bit read data is burst output from each of the eight data terminals 21. FIG. This also applies to FIGS. 4A and 4B described later.

  In response to the control signal S1, the arrangement of the read data on the data bus RWBS1 shown in FIG. 3A is changed in the data bus RWBS2 as shown in FIG. 3B. For example, when attention is focused on read data corresponding to DQ0, 8-bit read data that should have been burst output in the order of read data 0, 1, 2, 3, 4, 5, 6, 7 is stored in the BOC circuit 70. As shown in FIG. 3B, the bursts are output in the order of 7, 4, 5, 6, 3, 0, 1 and 2. The burst output order shown in FIG. 3B is an example, and how to change the burst output order is specified by the value of the control signal S1.

  As the control signal S1, a part of the column address input in synchronization with the read command can be used. For example, if the lower 3 bits (Y0 to Y2) of the column address are used, the burst output order can be changed to 8 ways. The order of burst output is not changed depending on the value of the control signal S1, and the relationship between the data bus RWBS2 and the read data is also maintained as shown in FIG. The state where the control signal S1 shows such a value means that the control signal S1 is at an inactive level.

  The DBI circuit 80 is a circuit for inverting the logic level of the read data on the data bus RWBS2 in response to the control signal S2. As shown in FIG. 2, the DBI circuit 80 includes an input node 81 and an output node 82. The input node 81 is connected to the data bus RWBS2, and the output node 82 is connected to the data bus RWBS3.

  4A and 4B are diagrams for explaining the function of the DBI circuit 80. FIG. 4A shows the value of read data on the data bus RWBS2, and FIG. 4B shows the value of read data on the data bus RWBS3. Yes.

  As shown in FIG. 4B, one bit of the control signal S2 is assigned for each burst output timing, and therefore the control signal S2 has an 8-bit configuration in this example. Then, the logic level of the 8-bit read data corresponding to the burst output timing in which the bit constituting the control signal S2 is the active level (low level in this example) is inverted. In the example shown in FIG. 4B, the bits corresponding to the burst output timings D0 to D4 are inactive level (high level), and the bits corresponding to the burst output timings D5 to D7 are active level (low level). . As a result, it can be seen that the logical level of the read data at the burst output timings D5 to D7 shown in FIG. 4A is inverted in FIG. 4B.

  As shown in FIG. 2, test read data TRD is also input to the DBI circuit 80 in this embodiment. The test read data TRD is data held in the multi-purpose register 53, and is used as test data output to the outside during the read leveling operation. Therefore, the present embodiment has a configuration in which the test read data TRD is supplied to the data bus RWBS via the DBI circuit 80.

  As described above, in the present embodiment, the BOC circuit 70 and the DBI circuit 80 are inserted in series in the data bus RWBS, and read data controlled by these circuits is supplied to the FIFO circuit 16 during normal read operation. Is done. In the read leveling operation, the test read data TRD held in the multipurpose register 53 is supplied from the DBI circuit 80 to the FIFO circuit 16 via the data bus RWBS3.

  FIG. 5 is a block diagram showing the configuration of the FIFO circuit 16 and the data input / output circuit 17.

  As shown in FIG. 5, the FIFO circuit 16 includes a serializer 16a and a deserializer 16b connected to the data bus RWBS3. The serializer 16a is a circuit used during a read operation, converts read data DQ (or test read data TRD) supplied in parallel via the data bus RWBS3 into serial data, and an output circuit included in the data input / output circuit 17 It plays the role of supplying to 17a. The operation of the serializer 16a is performed in synchronization with the output clock signal LCLK supplied from the DLL circuit 41 shown in FIG.

  On the other hand, the deserializer 16b is a circuit used during a write operation, and plays a role of converting the write data DQ supplied serially from the input buffer 17b included in the data input / output circuit 17 into parallel and supplying it to the data bus RWBS3. .

  As described above, the data input / output circuit 17 includes the output circuit 17a and the input buffer 17b. As shown in FIG. 5, the output circuit 17 a includes a level shift circuit (L / S) 91, an impedance adjustment circuit 92, a slew rate adjustment circuit 93, and an output buffer 94. The level shift circuit 91 is a circuit that converts read data DQ (or test read data TRD) having an amplitude from the ground potential VSS to the power supply potential VDD into an amplitude from the ground potential VSS to the power supply potential VDDQ. The impedance adjustment circuit 92 is a circuit that controls the impedance of the output buffer 94 based on an impedance designation signal (not shown). Further, the slew rate adjustment circuit 93 is a circuit that controls the slew rate of the read data DQ (or test read data TRD) output from the output buffer 94 based on a slew rate designation signal (not shown).

  The output buffer 94 drives the data terminal 21 based on the logical level of the read data DQ (or test read data TRD), the value of the impedance designation signal, and the value of the slew rate designation signal. As a result, the read data DQ (or test read data TRD) is output to the outside of the semiconductor device 10.

  FIG. 6 is a schematic plan view showing the layout of the semiconductor device 10.

  As shown in FIG. 6, the semiconductor device 10 according to the present embodiment has a memory cell region MA in which the memory cell array 11 is mainly disposed, and a peripheral circuit region PE in which peripheral circuits and external terminals are disposed. In this embodiment, the memory cell area MA is divided into two, and the peripheral circuit area PE is provided extending in the X direction so as to be sandwiched between the two memory cell areas MA.

  Four bank groups BG are provided in the memory cell area MA, and four memory banks are arranged in each bank group BG. The four memory banks constituting each bank group BG are divided into an area A1 where two memory banks are arranged and an area A2 where the remaining two memory banks are arranged, and are sandwiched between these areas A1 and A2. A data bus RWBS1 extends in the Y direction in the area. The data bus RWBS1 is connected to the data control area DC via some intermediate buffers BF. As shown in FIG. 6, the data control area DC is a circuit area including the BOC circuit 70, the DBI circuit 80, and the like. Although not shown, the data amplifier 60 is arranged in the memory cell area MA.

  In the present embodiment, one data control area DC is allocated to the two bank groups BG arranged on the left side shown in FIG. 6, and the two bank groups BG arranged on the right side shown in FIG. One data control area DC is allocated. Further, a multipurpose register (MPR) 53 is arranged in the vicinity of the data control area DC.

  As shown in FIG. 6, the data control area DC is connected to the output circuit area OC via the data bus RWBS3. The output circuit area OC is a circuit area including the FIFO circuit 16, the data input / output circuit 17, the data terminal 21, and the like. In the present embodiment, the output circuit area OC is divided into two, one output circuit area OC1 is provided with circuits corresponding to DQ0 to DQ7, and the other output circuit area OC2 is provided with DQ8 to DQ15. A circuit is arranged.

  With this configuration, the length of the signal path of the test read data TRD to be output via DQ0 to DQ7 and the length of the signal path of the test read data TRD to be output via DQ8 to DQ15 can be substantially matched. It becomes possible to improve the signal quality of the test read data TRD.

  FIG. 7 is a schematic plan view showing the layout of the region B shown in FIG. 6 in more detail.

  As shown in FIG. 7, each of the output circuit areas OC1 and OC2 includes two output pad areas DQP and two output control areas DQC. In FIG. 7, the shaded area W is an area where the data bus RWBS3 extends in the X direction. As shown in FIG. 7, a data control area DC is arranged between the output circuit areas OC1 and OC2, and read data DQ output from the data control area DC is transmitted via the data bus RWBS3 during a read operation. It is transferred to the output control area DQC.

  FIG. 8 is a block diagram for explaining a data bus structure based on a prototype considered by the present inventors in the process of reaching the invention.

  In the prototype shown in FIG. 8, a data bus RWBS4 connected to the multi-purpose register 53 is provided in addition to the data bus RWBS3 connected to the data control area DC, and one of the data buses RWBS3 and RWBS4 is connected by the multiplexer MUX0. It has a configuration connected to the output circuit area OC. According to such a configuration, either the read data DQ or the test read data TRD can be output in response to the control signal S3.

  However, when the data bus structure shown in FIG. 8 is adopted, a data bus RWBS4 is required separately from the data bus RWBS3. Here, when the data bus RWBS3 is composed of 64 signal wires, since the data bus RWBS4 also requires 64 signal wires, a total of 128 data buses RWBS3 and RWBS4 are arranged in the area W shown in FIG. Need to be placed in For this reason, it is necessary to enlarge the area of the region W shown in FIG. 7, which leads to an increase in the chip area.

  In each of the embodiments described below, the above-described problems caused by the prototype are solved, and the test read data TRD can be supplied to the data bus RWBS without increasing the number of data buses RWBS.

  FIG. 9 is a circuit diagram of the DBI circuit 80 according to the first embodiment of the present invention.

  As shown in FIG. 9, the DBI circuit 80 according to the first embodiment of the present invention includes a multiplexer MUX1 having input nodes N1, N2 and an output node N3. The input node N1 of the multiplexer MUX1 is connected to the input node 81, whereby the read data DQ is supplied via the data bus RWBS2. On the other hand, the read data DQ is supplied to the input node N2 of the multiplexer MUX1 via the data bus RWBS2 and the NAND gate circuit G1. When the read data DQ and the control signal S3 are input to the NAND gate circuit G1, and thus the control signal S3 is deactivated to a high level, the inverted signal of the read data DQ is applied to the input node N2 of the multiplexer MUX1. Will be supplied. The control signal S3 is activated to a low level when a read leveling operation is performed, and is fixed to a high level during a normal read operation.

  When the control signal S3 is activated to the low level, the output signal of the NAND gate circuit G1 is fixed to the high level, and therefore the input node N2 of the multiplexer MUX1 is also fixed to the high level. Further, since the inverter circuit INV is connected between the input nodes N2 and N1 of the multiplexer MUX1, when the control signal S3 is activated to the low level, the input node N1 of the multiplexer MUX1 is at the low level. Fixed to.

  As shown in FIG. 9, the selection signal SEL is input to the multiplexer MUX1, and one of the input nodes N1 and N2 is connected to the output node N3 based on the logic level. Specifically, the input node N1 is selected if the selection signal SEL is high level, and the input node N2 is selected if the selection signal SEL is low level.

  The selection signal SEL is generated by a NAND gate circuit G2 that receives the control signal S2 and the test read data TRD. As described above, since 1 bit is assigned to the control signal S2 for each burst output timing, 8 bits are provided for the 64-bit read data DQ. The logical level of the control signal S2 is designated according to whether the read data DQ should be inverted or not during the read operation in which the DBI function is used. During the read operation, all the test read data TRD are fixed at the high level. Thereby, the logic level of the selection signal SEL is determined by the logic level of the control signal S2. As described above, since the control signal S3 is fixed at the high level during the normal read operation, a signal obtained by inverting or not inverting the read data DQ based on the control signal S2 is output to the data bus RWBS3. Will be.

  On the other hand, during the read leveling operation, the control signal S3 is fixed at a low level and the control signal S2 is fixed at a high level. Thereby, the input nodes N1 and N2 of the multiplexer MUX1 are fixed to the low level and the high level, respectively, and the logic level of the selection signal SEL is determined by the logic level of the test read data TRD.

  Specifically, when the test read data TRD is at the low level, the selection signal SEL is at the high level, so that the input node N1 is selected. As a result, the data bus RWBS3 has the same low level as the test read data TRD. A signal is output. Conversely, when the test read data TRD is at a high level, the selection signal SEL is at a low level, so that the input node N2 is selected. As a result, the same high level signal as the test read data TRD is applied to the data bus RWBS3. Is output. Thus, during the read leveling operation, the test read data TRD is read out to the data bus RWBS3. That is, for each bit of the 64-bit test read data TRD on the 64-bit bus, the value of the corresponding input node N1, N2 of the 64-bit data bus RWBS2 is selected by the multiplexer MUX1, and the selection is made. By transmitting the result to the 64-bit data bus RWBS3, the test read data TRD is read out to the data bus RWBS3.

  With this configuration, the test read data TRD can be directly supplied to the data bus RWBS3 without providing the data bus RWBS4 or the like different from the data bus RWBS3. As a result, the number of signal wirings constituting the data bus RWBS does not increase, so that an increase in chip area can be prevented. In addition, in this embodiment, since the test read data TRD is supplied to the data bus RWBS using the multiplexer MUX1 used in the DBI circuit 80, it is necessary to insert an additional circuit or the like into the data bus RWBS. No. As a result, an increase in read data transfer time caused by inserting an additional circuit into data bus RWBS does not occur. The DBI function is used during normal read operations, but not used during read leveling operations. Therefore, even if the multiplexer MUX1 is shared by both the DBI function and the read leveling operation, these functions do not interfere with each other. .

  As described above, according to the present embodiment, the test read data TRD is transferred from the multipurpose register 53 without increasing the transfer time of the read data DQ or increasing the number of signal wires constituting the data bus RWBS. The data can be transferred to the data bus RWBS.

  FIG. 10 is a block diagram showing the configuration of the data controller 15 according to the second embodiment of the present invention.

  As shown in FIG. 10, the data controller 15 according to the present embodiment is different from the data controller 15 shown in FIG. 2 in that the connection order of the BOC circuit 70 and the DBI circuit 80 is reversed. Even with this configuration, the same effects as those of the first embodiment described above can be obtained. Thus, in the present invention, the connection order of the circuits in the data controller 15 is not particularly limited.

  In the first and second embodiments described above, the test read data TRD is transferred using the multiplexer MUX1 included in the DBI circuit 80, but the present invention is not limited to this.

  FIG. 11 is a block diagram showing the configuration of the data controller 15 according to the third embodiment of the present invention.

  As shown in FIG. 11, the data controller 15 according to the present embodiment is different from the data controller 15 shown in FIG. 2 in that the control signal S3 and the test read data TRD are input to the BOC circuit 70.

  FIG. 12 is a circuit diagram showing a part of the BOC circuit 70. A circuit portion for switching the connection relation between the signal wirings L1 and L2 constituting the data bus RWBS1 and the signal wirings L3 and L4 constituting the data bus RWBS2 is shown. This is shown schematically. As shown in FIG. 12, the BOC circuit 70 includes a multiplexer MUX2 that connects one of the signal lines L1 and L2 to the signal line L3 and connects the other of the signal lines L1 and L2 to the signal line L4. The selection is performed by the control signal S1. In this embodiment, the multiplexer MUX2 is used, and when the control signal S3 is activated, the test read data TRD is selected and output to the data bus RWBS2.

  Even if it is this structure, the same effect as each embodiment mentioned above can be acquired. Thus, the multiplexer used in the present invention may be included in any part in the data controller 15.

  FIG. 13 is a block diagram showing the configuration of the data controller 15 according to the fourth embodiment of the present invention.

  As shown in FIG. 13, the data controller 15 according to the present embodiment is different from the data controller 15 shown in FIG. 11 in that the connection order of the BOC circuit 70 and the DBI circuit 80 is reversed. Even with this configuration, the same effects as those of the third embodiment described above can be obtained.

  FIG. 14 is a block diagram showing the configuration of the data controller 15 according to the fifth embodiment of the present invention.

  As shown in FIG. 14, the data controller 15 according to the present embodiment is different from the data shown in FIG. 2 in that a multiplexer MUX3 is inserted between the output node 72 of the BOC circuit 70 and the input node 81 of the DBI circuit 80. This is different from the controller 15. The multiplexer MUX3 is a circuit that selects either the read data DQ supplied from the data bus RWBS2 or the test read data TRD supplied from the multipurpose register 53 based on the control signal S3. Even with such a configuration, it is possible to transfer the test read data TRD to the data bus RWBS without increasing the number of signal wires constituting the data bus RWBS.

  FIG. 15 is a block diagram showing the configuration of the data controller 15 according to the sixth embodiment of the present invention.

  As shown in FIG. 15, the data controller 15 according to the present embodiment is different from the data controller 15 shown in FIG. 14 in that the connection order of the BOC circuit 70 and the DBI circuit 80 is reversed. Even with this configuration, the same effects as those of the fifth embodiment described above can be obtained.

  FIG. 16 is a block diagram showing the configuration of the data controller 15 according to the seventh embodiment of the present invention.

  As shown in FIG. 16, the data controller 15 according to this embodiment is shown in FIG. 2 in that a multiplexer MUX4 is inserted between the input / output node 62 of the data amplifier 60 and the input node 71 of the BOC circuit 70. This is different from the data controller 15. The multiplexer MUX4 is a circuit that selects one of the read data DQ supplied from the data bus RWBS1 and the test read data TRD supplied from the multipurpose register 53 based on the control signal S3. Even with such a configuration, it is possible to transfer the test read data TRD to the data bus RWBS without increasing the number of signal wires constituting the data bus RWBS.

  FIG. 17 is a block diagram showing the configuration of the data controller 15 according to the eighth embodiment of the present invention.

  As shown in FIG. 17, in the data controller 15 according to the present embodiment, the connection order of the BOC circuit 70 and the DBI circuit 80 is reversed, and the multiplexer MUX4 is inserted between the data amplifier 60 and the DBI circuit 80. However, it is different from the data controller 15 shown in FIG. Even with this configuration, the same effects as those of the seventh embodiment described above can be obtained.

  FIG. 18 is a block diagram showing the configuration of the data controller 15 according to the ninth embodiment of the present invention.

  As shown in FIG. 18, the data controller 15 according to the present embodiment is different from the data controller 15 shown in FIG. 16 in that a tristate buffer 100 is inserted between the multiplexer MUX4 and the BOC circuit 70. Yes. The tristate buffer 100 is a circuit whose output node 102 is in a high impedance state during a write operation, and plays a role of reducing the load capacity of the data bus RWBS during the write operation. Thus, the present invention can be applied even when the data controller 15 includes other circuits such as the tristate buffer 100.

  FIG. 19 is a schematic plan view showing a layout of the semiconductor device 10 according to the tenth embodiment of the present invention.

  As shown in FIG. 19, the present embodiment is different from the layout shown in FIG. 6 in that the multipurpose register 53 in the vicinity of the data control area DC arranged on the right side shown in FIG. 19 is deleted. Yes. Since the other points are the same as those in the layout shown in FIG.

  In the present embodiment, when only DQ0 to DQ7 are used, the test read data TRD read from the multipurpose register 53 is supplied to the output circuit area OC1 via the left data control area DC. On the other hand, when DQ0 to DQ15 are used, a part of the test read data TRD read from the multipurpose register 53 is supplied to the output circuit area OC1 via the left data control area DC and tested. The remaining portion of the read data TRD is supplied from the output circuit area OC1 to the output circuit area OC2 via the right data control area DC. According to such a configuration, it is not necessary to arrange the multipurpose register 53 in the region B where the circuits are very dense in the layout, so that the chip area can be further reduced.

  Finally, the multi-purpose register 53 will be described. The multipurpose register 53 may have a plurality of pages. For example, the test read data TRD described in the present embodiment is stored in page 0, the command address parity error log is stored in page 1, the temperature sensor value, CAS latency value, etc. are stored in page 2, and page 3 Can store data used by vendors. Further, page 0 can be read / written, and pages 1 to 3 can be read-only. These pages can be selected by addresses A0 and A1. When writing to page 0, the multi-purpose register is externally input via the data input / output terminal 21, the data input / output circuit 17, and a signal path (not shown) provided between the data bus DB and the multi-purpose register 53. It is also possible to write data to 53. Page 0 is written as default values, for example, and the user can rewrite these values as appropriate. The page 0 has a plurality of MPR locations MPR0, MPR1, MPR2, and MPR3, and “01010101”, “00110011”, “000011111”, and “00000000” are stored as default values, respectively. These MPR values can be appropriately changed by the user. In the present embodiment, the test read data TRD at the time of the read operation shown in FIG. 9 is “11111111”, but this value may be a value written by a user in one MPR location. Each MPR location is composed of 8 bits. Therefore, as shown in FIG. 9, since the test read data TRD is 64 bits, it is generated by combining eight values of one MPR location.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Sense circuit 15 Data controller 16 FIFO circuit 16a Serializer 16b Deserializer 17 Data input / output circuit 17a Output circuit 17b Input buffer 18 Strobe circuit 19 Strobe controller 21 Data terminals 22, 23 Strobe terminals 24, 25 Clock terminal 26 Clock enable terminal 27 Address terminal 28 Command terminal 29 Alert terminal 30, 31, 34 Power supply terminal 32 Data mask terminal 33 ODT terminal 40 Clock generator 41 DLL circuit 42 Mode register 43 Command decoder 44 Control logic circuit 45 Output Circuit 46 Power supply circuit 51 Row control circuit 52 Column control circuit 53 Multipurpose circuit Jistor 60 Data amplifiers 61 and 62 Input / output node 70 BOC circuit 71 Input node 72 Output node 80 DBI circuit 81 Input node 82 Output node 91 Level shift circuit 92 Impedance adjustment circuit 93 Slew rate adjustment circuit 94 Output buffer 100 Tristate buffer 101 Input Node 102 Output node BF Intermediate buffer BG Bank group BL Bit line DC Data control area DQC Output control area DQP Output pad areas G1, G2 Gate circuit INV Inverter circuits L1-L4 Signal wiring MA Memory cell area MC Memory cells MUX0-MUX4 Multiplexer N1 , N2 Input node N3 Output nodes OC1, OC2 Output circuit area PE Peripheral circuit area RWBS1-RWBS4 Data bus SA Sense amplifier WL Word line

Claims (15)

A memory cell array having a plurality of memory cells;
A data bus consisting of a plurality of signal wirings;
A data amplifier for transferring read data consisting of a plurality of bits read from the memory cell array to the data bus;
An output circuit for outputting the read data transferred via the data bus to a data terminal;
In response to a first control signal, a BOC circuit that switches a correspondence relationship between the plurality of signal wirings constituting the data bus and the plurality of bits constituting the read data;
A DBI circuit for inverting the logic levels of the plurality of bits constituting the read data in response to a second control signal;
A multi-purpose register holding test read data consisting of multiple bits;
A multiplexer for transferring the test read data to the data bus in response to a third control signal;
The BOC circuit and the DBI circuit are inserted in series with the data bus,
The semiconductor device, wherein the multiplexer is inserted into the data bus between an output node of the data amplifier and an output node of one of the BOC circuit and the DBI circuit. A serializer that serially converts the parallel read data transferred via the data bus;
The semiconductor device according to claim 1, wherein the output circuit includes an output buffer that outputs the serial read data from the data terminal to the outside.   The semiconductor device according to claim 1, wherein the multiplexer is inserted between an input node and an output node of the DBI circuit. The multiplexer has first and second input nodes and an output node;
The output node of the multiplexer is connected to the output node of the DBI circuit;
The read data supplied to the input node of the DBI circuit is input to the first input node of the multiplexer,
An inverted signal of the read data supplied to the input node of the DBI circuit is input to the second input node of the multiplexer in response to the third control signal being at an inactive level. ,
The multiplexer is configured to connect one of the first and second input nodes to the output node in response to a selection signal generated based on at least the second control signal. 3. The semiconductor device according to 3.   In response to the third control signal being at an active level, the DBI circuit sets a first logic level that sets the first and second input nodes of the multiplexer to a first logic level and a second logic level, respectively. 5. The semiconductor device according to claim 4, further comprising: a circuit; and a second logic circuit that generates the selection signal by logically synthesizing the second control signal and the test read data. The second control signal is fixed to a predetermined logic level when the test read data is output from the data terminal,
6. The semiconductor device according to claim 5, wherein the test read data is fixed to a predetermined logic level when the read data is output from the data terminal.   The semiconductor device according to claim 1, wherein the multiplexer is inserted between an input node and an output node of the BOC circuit.   3. The multiplexer according to claim 1, wherein the multiplexer is inserted into the data bus between the output node of the data amplifier and an input node of one of the BOC circuit and the DBI circuit. The semiconductor device described.   The semiconductor device according to claim 8, wherein the multiplexer is inserted between the BOC circuit and the DBI circuit.   10. The semiconductor device according to claim 1, further comprising a tristate buffer inserted into the data bus and deactivated during a write operation. A memory cell array having a plurality of memory cells;
First and second data buses;
A data amplifier for transferring read data read from the memory cell array to the first data bus;
A first input node is connected to the first data bus, a second input node is connected to the first data bus via a first logic circuit, and an output node is connected to the second data bus. Connected multiplexers;
An output circuit for outputting the read data transferred via the second data bus to a data terminal;
A multi-purpose register to hold test lead data;
A second logic circuit that generates a selection signal based on the test read data and a second control signal,
The multiplexer connects one of the first and second input nodes to the output node based on the selection signal.   The first logic circuit inverts the logic level of the read data supplied through the first data bus in response to a third control signal being at an inactive level. The semiconductor device according to claim 11.   The test read data is fixed to a predetermined logic level in response to the third control signal being at an inactive level, whereby when the third control signal is at an inactive level, 13. The semiconductor device according to claim 12, wherein an inverted signal or a non-inverted signal of the read data is supplied to the second data bus based on the second control signal.   The first logic circuit fixes the first and second input nodes to the first and second logic levels, respectively, in response to a third control signal being at an active level. The semiconductor device according to any one of claims 11 to 13.   The second control signal is fixed at a predetermined logic level in response to the third control signal being at an active level, whereby when the third control signal is at an active level, The semiconductor device according to claim 14, wherein the test read data is supplied to the second data bus.

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