JP2014220729A - Encryption processing device, semiconductor memory, and memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique with which the content of encryption processing in an encryption processing device becomes hard to identify.SOLUTION: An encryption processing device 1 includes an encryption processing unit group 20 and a use state control unit 5. The encryption processing unit group 20 is constituted of a plurality of encryption processing units 2 each having an encryption function. The use state control unit 5 controls the use state of the plurality of encryption processing units 2 in the encryption processing device 1. The use state control unit 5 changes the use state of the plurality of encryption processing units 2.

Description

  The present invention relates to cryptographic processing technology.

  Conventionally, various techniques have been proposed for cryptographic processing. For example, Patent Document 1 discloses a technique for performing encryption processing in a semiconductor memory.

JP-A-7-219852

  In the cryptographic processing device, it is desirable that the contents of cryptographic processing performed by the cryptographic processing device are not easily specified.

  Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide a technique that makes it difficult to specify the content of cryptographic processing in a cryptographic processing device.

  In order to solve the above problems, an aspect of a cryptographic processing device according to the present invention includes a cryptographic processing unit group including a plurality of cryptographic processing units each having a cryptographic function, and the plurality of cryptographic processing units in the cryptographic processing device. A control unit that controls a usage mode of the plurality of cryptographic processing units. The control unit changes a usage mode of the plurality of cryptographic processing units.

  In the aspect of the cryptographic processing apparatus according to the present invention, the cryptographic processing unit group includes at least two cryptographic processing units that use different cryptographic algorithms.

  In one aspect of the cryptographic processing apparatus according to the present invention, the cryptographic processing unit group includes at least two cryptographic processing units that use the same cryptographic algorithm.

  In the aspect of the cryptographic processing apparatus according to the present invention, the cryptographic processing unit group includes at least two cryptographic processing units having different keys.

  In the aspect of the cryptographic processing apparatus according to the present invention, the cryptographic processing unit group includes at least two cryptographic processing units having the same key to be used.

  In one aspect of the cryptographic processing apparatus according to the present invention, the control unit determines a usage mode of the plurality of cryptographic processing units from a plurality of types of usage modes, and the plurality of types of usage modes are the plurality of encryption modes. A mode in which at least two of the processing units are used in combination is included.

  In the aspect of the cryptographic processing apparatus according to the present invention, the plurality of types of usage modes include a mode in which only one of the plurality of cryptographic processing units is used.

  In the aspect of the cryptographic processing apparatus according to the present invention, the cryptographic processing unit group includes first and second cryptographic processing units, and the plurality of types of usage modes are output from the first cryptographic processing unit. A first mode in which data is input to the second cryptographic processing unit as a session key, and a second mode in which data output from the second cryptographic processing unit is input to the first cryptographic processing unit as a session key. Including.

  In the aspect of the cryptographic processing apparatus according to the present invention, the cryptographic processing unit group includes first and second cryptographic processing units, and the plurality of types of usage modes are output from the first cryptographic processing unit. Both the data and the data output from the second encryption processing unit include an aspect in which the data is used as data for encrypting the data.

  One aspect of the semiconductor memory according to the present invention includes the above-described cryptographic processing device and a storage unit, and data read from the storage unit is encrypted by the cryptographic processing device.

  An aspect of the memory system according to the present invention includes the semiconductor memory described above and a host device that controls the semiconductor memory.

  In one aspect of the memory system according to the present invention, the control unit of the cryptographic processing device changes a usage mode of the plurality of cryptographic processing units when a power source of the memory system is turned on.

  In one aspect of the memory system according to the present invention, the control unit periodically changes the usage mode of the plurality of cryptographic processing units.

  Further, in one aspect of the memory system according to the present invention, the storage unit stores in advance control data for controlling usage modes of the plurality of cryptographic processing units, and the control unit stores the control unit. A usage mode of the plurality of cryptographic processing units is controlled based on the control data.

  According to the present invention, it is difficult to specify the content of cryptographic processing in the cryptographic processing device.

It is a figure which shows the structure of a cryptographic processing apparatus. It is a figure which shows the 1st usage condition of a some encryption processing part. It is a figure which shows the 2nd usage condition of a some encryption processing part. It is a figure which shows the 3rd usage condition of a some encryption processing part. It is a figure which shows the 4th usage condition of a some encryption processing part. It is a figure which shows the 5th usage condition of a some encryption processing part. It is a figure which shows the 5th usage condition of a some encryption processing part. It is a figure which shows the structure of a memory system. It is a flowchart which shows operation | movement of a memory system.

  FIG. 1 is a diagram showing a configuration of a cryptographic processing apparatus 1 according to an embodiment. The cryptographic processing apparatus 1 according to the present embodiment encrypts and decrypts data using, for example, a stream encryption method that is a kind of common key encryption method. Note that the cryptographic processing apparatus 1 may encrypt and decrypt data using a block encryption method which is a kind of a common key encryption method. The cryptographic processing device 1 may encrypt and decrypt data using a public key cryptosystem. In the present embodiment, data refers to digital data composed of at least one bit for convenience of explanation. For convenience of explanation, it is assumed that the data value is a value in decimal notation.

  As shown in FIG. 1, the cryptographic processing apparatus 1 includes a cryptographic processing unit group 20 including a plurality of cryptographic processing units 2. Each cryptographic processing unit 2 has a cryptographic function. A fixed master key 9 is input to each encryption processing unit 2. In the plurality of cryptographic processing units 2, the cryptographic algorithms used may be the same or different from each other. As an encryption algorithm used in the encryption processing unit 2, for example, DES (Data Encryption Standard) or AES (Advanced Encryption Standard) can be considered. In the plurality of cryptographic processing units 2, the master keys 9 used may be the same as each other or different from each other.

  In the present embodiment, the cryptographic processing device 1 includes, for example, two cryptographic processing units 2. Hereinafter, one and the other of the two cryptographic processing units 2 may be referred to as “first cryptographic processing unit 2a” and “second cryptographic processing unit 2b”, respectively. Also, the master key 9 input to the first encryption processing unit 2a and the master key 9 input to the second encryption processing unit 2b are referred to as “first master key 9a” and “second master key 9b”, respectively. There is.

  In addition to the cryptographic processing unit group 20, the cryptographic processing device 1 is provided with a first arithmetic circuit 3, a second arithmetic circuit 4, and a usage mode control unit 5. Each of the first arithmetic circuit 3 and the second arithmetic circuit 4 calculates and outputs an exclusive OR (XOR) of two input data.

  The usage mode control unit 5 controls usage modes of the plurality of cryptographic processing units 2 based on a control signal 10 input from the outside of the cryptographic processing device 1. That is, the usage mode of the plurality of cryptographic processing units 2 is determined based on the control signal 10. In the present embodiment, the control signal 10 includes first control data 11, second control data 12, and third control data 13. The usage mode control unit 5 determines usage modes of the plurality of cryptographic processing units 2 from a plurality of types of usage modes. In the present embodiment, for example, first to fifth usage modes are defined. The first to fifth usage modes include a mode in which only one of the plurality of cryptographic processing units 2 is used and a mode in which two of the plurality of cryptographic processing units 2 are used in combination. These usage modes will be described later in detail.

  The usage mode control unit 5 includes a first selection circuit 6, a second selection circuit 7, and a third selection circuit 8. The first selection circuit 6 selects one of the two input data based on the first control data 11, and outputs the selected data to the first encryption processing unit 2a. The first selection circuit 6 receives data output from the second encryption processing unit 2b and data in which all bits are zero (hereinafter referred to as “zero data”). When the first control data 11 composed of 1 bit indicates “1”, the first selection circuit 6 selects and outputs the data output from the second encryption processing unit 2b. On the other hand, the first selection circuit 6 selects and outputs zero data when the first control data 11 indicates “0”. When zero data is input from the first selection circuit 6, the first encryption processing unit 2a ignores the input of the zero data.

  The second selection circuit 7 selects one of the two input data based on the second control data 12, and outputs it to the second encryption processing unit 2b. The second selection circuit 7 receives data output from the first encryption processing unit 2a and zero data. When the second control data 12 composed of 1 bit indicates “1”, the second selection circuit 7 selects and outputs data output from the first encryption processing unit 2a. On the other hand, the second selection circuit 7 selects and outputs zero data when the second control data 12 indicates “0”. When zero data is input from the second selection circuit 7, the second encryption processing unit 2b ignores the input of the zero data.

  The third selection circuit 8 selects one of the three input data based on the third control data 13 and outputs it to the second arithmetic circuit 4. The third selection circuit 8 receives data output from the first encryption processing unit 2a, data output from the second encryption processing unit 2b, and data output from the first arithmetic circuit 3. When the third control data 13 composed of 2 bits indicates “0”, the third selection circuit 8 selects and outputs the data output from the first encryption processing unit 2a. The third selection circuit 8 selects and outputs the data output from the first arithmetic circuit 3 when the third control data 13 indicates “1”. Then, when the third control data 13 indicates “2”, the third selection circuit 8 selects and outputs the data output from the second encryption processing unit 2b.

  The first arithmetic circuit 3 calculates an exclusive OR of the data output from the first encryption processing unit 2 a and the second encryption processing unit 2 b and outputs the result to the third selection circuit 8. The second arithmetic circuit 4 calculates and outputs an exclusive OR of the data output from the third selection circuit 8 and the data to be encrypted (encryption target data). Thereby, the data to be encrypted is encrypted. The second arithmetic circuit 4 calculates and outputs an exclusive OR of the data output from the third selection circuit 8 and the encrypted data (encrypted data). As a result, the encrypted data is decrypted. In this way, the second arithmetic circuit 4 uses the data output from the third selection circuit 8 as a key stream (data for encrypting data), and encrypts or decrypts the input data. .

<About usage of multiple cryptographic processing units>
Next, an example of a plurality of types of usage modes related to the plurality of cryptographic processing units 2 will be described. Hereinafter, assuming that the value of the first control data 11 is a, the value of the second control data 12 is b, and the value of the third control data 13 is c, the first control data 11, the second control data 12, and the third control data. The value of 13 is represented by (a, b, c).

<About the first usage mode>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 1, 2), the usage mode of the plurality of cryptographic processing units 2 is the first usage mode. . FIG. 2 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the first usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the first usage mode, as shown in FIG. 2, the output data of the first cryptographic processing unit 2a is input to the second cryptographic processing unit 2b. Then, the output data of the second encryption processing unit 2 b is input to the second arithmetic circuit 4. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the first usage mode may be referred to as a “first configuration”.

  In the cryptographic processing apparatus 1 having the first configuration as shown in FIG. 2, the first cryptographic processing unit 2a initializes itself (initializes its own cryptographic algorithm) based on the first master key 9a. Then, the first encryption processing unit 2a after initialization generates and outputs a session key SK using its own encryption function. In other words, the first cryptographic processing unit 2a after initialization performs cryptographic processing to generate and output a session key SK. The second cryptographic processor 2b initializes itself (initializes its own cryptographic algorithm) based on the input key composed of the session key SK and the second master key 9b from the first cryptographic processor 2a. . The initialized second cryptographic processing unit 2b generates and outputs a key stream KS using its own cryptographic function. In other words, the second cryptographic processing unit 2b after initialization performs cryptographic processing to generate and output a key stream KS. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the second encryption processing unit 2b and the encryption target data. Thereby, in the second arithmetic circuit 4, the input data to be encrypted is encrypted and output. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the second encryption processing unit 2b and the encrypted data. Thereby, in the second arithmetic circuit 4, the input encrypted data is decrypted and output.

<About the second usage mode>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (1, 0, 0), the usage mode of the plurality of cryptographic processing units 2 is the second usage mode. . FIG. 3 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the second usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the second usage mode, as shown in FIG. 3, the output data of the second cryptographic processing unit 2b is input to the first cryptographic processing unit 2a. Then, the output data of the first encryption processing unit 2 a is input to the second arithmetic circuit 4. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the second usage mode may be referred to as a “second configuration”.

  In the cryptographic processing apparatus 1 having the second configuration as shown in FIG. 3, the second cryptographic processing unit 2b initializes itself based on the second master key 9b. Then, the second encryption processing unit 2b after initialization generates and outputs a session key SK using its own encryption function. The first cryptographic processor 2a initializes itself based on the input key composed of the session key SK from the second cryptographic processor 2b and the first master key 9a. The first cryptographic processing unit 2a after initialization generates and outputs a key stream KS using its own cryptographic function. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the first encryption processing unit 2a and the data to be encrypted. Thereby, in the second arithmetic circuit 4, the input data to be encrypted is encrypted and output. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the first encryption processing unit 2a and the encrypted data. Thereby, in the second arithmetic circuit 4, the input encrypted data is decrypted and output.

  In the first cryptographic processing unit 2a and the second cryptographic processing unit 2b, when the cryptographic algorithms used are the same and the master keys 9 used are the same, the first configuration The cryptographic processing apparatus 1 and the cryptographic processing apparatus 1 having the second configuration perform the same operations.

<About the third usage mode>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 0, 2) or (1, 0, 2), the usage mode of the plurality of cryptographic processing units 2 Is the third mode of use. FIG. 4 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the third usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the third usage mode, the output data of the second cryptographic processing unit 2b is input to the second arithmetic circuit 4 as shown in FIG. At this time, the first encryption processing unit 2a is not used. That is, when the usage mode of the plurality of cryptographic processing units 2 is the third usage mode, only the second cryptographic processing unit 2b among the multiple cryptographic processing units 2 is used. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the third usage mode may be referred to as a “third configuration”.

  In the cryptographic processing apparatus 1 having the third configuration as shown in FIG. 4, the second cryptographic processing unit 2b initializes itself based on the second master key 9b. Then, the second encryption processing unit 2b after initialization generates and outputs a key stream KS using its own encryption function. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the second encryption processing unit 2b and the encryption target data. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the second encryption processing unit 2b and the encrypted data.

<About the fourth usage mode>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 0, 0) or (0, 1, 0), the usage mode of the plurality of cryptographic processing units 2 Is a fourth mode of use. FIG. 5 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode, the output data of the first cryptographic processing unit 2a is input to the second arithmetic circuit 4 as shown in FIG. At this time, the second encryption processing unit 2b is not used. That is, when the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode, only the first cryptographic processing unit 2a among the multiple cryptographic processing units 2 is used. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode may be referred to as a “fourth configuration”.

  In the cryptographic processing apparatus 1 having the fourth configuration as shown in FIG. 5, the first cryptographic processing unit 2a initializes itself based on the first master key 9a. Then, the first cryptographic processing unit 2a after initialization generates and outputs a key stream KS using its own cryptographic function. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the first encryption processing unit 2a and the data to be encrypted. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the first encryption processing unit 2a and the encrypted data.

  In the first cryptographic processing unit 2a and the second cryptographic processing unit 2b, when the cryptographic algorithms used are the same and the master keys 9 used are the same, the third configuration The cryptographic processing apparatus 1 and the cryptographic processing apparatus 1 having the fourth configuration perform the same operation.

<About the fifth usage mode>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 0, 1), the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode. . FIG. 6 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode, as shown in FIG. 6, the output data of the first cryptographic processing unit 2a and the output data of the second cryptographic processing unit 2b are the first 1 is input to the arithmetic circuit 3. Then, the output data of the first arithmetic circuit 3 is input to the second arithmetic circuit 4. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode may be referred to as a “fifth configuration”.

  In the cryptographic processing apparatus 1 having the fifth configuration as shown in FIG. 6, the first cryptographic processing unit 2a initializes itself based on the first master key 9a. Then, the first encryption processing unit 2a after initialization generates and outputs the first key stream KS1 using its own encryption function. Also, the second encryption processing unit 2b initializes itself based on the second master key 9b. Then, the initialized second encryption processing unit 2b generates and outputs the second key stream KS2 using its own encryption function. The first arithmetic circuit 3 calculates an exclusive OR of the first key stream KS1 from the first encryption processing unit 2a and the second key stream KS2 from the second encryption processing unit 2b, and outputs the operation result to the first Output as 3 key stream KS3. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the third key stream KS3 output from the first arithmetic circuit 3 and the encryption target data. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the third key stream KS3 and the encrypted data.

  Here, when calculating the exclusive logical sum of the operation result of the exclusive OR of the first key stream KS1 and the second key stream KS2 and the encryption target data (or encryption data), the first key stream KS1 In the case where the exclusive OR of the three data of the second key stream KS2 and the encryption target data (or encryption data) is calculated, the obtained calculation results are the same. Therefore, when the first arithmetic circuit 3 and the second arithmetic circuit 4 are combined into one arithmetic circuit 34, the configuration shown in FIG. 6 is equivalent to the configuration using the arithmetic circuit 34 shown in FIG. In the configuration shown in FIG. 7, the arithmetic circuit 34 encrypts the encryption target data by calculating an exclusive logical sum of the first key stream KS1, the second key stream KS2, and the encryption target data. To do. Further, the arithmetic circuit 34 decrypts the encrypted data by calculating an exclusive logical sum of the first key stream KS1, the second key stream KS2, and the encrypted data.

  In the present embodiment, the usage mode control unit 5 includes a plurality of cryptographic processing units in the cryptographic processing device 1 in response to the control signal 10 (first control data 11, second control data 12, and third control data 13). The second usage mode is changed between the first to fifth usage modes. For example, when the values of the first control data 11, the second control data 12, and the third control data change from (0, 1, 2) to (1, 0, 0), the usage mode control unit 5 The usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 is changed from the first usage mode to the second usage mode. In addition, when the values of the first control data 11, the second control data 12, and the third control data change from (0, 1, 2) to (0, 0, 1), the usage mode control unit 5 The usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 is changed from the first usage mode to the fifth usage mode. Further, the usage mode control unit 5 changes the values of the first control data 11, the second control data 12 and the third control data from (1, 0, 0) to (0, 0, 2) or (1,0, 2 ), The usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 is changed from the second usage mode to the third usage mode. When the control signal 10 dynamically changes, the usage mode control unit 5 dynamically changes the usage modes of the plurality of cryptographic processing units 2.

  As described above, since the usage mode control unit 5 according to the present embodiment changes the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1, the content of the cryptographic processing in the cryptographic processing device 1 is specified. It becomes difficult. In other words, in the present embodiment, since the configuration of the cryptographic processing device 1 changes, it is difficult to specify the content of cryptographic processing in the cryptographic processing device 1. Therefore, by using the cryptographic processing device 1 according to the present embodiment to realize security for a device such as a semiconductor memory, the security strength of the device can be improved.

<Example of security implementation using a cryptographic processing device>
Next, an implementation example of security using the cryptographic processing apparatus 1 according to the present embodiment will be described. Here, as an example, a case where the security of the semiconductor memory is realized using the cryptographic processing device 1 will be described.

  FIG. 8 is a diagram showing a configuration of a memory system 100 having a semiconductor memory 200 in which security is realized by using the cryptographic processing device 1. The memory system 100 includes a semiconductor memory 200 having the cryptographic processing device 1 and a host device 300 that controls the semiconductor memory 200. The memory system 100 is a computer system mounted on a game device, for example. The game device includes a game device body and a game cartridge that can be attached to and detached from the game device body. The semiconductor memory 200 is built in the game cartridge, and the host device 300 is built in the game device body. The host device 300 is a kind of computer. The user can enjoy various types of games by exchanging the game card ridge attached to the game apparatus main body.

  The semiconductor memory 200 is, for example, a mask ROM (Read Only Memory). In addition to the cryptographic processing apparatus 1, the semiconductor memory 200 includes a host IF (interface) 210, a command decoder 220, a memory IF (interface) 230, a memory array 240 as a storage unit, and a control register 250. Yes.

  The cryptographic processing device 1 receives a command from the host device 300 through the host IF 210. The host device 300 is provided with a cryptographic processing device similar to the cryptographic processing device 1. The host device 300 encrypts the command using its own cryptographic processing device, and outputs the encrypted command to the semiconductor memory 200. The cryptographic processing device 1 decrypts the encrypted command from the host device 300 by the second arithmetic circuit 4 as described above, and outputs the decrypted command to the command decoder 220. Hereinafter, the cryptographic processing apparatus included in the host apparatus 300 may be referred to as a “host-side cryptographic processing apparatus”.

  The command decoder 220 decodes the input command and analyzes the command. When the command decoder 220 analyzes the input command and the command is a read command for instructing to read data from the memory array 240, the command decoder 220 stores control signals such as an address signal and a read signal through the memory IF 230. Output to array 240. As a result, data is output from the memory array 240. Data output from the memory array 240 is input to the cryptographic processing device 1. In the memory array 240, for example, a plurality of game programs and various data used in each game program are stored. The command decoder 220 extracts control data included in the input command and writes the extracted control data to the control register 250.

  The control register 250 includes a first register 251, a second register 252, a third register 253, and an initialization register 254. The first register 251 stores first control data 11 for controlling the first selection circuit 6 of the cryptographic processing device 1. The second register 252 stores second control data 12 for controlling the second selection circuit 7 of the cryptographic processing device 1. The third register 253 stores third control data 13 for controlling the third selection circuit 8 of the cryptographic processing device 1. The initialization register 254 stores an initialization flag 14 that is control data instructing initialization of the cryptographic processing device 1. The first control data 11, the second control data 12, the third control data 13 and the initialization flag 14 are output from the host device 300.

  The cryptographic processing device 1 encrypts the data output from the memory array 240 by the second arithmetic circuit 4 as described above. Data encrypted by the cryptographic processing device 1 is input to the host device 300 through the host IF 210. The host device 300 decrypts the encrypted data from the semiconductor memory 200 using the host-side cryptographic processing device. When a game program in the memory array 240 is input from the semiconductor memory 200, the host device 300 executes the game program.

  In the memory system 100 according to the present embodiment, the host device 300 determines the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200, and the control signal 10 ( The first control data 11, the second control data 12, and the third control data 13) are output to the semiconductor memory 200. In the cryptographic processing device 1, the usage mode control unit 5 sets usage modes of the plurality of cryptographic processing units 2 based on the control signal 10 from the host device 300. Here, since the content of the cryptographic processing in the cryptographic processing device 1 is determined by the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1, the security configuration in the semiconductor memory 200 is determined depending on the usage mode. It can be said that it will be decided. That is, the semiconductor memory 200 according to the present embodiment changes the security configuration by changing the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1. Hereinafter, the control signal 10 for determining the usage mode of the plurality of cryptographic processing units 2, that is, the control signal 10 for determining the security configuration in the semiconductor memory 200 may be referred to as “security configuration flag 10”.

  Next, the operation of the memory system 100 when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 changes will be described. FIG. 9 is a flowchart showing the operation. In the following description, for example, the operation of the memory system 100 when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 changes from the first usage mode to the second usage mode will be described.

  As shown in FIG. 9, in step s1, the host device 300 issues a security reconfiguration command. At this time, the host device 300 encrypts and outputs the security reconfiguration command by the host-side cryptographic processing device. The security reconfiguration command output from the host device 300 is input to the cryptographic processing device 1 through the host IF 210.

  The security reconfiguration command is a command for changing the security configuration in the semiconductor memory 200, that is, a command for changing the usage mode of the plurality of cryptographic processing units 2. The security reconfiguration command includes a security configuration flag 10 and an initialization flag 14. In this example, since the usage mode of the plurality of cryptographic processing units 2 changes from the first usage mode to the second usage mode, the security reconfiguration command includes a security configuration flag corresponding to the second usage mode. 10 is included. That is, the values of the first control data 11, the second control data 12, and the third control data 13 constituting the security configuration flag 10 included in the security reconfiguration flag correspond to the second usage mode (1, 0, 0).

  Next, in step s2, the cryptographic processing apparatus 1 decrypts the input encrypted security reconfiguration command. Here, since the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 is the first usage mode (see FIG. 2), in the cryptographic processing device 1, the second arithmetic circuit 4 includes the second cryptographic circuit. By calculating the exclusive logical sum of the key stream KS output from the processing unit 2b and the security reconfiguration command, the security reconfiguration command is decrypted. The decrypted security reconfiguration command is input to the command decoder 220.

  Next, in step s3, the command decoder 220 decodes the input security reconfiguration command, and extracts the security configuration flag 10 and the initialization flag 14 from the security reconfiguration command. In step s 4, the command decoder 220 transfers the extracted security configuration flag 10 to the control register 250. The control register 250 transfers the first control data 11, the second control data 12, and the third control data 13 constituting the transferred security configuration flag 10 to the first register 251, the second register 252, and the third register 253. Remember each one. The first control data 11, the second control data 12, and the third control data 13 stored in the first register 251, the second register 252, and the third register 253 are input to the cryptographic processing device 1.

  Next, in step s5, in the cryptographic processing apparatus 1, the usage mode control unit 5 changes the usage mode of the plurality of cryptographic processing units 2 in accordance with the security configuration flag 10 (control signal 10) output from the control register 250. Let Here, since the values of the first control data 11, the second control data 12, and the third control data 13 are (1, 0, 0), the usage mode control unit 5 includes a plurality of encryption processing units 2. The usage mode is changed to the second usage mode. As a result, the configuration of the cryptographic processing device 1 changes from the configuration shown in FIG. 2 to the configuration shown in FIG.

  Next, in step s 6, the command decoder 220 transfers the extracted initialization flag 14 to the control register 250. The control register 250 stores the transferred initialization flag 14 in the initialization register 254. The initialization flag 14 stored in the initialization register 254 is input to the cryptographic processing device 1.

  Next, in step s7, in the cryptographic processing apparatus 1 that has received the initialization flag 14, each cryptographic processing unit 2 is initialized. Here, since the usage mode of the plurality of cryptographic processing units 2 is the second usage mode, the second cryptographic processing unit 2b is initialized based on the second master key 9b. The first cryptographic processing unit 2a is initialized based on the input key composed of the session key SK and the first master key 9a output from the second cryptographic processing unit 2b after initialization. Thereafter, in the cryptographic processing device 1, the command from the host device 300 is decrypted with the key stream KS output from the first cryptographic processing unit 2a. Further, the data from the memory array 240 is encrypted with the key stream KS output from the first encryption processing unit 2a.

  When the host device 300 changes the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200 by issuing a security reconfiguration command, the host device 300 uses a plurality of The usage mode of the cryptographic processing unit is changed in the same manner. For example, when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 changes from the third usage mode to the fifth usage mode, the use of the multiple cryptographic processing units in the host-side cryptographic processing device The aspect also changes from the third usage mode to the fifth usage mode. Thereby, even if the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200 changes, the host device 300 can appropriately decrypt the data from the semiconductor memory 200. Further, the semiconductor memory 200 can appropriately decode the command from the host device 300.

  As the memory system 100 operates as described above, the security configuration in the semiconductor memory 200 changes. Therefore, the security strength of the semiconductor memory 200 is improved. Therefore, it becomes difficult to specify the contents of data such as a game program in the memory array 240. Therefore, illegal duplication of the game cartridge can be suppressed.

  In the present embodiment, for example, the host device 300 issues a security reconfiguration command each time the memory system 100 is powered on. Thereby, every time the power supply of the memory system 100 is turned on, the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200 changes. In this case, in the cryptographic processing apparatus 1, the usage mode control unit 5 changes the usage mode of the plurality of cryptographic processing units 2 when the memory system 100 is powered on.

  Further, the host device 300 may issue a security reconfiguration command periodically. Thereby, the usage mode of the some encryption processing part 2 in the encryption processing apparatus 1 changes regularly. In this case, in the cryptographic processing apparatus 1, the usage mode control unit 5 periodically changes the usage modes of the plurality of cryptographic processing units 2.

  The usage modes of the plurality of cryptographic processing units 2 may change in any order between the first to fifth usage modes. For example, the usage modes of the plurality of cryptographic processing units 2 may change in the order of the first usage mode, the second usage mode, the third usage mode, the fourth usage mode, and the fifth usage mode. . The usage modes of the plurality of cryptographic processing units 2 may change in the order of the first usage mode, the third usage mode, the fifth usage mode, the second usage mode, and the fourth usage mode. .

  In the above example, the security configuration flag 10 (control signal 10) for controlling the usage mode of the plurality of cryptographic processing units 2 is included in the security reconfiguration command, but is stored in the memory array 240 in advance. Also good. In this case, a plurality of security configuration flags 10 respectively corresponding to the first to fifth usage modes are stored in the memory array 240 in advance. In the semiconductor memory 200, when a security reconfiguration command is received from the host device 300, one of the plurality of security configuration flags 10 is read from the memory array 240 and stored in the control register 250. When the security configuration flag 10 written to the control register 250 from the memory array 240 is changed, the usage mode of the plurality of cryptographic processing units 2 is changed.

  The semiconductor memory 200 notifies the host apparatus 300 of the security configuration flag 10 written to the control register 250 from the memory array 240, that is, the security configuration flag 10 used for controlling the usage mode of the plurality of cryptographic processing units 2. The host device 300 sets the usage mode of the plurality of cryptographic processing units in the host-side cryptographic processing device to the usage mode corresponding to the notified security configuration flag 10. Thereby, even if the semiconductor memory 200 changes the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 itself, the usage mode of the plurality of cryptographic processing units 2 in the semiconductor memory 200, The usage mode of the plurality of cryptographic processing units in the host device 300 matches. Therefore, the host device 300 can appropriately decrypt the data from the semiconductor memory 200. Further, the semiconductor memory 200 can appropriately decode the command from the host device 300.

  In the above example, the first to fifth usage modes are defined as usage modes of the plurality of cryptographic processing units 2 in the cryptographic processing device 1, but at least of the first to fifth usage modes. Only two usage modes may be defined. Moreover, usage modes other than the first to fifth usage modes may be defined.

  In the above example, the cryptographic processing unit group 20 of the cryptographic processing device 1 is configured by the two cryptographic processing units 2, but may be configured by three or more cryptographic processing units 2.

  When the cryptographic processing unit group 20 is composed of first to third cryptographic processing units, various usage modes can be considered as usage modes of the first to third cryptographic processing units 2.

  For example, the output data of the first cryptographic processing unit 2 is input to the second cryptographic processing unit 2 as the first session key, and the output data of the second cryptographic processing unit 2 is output to the third cryptographic processing unit 2 as the second session key. Thus, a mode in which the output data of the third encryption processing unit 2 is used as a key stream is conceivable.

  Also, the output data of the third cryptographic processing unit 2 is input to the second cryptographic processing unit 2 as the first session key, and the output data of the second cryptographic processing unit 2 is output to the first cryptographic processing unit 2 as the second session key. Thus, a mode in which the output data of the first encryption processing unit 2 is used as a key stream is conceivable.

  In addition, the output data of the first cryptographic processing unit 2 and the output data of the second cryptographic processing unit 2 are input to the third cryptographic processing unit 2 as session keys, and the output data of the third cryptographic processing unit 2 is used as a key stream. A possible embodiment is conceivable.

  Also, the output data of the second cryptographic processing unit 2 and the output data of the third cryptographic processing unit 2 are input to the first cryptographic processing unit 2 as session keys, and the output data of the first cryptographic processing unit 2 is used as a key stream. A possible embodiment is conceivable.

  Further, a mode in which the output data of the first cryptographic processing unit 2, the output data of the second cryptographic processing unit 2, and the output data of the third cryptographic processing unit 2 are used as a key stream is conceivable.

  The cryptographic processing unit group 20 may include at least two cryptographic processing units 2 that use different cryptographic algorithms, or include at least two cryptographic processing units 2 that use the same cryptographic algorithm. May be.

  For example, when the cryptographic processing unit group 20 is composed of the first to third cryptographic processing units 2, the cryptographic algorithms used in the first and second cryptographic processing units 2 are the same as each other, The cryptographic algorithm used in the second cryptographic processing unit 2 and the cryptographic algorithm used in the third cryptographic processing unit 2 are made different from each other.

  Further, when the cryptographic processing unit group 20 includes the first to fourth cryptographic processing units 2, for example, the cryptographic algorithms used in the first to third cryptographic processing units 2 are different from each other, The cryptographic algorithms used in the third and fourth cryptographic processing units 2 are the same.

  In addition, when the cryptographic processing unit group 20 includes the first to fourth cryptographic processing units 2, for example, the cryptographic algorithms used in the first and second cryptographic processing units 2 are the same, and the third The encryption algorithms used in the fourth encryption processing unit 2 are the same. For example, the cryptographic algorithms used in the first and second cryptographic processing units 2 and the cryptographic algorithms used in the third and fourth cryptographic processing units 2 are made different from each other.

  When the cryptographic processing unit group 20 includes at least two cryptographic processing units 2 that use different cryptographic algorithms, by changing the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1, The content of the cryptographic processing in the cryptographic processing device 1 is further difficult to be specified. Therefore, the security strength can be further improved by using the cryptographic processing apparatus 1 for security of the semiconductor memory 200 or the like.

  Further, the cryptographic processing unit group 20 may include at least two cryptographic processing units 2 having different master keys 9 to be used, and includes at least two cryptographic processing units 2 having the same master key 9 to be used. It may be included.

  For example, when the cryptographic processing unit group 20 includes the first to third cryptographic processing units 2, the master keys 9 used in the first and second cryptographic processing units 2 are the same as each other, The master key 9 used in the second cryptographic processing unit 2 and the master key 9 used in the third cryptographic processing unit 2 are made different from each other.

  Further, when the cryptographic processing unit group 20 includes the first to fourth cryptographic processing units 2, for example, the master keys 9 used in the first to third cryptographic processing units 2 are different from each other, The master keys 9 used in the first and fourth cryptographic processing units 2 are the same.

  Further, when the cryptographic processing unit group 20 includes the first to fourth cryptographic processing units 2, for example, the master keys 9 used in the first and second cryptographic processing units 2 are the same as each other, The master keys 9 used in the third and fourth cryptographic processing units 2 are the same. Then, the master key 9 used in the first and second cryptographic processing units 2 is different from the master key 9 used in the third and fourth cryptographic processing units 2.

  When the cryptographic processing unit group 20 includes at least two cryptographic processing units 2 having different keys, the encryption processing unit 1 changes the usage mode of the plurality of cryptographic processing units 2 to change the encryption mode. The content of the cryptographic process in the processing device 1 is further difficult to be specified. Therefore, the security strength can be further improved by using the cryptographic processing apparatus 1 for security of the semiconductor memory 200 or the like.

  In the above example, the encryption processing unit 2 generates and outputs a key such as a session key and a key stream. However, the input data may be encrypted so that the encrypted data can be output. good. In this case, for example, when the usage mode of the plurality of cryptographic processing units 2 is the first usage mode as shown in FIG. 2, the second cryptographic processing unit 2b is connected to the first cryptographic processing unit 2a. Using the output session key SK, the input data (plain text) is encrypted, and the encrypted data is output. For example, when the usage mode of the plurality of cryptographic processing units 2 is the second usage mode as illustrated in FIG. 3, the first cryptographic processing unit 2a is output from the second cryptographic processing unit 2b. Using the session key SK, the input data (plain text) is encrypted, and the encrypted data is output.

  As described above, the cryptographic processing device 1, the semiconductor memory 200, and the memory system 100 have been described in detail. However, the above description is illustrative in all aspects, and the present invention is not limited thereto. The various modifications described above can be applied in combination as long as they do not contradict each other. And it is understood that the countless modification which is not illustrated can be assumed without deviating from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Cryptographic processing apparatus 2 Cryptographic processing part 5 Usage mode control part 9 Master key 100 Memory system 200 Semiconductor memory 240 Memory array 300 Host apparatus

Claims (14)

A cryptographic processing device,
A cryptographic processing unit group consisting of a plurality of cryptographic processing units each having a cryptographic function;
A control unit that controls a usage mode of the plurality of cryptographic processing units in the cryptographic processing device,
The control unit is a cryptographic processing device that changes a usage mode of the plurality of cryptographic processing units. The cryptographic processing device according to claim 1,
The cryptographic processing unit group includes at least two cryptographic processing units that use different cryptographic algorithms. A cryptographic processing device according to any one of claims 1 and 2,
The cryptographic processing unit group includes at least two cryptographic processing units that use the same cryptographic algorithm. A cryptographic processing device according to any one of claims 1 to 3,
The cryptographic processing unit group includes a cryptographic processing device including at least two cryptographic processing units that use different keys. The cryptographic processing device according to any one of claims 1 to 4,
The cryptographic processing unit group includes a cryptographic processing device including at least two cryptographic processing units that use the same key. A cryptographic processing device according to any one of claims 1 to 5,
The control unit determines a usage mode of the plurality of cryptographic processing units from a plurality of types of usage modes,
The plurality of types of usage modes include a mode in which at least two of the plurality of cryptographic processing units are used in combination. The cryptographic processing device according to claim 6,
The plurality of types of usage modes include a mode in which only one of the plurality of cryptographic processing units is used. The cryptographic processing apparatus according to any one of claims 6 and 7,
The cryptographic processing unit group includes first and second cryptographic processing units,
The multiple types of usage modes are:
A first mode in which data output from the first cryptographic processing unit is input to the second cryptographic processing unit as a session key;
And a second mode in which data output from the second cryptographic processor is input to the first cryptographic processor as a session key. The cryptographic processing apparatus according to any one of claims 6 and 7,
The cryptographic processing unit group includes first and second cryptographic processing units,
In the plurality of types of usage modes, both the data output from the first cryptographic processing unit and the data output from the second cryptographic processing unit are used as data for encrypting data. Including a cryptographic processing device. The cryptographic processing device according to any one of claims 1 to 9,
A storage unit,
A semiconductor memory in which data read from the storage unit is encrypted by the cryptographic processing device. A semiconductor memory according to claim 10;
A memory system comprising: a host device that controls the semiconductor memory. 12. The memory system according to claim 11, wherein
The control unit of the cryptographic processing device is configured to change a usage mode of the plurality of cryptographic processing units when a power source of the memory system is turned on. A memory system according to any one of claims 11 and 12,
The said control part is a memory system which changes the usage condition of these encryption processing parts regularly. A memory system according to any one of claims 11 to 13,
The storage unit stores in advance control data for controlling a usage mode of the plurality of cryptographic processing units,
The said control part is a memory system which controls the usage condition of these encryption processing parts based on the said control data which the said memory | storage part memorize | stores.

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