JP2014216402A - Semiconductor device, electro-optic device, semiconductor device manufacturing method, electro-optic device manufacturing device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving reliability, an electro-optic device, a semiconductor manufacturing method, an electro-optic device manufacturing method, and an electronic apparatus.SOLUTION: A gate electrode 30g is formed into a cylindrical shape having a first opening hole opened on a surface side of a first base material 10a, and a second opening hole opened on a side away from the first base material 10a, and is electrically connected to any of plural scanning lines 3c via a contact hole CNT1 of a first inter-layer insulation layer 11b arranged between the gate electrode 30g and the scanning line 3c. A semiconductor layer 30a is arranged in an opening hole of the gate electrode 30g via a gate insulation layer 11g, and a data line side source drain region 30s is arranged on the first opening hole side, and is electrically connected to a relay electrode 51. A pixel electrode side source drain region 30d is arranged on the second opening hole side.

Description

  The present invention relates to a semiconductor device, an electro-optical device, a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, an electronic apparatus, and the like.

  As one of the electro-optical devices, for example, an active drive type liquid crystal device including a transistor (semiconductor device) for each pixel as an element for switching control of a pixel electrode is known. Liquid crystal devices are used in, for example, direct-view displays and projector light valves.

  The transistor is generally provided such that the semiconductor layer is substantially parallel to the surface of the substrate. The area where the transistor is provided needs to be a light-shielding area, and if this area is large, the aperture ratio decreases. Therefore, for the purpose of further improving the aperture ratio, for example, in the method described in Patent Document 1, the semiconductor layer is arranged in a direction substantially perpendicular to the surface of the substrate, whereby the transistor region can be reduced in a plane. Thus, the light shielding area can be reduced.

Japanese Patent Laid-Open No. 7-321228

  However, in the method described in Patent Document 1, when high temperature polysilicon is applied to the semiconductor layer, it is necessary to keep the substrate at a high temperature until an electrode is formed on the upper layer of the substrate. When low resistance wiring (aluminum etc.) is used, there exists a subject that manufacture is difficult, such as disconnection.

  An aspect of the present invention has been made to solve at least a part of the above problems, and can be realized as the following forms or application examples.

  Application Example 1 A semiconductor device according to this application example includes one of a source region and a drain region, the other of the source region and the drain region, a channel region, a first electrode, a second electrode, and a gate electrode. And a gate insulating film disposed between the channel region and the gate electrode, the gate electrode having an opening, the channel region being disposed in the opening, and the first The electrode is electrically connected to one of the source region and the drain region through a first contact hole opened in a first insulating film covering the gate electrode, and the second electrode is connected to the first insulating film. It is electrically connected to the other of the source region and the drain region through the opened second contact hole.

  According to this application example, a (cylindrical) gate electrode extending in a direction away from the surface side of the substrate is disposed so as to cover the sidewall of the semiconductor layer, and one of the source region and the drain region is disposed on the surface side of the substrate. Since the transistor penetrating in the vertical direction is formed in which the other of the source region and the drain region is arranged on the side away from the surface, the transistor region can be reduced in a plan view, and the transistor can be reduced to an electro-optical device. When applied to, the aperture ratio can be improved. In addition, since the region of the transistor can be reduced, the light shielding property can be improved.

  Application Example 2 In the semiconductor device according to the application example described above, a first LDD region is disposed between the channel region and one of the source region and the drain region, and the channel region, the source region, and the A second LDD region is preferably disposed between the other drain region.

  According to this application example, since the first LDD region and the second LDD region are arranged, it is possible to suppress the leakage current from flowing through the channel region.

  Application Example 3 In the semiconductor device according to the application example described above, it is preferable that the first electrode is disposed inside the first contact hole and the second electrode is disposed inside the second contact hole.

  According to this application example, the first electrode and the second electrode are provided on the second insulating layer disposed on the upper layer of the gate electrode after the formation of the transistor that needs to be subjected to the high temperature treatment on the substrate is completed. It is not necessary to raise the temperature of the substrate after forming the film, and it is possible to suppress the occurrence of problems such as disconnection of the wiring.

  Application Example 4 An electro-optical device according to this application example includes the semiconductor device described above, a pixel electrode electrically connected to the semiconductor device, an element substrate including the semiconductor device and the pixel electrode, And a counter substrate disposed opposite to the element substrate, and an electro-optic layer sandwiched between the element substrate and the counter substrate.

  According to this application example, since the area of the semiconductor device in plan view is reduced, the light shielding area of the electro-optical device can be reduced, and the aperture ratio can be improved.

  Application Example 5 A method of manufacturing a semiconductor device according to this application example includes a step of forming one of a source region and a drain region, and a gate electrode formation for forming a gate electrode on one of the source region and the drain region. A step of forming an opening hole in the gate electrode in a region overlapping with a part of one of the source region and the drain region in plan view; and gate insulation so as to cover the opening hole and the gate electrode Forming a gate insulating layer, forming a semiconductor film in the opening hole and on the gate insulating layer, and implanting impurity ions into the semiconductor film to form a channel in the opening hole; Forming a region, further implanting impurity ions into the semiconductor film to form the other of the source region and the drain region, and the semiconductor Forming a first insulating film covering the film; forming a first contact hole in a region overlapping with one of the source region and the drain region of the first insulating film in plan view; Forming a second contact hole in a region overlapping with one of the source region and the drain region in plan view, and a first electrode electrically connected to one of the source region and the drain region And forming a second electrode that is electrically connected to the other of the source region and the drain region.

  According to this application example, the semiconductor layer is formed in the opening hole of the (cylinder) gate electrode penetrating in the surface direction of the substrate, and one of the source region and the drain region is formed on the surface side of the substrate. Since the transistor penetrating in the vertical direction, which forms the other of the source region and the drain region on the side away from the surface, is formed, the transistor region in plan view can be reduced, and the aperture ratio can be improved. . In addition, since the region of the transistor can be reduced, the light shielding property can be improved.

  Application Example 6 In the method of manufacturing a semiconductor device according to the application example described above, impurity ions having a concentration lower than that of the other of the source region and the drain region are implanted into the semiconductor film over the opening hole, thereby forming the other LDD region. Is preferably formed.

  According to this application example, since the first LDD region and the second LDD region are formed, it is possible to suppress leakage current from flowing in the channel region.

  Application Example 7 In the electro-optical device manufacturing method according to this application example, the semiconductor device and the pixel electrode are electrically connected through a contact hole, and an electro-optical layer is formed on the pixel electrode. And a step of performing.

  According to this application example, since the area of the semiconductor device in plan view is reduced, the light shielding area can be reduced, and the aperture ratio of the electro-optical device can be improved.

  Application Example 8 An electronic apparatus according to this application example includes the semiconductor device or the electro-optical device described above.

  According to this application example, since the above-described semiconductor device or electro-optical device is provided, an electronic apparatus with high display quality can be provided.

FIG. 2 is a schematic plan view illustrating a configuration of a liquid crystal device as an electro-optical device according to an embodiment. FIG. 2 is a schematic cross-sectional view taken along the line H-H ′ of the liquid crystal device illustrated in FIG. 1. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. FIG. 6 is a schematic cross-sectional view illustrating structures of a liquid crystal device and a semiconductor device. The schematic plan view which looked at the semiconductor device from the upper part among the liquid crystal devices shown in FIG. 5 is a flowchart showing a method for manufacturing a liquid crystal device in the order of steps. FIG. 5 is a schematic cross-sectional view mainly showing a method for manufacturing a semiconductor device among methods for manufacturing a liquid crystal device. FIG. 5 is a schematic cross-sectional view mainly showing a method for manufacturing a semiconductor device among methods for manufacturing a liquid crystal device. FIG. 5 is a schematic cross-sectional view mainly showing a method for manufacturing a semiconductor device among methods for manufacturing a liquid crystal device. The schematic plan view which follows the A-A 'line | wire of the semiconductor device shown in FIG.9 (h). Schematic which shows the structure of the projection type display apparatus provided with the liquid crystal device.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

  In this embodiment, an active matrix liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of the liquid crystal device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector).

<Configuration of liquid crystal device as electro-optical device>
FIG. 1 is a schematic plan view showing a configuration of a liquid crystal device as an electro-optical device. 2 is a schematic cross-sectional view taken along the line HH ′ of the liquid crystal device shown in FIG. FIG. 3 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device. Hereinafter, the configuration of the liquid crystal device will be described with reference to FIGS.

  As shown in FIGS. 1 and 2, the liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 which are disposed to face each other, and a liquid crystal layer 15 as an electro-optical layer sandwiched between the pair of substrates. Have. As the first base material 10a as the substrate constituting the element substrate 10 and the second base material 20a constituting the counter substrate 20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used.

  The element substrate 10 is larger than the counter substrate 20, and both the substrates are bonded via a sealing material 14 disposed along the outer periphery of the counter substrate 20. In the element substrate 10, liquid crystal having positive or negative dielectric anisotropy is sealed between the opposing substrates 20 inside the sealing material 14 provided in an annular shape in plan view, thereby forming a liquid crystal layer 15. For the sealing material 14, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. Spacers (not shown) are mixed in the sealing material 14 to keep the distance between the pair of substrates constant.

  A display area E in which a plurality of pixels P are arranged is provided inside the inner edge of the sealing material 14. The display area E may include dummy pixels arranged so as to surround the plurality of pixels P in addition to the plurality of pixels P contributing to display. Although not shown in FIGS. 1 and 2, a light shielding film (black matrix: BM) for planarly dividing the plurality of pixels P in the display area E is provided on the counter substrate 20.

  A data line driving circuit 22 is provided between the sealing material 14 along one side of the element substrate 10 and the one side. Further, an inspection circuit 25 is provided between the sealing material 14 and the display area E along the other one side facing the one side. Further, a scanning line driving circuit 24 is provided between the sealing material 14 and the display area E along the other two sides that are orthogonal to the one side and face each other. A plurality of wirings 29 connecting the two scanning line driving circuits 24 are provided between the sealing material 14 and the inspection circuit 25 along the other one side facing the one side.

  A light shielding film 18 (parting portion) is provided between the sealing material 14 arranged in an annular shape on the counter substrate 20 and the display region E. The light shielding film 18 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding film 18 is a display area E having a plurality of pixels P. Although not shown in FIG. 1, a light shielding film that divides a plurality of pixels P in a plane is also provided in the display area E.

  Wirings connected to the data line driving circuit 22 and the scanning line driving circuit 24 are connected to a plurality of external connection terminals 65 arranged along the one side. Hereinafter, the direction along the one side will be referred to as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other will be described as the Y direction.

  As shown in FIG. 2, on the surface of the first base material 10a on the liquid crystal layer 15 side, a transparent pixel electrode 27 provided for each pixel P and a thin film transistor (TFT: Thin Film Transistor, which is a switching element) are provided. Hereinafter, it is referred to as “TFT 30”), signal wirings, and an alignment film 28 covering them.

  In addition, a light shielding structure is employed that prevents light from entering the semiconductor layer (active layer) in the TFT 30 to make the switching operation unstable. The element substrate 10 in the present invention includes at least the pixel electrode 27, the TFT 30, and the alignment film 28.

  On the surface of the counter substrate 20 on the liquid crystal layer 15 side, a light shielding film 18, a planarizing layer 33 formed so as to cover the light shielding film 18, a counter electrode 31 provided so as to cover the planarizing layer 33, An alignment film 32 that covers the electrode 31 is provided. The counter substrate 20 in the present invention includes at least the counter electrode 31 and the alignment film 32.

  As shown in FIG. 1, the light shielding film 18 surrounds the display area E and is provided at a position where the scanning line driving circuit 24 and the inspection circuit 25 overlap in a plan view (illustration is simplified). Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is shielded, and the peripheral circuit is prevented from malfunctioning due to the light. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

  The planarizing layer 33 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the light shielding film 18 with optical transparency. As a method for forming such a planarization layer 33, for example, a method of forming a film by using a plasma CVD (Chemical Vapor Deposition) method or the like can be cited.

  The counter electrode 31 is made of a transparent conductive film such as ITO (Indium Tin Oxide), for example, covers the planarization layer 33, and includes an element substrate by vertical conduction portions 26 provided at the four corners of the counter substrate 20 as shown in FIG. It is electrically connected to the wiring on the 10 side.

  The alignment film 28 covering the pixel electrode 27 and the alignment film 32 covering the counter electrode 31 are selected based on the optical design of the liquid crystal device 100. For example, an inorganic alignment film formed by depositing an inorganic material such as SiOx (silicon oxide) using a vapor deposition method and substantially vertically aligning with liquid crystal molecules having negative dielectric anisotropy can be given.

  Such a liquid crystal device 100 is a transmission type, and the transmittance of the pixel P when the voltage is not applied is normally white larger than the transmittance when the voltage is applied, or the transmittance of the pixel P when the voltage is not applied. A normally black mode optical design is employed, which is smaller than the transmittance when a voltage is applied. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  As shown in FIG. 3, the liquid crystal device 100 includes a plurality of scanning lines 3a and a plurality of data lines 6a that are insulated from each other and orthogonal to each other at least in the display region E, and a capacitor line 3b as a common potential wiring. The direction in which the scanning line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction.

  A pixel electrode 27, a TFT 30, and a storage capacitor 16 are provided in a region divided by the scanning line 3a, the data line 6a, the capacitor line 3b, and these signal lines, and these constitute a pixel circuit of the pixel P. doing.

  The scanning line 3 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the data line side source / drain region (source region) of the TFT 30. The pixel electrode 27 is electrically connected to the pixel electrode side source / drain region (drain region) of the TFT 30.

  The data line 6a is connected to the data line driving circuit 22 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 22 to the pixels P. The scanning line 3a is connected to the scanning line driving circuit 24 (see FIG. 1), and supplies the scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 24 to each pixel P.

  The image signals D1 to Dn supplied from the data line driving circuit 22 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 24 supplies the scanning signals SC1 to SCm to the scanning line 3a at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 as a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 27 at a predetermined timing. It is the structure written in. The predetermined level of the image signals D1 to Dn written to the liquid crystal layer 15 through the pixel electrode 27 is held for a certain period between the pixel electrode 27 and the counter electrode 31 disposed to face the liquid crystal layer 15. The

  In order to prevent the retained image signals D1 to Dn from leaking, a storage capacitor 16 is connected in parallel with a liquid crystal capacitor formed between the pixel electrode 27 and the counter electrode 31. The storage capacitor 16 is provided between the pixel electrode side source / drain region of the TFT 30 and the capacitor line 3b.

<Configuration of liquid crystal device and semiconductor device>
FIG. 4 is a schematic cross-sectional view showing the structure of a liquid crystal device and a TFT as a semiconductor device. FIG. 5 is a schematic plan view of the semiconductor device of the liquid crystal device shown in FIG. 4 as viewed from above. Hereinafter, the structures of the liquid crystal device and the semiconductor device will be described with reference to FIGS. 4 and 5 show cross-sectional positional relationships among the constituent elements, and are expressed on an expressible scale.

  As shown in FIG. 4, the liquid crystal device 100 includes an element substrate 10 that is one of a pair of substrates, and a counter substrate 20 (not shown) that is the other substrate disposed to face the element substrate 10. Yes. As described above, the first base material 10a configuring the element substrate 10 is configured by, for example, a quartz substrate.

  As shown in FIGS. 4 and 5, on the first base material 10a, for example, a lower light-shielding film 3c containing a material such as Al (aluminum), Ti (titanium), Cr (chromium), or W (tungsten). Is formed. The lower light-shielding film 3c is planarly patterned in a lattice shape and defines an opening area of each pixel P. In this specification, the lower light-shielding film 3c has conductivity, is formed in a pattern that is conductive only in the scanning line direction and is divided in the source line direction, and functions as a part of the scanning line 3a. I am doing so.

  As shown in FIGS. 4 and 5, a base insulating layer 11a made of a silicon oxide film or the like is provided on the lower light-shielding film 3c (scanning line). A TFT 30 as a semiconductor device is formed on the base insulating layer 11a. A part of the formation region of the TFT 30 on the base insulating layer 11a includes a data line side source / drain region 30s (one of the source region and the drain region) in the semiconductor layer 30a made of polysilicon (high purity polycrystalline silicon) or the like. Is arranged.

  The semiconductor layer 30a is formed as an N-type TFT 30 by implanting N-type impurity ions such as phosphorus (P) ions. Specifically, the semiconductor layer 30a includes, for example, a channel region 30c, a data line side LDD (Lightly Doped Drain) region 30s1 (first LDD region), a data line side source / drain region 30s, and a pixel electrode side LDD region 30d1. (Second LDD region) and a pixel electrode side source / drain region 30d (the other of the source region and the drain region).

  The channel region 30c is doped with P-type impurity ions such as boron (B) ions. The other regions (30s, 30s1, 30d, 30d1) are doped with N-type impurity ions such as phosphorus (P) ions. Thus, the TFT 30 is formed as an N-type TFT.

  A first interlayer insulating layer 11b (first insulating layer) made of a silicon oxide film or the like is provided on the data line side source / drain region 30s and the base insulating layer 11a. A contact hole CNT1 that penetrates to the lower light-shielding film 3c is provided in the first interlayer insulating layer 11b and the base insulating layer 11a. A region on the first interlayer insulating layer 11b that overlaps a portion of the data line side source / drain region 30s in plan view is electrically connected to the lower light-shielding film 3c (scanning line) through the contact hole CNT1. A gate electrode 30g made of a silicon film or the like is provided.

  An opening 35 penetrating the gate electrode 30g is provided in a part of the gate electrode 30g in a region where the gate electrode 30g and the data line side source / drain region 30s overlap in plan view. Further, a contact hole CNT2 penetrating to the data line side source / drain region 30s is provided in the first interlayer insulating layer 11b extending from the opening hole 35 (on the first opening hole side). Inside the opening hole 35 is a channel region 30c in the semiconductor layer 30a. The contact hole CNT2 is a data line side LDD region 30s1 in the semiconductor layer 30a.

  A gate insulating layer 11g is provided on the surface of the gate electrode 30g and the surface of the first interlayer insulating layer 11b from the opening hole 35 of the gate electrode 30g. That is, the channel region 30c is disposed inside the gate insulating layer 11g in the opening 35 of the gate electrode 30g.

  A pixel electrode side LDD region 30d1 is arranged on the channel region 30c in the opening hole 35 of the gate electrode 30g (on the second opening hole side), and a pixel electrode side source / drain region 30d is arranged around it. ing. In other words, the data line side source / drain region 30s, the data line side LDD region 30s1, the channel region 30c, the pixel electrode side LDD region 30d1, and the pixel electrode side source / drain region 30d extend from the lower layer side to the upper layer side (vertical direction). TFT 30.

  A second interlayer insulating layer 11c made of a silicon oxide film or the like is provided on the pixel electrode side LDD region 30d1, the pixel electrode side source / drain region 30d, and the gate insulating layer 11g. A contact hole CNT3 (first contact hole) is provided in the first interlayer insulating layer 11b, the gate insulating layer 11g, and the second interlayer insulating layer 11c overlapping with a part of the data line side source / drain region 30s in plan view. . The second interlayer insulating layer 11c is provided with a contact hole CNT4 (second contact hole) in a region overlapping the pixel electrode side source / drain region 30d in plan view.

  On the second interlayer insulating layer 11c, a conductive film is formed using a light-shielding conductive material such as Al (aluminum) and patterned to form a data line side source / drain region via the contact hole CNT3. A relay electrode 51 (first electrode) and a data line 6a connected to 30s are formed. At the same time, a relay electrode 52 (second electrode) connected to the pixel electrode side source / drain region 30d through the contact hole CNT4 is formed.

  A third interlayer insulating layer 11d made of a silicon oxide film or the like is provided on the data line 6a, the relay electrodes 51 and 52, and the second interlayer insulating layer 11c. The third interlayer insulating layer 11d is made of, for example, silicon oxide or nitride, and is subjected to a flattening process for flattening surface irregularities caused by covering the region where the TFT 30 is provided. Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating. The third interlayer insulating layer 11d is provided with a contact hole CNT5 in a region overlapping the relay electrode 52 in plan view.

  A capacitor line 3b (COM potential) that forms part of the storage capacitor 16 is formed on the third interlayer insulating layer 11d. For example, the capacitor line 3b has a laminated structure in which an aluminum (Al) film is disposed in a lower layer and a titanium nitride (TiN) film is disposed in an upper layer.

  A capacitive insulating film 16b made of alumina, a silicon nitride film or the like is formed on the capacitive line 3b so as to cover the capacitive line 3b. Further, a stopper film 16c1 made of a silicon oxide film or the like is formed on the capacitive insulating film 16b in the vicinity of the region overlapping the contact hole CNT6 region in plan view. The stopper film 16c1 may be formed before the capacitor insulating film 16b is formed, that is, between the capacitor line 3b and the capacitor insulating film 16b.

  On the stopper film 16c1, the capacitor insulating film 16b, and the third interlayer insulating layer 11d, a light-shielding conductive part material such as Al (aluminum) is filled so as to fill the contact hole CNT5 and cover the third interlayer insulating layer 11d. A conductive film is formed and patterned to form a relay electrode 53 connected to the pixel electrode side source / drain region 30d through the contact hole CNT5 and a capacitor electrode as a pixel electrode potential layer constituting the storage capacitor 16 16c is formed. Note that the capacitor electrode 16c and the capacitor electrode 16c adjacent to each other are patterned on the stopper film 16c1 described above.

  A fourth interlayer insulating layer 11e made of a silicon oxide film or the like is formed on the capacitor electrode 16c. A contact hole CNT6 that penetrates through the fourth interlayer insulating layer 11e is formed. A planarization process may be performed on the fourth interlayer insulating layer 11e in the same manner as the third interlayer insulating layer 11d.

  The contact hole CNT6 that penetrates the fourth interlayer insulating layer 11e is formed, for example, at a position that overlaps the stopper film 16c1 in a plan view in the capacitive electrode 16c. A transparent conductive film such as ITO is formed on the fourth interlayer insulating layer 11e so as to fill the contact hole CNT6. Then, by patterning this transparent conductive film, the pixel electrode 27 connected to the capacitor electrode 16c through the contact hole CNT6 is formed.

  The capacitor electrode 16c is electrically connected to the pixel electrode side source / drain region 30d of the TFT 30 via the relay electrode 53, the contact hole CNT5, the relay electrode 52, and the contact hole CNT4, and is connected to the pixel electrode via the contact hole CNT6. 27 is electrically connected.

On the pixel electrode 27 and the fourth interlayer insulating layer 11e, an alignment film 28 (see FIG. 2) is formed by obliquely depositing an inorganic material such as silicon oxide (SiO ₂ ). On the alignment film 28, a liquid crystal layer 15 in which liquid crystal or the like is sealed in a space surrounded by the sealing material 14 (see FIGS. 1 and 2) is provided.

On the other hand, the counter electrode 31 is provided over the entire surface of the second base material 20a (the liquid crystal layer 15 side) (see FIG. 2). On the counter electrode 31, an alignment film 32 is formed by obliquely depositing an inorganic material such as silicon oxide (SiO ₂ ). The counter electrode 31 is made of a transparent conductive film such as an ITO film, for example, like the pixel electrode 27 described above.

  The liquid crystal layer 15 takes a predetermined alignment state by the alignment films 28 and 32 in a state where no electric field is generated between the pixel electrode 27 and the counter electrode 31. The sealing material 14 is an adhesive made of, for example, a photocurable resin or a thermosetting resin, for bonding the element substrate 10 and the counter substrate 20 around them, and a distance between the two substrates is set to a predetermined value. Spacers such as glass fiber or glass beads are mixed. Hereinafter, a method for manufacturing the liquid crystal device 100 will be described.

<Liquid Crystal Device and Semiconductor Device Manufacturing Method>
FIG. 6 is a flowchart showing a manufacturing method of the liquid crystal device in the order of steps. 7 to 9 are schematic cross-sectional views mainly showing a method for manufacturing a semiconductor device among methods for manufacturing a liquid crystal device. FIG. 10 is a schematic plan view taken along line AA ′ of the semiconductor device shown in FIG. Hereinafter, a method for manufacturing a liquid crystal device and a method for manufacturing a semiconductor device will be described with reference to FIGS.

  First, a manufacturing method on the element substrate 10 side will be described. First, in step S11, a TFT 30 as a semiconductor device is formed on a first base material 10a made of a quartz substrate or the like. Specifically, as shown in FIG. 7A (first source / drain region forming step), a lower light-shielding film 3c (scanning line) made of aluminum or the like is formed on the first base material 10a. Thereafter, a base insulating layer 11a made of a silicon oxide film or the like is formed using a known film forming technique.

  Next, the data line side source / drain region 30s in the semiconductor layer 30a is formed on the base insulating layer 11a. First, a polysilicon film is formed on the base insulating layer 11a. Next, for example, when an N-type TFT 30 is formed, N-type impurity ions such as phosphorus (P) ions are implanted. Thereafter, patterning is performed to form the data line side source / drain region 30s.

  In the step (gate electrode formation step) shown in FIG. 7B, the gate electrode 30g is formed. First, a first interlayer insulating layer 11b made of an NSG film (Non doped Silicate Glass) or the like is formed on the data line side source / drain region 30s and the underlying insulating layer 11a. Next, a contact hole CNT1 that penetrates the base insulating layer 11a and the first interlayer insulating layer 11b is formed.

  Thereafter, the contact hole CNT1 is filled, and a polysilicon film (gate electrode film) is formed on the first interlayer insulating layer 11b. Thereafter, the gate electrode 30g is patterned by using a photolithography technique and an etching technique. The thickness of the gate electrode 30g is, for example, 1.5 μm. As a result, the gate electrode 30g and the lower light-shielding film 3c (scanning line) are electrically connected via the contact hole CNT1.

  In the step (opening hole forming step) shown in FIG. 7C, the opening hole 35 is formed in the gate electrode 30g. Specifically, for example, it is formed using a photolithography technique and an etching technique. The diameter of the opening hole 35 is, for example, 0.5 μm to 0.6 μm. The gate electrode 30g and the opening hole 35 can be formed simultaneously.

  In the step (gate insulating layer forming step) shown in FIG. 8D, the gate insulating layer 11g is formed. Specifically, the gate insulating layer 11g is formed on the gate electrode 30g including the sidewall of the opening 35 and on the first interlayer insulating layer 11b. The thickness of the gate insulating layer 11g is, for example, 800 mm.

  In the step shown in FIG. 8E, a contact hole CNT2 connected to the opening hole 35 is formed. Specifically, for example, the contact hole CNT2 is formed in the first interlayer insulating layer 11b by reactive ion etching (RIE).

  In the step shown in FIG. 8F, an amorphous silicon film (ASi) 34 (semiconductor film) is formed and a data line side LDD region 30s1 is formed. First, an amorphous silicon film 34 is formed in the opening hole 35 and in the contact hole CNT2. Specifically, for example, the film is formed by using a CVD method (Chemical Vapor Deposition).

  Next, the substrate is subjected to a heat treatment to diffuse the P (phosphorus) implanted in the above into the contact hole CNT2. As a result, the data line side LDD region 30s1 which is a low concentration impurity ion region is formed in the contact hole CNT2.

  In the step shown in FIG. 9G (impurity ion implantation step), the channel region 30c, the pixel electrode side LDD region 30d1, and the pixel electrode side source / drain region 30d are formed. First, P-type impurity ions such as B (boron) are implanted into a region to be the channel region 30c. At this time, the implantation energy is adjusted so that the B concentration profile has a peak around the center of the channel.

  Next, N-type impurity ions (low concentration) such as phosphorus (P) ions are implanted into the amorphous silicon film 34 on the channel region 30c to form the pixel electrode side LDD region 30d1. At this time, the P concentration profile is adjusted by the implantation energy so that P is not implanted into the channel as much as possible. Thereafter, the pixel electrode side LDD region 30d1 is covered with a resist, and N-type impurity ions (high concentration) such as phosphorus (P) ions are implanted into the amorphous silicon film 34 around the pixel electrode side LDD region 30d1 to form a pixel. An electrode-side source / drain region 30d is formed.

  As described above, the semiconductor layer 30a having the data line side source / drain region 30s, the data line side LDD region 30s1, the channel region 30c, the pixel electrode side LDD region 30d1, and the pixel electrode side source / drain region 30d is completed in this order from the lower layer side. .

  In the step shown in FIG. 9H, the data line 6a and the relay electrodes 51 and 52 are formed. First, a second interlayer insulating layer 11c made of a silicon oxide film or the like is formed on the pixel electrode side LDD region 30d1, the pixel electrode side source / drain region 30d, and the gate insulating layer 11g. Next, a contact hole CNT3 that penetrates the second interlayer insulating layer 11c, the gate insulating layer 11g, and the first interlayer insulating layer 11b is formed by using a photolithography technique and an etching technique, and penetrates the second interlayer insulating layer 11c. A contact hole CNT4 is formed.

  Next, a light-shielding conductive member such as aluminum is formed on the second interlayer insulating layer 11c while filling the contact holes CNT3 and CNT4, and the conductive member is patterned. As a result, the relay electrode 51 and the data line 6a electrically connected to the contact hole CNT3 are formed, and the relay electrode 52 electrically connected to the contact hole CNT4 is formed. Thus, the TFT 30 is completed.

  Next, description will be made with reference to FIG. In step S12, the pixel electrode 27 is formed. Specifically, the third interlayer insulating layer 11d, the storage capacitor 16, and the fourth interlayer insulating layer 11e are formed on the TFT 30 by using a known film forming technique, photolithography technique, and etching technique, and the fourth interlayer insulating film is formed. A pixel electrode 27 is formed on the insulating layer 11e.

  In step S13, the alignment film 28 is formed. Specifically, an alignment material 28 having a columnar structure is formed by obliquely vapor-depositing an inorganic material such as silicon oxide on the entire fourth interlayer insulating layer 11e provided with the pixel electrode 27.

  Next, a manufacturing method on the counter substrate 20 side will be described. First, in step S21, the counter electrode 31 is formed on the second base material 20a made of a translucent material such as a quartz substrate by using a well-known film forming technique.

In step S <b> 22, the alignment film 32 is formed on the counter electrode 31. As a manufacturing method of the alignment film 32, for example, an oblique deposition method in which an inorganic material such as silicon oxide (SiO ₂ ) is obliquely deposited is used. Thus, the counter substrate 20 is completed. Next, a method for bonding the element substrate 10 and the counter substrate 20 will be described.

  In step S <b> 31, the sealing material 14 is applied on the element substrate 10. Specifically, for example, the relative positional relationship between the element substrate 10 and a dispenser (also possible with a discharge device) is changed, so that the periphery of the display area E in the element substrate 10 (so as to surround the display area E). The sealing material 14 is applied.

  In step S32, the element substrate 10 and the counter substrate 20 are bonded together. Specifically, the element substrate 10 and the counter substrate 20 are bonded to the element substrate 10 through the applied sealing material 14.

  In step S33, liquid crystal is injected into the structure from the liquid crystal injection port, and then the liquid crystal injection port is sealed with a sealing material. Thus, the liquid crystal device 100 is completed.

  FIG. 10 shows a cross-sectional view of the vicinity of the opening 35 of the gate electrode 30g. As shown in FIG. 10, a through-type TFT 30 has a gate insulating layer 11g disposed around a channel region 30c and a gate electrode 30g disposed around the gate insulating layer 11g. According to this, the area of the TFT 30 in a plan view can be reduced, and the aperture ratio can be improved. Further, since the data line side source / drain region 30s and the pixel electrode side source / drain region 30d are arranged in the vertical direction, the light shielding property can be improved.

<Configuration of electronic equipment>
Next, a projection display device as an electronic apparatus according to the present embodiment will be described with reference to FIG. FIG. 11 is a schematic diagram showing a configuration of a projection display device including the above-described liquid crystal device.

  As shown in FIG. 11, the projection display apparatus 1000 of the present embodiment includes a polarization illumination device 1100 arranged along the system optical axis L, two dichroic mirrors 1104 and 1105 as light separation elements, and three Reflective mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a cross dichroic as a light combiner A prism 1206 and a projection lens 1207 are provided.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

  The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205. Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204. The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206.

  In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and the emission side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection display apparatus 1000, since the liquid crystal light valves 1210, 1220, and 1230 are used, high reliability can be obtained.

  The electronic device on which the liquid crystal device 100 is mounted includes a projection display device 1000, a head-up display, a smartphone, an EVF (Electrical View Finder), a mobile mini projector, a mobile phone, a mobile computer, a digital camera, and a digital video. It can be used for various electronic devices such as cameras, displays, in-vehicle devices, audio devices, exposure devices, and lighting devices.

  As described above in detail, according to the TFT 30, the liquid crystal device 100, the manufacturing method of the TFT 30, the manufacturing method of the liquid crystal device 100, and the electronic apparatus of the present embodiment, the following effects can be obtained.

  (1) According to the TFT 30, the liquid crystal device 100, the manufacturing method of the TFT 30, and the manufacturing method of the liquid crystal device 100 of the present embodiment, the gate insulating layer 11g and the gate electrode 30g are provided so as to cover the periphery of the columnar semiconductor layer 30a. The data line side source / drain region 30s and the data line side LDD region 30s1 are disposed on the first base material 10a side of the semiconductor layer 30a, and the pixel electrode side LDD is disposed on the side away from the first base material 10a side of the semiconductor layer 30a. The region 30d1 and the pixel electrode side source / drain region 30d are disposed. As described above, since the TFT 30 is formed through the gate electrode 30g in the vertical direction, the area of the TFT 30 in a plan view can be reduced, and the aperture ratio can be improved. Further, since the data line side source / drain region 30s and the pixel electrode side source / drain region 30d are arranged in the vertical direction, the light shielding property can be improved. In addition, since the LDD regions 30s1 and 30d1 are disposed, it is possible to suppress a leakage current from flowing through the channel region 30c.

  (2) According to the TFT 30, the liquid crystal device 100, the manufacturing method of the TFT 30, and the manufacturing method of the liquid crystal device 100 according to the present embodiment, the relay electrodes 51 and 52 are provided on the third interlayer insulating layer 11d disposed above the gate electrode 30g. Therefore, the wiring connected to the relay electrodes 51 and 52 is separated from the first base material 10a side, and the occurrence of problems such as disconnection of the wiring is suppressed when the element substrate 10 is subjected to a high temperature treatment. be able to.

  (3) According to the electronic apparatus of this embodiment, since the above-described liquid crystal device 100 is provided, an electronic apparatus with high display quality can be provided.

  The aspect of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. It is included in the range. Moreover, it can also implement with the following forms.

(Modification 1)
As described above, the electro-optical device is not limited to being applied to the liquid crystal device 100, and may be applied to, for example, an organic EL device, a plasma display, electronic paper, or the like.

  3a ... scanning line, 3b ... capacitance line, 3c ... lower light shielding film (scanning line), CNT1, 2, 5, 6 ... contact hole, CNT3 ... contact hole (first contact hole), CNT4 ... contact hole (second) Contact hole), 6a ... data line, 10 ... element substrate, 10a ... first base material, 11a ... underlying insulating layer, 11b ... first interlayer insulating layer (first insulating layer), 11c ... second interlayer insulating layer, 11d 3rd interlayer insulating layer 11e 4th interlayer insulating layer 11g Gate insulating layer 14 Sealing material 15 Liquid crystal layer as electro-optic layer 16 Storage capacitor 16b Capacitor insulating film 16c Capacitor Electrode, 18 ... Light-shielding film, 20 ... Counter substrate, 20a ... Second base material, 22 ... Data line driving circuit, 24 ... Scanning line driving circuit, 25 ... Inspection circuit, 26 ... Vertical conduction part, 27 ... Pixel electrode, 28 32 ... Alignment film 29 ... wiring, 30 ... TFT, 30a ... semiconductor layer, 30c ... channel region, 30d ... pixel electrode side source / drain region (the other of the source region and drain region), 30d1 ... pixel electrode side LDD region (second LDD region), 30g ... Gate electrode, 30s ... Data line side source / drain region (one of source region and drain region), 30s1 ... Data line side LDD region (first LDD region), 31 ... Counter electrode, 33 ... Flattening layer, 35 ... Open hole 51 ... Relay electrode as first electrode, 52 ... Relay electrode as second electrode, 53 ... Relay electrode, 65 ... Terminal for external connection, 100 ... Liquid crystal device, 1000 ... Projection display device, 1100 ... Polarized illumination device DESCRIPTION OF SYMBOLS 1101 ... Lamp unit 1102 ... Integrator lens 1103 ... Polarization conversion element, 1104, 1105 ... Dichroic Kumira, 1106,1107,1108 ... reflecting mirror, 1201,1202,1203,1204,1205 ... relay lens, 1206 ... cross dichroic prism, 1207 ... projection lens, 1210, 1220 ... liquid crystal light valves, 1300 ... screen.

Claims (8)

One of a source region and a drain region;
The other of the source region and the drain region;
A channel region;
A first electrode;
A second electrode;
A gate electrode;
A gate insulating film disposed between the channel region and the gate electrode;
Including
The gate electrode has an opening;
The channel region is disposed in the aperture;
The first electrode is electrically connected to one of the source region and the drain region through a first contact hole opened in a first insulating film covering the gate electrode,
The semiconductor device, wherein the second electrode is electrically connected to the other of the source region and the drain region through a second contact hole opened in the first insulating film. The semiconductor device according to claim 1,
A first LDD region is disposed between the channel region and one of the source region and the drain region,
A semiconductor device, wherein a second LDD region is disposed between the channel region and the other of the source region and the drain region. The semiconductor device according to claim 1 or 2, wherein
A semiconductor device, wherein the first electrode is disposed inside the first contact hole, and the second electrode is disposed inside the second contact hole. The semiconductor device according to any one of claims 1 to 3, a pixel electrode electrically connected to the semiconductor device, an element substrate including the semiconductor device and the pixel electrode,
A counter substrate disposed opposite to the element substrate;
An electro-optic layer sandwiched between the element substrate and the counter substrate;
An electro-optical device comprising: Forming one of a source region and a drain region;
Forming a gate electrode on one of the source region and the drain region; and
An opening forming step of forming an opening in the gate electrode in a region overlapping with one of the source region and the drain region in plan view;
A gate insulating layer forming step of forming a gate insulating layer so as to cover the opening hole and the gate electrode;
Forming a semiconductor film in the opening and on the gate insulating layer;
Implanting impurity ions into the semiconductor film to form a channel region in the opening;
Further, an impurity ion implantation step of implanting impurity ions into the semiconductor film to form the other of the source region and the drain region;
Forming a first insulating film covering the semiconductor film;
A first contact hole is formed in a region overlapping with one of the source region and the drain region of the first insulating film in plan view, and one of the source region and the drain region of the first insulating film is formed. Forming a second contact hole in a region overlapping the portion in plan view;
Forming a first electrode electrically connected to one of the source region and the drain region, and a second electrode electrically connected to the other of the source region and the drain region;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 5,
A method of manufacturing a semiconductor device, wherein impurity ions having a lower concentration than the other of the source region and the drain region are implanted into the semiconductor film over the opening hole to form the other LDD region. A process including a method for manufacturing a semiconductor device according to claim 5;
Electrically connecting the semiconductor device and the pixel electrode through a contact hole;
Forming an electro-optic layer on the pixel electrode;
A method for manufacturing an electro-optical device.   An electronic apparatus comprising the semiconductor device according to claim 1 or the electro-optical device according to claim 4.

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