JP2014192400A - Mark forming method, mark detecting method, and device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mark forming method which can be used when forming a circuit pattern using a self-organization of a block copolymer.SOLUTION: A mark forming method comprises: a step 108 of exposing a reticle pattern image to a wafer and forming a resist mark which includes a recess and in which a self-organization region is not formed in a polymer layer including a block copolymer in a scribe line region on the basis of a wafer mark pattern image; a step 110 of applying the polymer layer including the block copolymer to the wafer; a step 112 of forming a self-organization region in at least a part of the applied polymer layer; a step 114 of selectively removing a part of the formed self-organization region; and steps 116 and 118 of forming a wafer mark using the resist mark.

Description

  The present invention relates to a mark formation technique for forming a mark on a substrate, a mark detection technique for detecting a mark formed on the substrate, and a device manufacturing technique using the mark formation technique or the mark detection technique.

  A semiconductor device typically includes multiple layers of circuit patterns formed on a substrate, and a predetermined layer of the substrate is used to accurately align the multiple layers of circuit patterns with each other in the semiconductor device manufacturing process. An alignment mark for positioning or alignment is formed in the mark forming region. When the substrate is a semiconductor wafer (hereinafter simply referred to as a wafer), the alignment mark is also called a wafer mark.

  A conventional finest circuit pattern of a semiconductor device has been formed by using a dry or immersion lithography process using a dry or immersion exposure apparatus having an exposure wavelength of 193 nm, for example. It is expected that it is difficult to form a circuit pattern finer than, for example, a 22 nm node even if conventional optical lithography is combined with a recently developed double patterning process.

  In this regard, nanoscale microstructures (sub-lithography) using Directed Self-Assembly of a block copolymer (Block Co-Polymer) between patterns formed using a lithography process recently. It has been proposed to form a circuit pattern finer than the resolution limit of the current lithography technology by generating (structure) (see, for example, Japanese Patent Application Laid-Open No. 2010-269304). The patterned structure of a block copolymer is also known as a microdomain (microphase separation domain) or simply a domain.

US Patent Application Publication No. 2010/0297847

  By using directional self-assembly of block copolymers, it is possible to form nanoscale fine circuit patterns in a certain layer of the substrate. Furthermore, it may be required to form an alignment mark in the layer together with the circuit pattern. However, if the alignment mark is simply formed by a conventional method, an unexpected fine structure is formed in the alignment mark itself due to the self-organization of the block copolymer, and it becomes difficult to detect the alignment mark in the subsequent process. There is a risk that the overlay accuracy between the two layers will decrease.

  In view of such circumstances, it is an object of an aspect of the present invention to provide a mark forming technique that can be used when forming a circuit pattern using self-organization of a block copolymer.

  According to the first aspect, the mask image is exposed to the region including the mark formation region of the substrate, and the polymer layer including the block copolymer is self-exposed to the mark formation region based on the first portion of the mask image. Forming a first mark including a portion where no organized region is formed, applying the polymer layer including the block copolymer to the region including the mark forming region, and at least of the applied polymer layer Performing a process for forming a self-organized region in a part, performing a process for selectively removing a part of the formed self-organized region, and using the first mark Forming a first positioning mark on the mark forming region of the substrate.

  According to the second aspect, in the mark forming method according to the first aspect, the first mark has a width in which a self-assembled region is not formed over the entire length in the polymer layer including the block copolymer. Based on a second portion that is different from the first portion of the mask image in the mark formation region in parallel with the formation of the first mark in the mark formation region of the substrate. Forming a second mark having a second recess having a width wider than the first recess, and using the first mark to form the first positioning mark in the mark forming region; In parallel, a mark forming method is provided in which a second positioning mark is formed in the mark forming region using the second mark.

  According to the third aspect, there is provided a method for detecting a positioning mark formed in a mark forming region of a substrate by the mark forming method of the first or second aspect, and generating a detection signal for the positioning mark. Determining, based on the detection signal, the presence or absence of a mark portion formed based on a portion where at least part of the self-organized region of the polymer layer is removed in the mark forming region; A mark detection method is provided.

  According to a fourth aspect, there is provided a method for detecting the first and second positioning marks formed in the mark forming region of the substrate by the mark forming method of the second aspect, wherein the first and second Generating a detection signal for the positioning mark, and selecting a mark to be used for positioning the substrate from the first and second positioning marks based on the detection signal Are provided.

  According to the fifth aspect, the mark for interlayer alignment is formed on the substrate using the mark forming method of the first or second aspect, and alignment is performed using the mark for alignment. Thus, a device manufacturing method is provided that includes exposing the substrate and processing the exposed substrate.

  According to the aspect of the present invention, the positioning mark is formed in the mark forming region of the substrate using the first mark including the portion where the self-organized region is not formed in the polymer layer including the block copolymer. When a circuit pattern is formed using self-organization of a block copolymer, a detectable mark can be formed together with the circuit pattern.

(A) is a block diagram showing a main part of a pattern forming system used in an example of an embodiment, and (B) is a diagram showing a schematic configuration of an exposure apparatus in FIG. 1 (A). FIG. 3A is a plan view showing a device layer with a wafer, and FIG. 3B is an enlarged plan view showing one wafer mark and a part of a circuit pattern in FIG. It is a flowchart which shows an example of the formation method of the pattern containing a mark. (A), (B), (C), (D), (E), (F), and (G) are enlarged sectional views each showing a part of a wafer pattern that gradually changes during the pattern formation process. It is. (A) is an enlarged plan view showing a part of a pattern for a mark of a reticle and a device, and (B) is an enlarged plan view showing a part of a pattern formed on a wafer. It is a figure which shows the comparison result of the dispersion | variation in the alignment precision at the time of using two marks. FIG. 7A is an enlarged plan view showing a part of the formed wafer mark, FIG. 7B is a diagram showing an example of an image signal of the mark image of FIG. 7A, and FIG. It is a figure which shows an example of the differential signal of this imaging signal. (A) is a top view which shows an example of the shot arrangement | sequence of the wafer of a modification, (B) is an enlarged view of the B section in FIG. 8 (A). It is a flowchart which shows an example of the manufacturing process of an electronic device.

An example of a preferred embodiment of the present invention will be described with reference to FIGS. First, an example of a pattern forming system used for forming a circuit pattern of an electronic device (microdevice) such as a semiconductor element in the present embodiment will be described.
FIG. 1A shows a main part of the pattern forming system of the present embodiment, and FIG. 1B shows a scanning exposure apparatus (projection exposure apparatus) comprising a scanning stepper (scanner) in FIG. ) 100 schematic configuration. 1A, a pattern forming system includes an exposure apparatus 100 that exposes a wafer (semiconductor wafer) coated with a photosensitive material, and a coater / developer that applies and develops a photoresist (resist) as the photosensitive material on the wafer. 200, thin film forming apparatus 300, etching apparatus 400 for performing dry or wet etching on a wafer, and polymer processing for processing a polymer (polymer) including a block copolymer (Block Co-Polymer: BCP) described later An apparatus 500, an annealing apparatus 600, a transfer system 700 for transferring a wafer between these apparatuses, a host computer (not shown), and the like are included.

  The block copolymer used in the present invention is a polymer containing a monomer (monomer) present in more than one block unit, or a polymer derived from these monomers. Each block of monomers includes a repeating sequence of monomers. Any polymer such as a diblock copolymer or a triblock copolymer can be used as the block copolymer. Of these, the diblock copolymer has two different monomer blocks. The diblock copolymer can be abbreviated as Ab-B, where A is the first block polymer, B is the second block polymer, -b- is the A and B block. It is a diblock copolymer having For example, PS-b-PMMA represents a diblock copolymer of polystyrene (PS) and polymethyl methacrylate (PMMA). In addition to the chain block copolymer, a block copolymer having another structure, such as a star copolymer, a branched copolymer, a hyperbranched copolymer, or a graft copolymer, is used as the block of the present invention. It can also be used as a copolymer.

  The block copolymer has a tendency (blocking tendency) that individual blocks (monomers) constituting the block copolymer gather to form individual microphase separation domains also called microdomains or simply domains. This phase separation is also a kind of self-assembly. The spacing and morphology of the different domains depends on the interaction, volume fraction, and number of different blocks within the block copolymer. The domain of the block copolymer can be formed, for example, as a result of annealing (annealing). Heating or baking, which is part of annealing, is a common process that raises the temperature of the substrate and its coating layer (thin film layer) above ambient temperature. Annealing can include thermal annealing, thermal gradient annealing, solvent vapor annealing, or other annealing methods. Thermal annealing, sometimes referred to as thermosetting, is used to induce phase separation and can also be used as a process to reduce or eliminate defects in layers of lateral microphase separation domains. . Annealing generally involves heating at a temperature above the glass transition temperature of the block copolymer for a period of time (eg, minutes to days).

  Further, in this embodiment, directed self-assembly (DSA) is applied to a polymer including a block copolymer to form a circuit pattern and / or alignment mark suitable for a semiconductor device. To form nanoscale-ordered domains. Directed self-organization is a spatial arrangement (topographic structure) defined by a pre-pattern or guide pattern, for example, using a resist pattern formed by a lithography process as a pre-pattern or guide pattern. It is a technology that controls the placement. As a directivity self-organization method, for example, a grapho-epitaxy process using a three-dimensional pre-pattern or a guide pattern is used, but a planar pre-pattern or guide pattern is provided on the ground. A chemo-epitaxy process can also be used.

  In FIG. 1B, an exposure apparatus 100 includes an illumination system 10, a reticle stage RST that holds a reticle R (mask) that is illuminated by exposure illumination light (exposure light) IL from the illumination system 10, and a reticle R. A projection unit PU including a projection optical system PL that projects the emitted illumination light IL onto the surface of the wafer W (substrate), a wafer stage WST that holds the wafer W, and a computer that comprehensively controls the operation of the entire apparatus. A main control device (not shown) is provided. In FIG. 1B, the reticle R and the wafer W are relative to each other in a plane that is parallel to the optical axis AX of the projection optical system PL and is orthogonal to the Z axis (this is substantially a horizontal plane in this embodiment). Take the Y-axis along the scanned direction, the X-axis along the direction orthogonal to the Z-axis and Y-axis, and rotate (tilt) directions around the X-axis, Y-axis, and Z-axis, respectively, θx, θy , And θz direction will be described.

  The illumination system 10 includes a light source that generates illumination light IL and an illumination optical system that illuminates the reticle R with the illumination light IL, as disclosed in, for example, US Patent Application Publication No. 2003/025890. As the illumination light IL, for example, ArF excimer laser light (wavelength 193 nm) is used. Note that as the illumination light IL, KrF excimer laser light (wavelength 248 nm), a harmonic of a YAG laser or a solid-state laser (such as a semiconductor laser) can be used.

  The illumination optical system includes a polarization control optical system, a light quantity distribution forming optical system (such as a diffractive optical element or a spatial light modulator), an optical integrator (such as a fly-eye lens or a rod integrator (an internal reflection type integrator)), etc. An optical system, a reticle blind (fixed and variable field stop), and the like (both not shown) are included. The illumination system 10 illuminates a slit-like illumination area IAR elongated in the X direction on the pattern surface (lower surface) of the reticle R defined by the reticle blind, such as dipole illumination, quadrupole illumination, annular illumination, or normal illumination. Under certain conditions, the illumination light IL having a predetermined polarization state is illuminated with a substantially uniform illuminance distribution.

  A reticle stage RST that holds the reticle R by vacuum suction or the like is movable on the upper surface of the reticle base (not shown) parallel to the XY plane at a constant speed in the Y direction, and in the X and Y positions. And the rotation angle in the θz direction can be adjusted. The position information of the reticle stage RST is, for example, with a resolution of about 0.5 to 0.1 nm through the movable mirror 14 (or the mirror-finished side surface of the stage) by the reticle interferometer 18 including a multi-axis laser interferometer. Always detected. The position and speed of reticle stage RST are controlled by controlling a reticle stage drive system (not shown) including a linear motor and the like based on the measurement value of reticle interferometer 18.

  The projection unit PU disposed below the reticle stage RST includes a lens barrel 24 and a projection optical system PL having a plurality of optical elements held in the lens barrel 24 in a predetermined positional relationship. The projection optical system PL is, for example, telecentric on both sides and has a predetermined projection magnification β (for example, a reduction magnification of 1/4 times, 1/5 times, etc.). Due to the illumination light IL that has passed through the reticle R, an image of the circuit pattern in the illumination area IAR of the reticle R passes through the projection optical system PL to form an exposure area IA (conjugation with the illumination area IAR) in one shot area of the wafer W. Region). The wafer W (substrate) of the present embodiment is a thin film for pattern formation (oxidation) on the surface of a disk-shaped substrate having a diameter of about 200 to 450 mm made of, for example, silicon (or SOI (silicon on insulator)). Film, metal film, polysilicon film, etc.). Further, a photoresist is applied to the surface of the wafer W to be exposed with a predetermined thickness (for example, about several tens of nm to 200 nm).

  Further, the exposure apparatus 100 performs exposure using a liquid immersion method, so that the lower end of the lens barrel 24 that holds the tip lens 26 that is the optical element on the most image plane side (wafer W side) constituting the projection optical system PL. A nozzle unit 32 that constitutes a part of the local liquid immersion device 30 for supplying the liquid Lq between the tip lens 26 and the wafer W is provided so as to surround the periphery of the part. The supply port for the liquid Lq of the nozzle unit 32 is connected to a liquid supply device (not shown) via a supply flow path and a supply pipe 34A. The liquid Lq recovery port of the nozzle unit 32 is connected to a liquid recovery device (not shown) via a recovery flow path and a recovery pipe 34B. The detailed configuration of the local immersion apparatus 30 is disclosed in, for example, US Patent Application Publication No. 2007/242247.

  Wafer stage WST is mounted on upper surface 12a of base board 12 parallel to the XY plane so as to be movable in the X and Y directions and rotatable in the θz direction. Wafer stage WST is provided in stage body 20, wafer table WTB mounted on the upper surface of stage body 20, and stage body 20, and the position (Z) of wafer table WTB (wafer W) with respect to stage body 20 (Z Position) and a Z-leveling mechanism that relatively drives the tilt angles in the θx direction and the θy direction. Wafer table WTB is provided with a wafer holder (not shown) that holds wafer W on a suction surface substantially parallel to the XY plane by vacuum suction or the like. Around the wafer holder (wafer W) on the upper surface of wafer table WTB, a flat plate (repellent repellent surface) that is substantially flush with the surface of wafer W (wafer surface) and that has been subjected to a liquid repellent treatment with respect to liquid Lq. (Liquid plate) 28 is provided. Further, during exposure, for example, based on the measurement value of an oblique focus type autofocus sensor (not shown), the Z leveling of wafer stage WST is performed so that the wafer surface is focused on the image plane of projection optical system PL. The mechanism is driven.

  Further, reflection surfaces are formed on the end surfaces in the Y direction and X direction of wafer table WTB by mirror finishing. By projecting an interferometer beam from a plurality of laser interferometers constituting the wafer interferometer 16 onto its reflecting surface (which may be a moving mirror), the position information of the wafer stage WST (at least in the X and Y directions) And a rotation angle in the θz direction) are measured with a resolution of about 0.5 to 0.1 nm, for example. The position and speed of wafer stage WST are controlled by controlling a wafer stage drive system (not shown) including a linear motor and the like based on the measured values. Note that the position information of wafer stage WST may be measured by an encoder type detection apparatus having a diffraction grating scale and a detection head.

  The exposure apparatus 100 also projects the wafer alignment system ALS composed of an image processing type FIA (Field Image Alignment) system that measures the position of a predetermined wafer mark (alignment mark) on the wafer W, and projection optics for the alignment mark of the reticle R. In order to measure the position of the image by system PL, an aerial image measurement system (not shown) built in wafer stage WST is provided. Using these aerial image measurement systems (reticle alignment systems) and wafer alignment systems ALS, alignment between the reticle R and each shot area of the wafer W is performed.

  When the wafer W is exposed, the wafer stage WST is moved (stepped) in the X and Y directions, so that the shot area to be exposed on the wafer W moves to the front of the exposure area IA. Further, the liquid Lq is supplied between the projection optical system PL and the wafer W from the local liquid immersion device 30. Then, while projecting an image of a part of the pattern of the reticle R by the projection optical system PL onto one shot area of the wafer W, the reticle R and the wafer W are synchronized in the Y direction via the reticle stage RST and the wafer stage WST. The pattern image of the reticle R is scanned and exposed to the shot area. By repeating the step movement and scanning exposure, the image of the pattern of the reticle R is exposed to each shot area of the wafer W by the step-and-scan method and the liquid immersion method. Note that the exposure apparatus 100 may be a dry method, and in this case, the local immersion apparatus 30 can be omitted.

  Next, as an example, the device pattern to be manufactured in this embodiment is a circuit pattern for an SRAM (Static RAM) gate cell as a semiconductor element, and this circuit pattern is a polymer pattern including a block copolymer. Formed using directional self-organization (DSA). Further, in the present embodiment, a wafer mark as an alignment mark for positioning or alignment is also formed on the device layer of the wafer W on which the device pattern is formed.

  FIG. 2A shows the wafer W on which the device pattern and the wafer mark are formed. In FIG. 2A, the surface of the wafer W is provided with a number of shot areas SA (device pattern formation areas) with a scribe line area SL (mark formation area) having a predetermined width in the X and Y directions. A device pattern DP1 is formed in each shot area SA, and a wafer mark WM is formed in a scribe line area SL attached to each shot area SA. For example, if the diameter of the wafer W is 300 mm, about 100 shot areas SA are formed on the surface of the wafer W as an example. The diameter of the wafer W is not limited to 300 mm, and a large wafer such as a 450 mm wafer may be used.

  As shown in FIG. 2B, which is an enlarged view of a portion B in FIG. 2A, the device pattern DP1 has a plurality of line patterns 40Xa extending in the Y direction arranged in a substantially period (pitch) px1 in the X direction. The line and space pattern (hereinafter referred to as L & S pattern) 40X and the L & S pattern 40Y in which a plurality of line patterns extending in the X direction are arranged with a period py1 in the Y direction are included. The line pattern 40Xa and the like are made of, for example, metal, and the line width is about ½ or less of the period px1 or the like. As an example, the periods px1 and py1 are substantially equal, and the period px1 is the finest period (hereinafter referred to as a period pmin) obtained by combining immersion lithography with a wavelength of 193 nm and, for example, a so-called double patterning process. It is about a fraction of that. For example, 1/2 of the period px1 is smaller than about 22 nm. When the L & S patterns 40X and 40Y having such a fine period are formed, a linear domain is formed for each different block when the polymer including the block copolymer is subjected to directional self-assembly. The

  Further, the wafer mark WM in the scribe line area SL is an X-axis wafer mark 44X in which line pattern areas 44Xa and space pattern areas 44Xb that are elongated in the Y direction and have the same width in the X direction are arranged in the X direction with a period p1. Also included are two Y-axis wafer marks 44YA and 44YB in which line pattern regions 44Ya and space pattern regions 44Yb that are elongated in the X direction and have the same width in the Y direction are arranged in the X direction with a period p2. Wafer marks 44YA and 44YB are arranged so as to sandwich wafer mark 44X in the Y direction. As an example, the periods p1 and p2 are equal, and the widths of the line pattern regions 44Xa and 44Ya (approximately ½ of the period p1) are about several tens of times the resolution limit (period) in immersion lithography with a wavelength of 193 nm. .

  Furthermore, the line pattern regions 44Xa and 44Ya and the space pattern regions 44Xb and 44Yb may be regions that have different reflectivities for detection light when detected by the wafer alignment system ALS in FIG. In this case, if the wavelength λa of the detection light of the wafer alignment system ALS and the numerical aperture NA of the objective optical system are used, the resolution limit (optically detectable limit) of the wafer alignment system ALS is λa / (2NA). Further, in order to detect the wafer marks 44X, 44YA, 44YB by the wafer alignment system ALS, ½ of the period p1 of the wafer mark 44X needs to be equal to or greater than the resolution limit, and the wafer mark is detected by the wafer alignment system ALS. The conditions under which 44X, 44YA, and 44YB can be detected are as follows.

p1 / 2 ≧ λa / (2NA) (1)
As an example, if the wavelength λa is 600 nm and the numerical aperture NA is 0.9, the period p1 may be about 670 nm or more. In this embodiment, directional self-organization in which a linear domain is formed when the device pattern DP1 is formed is applied. However, as described later, when forming the wafer marks 44X, 44YA and the like, It is considered that the directivity self-organization of coalescence does not occur substantially.

  Hereinafter, an example of a pattern forming method for forming a pattern including the wafer marks 44X, 44YA, 44YB and the device pattern DP1 shown in FIG. 2B using the pattern forming system of this embodiment will be described with reference to FIG. This will be described with reference to a flowchart. As an example, as shown in FIG. 4A, a surface portion of a substrate 50 such as silicon of the wafer W is defined as a first device layer DL1 on which a wafer mark and a device pattern are formed.

  First, in step 102 of FIG. 3, a hard mask layer 52 such as an oxide film or a nitride film is formed on the surface of the device layer DL1 of the wafer W using the thin film forming apparatus 300, and the hard coater / developer 200 is used to For example, a positive resist layer 54 is coated on the mask layer 52 (see FIG. 4A). Note that an antireflection film (Bottom Anti-Reflection Coating: BARC) may be used as the hard mask layer 52. Then, the reticle R is loaded onto the reticle stage RST of the exposure apparatus 100, the illumination condition of the exposure apparatus 100 is set to, for example, quadrupole illumination so that the finest pattern can be exposed in the X direction and the Y direction, and alignment of the reticle R is performed. To load the wafer W onto the exposure apparatus 100 (step 104).

  As shown in FIG. 5A, the pattern RP formed on the reticle R includes a device pattern 45D and X-axis and Y-axis wafer mark (alignment mark) patterns 45X, 45YA, and 45YB. Contains. The device pattern 45D has a plurality of light-shielding line patterns 45DX and 45DY formed in the X direction and the Y direction at periods close to the resolution limit of the exposure apparatus 100, respectively. Then, using the period p1 of the wafer mark 44X in FIG. 2B and the projection magnification β of the projection optical system PL of the exposure apparatus 100, the pattern 45X has a width p1 / (2β) in the X direction in the light shielding film. A plurality of opening patterns 45Xa elongated in the direction are formed with a period p1 / β in the X direction, and the patterns 45YA and 45YB each have a plurality of elongated patterns in the X direction with a width p1 / (2β) in the Y direction in the light shielding film. The opening pattern 45YAa is formed in the Y direction with a period p1 / β. A region between the two opening patterns 45Xa or 45YAa is a space pattern 45Xb or 45YAb made of a light shielding film, respectively. Hereinafter, for convenience of explanation, it is assumed that the image of the reticle pattern by the projection optical system PL is an erect image.

  Then, the image of the pattern RP of the reticle R is exposed to each shot area SA of the wafer W and the scribe line area SL attached thereto by the immersion method (step 106). At this time, an image 45DXP of the device X-axis line pattern 45DX is exposed to each shot area SA, and an image 45XP of the X-axis wafer mark pattern 45X is exposed to the scribe line area SL (FIG. 4 ( A)). At the same time, an image of a Y-axis line pattern 45DY (not shown) for the device and images of Y-axis wafer mark patterns 45YA and 45YB (not shown) are also exposed.

  The exposed wafer W is unloaded, the resist is developed by the coater / developer 200, and a resist pattern 54P (see FIG. 4B) indicated by a dotted line is formed. Thereafter, slimming of the resist pattern 54P and a resist curing process are performed (step 108). Note that the exposure amount can be adjusted to be large so that the line width of the resist pattern is narrowed during exposure of the pattern image of the reticle R. In this case, slimming can be omitted.

  By slimming the resist pattern 54P, as shown in FIG. 4B, a concave portion 45X1a corresponding to the wafer mark opening pattern 45Xa in FIG. 5A, a convex portion 54A1 corresponding to the wafer mark space pattern 45Xb, In addition, a plurality of line-like patterns (hereinafter referred to as guide patterns) 54A that are elongated in the Y direction corresponding to the thinned pattern of the X-axis line pattern 45DX for the device are formed. The line width of the guide pattern 54A is, for example, about one-tenth to several-tenth of the resolution limit in terms of period in immersion lithography with a wavelength of 193 nm.

  A region between the wafer mark pattern and the device pattern is a convex portion 54A2. The convex portions 54A1 and 54A2 and the guide pattern 54A are resist patterns formed on the hard mask layer 52, respectively. An X-axis wafer mark registration mark RPX is formed from the plurality of concave portions 45X1a and the convex portions 54A1 between them. In the present embodiment, a resist pattern having a fine period corresponding to the guide pattern 54A is not formed in the region where the resist mark RPX is formed. Since the width of the wafer mark opening pattern 45Xa in the X direction is considerably larger than the width of the device X-axis line pattern 45DX, the width of the wafer mark recess 45X1a after slimming is substantially equal to the width in the X direction. Therefore, it can be regarded as 1/2 of the period p1 of the wafer mark.

  In this embodiment, the width in the X direction of the recess 45X1a of the registration mark RPX is such that the polymer containing the block copolymer (BCP) described later is applied to the recess 45X1a. ) Is set so wide that it does not occur. In other words, the recess 45X1a is a non-matching region with respect to the polymer containing the block copolymer. On the other hand, the region between the plurality of guide patterns 54A for the device pattern is a region where the directivity self-organization of the polymer occurs, that is, a matching region with respect to the polymer. Thus, in order for the recess 45X1a to be a non-aligned region with respect to the polymer containing the block copolymer, the width in the measurement direction (here, the X direction) of the recess 45X1a may be approximately 1 μm or more as described later. preferable. Further, the cycle of the wafer mark in the measurement direction is, for example, almost twice the width of the recess 45X1a. If the cycle is too large, the alignment accuracy may be reduced. Therefore, it is preferable that the period of the wafer mark in the X direction is about 6 μm or less, that is, the width of the recess 45X1a in the X direction is about 3 μm or less.

  In this regard, the present inventor forms a resist pattern including recesses 45X1a having different widths in the scribe line area provided in each shot area of a plurality of wafers, and based on these resist patterns, the plurality of sheets are formed. Wafer marks were formed by changing the thickness of the polymer relative to each other. Then, a plurality of wafer marks are selected from the plurality of wafers, the position of the selected wafer mark is measured by the wafer alignment system ALS, and the standard deviation regarding the difference between the measured value and the target position is measured as the variation of the measured value. Of 3 times (so-called 3σ).

  FIG. 6 shows the variation (here 3σ) VAR of the measurement values of the positions of wafer marks formed on a plurality of wafers under different conditions. In addition, “Ref” on the horizontal axis in FIG. 6 indicates a wafer on which a mark is formed in a conventional lithography process in which a polymer containing a block copolymer is not applied, and “TK”, “TNaA”, and “TNb” are Each shows a wafer coated with the thickest polymer, a wafer coated thinnest, and a wafer coated thinly next. The dotted broken line B1 and the solid broken line B3 in FIG. 6 indicate the variation VAR of the measurement value of the wafer mark when the width of the recess 45X1a is 1 μm and 3 μm, respectively. As shown in FIG. 6, the variation in the wafer mark measurement value (polygonal line B3) when the width of the recess 45X1a is 3 μm is almost the same as the measurement value of the wafer mark formed in the conventional lithography process regardless of the thickness of the polymer layer. It can be seen that it is close to variation and highly practical. On the other hand, the variation (measurement line B1) of the wafer mark measurement value when the width of the recess 45X1a is 1 μm is larger than the variation of the measurement value of the wafer mark formed in the conventional lithography process, particularly when the polymer layer is thick. However, it can be seen that by reducing the thickness of the polymer layer, variations in measured values can be reduced to a practical range. From this result, the width of the recess 45X1a when forming the wafer mark is preferably about 1 μm to 3 μm. Depending on the required alignment accuracy, the width of the recess 45X1a may be 3 μm or more.

  Next, in step 110, the wafer W on which the resist mark RPX and the device pattern guide pattern 54A of FIG. 4B are formed is transferred to the polymer processing apparatus 500, and for example, by spin coating, the resist mark RPX and the device pattern. A polymer layer 56 containing a block copolymer is applied (formed) to the surface of the wafer W so as to cover the guide pattern 54A and the like. In this embodiment, as a block copolymer, a diblock copolymer (PS-b-PMMA) of polystyrene (PS) and polymethyl methacrylate (PMMA) is used as an example. The polymer layer 56 is a block copolymer itself, but may contain a solvent for improving the coating property and / or an additive for facilitating self-assembly. By spin coating, the polymer layer 56 is deposited in the plurality of recesses 45X1a constituting the resist mark RPX and in the region between the plurality of guide patterns 54A for the device pattern (see FIG. 4C). By spin coating, the polymer layer 56 is not applied thicker than the heights of the convex portions 54A1 and 54A2 and the guide pattern 54A. Furthermore, in this embodiment, since the width of the recess 45X1a is wide, the polymer layer 56a deposited in the recess 45X1a tends to have a thinner central portion than the peripheral portion.

  Then, the wafer W on which the polymer layers 56 and 56a are formed is transferred to the annealing apparatus 600, and the polymer layers 56 and 56a are subjected to annealing (for example, thermal annealing), so that the polymer layer 56 has a directional self-assembly (DSA). ) To separate into two types of domains (step 112). That is, as shown in FIG. 4D, the polymer layer 56 between the device pattern guide patterns 54A is a lyophilic first domain 56A made of linear PMMA (polymethyl methacrylate) elongated in the Y direction. And the liquid repellent second domain 56B made of linear PS (polystyrene) elongated in the Y direction are phase-separated into a state of being arranged in the X direction with a fine period. Since the guide pattern 54A (resist pattern) is lyophilic, a lyophilic domain 56A is formed in a portion adjacent to the guide pattern 54A. The fine period is, for example, about 1 to 1/10 of the period of the plurality of guide patterns 54A, and the widths in the X direction of the two types of domains 56A and 56B are substantially the same.

  On the other hand, since the width of the recess 45X1a of the registration mark RPX is wide, the directivity self-assembly is not substantially generated in the polymer layer 56a in the recess 45X1a. However, in the region near the convex portions 54A1 and 54A2 in the concave portion 45X1a, the lyophilic first domain 56aA and the liquid repellent second domain 56aB may be alternately formed in an incomplete shape. is there. The domains 56aA and 56aB are lower in height than the domains 56A and 56B, and the period is not uniform. In this embodiment, the polymer layer 56 is separated into two types of elongated domains along the elongated guide pattern 54A. At this time, the annealing of the polymer layer 56 (wafer W) is also performed under conditions that allow easy separation into two types of elongated domains.

  In this case, as shown in FIG. 5B, in the shot area SA of the wafer W, domains 56A and 56B are periodically formed between a plurality of X-axis guide patterns 54A, and a plurality of Y-axis guides are formed. The first and second domains 56C and 56D are periodically formed between the patterns 54B. In the scribe line area SL adjacent to the shot area SA, the domains 56aA and 56aB (the domain 56aA is not shown) may be formed in an incomplete shape in the recess 45X1a of the X-axis registration mark 45X1. The first and second domains 56bA and 56bB (domain 56bA not shown) may be formed in an incomplete shape in the recesses 45YA1a and the like of the shaft registration marks 45YA1 and 45YB1.

  Then, the wafer W is transferred to the etching apparatus 400, and subjected to, for example, oxygen plasma etching. As shown in FIG. 4E, the lyophilic first of the domains 56A and 56B formed on the wafer W. Domain 56A is selectively removed (step 114). At this time, if the domains 56aA and 56aB are formed in the recess 45X1a, the lyophilic first domain 56aA is removed. Furthermore, the polymer layer 56a left in a state where no directional self-organization has occurred in the recess 45X1a is substantially removed.

  Thereafter, the hard mask layer 52 of the wafer W is etched using the resist mark RPX, the guide pattern 54A, and the periodically remaining liquid-repellent domains 56B as a mask, so that a plurality of convex portions are formed on the hard mask layer 52. Opening 45X2a corresponding to 52a and recess 45X1a is formed (see FIG. 4F), and the remaining resist and domain 56B are removed (step 116). The portions of the hard mask layer 52 corresponding to the convex portions 54A1 and 54A2 of the resist pattern become convex portions 52b and 52c, respectively. At this time, even if the domain 56aB is left slightly in the peripheral portion in the recess 45X1a, the domain 56aB is almost removed, for example, when the hard mask layer 52 is etched. However, if the domain 56aB is left, a convex portion corresponding to the domain 56aB is formed on the hard mask layer 52, and this convex portion may affect the shape of the finally formed wafer mark. There is.

  Then, the first device layer DL1 of the wafer W is etched through the hard mask layer 52 in which the plurality of convex portions 52a to 52c are formed, and as shown in FIG. A plurality of elongated recesses 41Xa in the Y direction are respectively formed in the region corresponding to the domain 56A, and the recesses 45X3a are formed in the region corresponding to the opening 45X2a (first half of step 118). Further, the wafer W is transferred to the thin film forming apparatus 300, and metal (for example, copper) ME is embedded in the recesses 41Xa and 45X3a of the device layer DL1 of the wafer W, and as shown in FIG. A 40X line pattern 40Xa is formed, and a line pattern region 44Xa of the X-axis wafer mark 44X is formed (second half of step 118).

  Through the above steps, the scribe line region SL of the first device layer DL1 of the wafer W has a line pattern region 44Xa made of metal and a space pattern region 44Xb made of a base, as shown in FIG. X-axis wafer marks 44X arranged in the X direction with a period p1 are formed. Furthermore, the line pattern region 44Ya having a shape obtained by rotating the line pattern region 44Xa by 90 degrees and the space pattern region 44Yb are arranged in the Y direction at a cycle p2 (here, equal to p1) so as to sandwich the wafer mark 44X in the Y direction. The two wafer marks 44YA and 44YB on the Y axis are formed. These wafer marks 44X and 44YA, 44YB can be detected by a wafer alignment system ALS provided in the exposure apparatus 100.

At the same time as the wafer marks 44X, 44YA, and 44YB are formed, each shot area SA of the wafer W has a periodicity as a device pattern using directional self-organization of a polymer layer containing a block copolymer. L & S patterns 40X and 40Y of px1 and py1 are formed.
Thereafter, when the second device layer is formed on the device layer DL1 of the wafer W, a thin film is formed on the device layer DL1 of the wafer W and coated with a resist (step 120). Then, a second device layer reticle (reticle R1) is loaded onto reticle stage RST of exposure apparatus 100, and wafer W is loaded onto wafer stage WST (step 122). Further, wafer mark WM (wafer marks 44X, 44YA, 44YB) attached to a plurality of shot areas (so-called alignment shots) selected from all shot areas SA of wafer W by wafer alignment system ALS of exposure apparatus 100. ) Is detected (step 124). For example, when about 100 shot areas SA are formed on the wafer W, about 20 alignment shots are selected as an example.

  Thereafter, a calculation unit (not shown) that processes the detection signals of the wafer alignment system ALS determines whether the detected signals of all the measured wafer marks WM are good or bad (step 126). Here, an example of a method for determining the quality of the detection signal for the X-axis wafer mark 44X shown in FIG. 7A will be described. In this case, since the wafer alignment system ALS is an image processing system, an image signal DSX shown in FIG. 7B is obtained as a detection signal by capturing an image of the wafer mark 44X. The horizontal axis in FIG. 7B indicates the positions of a plurality of pixels arranged in a direction corresponding to the measurement direction (here, the X direction) of the image sensor of the wafer alignment system ALS.

  The calculation unit detects the following amounts (a1) to (a11) as an example of the feature amount of the imaging signal DSX. In the following description, a portion of the period p1 formed by the line pattern region 44Xa and the space pattern region 44Xb in the wafer mark 44X is referred to as a mark unit. It should be noted that feature amounts are similarly detected for the Y-axis wafer marks 44YA and 44YB.

(A1) X at the position where the imaging signal of the image of a plurality of (in this case, four) mark units (area including the line pattern area 44Xa) of the wafer mark 44X has the maximum value (position values indicated by arrows A1 to A4). Intervals pm1, pm2, pm3 in the direction.
(A2) The maximum value <pmmax> and the minimum value <pmmin> among the intervals pm1 to pm3.

(A3) Deviation δpm1 of the average value <pm> of the intervals pm1 to pm3 from the design value <pmx>.
(A4) A difference δpm2 between the maximum value <pmmax> and the minimum value <pmmin> of the intervals pm1 to pm3.
In addition, if the domain 56aB is left slightly in the peripheral portion in the wafer mark recess 45X1a in FIG. 4E, and a convex portion corresponding to the domain 56aB is formed in the hard mask layer 52, A fine line-shaped pattern (pattern having an unnecessary fine structure caused by the block copolymer) is included in the line pattern region 44Xa of the wafer mark 44X to be finally formed. Further, since the pattern having the unnecessary fine structure is considered to be different for each of the plurality of line pattern regions 44Xa, the width (line width) d of the line pattern region 44Xa in FIG. 7A is a target value. It has a variation δ with respect to p1 / 2. For this reason, the waveform of the imaging signal DSX in FIG. 7B changes for each of the plurality of line pattern regions 44Xa. When the area ratio of patterns having unnecessary fine structures increases, for example, the difference δpm2 between the maximum value and the minimum value of the intervals pm1 to pm3 is assumed to increase. For this reason, an unnecessary fine structure is obtained by an increase from a predetermined target value of the difference δpm2 (for example, an average value of differences measured for a wafer mark formed without applying a polymer containing a block copolymer). It is possible to estimate the amount of patterns having

  Further, when the increment of the difference δpm2 with respect to the predetermined target value exceeds a certain value, the self-organization of the polymer layer 56a is carried out in the recess 45X1a for the wafer mark in the scribe line area SL (mark formation area). It is possible to determine that a mark portion formed based on a portion (domain 56aB) from which at least a portion (domain 56aA) has been removed remains. The wafer mark 44X determined to have such a mark portion remaining may be excluded from the measurement target.

(A5) The maximum value and the minimum value of the imaging signal in the region where the image of the wafer mark 44X is formed, and the contrast (amplitude / average value) of the imaging signal.
(A6) An average value <imax> such as a maximum value (position values indicated by arrows A1 to A4) imax1 of an imaging signal in a plurality of mark unit images of the wafer mark 44X.
(A7) An average value <imin> such as the minimum value imin1 of the imaging signal in the image of the plurality of mark units of the wafer mark 44X.

(A8) Difference between the average value <imax> and the average value <imin>.
(A9) An average value of the maximum values of the inclination amount of the imaging signal (the amount of change in the imaging signal with respect to the change in the position in the X direction) in the image of the plurality of mark units.
In order to obtain this value, as shown in FIG. 7C, the differential signal dDSX / dx of the imaging signal DSX is obtained, and the differential of the image of each mark unit (line pattern region 44Xa and space pattern region 44Xb) is obtained. The absolute value SLL1 of the maximum value of the positive value of the signal and the absolute value SLR1 of the maximum value of the negative value are obtained, and the average value of the larger one of these values (the maximum value in the mark unit) is calculated. That's fine.

(A10) A difference between the maximum value and the minimum value of the inclination amount of the imaging signal in the image of a plurality of mark units.
(A11) An average value of the difference between the absolute value SLL1 and the like of the positive inclination amount and the absolute value SLR1 and the like of the negative inclination amount of the imaging signal in the plurality of mark unit images.
Then, the calculation unit calculates the feature amount and a predetermined target value (for example, a polymer including a block copolymer) for each of the feature amounts (a1) to (a11) obtained with respect to the plurality of measured wafer marks. The average value of the feature values obtained for a wafer mark formed without coating is determined, and when these differences exceed a reference value defined for each feature value, It is determined that the detection signal is defective. Note that when a difference of a certain ratio (for example, a ratio of 50% or more) of the differences exceeds a corresponding reference value, the detection signal of the wafer mark may be determined to be defective. In addition, it is only necessary to detect at least some of the feature amounts of (a1) to (a11).

  In the next step 128, the calculation unit determines whether or not the number of wafer marks determined to have a good detection signal is equal to or greater than a predetermined number (here, the number that provides the necessary alignment accuracy). If the number of wafer marks determined to have a good detection signal is smaller than the predetermined number, the process proceeds to step 132, for example, the wavelength of the detection light of the wafer alignment system ALS, the polarization state, and the imaging optics The detection conditions such as the numerical aperture of the system are changed, and the process returns to step 124 to repeat the operation after the detection of the wafer mark in the alignment shot. Note that the alignment shot (the position of the wafer mark to be measured) may be changed instead of changing the detection condition or together with the change of the detection condition.

  If the number of wafer marks determined to have a good detection signal in step 128 is greater than or equal to a predetermined number, the process proceeds to step 130 and a plurality of wafers for which the detection signal is determined to be good. The mark used for alignment is selected from the marks, and the coordinate of each shot area of the wafer W is obtained by using, for example, the enhanced global alignment (EGA) method using the position measured with respect to the selected mark. The wafer W is aligned.

Thereafter, an image of the pattern of the reticle R1 is exposed to each shot area SA of the wafer W (step 134), and pattern formation such as resist development and etching is performed in the next process (step 136), thereby forming the second device layer. A pattern is formed. Furthermore, when forming the third device layer, another reticle R2 is used.
As described above, according to the pattern forming method of the present embodiment, each shot area SA of the wafer W is finer than the resolution limit of the immersion lithography using the directional self-organization of the polymer layer including the block copolymer. In addition to forming the L & S patterns 40X and 40Y having a simple structure, a wafer mark 44X having a structure that can be detected by the wafer alignment system ALS can be formed in the scribe line region SL. For this reason, the wafer W can be aligned with high accuracy in the next step.

  As described above, in the mark forming method using the pattern forming system according to the present embodiment, the image of the pattern of the reticle R is exposed to the scribe line area SL (mark forming area) and the shot area SA of the wafer W. Based on the image 45XP (first portion) of the wafer mark pattern 45X, the scribe line region SL includes a resist mark RPX including a recess 45X1a (portion) in which a self-assembled region is not formed in the polymer layer including the block copolymer. Forming (first mark) 108. Further, the mark forming method includes a step 110 of applying a polymer layer 56, 56a containing the block copolymer to the scribe line region SL and the shot region SA, and a polymer layer 56 of at least a part of the applied polymer layer. A step 112 for performing a process for forming a self-organized region on the substrate, and a step 114 for performing a process for selectively removing a part of the formed self-organized region (lyophilic domain 56A); And steps 116 and 118 for forming a wafer mark 44X (first positioning mark) in the scribe line area SL of the wafer W using the resist mark RPX.

  According to this mark forming method, the wafer mark 44X is formed in the scribe line region SL of the wafer W using the resist mark RPX including the portion where the self-organized region is not formed in the polymer layer including the block copolymer. Therefore, when forming a circuit pattern using self-organization of the block copolymer, a detectable wafer mark can be formed together with the circuit pattern.

  The mark detection method of the present embodiment is a detection method of a positioning wafer mark 44X formed in the scribe line area SL of the wafer W by the mark formation method of the present embodiment, and an imaging signal of the wafer mark 44X. (Detection signal) generation step 124, and based on the imaging signal, based on the portion (domain region 56aB) from which at least a part of the self-organized region of the polymer layer 56a is removed in the scribe line region SL. And step 126 for determining the presence or absence of the formed mark portion. According to this mark detection method, it is possible to detect a mark in which a mark portion formed based on the domain region 56aB remains. If the remaining amount is large, the alignment accuracy of the wafer W can be improved by taking measures such as not using the detection result of the mark for alignment.

In the above embodiment, the following modifications are possible.
In the above embodiment, one wafer mark is formed in the area attached to each shot area of the wafer. On the other hand, as shown in the modified examples of FIGS. 8A and 8B, a plurality of wafer marks having different shapes may be formed in the region attached to each shot region.
FIG. 8A shows a shot arrangement of the wafer W1 of this modified example, and FIG. 8B shows an enlarged view of a portion B including a scribe line region SL between certain shots in FIG. 8A. In FIG. 8A, N shots SAn (n = 1 to N) are provided on the surface of the wafer W1 (N is an integer of about several 10 to 100, for example). Then, as shown in FIG. 8B, first and second wafer marks WM1 and WM2 are formed in the scribe line area SL between the shot areas SAn by using the same pattern forming method as in the above embodiment. To do. Note that the wafer marks to be formed are not limited to the two types WM1 and WM2, and three or more types of marks may be formed.

  The first wafer mark WM1 includes an X-axis wafer mark in which line pattern regions 44XAa and space pattern regions 44XAb elongated in the Y direction are arranged with a period pA1 in the X direction, and line pattern regions 44YCa and space patterns elongated in the X direction, respectively. The region 44YCb includes two wafer marks on the Y-axis in which the regions 44YCb are arranged in the Y direction at the same cycle. The width of the line pattern areas 44XAa and 44YCa is approximately pA1 / 2. The second wafer mark WM2 includes an X-axis wafer mark in which line pattern regions 44XBa and space pattern regions 44XBb elongated in the Y direction are arranged with a period pB1 smaller than the period pA1 in the X direction, and elongated in the X direction. It includes two Y-axis wafer marks in which the line pattern region 44YDa and the space pattern region 44YDb are arranged at the same cycle in the Y direction. The width of the line pattern regions 44XBa and 44YDa is approximately pB1 / 2.

In addition, the width (pA1 / 2) of the line pattern regions 44XAa and 44YCa and the width (pB1 / 2) of the line pattern regions 44XBa and 44YDa are such that the self-assembled region is formed in the polymer layer including the block copolymer therebetween. The width is not formed, and the width is, for example, about 1 to 3 μm.
In this modification, when performing alignment of the wafer W1 in FIG. 8A on which the two wafer marks in FIG. 8B are formed, for example, J shots (for example, about 20 shots) which are shaded. The area SA is selected as the alignment shot ASj (j = 1 to J), and the positions of the two wafer marks WM1 and WM2 attached to the alignment shot ASj are detected by the wafer alignment system ALS of the exposure apparatus 100. Further, as in step 126 described above, the quality of the detection signals (for example, imaging signals) of the two wafer marks WM1 and WM2 is determined, and the alignment of the wafer W1 is performed using the wafer mark determined to have a good detection signal. I do. According to this detection method, a microstructure formed by the formation of the self-organized region in the polymer layer containing the block copolymer remains in one of the two wafer marks WM1 and WM2. In addition, the alignment of the wafer W1 can be performed with high accuracy.

For example, when the detection signals of the two wafer marks WM1 and WM2 are both good, for example, the mark having the smaller sum of squares of errors from the reference value of the feature amount of the detection signal (imaging signal) is used. You may do it.
In the above embodiment, the device pattern is a line pattern, but the device pattern is a hole array composed of a large number of minute holes (vias or through holes) periodically arranged in the X direction and the Y direction. The pattern forming method of the above-described embodiment can be applied even when including.

  Next, when a semiconductor device (electronic device) such as an SRAM is manufactured using the pattern forming method of each of the above-described embodiments, the semiconductor device performs a function / performance design of the semiconductor device as shown in FIG. 221; manufacturing a mask (reticle) based on this design step 222; manufacturing a semiconductor device substrate (or wafer substrate) 223; substrate processing step 224; device assembly step (dicing process, bonding process) , Including a processing process such as a packaging process) 225, an inspection step 226, and the like. Further, the substrate processing step 224 includes the pattern forming method of the above-described embodiment, and the pattern forming method includes a step of exposing the reticle pattern to the substrate with an exposure apparatus, a step of developing the exposed substrate, and a developing process. It includes a process of heating (curing) and etching the substrate.

In other words, the device manufacturing method includes a substrate processing step 224, and the substrate processing step 224 includes a step of forming a device pattern and a wafer mark on the substrate using the pattern forming method of the above-described embodiment. Yes.
According to this device manufacturing method, a semiconductor device including a circuit pattern finer than the resolution limit of the exposure apparatus can be manufactured with high accuracy using the exposure apparatus.

The device to be manufactured in the above embodiment can be any semiconductor device such as DRAM, CPU, DSP other than SRAM. Furthermore, the pattern forming method of the above-described embodiment can also be applied when manufacturing an imaging device other than a semiconductor device, or an electronic device (microdevice) such as MEMS (Microelectromechanical Systems).
Further, in the above embodiment, as the exposure apparatus, a dry type exposure apparatus that is not an immersion type may be used. In addition to an exposure apparatus that uses ultraviolet light as exposure light, an EUV exposure apparatus that uses EUV light (Extreme Ultraviolet Light) having a wavelength of several nanometers to several tens of nanometers as exposure light, or an electron beam exposure that uses an electron beam as exposure light. An apparatus or the like may be used.

  Moreover, in said embodiment, the diblock copolymer which consists of (PS-b-PMMA) is used as a block copolymer. Other usable block copolymers include, for example, poly (styrene-b-vinylpyridine), poly (styrene-b-butadiene), poly (styrene-b-isoprene), poly (styrene-b- Methyl methacrylate), poly (styrene-b-alkenyl aromatic), poly (isoprene-b-ethylene oxide), poly (styrene-b- (ethylene-propylene)), poly (ethylene oxide-b-caprolactone), poly (butadiene- b-ethylene oxide), poly (styrene-bt-butyl (meth) acrylate), poly (methyl methacrylate-bt-butyl methacrylate), poly (ethylene oxide-b-propylene oxide), poly (styrene-b-tetrahydrofuran) ), Poly (styrene-b-isoprene) diblock or triblock co-polymers such as b-ethylene oxide), poly (styrene-b-dimethylsiloxane), or poly (methyl methacrylate-b-dimethylsiloxane), or combinations comprising at least one of these block copolymers. There are polymers and the like. Furthermore, a random copolymer can also be used as the block copolymer.

Desirably, the block copolymer has an overall molecular weight and polydispersity that can be further processed.
The polymer layer containing the block copolymer can be applied by a solvent casting method in which, for example, a solvent is volatilized after applying a liquid obtained by dissolving the polymer layer in a solvent. The solvent that can be used in this case varies depending on the components of the block copolymer and, if used temporarily, the solubility conditions of various additives. Exemplary casting solvents for these components and additives include propylene glycol monomethyl ether acetate (PGMEA), ethoxyethyl propionate, anisole, ethyl lactate, 2-heptanone, cyclohexanone, amyl acetate, γ-butyrolactone (GBL) , Toluene and the like.

  Additives that can be added to the polymer layer containing the block copolymer include additional polymers (homopolymers, star polymers and copolymers, hyperbranched polymers, block copolymers, graft copolymers, hyperbranched copolymers). Polymers, random copolymers, cross-linked polymers, and inorganic containing polymers), small molecules, nanoparticles, metal compounds, inorganic containing molecules, surfactants, photoacid generators, thermal acid generators, base quenchers, It can be selected from the group consisting of a curing agent, a crosslinking agent, a chain extender, and a combination comprising at least one of the foregoing. Here, the one or more additives associate with the block copolymer to form part of one or more self-assembling domains.

  In addition, this invention is not limited to the above-mentioned embodiment, A various structure can be taken in the range which does not deviate from the summary of this invention.

  R, R1 ... reticle, W ... wafer (substrate), ALS ... wafer alignment system, SL ... scribe line area, SA ... shot area, RPX ... resist mark, DL1 ... device layer, 44X, 44YA, 44YB ... wafer mark, 44Xa 44YA ... line pattern region, 44Xb, 44Yb ... space pattern region, 50 ... base material, 52 ... hard mask layer, 54 ... resist layer, 54A ... guide pattern, 56 ... polymer layer containing BCP, 56A ... lyophilic Domain, 56B ... Liquid-repellent domain, 100 ... Exposure device

Claims (11)

A mask image is exposed to a region including a mark formation region of the substrate, and a portion where a self-organized region is not formed in the polymer layer including the block copolymer is formed in the mark formation region based on the first portion of the mask image. Forming a first mark including:
Applying the polymer layer containing the block copolymer to a region including the mark forming region;
Performing a process for forming a self-assembled region in at least a portion of the applied polymer layer;
Performing a process for selectively removing a part of the self-organized region to be formed;
Forming a first positioning mark in the mark formation region of the substrate using the first mark;
A mark forming method including:   2. The mark forming method according to claim 1, wherein the first mark has a first recess having a width in which a self-assembled region is not formed over the entire length in the polymer layer including the block copolymer.   The mark forming method according to claim 2, wherein the first mark has a plurality of the first recesses arranged in the measurement direction with the protrusions interposed therebetween.   The mark forming method according to claim 2 or 3, wherein a width of the first concave portion of the first mark is 1 to 3 µm. In parallel with the formation of the first mark in the mark formation region of the substrate, the mark formation region has a second portion different from the first portion of the mask image based on the first recess. Forming a second mark having a second recess having a wider width,
In parallel with forming the first positioning mark in the mark forming area using the first mark, the second positioning mark is formed in the mark forming area using the second mark. The mark formation method according to any one of claims 2 to 4. Exposing the mask image to a region including the mark forming region of the substrate includes exposing the mask image to a device pattern forming region adjacent to the mark forming region of the substrate;
In parallel with forming the first mark in the mark formation region of the substrate, the block copolymer is formed in the device pattern formation region based on a third portion different from the first portion of the mask image. Forming a first pattern in which a self-assembled region is formed in the polymer layer comprising:
In parallel with forming the positioning mark in the mark forming region of the substrate using the first mark, the self-organized region partially removed and using the self-organized region of the substrate. The mark formation method according to claim 1, wherein the second pattern is formed in the device pattern formation region.   The mark forming method according to claim 6, wherein the first pattern has a region having a width capable of forming a self-assembled region in the polymer layer containing the block copolymer. The first pattern includes a plurality of convex line-shaped guide patterns periodically formed to form a self-organized region in the polymer layer,
The mark forming method according to claim 6, wherein the first mark does not include a pattern corresponding to the guide pattern. A method for detecting a positioning mark formed in a mark formation region of a substrate by the mark formation method according to claim 1,
Generating a detection signal for the positioning mark;
Based on the detection signal, determining the presence or absence of a mark portion formed based on a portion in which at least a part of the self-organized region of the polymer layer is removed in the mark forming region;
Mark detection method including A method of detecting the first and second positioning marks formed in the mark forming region of the substrate by the mark forming method according to claim 5,
Generating detection signals for the first and second positioning marks;
Selecting a mark to be used for positioning the substrate from the first and second positioning marks based on the detection signal;
Mark detection method including Forming a mark for alignment between layers on a substrate using the mark forming method according to claim 1;
Aligning using the alignment mark, exposing the substrate;
Processing the exposed substrate. A device manufacturing method comprising:

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