JP2014171238A - Receiving apparatus and method for setting gain - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiving apparatus capable of improving reception characteristics.SOLUTION: A receiving apparatus comprises: a clock data recovery circuit 2 for generating an extracted clock CLK on the basis of reception data D1; and a gain setting section 3 for setting a gain parameter G1 of a filter circuit 11 in the clock data recovery circuit 2 in accordance with a jitter amount of the reception data D1.

Description

  The present invention relates to a receiving apparatus and a gain setting method.

  In recent years, it has become indispensable to process and transfer large-capacity data at high speed, and there is an increasing demand for high-speed interfaces. In such a high-speed serial interface, a clock data recovery system that transmits data with a clock overlapped is widely used. A receiving apparatus that employs this clock data recovery method requires a clock data recovery (CDR) circuit that extracts a clock synchronized with the received data from the received data.

  As a conventional CDR circuit, one having a function of adjusting response sensitivity of a loop of the CDR circuit in accordance with a phase difference between received data and a clock is known (see, for example, Patent Document 1). In this CDR circuit, as the phase difference between the received data and the clock increases, the response sensitivity of the loop of the CDR circuit increases, so that the convergence speed increases and the phase difference between the received data and the clock can be reduced at high speed. . On the other hand, since the response sensitivity is lowered as the phase difference between the received data and the clock becomes smaller, the stability in a state where the received data and the clock substantially match is improved.

  As a CDR circuit for adjusting response sensitivity, for example, the one disclosed in Patent Document 2 is known.

JP 2005-150890 A JP 2008-236735 A

  Incidentally, since the received data usually includes jitter, an allowable jitter amount is defined for each serial interface. A receiving apparatus using such a serial interface must be able to normally receive received data including jitter up to the allowable amount.

  However, in the CDR circuit described above, the response sensitivity is adjusted only in accordance with the phase difference amount, that is, a specific response sensitivity is always set for a certain phase difference amount. For this reason, in the CDR circuit, for example, when the phase difference amount is small, a low response sensitivity is always set. However, when the response sensitivity is set to be low in this way, when the jitter amount of the received data is large, there is a possibility that the received data cannot be normally received even if the jitter amount is within the above allowable amount. In the CDR circuit, high response sensitivity is always set when the phase difference amount is large. However, when the response sensitivity is set high in this way, the phase will fluctuate excessively when the amount of jitter in the received data is small, resulting in a problem that the stability of the clock deteriorates.

  An object of the receiving apparatus is to improve reception characteristics.

  A disclosed receiving device filters a clock data recovery circuit that generates a clock based on received data, and filters a phase difference between the received data and the clock in the clock data recovery circuit according to a jitter amount of the received data A setting unit for setting the gain of the filter processing.

  According to the disclosed receiving apparatus, it is possible to improve reception characteristics.

The block diagram which shows the receiver of 1st Embodiment. The block circuit diagram which shows the circuit structural example of a filter circuit. 5 is a flowchart illustrating a method for setting a gain parameter according to the first embodiment. (A)-(f) The characteristic view which shows the characteristic of a CDR circuit. The block diagram which shows the receiver of 2nd Embodiment. Explanatory drawing for demonstrating the setting method of the gain parameter of 2nd Embodiment. The flowchart which shows the setting method of the gain parameter of 2nd Embodiment. The flowchart which shows the setting method of the gain parameter of 2nd Embodiment. The block diagram which shows the receiver of 3rd Embodiment. The block diagram which shows the receiver of 4th Embodiment. The block circuit diagram which shows the structural example of a jitter measurement circuit. The wave form diagram which shows operation | movement of a jitter measurement circuit. The wave form diagram which shows operation | movement of a jitter measurement circuit. The flowchart which shows the setting method of the gain parameter of 4th Embodiment. Explanatory drawing for demonstrating a jitter measurement timing.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.
The receiving device includes a receiver circuit 1, a clock data recovery circuit (CDR circuit) 2, a gain setting unit 3, a D-flip flop circuit (D-FF circuit) 4, and a logic unit 5.

  The receiver circuit 1 receives differential serial data from a transmission device (not shown). The receiver circuit 1 generates H / L-judged serial data D1 from the input level of the received differential serial data and outputs the serial data D1 to the CDR circuit 2 and the D-FF circuit 4. To do.

  The CDR circuit 2 generates an extracted clock CLK extracted from the serial data (received data) D1. The extracted clock CLK is a clock synchronized with the reception data D1. The CDR circuit 2 outputs the generated extracted clock CLK to the D-FF circuit 4 and the logic unit 5.

  The gain setting unit 3 sets the gain parameter (gain) G1 of the filter circuit 11 in the CDR circuit 2 according to the jitter amount of the reception data D1. When the gain parameter G1 is changed, the tracking characteristic of the CDR circuit 2 (tracking characteristic with respect to the reception data D1) is also changed. That is, the gain setting unit 3 sets the tracking characteristic of the CDR circuit 2 according to the jitter amount of the reception data D1.

  The D-FF circuit 4 receives the received data D1 from the receiver circuit 1 at its data terminal, and receives the extracted clock CLK from the CDR circuit 2 at its clock terminal. The D-FF circuit 4 samples the received data D1 in synchronization with the rising edge of the extracted clock CLK, and outputs the sampled data to the logic unit 5 as retiming data.

The logic unit 5 executes various processes based on the retiming data from the D-FF circuit 4 and the extracted clock CLK from the CDR circuit 2.
Next, the internal configuration of the CDR circuit 2 will be described.

The CDR circuit 2 includes a phase comparison circuit 10, a filter circuit 11, and a phase correction control circuit 12.
The phase comparison circuit 10 compares the phase of the reception data D1 with the phase of the extraction clock CLK fed back from the phase correction control circuit 12, thereby indicating phase difference information indicating the phase difference between the reception data D1 and the extraction clock CLK. D2 is generated. The phase comparison circuit 10 outputs the generated phase difference information D2 to the filter circuit 11 and the gain setting unit 3. Specifically, the phase comparison circuit 10 determines the phase advance / delay between the reception data D1 and the extracted clock CLK extracted from the reception data D1. Further, based on the determination result, the phase comparison circuit 10 converts the data into +1 when the phase is advanced and -1 when the phase is delayed. Then, the phase comparison circuit 10 filters the data converted into digital phase difference information (phase code) D2 obtained by adding a predetermined period (for example, 10 periods) of the extracted clock CLK with a built-in adder. Output to the circuit 11 and the gain setting unit 3. This predetermined period is set according to the communication rate and the like.

  The filter circuit 11 cumulatively averages (filters) the phase difference information D2 to generate the phase control code D3 and outputs the phase control code D3 to the phase correction control circuit 12. The response sensitivity of the filter circuit 11 is set by the gain parameter G1 set by the gain setting unit 3. Further, the response sensitivity of the filter circuit 11 is reflected in the tracking characteristic of the CDR circuit 2. That is, the tracking characteristic of the CDR circuit 2 is determined by the gain parameter G1 of the filter circuit 11.

  The phase correction control circuit 12 generates an extraction clock CLK having an arbitrary phase from 0 to 2π from the phase control code D3. That is, the phase correction control circuit 12 determines the phase of the extracted clock CLK based on the phase control code D3. For example, when the phase control code D3 can take 64 codes, the phase correction control circuit 12 uses the clock of one phase condition among the phase conditions obtained by dividing 0 to 2π into 64 as the extracted clock CLK according to this code. Generate. Then, the CDR circuit 2 feeds back the extracted clock CLK to the phase comparison circuit 10, and controls the phase of the extracted clock CLK so that the phase of the extracted clock CLK is optimal by comparing the phase of the extracted clock CLK with the received data D1 as needed. ing.

  Note that a PLL (Phase Locked Loop) is often used as the CDR circuit, but the phase comparison circuit 10, the filter circuit 11, and the phase correction control circuit 12 described above are different from the PLL in that the extracted clock CLK is extracted from the received data D1. Is a unique circuit for generating In particular, in the case of a PLL, an oscillation circuit (for example, a VCO) is used to generate the extracted clock CLK. The phase correction control circuit 12 determines the phase of the extracted clock CLK according to the output of the filter circuit 11. It is a circuit and is different from an oscillation circuit.

Next, an example of the internal configuration of the filter circuit 11 will be described with reference to FIG.
As shown in FIG. 2, the filter circuit 11 is a digital filter. The filter circuit 11 includes multipliers 31 and 32, adders 33 and 34, and D-FF circuits 35 and 36.

  The multiplier 31 receives the phase difference information D2 from the phase comparison circuit 10 and the fixed gain parameter G. The multiplier 31 outputs a multiplication value obtained by multiplying the phase difference information D2 by the gain parameter G to the adder 33. The adder 33 adds the output signal of the D-FF circuit 35 to the multiplication value from the multiplier 31 and outputs the addition value to the data terminal of the D-FF circuit 35. A clock signal CLKDF obtained by dividing the extracted clock CLK by a predetermined period (for example, 10 periods) is input to the clock terminal of the D-FF circuit 35. Therefore, the D-FF circuit 35 outputs the addition value input from the adder 33 to the adders 33 and 34 in synchronization with the clock signal CLKDF.

  On the other hand, the multiplier 32 receives the phase difference information D2 from the phase comparison circuit 10 and the gain parameter G1 set by the gain setting unit 3. The multiplier 32 outputs a multiplication value obtained by multiplying the phase difference information D2 by the gain parameter G1 to the adder 34.

  The output signal of the D-FF circuit 36 is input to the adder 34 together with the output signal of the D-FF circuit 35 and the multiplication value from the multiplier 32. The adder 34 adds the output signals of the D-FF circuits 35 and 36 and the multiplication value from the multiplier 32 and outputs the addition value to the data terminal of the D-FF circuit 36. The clock signal CLKDF is input to the clock terminal of the D-FF circuit 36. Therefore, the D-FF circuit 36 outputs the added value from the adder 34 to the phase correction control circuit 12 as the phase control code D3 in synchronization with the clock signal CLKDF.

  The filter circuit 11 configured in this way accumulates and averages the phase difference information D2 for a predetermined period (10 periods in this example) of the extracted clock CLK according to the response sensitivity set by the gain parameters G and G1. A control code D3 is generated. Here, when the gain parameter G1 is set high by the gain setting unit 3, the response sensitivity of the filter circuit 11 becomes high. Along with this, the follow-up characteristic of the CDR circuit 2 also increases. More specifically, in the filter circuit 11, the multiplication value of the multiplier 32 changes and the phase control code D3 also changes according to the gain parameter G1. That is, even if the phase difference information D2 input to the filter circuit 11 has the same value, the phase control code D3 increases as the gain parameter G1 increases. As a result, the phase correction control circuit 12 increases the amount of phase fluctuation of the extracted clock CLK in one phase control. For this reason, as the gain parameter G1 of the filter circuit 11 increases, the follow-up characteristic of the CDR circuit 2 increases. Similarly, the tracking characteristic of the CDR circuit 2 becomes smaller as the gain parameter G1 of the filter circuit 11 becomes lower.

Next, an example of the internal configuration of the gain setting unit 3 will be described with reference to FIG.
The gain setting unit 3 monitors the amount of phase difference between the reception data D1 and the extracted clock CLK, thereby determining the magnitude of the jitter amount of the reception data D1 with respect to the gain parameter G1, and according to the jitter amount. Set the gain parameter G1. Specifically, the gain setting unit 3 changes the gain parameter G1 so that the phase difference is reduced based on the initial value of the gain parameter G1 when the phase difference amount is equal to or greater than a predetermined reference value. The gain setting unit 3 includes an arithmetic circuit 21, a comparison number register 22, a reference value register 23, and a determination circuit 24.

  The arithmetic circuit 21 receives the phase difference information D 2 from the phase comparison circuit 10 and the set number M from the comparison number register 22. The arithmetic circuit 21 calculates an average value AVE of the phase difference information D2 for the set number of times M (for example, 10 times), and outputs the average value AVE to the determination circuit 24. The arithmetic circuit 21 determines whether or not the number of phase comparisons has reached the set number M based on the counting operation of the built-in counter 21a.

  The reference value register 23 stores a reference value T1 of a preset phase difference amount. The reference value T1 is a threshold value for determining whether or not the average value AVE of the phase difference information D2 is at a level for changing the gain parameter G1.

  The determination circuit 24 sets the gain parameter G1 of the filter circuit 11 based on the comparison result obtained by comparing the average value AVE of the phase difference information D2 with the reference value T1 from the reference value register 23. Specifically, the determination circuit 24 does not change the gain parameter G1 when the average value AVE is less than the reference value T1. On the other hand, when the average value AVE is equal to or greater than the reference value T1, the determination circuit 24 changes the gain parameter G1 so that the average value AVE becomes small. Then, the determination circuit 24 outputs the set gain parameter G1 to the filter circuit 11. Note that the initial value of the gain parameter G1 in the present embodiment is set to a low value so that the follow-up characteristic of the CDR circuit 2 becomes small (see FIG. 4A).

  By the way, the phase difference amount (phase difference information D2) between the reception data D1 and the extracted clock CLK in the phase comparison circuit 10 is the jitter amount of the reception data D1 and the tracking characteristic of the CDR circuit 2 determined by the gain parameter G1. The value increases when the relationship is not appropriate. Specifically, the phase difference information D2 becomes large when the gain parameter G1 is low (when the tracking characteristic of the CDR circuit 2 is small) even though the jitter amount of the reception data D1 is large. On the contrary, the phase difference information D2 becomes large even when the gain parameter G1 is high (when the follow-up characteristic of the CDR circuit 2 is large) although the amount of jitter of the reception data D1 is small.

  For this reason, the determination circuit 24 determines whether the average value AVE of the phase difference information D2 is equal to or greater than the reference value T1, thereby tracking the CDR circuit 2 determined by the jitter amount of the reception data D1 and the gain parameter G1. It is determined whether the relationship with the characteristic is appropriate. At this time, since the initial value of the gain parameter G1 is set low as described above, when the average value AVE of the phase difference information D2 is equal to or greater than the reference value T1, this is the amount of jitter of the reception data D1. It can be determined that this is due to the large size. That is, since the jitter amount of the received data D1 with respect to the gain parameter G1 (its initial value) set low is large, it can be determined that the average value AVE is equal to or greater than the reference value T1. Therefore, when the average value AVE is greater than or equal to the reference value T1, the determination circuit 24 according to the present embodiment increases the gain parameter G1 so that the average value AVE (phase difference amount) becomes small. With this change, the tracking characteristic of the CDR circuit 2 is changed so as to increase, so that the tracking characteristic approaches an appropriate value with respect to the jitter amount of the reception data D1.

Next, a method for setting the gain parameter G1 (tracking characteristic of the CDR circuit 2) in the receiving apparatus configured as described above will be described with reference to FIGS.
First, before starting communication, the arithmetic circuit 21, the counter 21a, and the gain parameter G1 are initialized (step S1). The initial value of the gain parameter G1 at this time is set to a low value so that the tracking characteristic of the CDR circuit 2 becomes small. Thereafter, it waits until communication is started (step S2). When communication is started (YES in step S2), the phase of the received data D1 is compared with the phase of the extraction clock CLK in the phase comparison circuit 10 (step S2). S3).

  Next, when the number of phase comparisons is less than the set number M (NO in step S4), the counter 21a is incremented (step S5), and the process returns to step S3. On the other hand, when the number of phase comparisons reaches the set number M (YES in step S4), the arithmetic circuit 21 calculates an average value AVE of the M phase difference information D2 (phase difference amount). (Step S6).

  Subsequently, in the determination circuit 24, it is determined whether or not the average value AVE is greater than or equal to the reference value T1 (step S7). In other words, in step S7, it is determined whether or not the current gain parameter G1 (here, the initial value) with respect to the jitter amount of the reception data D1 is an appropriate value. At this time, when the average value AVE is equal to or greater than the reference value T1, the determination circuit 24 determines that the jitter amount of the reception data D1 with respect to the initial value of the gain parameter G1 is large, that is, the gain parameter for the jitter amount of the reception data D1. It is determined that G1 is low. This point will be described in detail below.

  In this embodiment, the initial value of the gain parameter G1 is set low, and the average value AVE of the phase difference information D2 is monitored as the jitter amount, so that the relationship between the set gain parameter G1 and the jitter amount of the received data D1 is obtained. Judging whether it is appropriate or not. In other words, by setting the initial value of the gain parameter G1 low, the phase difference information D2 changes in proportion to the jitter amount of the reception data D1, and the phase difference information D2 is used as the jitter amount of the reception data D1. It can be monitored. Specifically, since the initial value of the gain parameter G1 is set low, the phase difference information D2 increases as the jitter amount of the reception data D1 increases, while the phase difference information decreases as the jitter amount of the reception data D1 decreases. D2 becomes smaller. Therefore, when the average value AVE is equal to or greater than the reference value T1, as described above, it is determined that the jitter amount of the reception data D1 with respect to the initial value of the gain parameter G1 is large, that is, the gain parameter for the jitter amount of the reception data D1. It can be determined that G1 is low.

  Therefore, when the average value AVE is equal to or greater than the reference value T1 (YES in step S7), the determination circuit 24 increases the gain parameter G1 as indicated by the broken line arrow in FIG. 4A (step S8). The follow-up characteristic of the CDR circuit 2 is increased. As a result, the tracking characteristic of the CDR circuit 2 approaches an appropriate value with respect to the jitter amount of the reception data D1, so that the phase difference amount (average value AVE) between the reception data D1 and the extracted clock CLK becomes small. As described above, when the average value AVE is equal to or greater than the reference value T1, the determination circuit 24 changes the gain parameter G1 so that the average value AVE becomes small. Thereafter, the arithmetic circuit 21 and the counter 21a are reset (step S9), and the process returns to step S3.

  Then, steps S3 to S6 are executed again, and the phase difference amount (phase difference) between the received data D1 and the extracted clock CLK generated according to the tracking characteristic of the CDR circuit 2 determined by the gain parameter G1 changed in step S8. An average value AVE of information D2) is calculated. Subsequently, it is determined whether or not the calculated average value AVE is greater than or equal to the reference value T1 (step S7). That is, it is determined whether or not the relationship between the gain parameter G1 changed in step S8 and the jitter amount of the received data D1 is appropriate. At this time, if the average value AVE is equal to or greater than the reference value T1, the determination circuit 24 determines that the relationship between the two is not appropriate because the amount of jitter of the received data D1 with respect to the current gain parameter G1 is large. Therefore, the determination circuit 24 further increases the gain parameter G1 as indicated by the broken line arrow in FIG. 4A so that the average value AVE of the phase difference information D2 becomes small (step S8).

  Thereafter, the processes in steps S3 to S9 are repeatedly executed until the average value AVE of the phase difference amount becomes less than the reference value T1 in step S7. That is, the process of calculating the average value AVE of the phase difference amount (steps S3 to S6), comparing the average value AVE with the reference value T1 (step S7), and increasing the gain parameter G1 (steps S8 and S9) is repeatedly executed. Is done. Through such a series of processing, the gain parameter G1 is changed so as to gradually increase, and the tracking characteristic of the CDR circuit 2 gradually approaches an appropriate value for the jitter amount of the received data D1, and the average value of the phase difference amount AVE gradually decreases.

  When the average value AVE is smaller than the reference value T1 (NO in step S7), the determination circuit 24 determines that the relationship between the current gain parameter G1 and the jitter amount of the received data D1 is appropriate, and the gain parameter The process ends without changing G1. That is, at this time, an appropriate gain parameter G1 corresponding to the jitter amount of the reception data D1 is set, and an appropriate tracking characteristic of the CDR circuit 2 is set for the jitter amount of the reception data D1. For example, as shown in FIG. 4B, the gain parameter G1 is set higher as the jitter amount of the received data D1 increases. When the gain parameter G1 is set according to the jitter amount of the reception data D1 in this way, as shown in FIG. 4C, the average value AVE of the phase difference amount is always set regardless of the jitter amount of the reception data D1. It becomes smaller than the reference value T1 (see hatching).

According to this embodiment described above, the following effects can be obtained.
(1) In the case of the conventional CDR circuit, as shown in FIG. 4D, the response sensitivity (gain) is associated with the phase difference amount between the reception data D1 and the extracted clock CLK on a one-to-one basis. Yes. That is, as shown in FIGS. 4E and 4F, the gain of the conventional CDR circuit is set according to only the phase difference amount regardless of the jitter amount of the received data. For this reason, as shown in FIG. 4 (e), even if the jitter amount of the received data is the same (see the broken line), the gain also varies if the phase difference amount varies. In such a conventional CDR circuit, when the amount of jitter of received data is small (see the broken line arrow in FIG. 4 (f)), the phase difference amount is large due to the fact that the gain is set high. Even in the case of (see the one-dot chain line arrow), the gain is set higher according to the phase difference amount (see the thick arrow). Then, there is a problem that the relationship between the jitter amount and gain of the received data gets worse and the phase difference amount further increases. This problem similarly occurs even if the gain and the phase difference amount have a non-linear relationship as indicated by a broken line in FIG.

  On the other hand, in the gain setting unit 3 of the present embodiment, the gain parameter G1 of the filter circuit 11 in the CDR circuit 2 is set according to the jitter amount of the reception data D1. Thereby, the gain parameter G1 suitable for the jitter amount of the reception data D1 can be set. As a result, it is possible to set the tracking characteristic of the CDR circuit 2 suitable for the jitter amount of the received data D1. Accordingly, the reception data D1 can be normally received regardless of the jitter amount, and the reception characteristics (jitter tolerance) can be improved.

  Further, according to the above configuration, the gain parameter G1 is set low despite the large amount of jitter as in the conventional CDR circuit, or the gain parameter G1 is set high despite the small amount of jitter. Is suppressed. Therefore, the occurrence of any problem that occurs in the above-described conventional CDR circuit can be suppressed.

  (2) The phase difference amount between the received data D1 and the extracted clock CLK is monitored as a jitter amount, and the gain parameter G1 of the filter circuit 11 is set according to the phase difference amount. According to this, the gain parameter G1 can be set based on the phase difference information D2 generated by the phase comparison circuit included in the conventional CDR circuit. Therefore, an increase in the circuit scale for monitoring the jitter amount can be suppressed.

  (3) The phase difference amount between the received data D1 and the extracted clock CLK is monitored as a jitter amount, and the gain parameter G1 is changed so that the phase difference amount becomes small based on the initial value of the gain parameter G1. Here, if the relationship between the jitter amount of the received data D1 and the gain parameter G1 (following characteristic of the CDR circuit 2) is appropriate, the phase difference amount becomes small. For this reason, if the gain parameter G1 is changed so as to reduce the phase difference amount, the gain parameter G1 is naturally set to an appropriate value with respect to the jitter amount. Therefore, according to this configuration, the gain parameter G1 can be appropriately set with a simple control configuration.

  (4) By setting the initial value of the gain parameter G1 to be low so that the tracking characteristic of the CDR circuit 2 becomes small, the phase difference information D2 changes in proportion to the jitter amount of the reception data D1. Thereby, the phase difference information D2 can be monitored as the jitter amount of the reception data D1.

  (5) The average value AVE of the phase difference information D2 is calculated, and the average value AVE is compared with the reference value T1. Thereby, compared with the case where phase difference information D2 and reference value T1 are compared, the accuracy of change control of gain parameter G1 can be improved. That is, when the phase difference information D2 and the reference value T1 are directly compared, the gain parameter G1 is changed even when the phase difference information D2 is larger than the reference value T1. Such a problem can be avoided when the average value AVE is calculated.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. In the receiving apparatus of this embodiment, the internal configuration of the gain setting unit 3a is different from that of the first embodiment. Hereinafter, the difference from the first embodiment will be mainly described. In addition, the same code | symbol is attached | subjected and shown to the member similar to the member shown to previous FIGS. 1-4, and detailed description about each of these elements is abbreviate | omitted.

  The gain setting unit 3a determines the magnitude of the jitter amount of the reception data D1 with respect to the gain parameter G1 by monitoring the phase difference amount between the reception data D1 and the extracted clock CLK, and the gain parameter G1 corresponding to the jitter amount. Set. Further, when the jitter amount of the received data D1 varies depending on the operating state of the apparatus, the gain setting unit 3a sets a gain parameter G1 corresponding to the varied jitter amount. Specifically, when the phase difference amount is equal to or greater than the reference value T1, the gain setting unit 3a sets the gain parameter so that the phase difference amount becomes small based on the change in the phase difference amount before and after the change of the gain parameter G1. Change G1.

  As shown in FIG. 5, the gain setting unit 3a includes an arithmetic circuit 21, a comparison number register 22, a reference value register 23, a first determination circuit 25, a current register 26, a pre-register 27, a second register A determination circuit 28 and a selector 29 are included.

The arithmetic circuit 21 calculates the average value AVE of the phase difference information D2 and outputs the average value AVE to the first determination circuit 25 and the current register 26.
The first determination circuit 25 sets the gain parameter G1a based on the comparison result obtained by comparing the average value AVE of the phase difference information D2 and the reference value T1 from the reference value register 23, and selects the gain parameter G1a from the selector. 29. Specifically, the first determination circuit 25 changes the gain parameter G1a when the average value AVE is greater than or equal to the reference value T1, while changing the gain parameter G1a when the average value AVE is less than the reference value T1. do not do. The first determination circuit 25 outputs a determination signal JS indicating whether or not the average value AVE is equal to or greater than the reference value T1 to the second determination circuit 28. The initial value of the gain parameter G1a is set to an arbitrary value (for example, the center value of the setting range).

  The current register 26 is a register that holds the average value AVE of the latest phase difference information D2. Each time the average value AVE is calculated in the arithmetic circuit 21, the calculated average value AVE is written into the current register 26. The current register 26 outputs the last average value AVE held as the current average value AVE1 to the pre-register 27 and the second determination circuit 28.

  The pre-register 27 is a register that holds the average value AVE of the previous phase difference information D2. Each time the average value AVE is calculated in the arithmetic circuit 21, the current average value AVE1 output from the current register 26 is written in the pre-register 27. The pre-register 27 outputs the held average value AVE1 (the previous average value AVE) to the second determination circuit 28 as the pre-average value AVE2.

  The second determination circuit 28 sets the gain parameter G1b based on the determination signal JS from the first determination circuit 25, the current average value AVE1, the pre-average value AVE2, and the previous control information of the gain parameter G1. Then, the second determination circuit 28 outputs the set gain parameter G1b to the selector 29. The second determination circuit 28 includes a register 28a that holds previous control information indicating how the gain parameter G1 (gain parameters G1a, G1b) was changed and controlled last time.

  The second determination circuit 28 sets the gain parameter G1b according to the jitter amount of the reception data D1 that varies from time to time so as to be suitable for the jitter amount. Specifically, the second determination circuit 28 does not change the gain parameter G1b when the gain parameter G1 is appropriately set with respect to the jitter amount of the reception data D1. Specifically, the second determination circuit 28 does not change the gain parameter G1b when the determination signal JS indicating that the average value AVE (current average value AVE1) is less than the reference value T1 is input.

  On the other hand, when the gain parameter G1 is not appropriately set with respect to the jitter amount of the reception data D1, the second determination circuit 28 determines the phase difference information according to the phase difference information D2 (jitter amount). The gain parameter G1b is changed so that D2 becomes small. Specifically, when the determination signal JS indicating that the average value AVE is equal to or greater than the reference value T1 is input, the second determination circuit 28, as shown in FIG. 6, and the current average value AVE1 and the pre-average The gain parameter G1b is increased or decreased based on the comparison result with the value AVE2 and the previous control information of the gain parameter G1. In the following description, control for increasing the gain parameter G1 (gain parameter G1a or G1b) is UP change, and control for decreasing the gain parameter G1 is DOWN change.

  The selector 29 shown in FIG. 5 selects either the gain parameter G1a from the first determination circuit 25 or the gain parameter G1b from the second determination circuit 28, and uses the selected parameter as the gain parameter G1 to the filter circuit 11. Output. Specifically, the selector 29 selects the gain parameter G1a in the first change control after the start of communication, and selects the gain parameter G1b in the second and subsequent change control after the communication starts. For this reason, the gain parameter G1a is used only for the first change control of the gain parameter G1 after the start of communication. Then, the gain parameter G1b is used for the change control of the gain parameter G1 for the second and subsequent times after the start of communication.

Next, a method for setting the gain parameter G1 (tracking characteristics of the CDR circuit 2) in the receiving apparatus configured as described above will be described with reference to FIGS.
First, processes similar to steps S1 to S6 of the first embodiment are executed from step S11 to S16 shown in FIG. As a result, the average value AVE of the phase difference information D2 at the first time after the start of communication is calculated by the arithmetic circuit 21 (step S16).

  Next, the average value AVE calculated in step S16 is written in the current register 26 (step S17). Subsequently, in the first determination circuit 25, it is determined whether or not the average value AVE calculated in step S16 is greater than or equal to the reference value T1 (step S18). At this time, if the average value AVE is equal to or greater than the reference value T1, the initial value of the gain parameter G1a is not appropriate for the jitter amount, and therefore the first determination circuit 25 performs fixed change control with respect to the gain parameter G1a. Here, the UP change is executed (step S19). In the first change control of the gain parameter G1 after the start of communication, the gain parameter G1a is used, so that the gain parameter G1 is changed by changing the gain parameter G1a. Thereafter, the process proceeds to step S20 shown in FIG.

  On the other hand, when the average value AVE calculated in step S16 is less than the reference value T1 (NO in step S18), since the initial value of the gain parameter G1a is an appropriate value for the jitter amount, the gain parameter G1a The process proceeds to step S20 without changing. Information indicating how the gain parameter G1a is changed (here, UP changed or not changed) is stored in the register 28a in the second determination circuit 28 as previous control information.

  Next, in step S20 shown in FIG. 8, the arithmetic circuit 21 and the counter 21a are once reset. Subsequently, processes similar to steps S13 to S16 are executed from step S21 to S24. Accordingly, the arithmetic circuit 21 calculates the average value AVE of the phase difference information D2 for the second and subsequent times after the start of communication (step S24).

  Then, the current average value AVE1 held in the current register 26 is written into the pre-register 27 (step S25). That is, the previous average value AVE, here, the average value AVE of the phase difference information D2 at the first time after the start of communication is written in the pre-register 27. Subsequently, the latest average value AVE calculated in step S24, here, the average value AVE of the phase difference information D2 at the second time after the start of communication is written in the current register 26.

  Next, it is determined whether or not to change the gain parameter G1, here the gain parameter G1b (step S27). Specifically, when the first determination circuit 25 determines that the average value AVE is less than the reference value T1, the current gain parameter G1 is an appropriate value with respect to the jitter amount. The process returns to step S20 without changing the parameters G1 and G1b.

  On the other hand, when the first determination circuit 25 determines that the average value AVE calculated in step S24 is equal to or greater than the reference value T1, the second determination circuit 28 changes the gain parameter G1b according to FIG. (Step S28). That is, in this case, the second determination circuit 28 sets the gain parameter G1b so that the average value AVE is reduced based on the previous control information of the gain parameter G1 and the comparison result between the current average value AVE1 and the pre-average value AVE2. To change. It should be noted that since the gain parameter G1b is used in the gain parameter G1 change control for the second and subsequent times after the start of communication, the gain parameter G1 is changed by changing the gain parameter G1b. For this reason, in the following description, for convenience of explanation, it will be described that the second determination circuit 28 changes the gain parameter G1.

Here, the change control of the gain parameter G1 in the second determination circuit 28 will be described in detail with reference to FIG.
First, a case where the previous control of the gain parameter G1 (for example, the change control in step S19 shown in FIG. 7) is UP change will be described. When the current average value AVE1 that is the phase difference amount after the UP change is larger than the pre-average value AVE2 that is the phase difference amount before the UP change, the second determination circuit 28 at this time changes the UP change. Thus, it is determined that the follow-up characteristic of the CDR circuit 2 has changed in the direction of deterioration. Here, “changes in the direction in which the follow-up characteristic deteriorates” means that the value of the gain parameter G1 subjected to the change control moves away from an appropriate value for the jitter amount of the reception data D1. Therefore, the second determination circuit 28 in this case changes the gain parameter G1 so that the phase difference amount becomes small. Specifically, the second determination circuit 28 executes a DOWN change in the direction opposite to the previous UP change with respect to the gain parameter G1. More specifically, the gain parameter G1 before the UP change is the first gain, and the second gain having a difference in the UP direction (first direction) with respect to the first gain is the gain parameter G1 after the UP change. Then, the second determination circuit 28 changes the second gain to a gain having a difference in the DOWN direction (second direction) with respect to the first gain. In other words, the second determination circuit 28 in this case executes the DOWN change for the gain parameter G1 so as to be lower than the gain parameter G1 before the previous UP change. By such change control, the follow-up characteristic of the CDR circuit 2 changes in a direction to improve, and the average value AVE of the phase difference information D2 becomes small. Note that “changes in the direction in which the follow-up characteristic is improved” means that the value of the gain parameter G1 subjected to the change control approaches an appropriate value for the jitter amount of the reception data D1.

  On the other hand, when the current average value AVE1 that is the phase difference amount after the UP change is smaller than the pre-average value AVE2 that is the phase difference amount before the UP change, the second determination circuit 28 performs the CDR change by the UP change. It is determined that the tracking characteristic of the circuit 2 has changed in the direction of improvement. Therefore, in this case, the second determination circuit 28 performs the same UP change as the previous time on the gain parameter G1 so that the phase difference amount is further reduced. Specifically, if the second determination circuit 28 sets the gain parameter G1 before and after the UP change as the first gain and the second gain, respectively, the second determination circuit 28 The gain is changed to a gain having a difference in the UP direction (first direction) with respect to the second gain. In other words, the second determination circuit 28 in this case executes the UP change for the gain parameter G1 so as to be higher than the gain parameter G1 after the previous UP change. By such change control, the follow-up characteristic of the CDR circuit 2 changes in a further improving direction, and the average value AVE of the phase difference information D2 is further reduced.

  Similarly, when the previous control of the gain parameter G1 is a DOWN change and the current average value AVE1 becomes larger than the pre-average value AVE2, the second determination circuit 28 changes the DOWN with respect to the gain parameter G1. Execute UP change in the opposite direction. The second determination circuit 28 further changes the gain parameter G1 DOWN when the previous control of the gain parameter G1 is a DOWN change and the current average value AVE1 becomes smaller than the pre-average value AVE2.

  As described above, when the average value of the phase difference information D2 becomes large before and after the change of the gain parameter G1 (AVE2 <AVE1), the second determination circuit 28 has a direction opposite to the previous time with respect to the gain parameter G1. Change control (UP → DOWN or DOWN → UP) is executed. Specifically, when the previous control is an UP change, the second determination circuit 28 in this case executes the DOWN change so that the gain parameter G1 becomes lower than the previous gain change, and the previous control is DOWN. If it is a change, the UP change is executed so as to be higher than the gain parameter G1 before the DOWN change. On the other hand, when the average value of the phase difference information D2 becomes small before and after the change of the gain parameter G1 (AVE2> AVE1), the second determination circuit 28 performs change control in the same direction as the previous time with respect to the gain parameter G1. (UP → UP or DOWN → DOWN) is executed. With these change controls, the gain parameter G1 (tracking characteristic of the CDR circuit 2) approaches an appropriate value for the jitter amount of the reception data D1, and the average value AVE of the phase difference information D2 becomes small. Such change control of the gain parameter G1 is repeatedly executed until the average value AVE of the phase difference information D2 becomes less than the reference value T1 (steps S20 to S28).

  Next, a case where the gain parameter G1 has not been changed last time, that is, a case where the pre-average value AVE2 that is the previous phase difference amount is less than the reference value T1 will be described. At this time, the second determination circuit 28 determines that the jitter amount of the reception data D1 has changed when the current average value AVE1 becomes larger than the pre-average value AVE2 less than the reference value T1. That is, it is determined that the tracking characteristic of the CDR circuit 2 has changed in a direction that deteriorates due to a variation in the jitter amount of the received data D1. However, in this case, it is impossible to know how the jitter amount of the received data D1 has changed (whether it has increased or decreased). Therefore, the second determination circuit 28 in this case executes fixed change control (UP change or DOWN change) set in advance for the gain parameter G1. If the tracking characteristic of the CDR circuit 2 changes due to this change control, the change control in the opposite direction to the gain parameter G1 is executed in the next change control, whereby the tracking of the CDR circuit 2 is performed. Control can be performed so that the characteristics change in a direction of improvement. As a result, the average value AVE of the phase difference information D2 can be reduced.

  Subsequently, a case where the pre-average value AVE2 and the current average value AVE1 are equal will be described. The second determination circuit 28 at this time performs fixed change control (UP change, DOWN change, or the same change control as the previous time) set in advance for the gain parameter G1, regardless of the previous change control of the gain parameter G1. Run. That is, when the pre-average value AVE2 and the current average value AVE1 are equal, it is unclear whether the previous change control was appropriate, so the second determination circuit 28 performs fixed change control on the gain parameter G1. Run. Even when the follow-up characteristic of the CDR circuit 2 is deteriorated by this change control, the follow-up of the CDR circuit 2 is performed by executing the change control in the opposite direction to the gain parameter G1 in the next change control. Control can be performed so that the characteristics change in a direction of improvement. As a result, the average value AVE of the phase difference information D2 can be reduced.

  As described above, in step S28, the gain parameter G1 is increased or decreased so that the average value AVE of the phase difference information D2 becomes smaller. Then, it returns to step S20 and steps S20-S28 are repeatedly performed until communication is complete | finished. When the average value AVE of the phase difference information D2 becomes smaller than the reference value T1 by such a series of processing, the jitter amount of the CDR circuit 2 appropriate to the jitter amount of the reception data D1 at that time Is set.

According to the embodiment described above, in addition to the effects (1), (2), and (5) of the first embodiment, the following effects can be obtained.
(6) The phase difference amount between the received data D1 and the extracted clock CLK is monitored as a jitter amount, and the gain parameter G1 is increased or decreased so that the phase difference amount becomes smaller based on the change in the phase difference amount before and after the gain parameter G1 is changed. I tried to do it. Thereby, even if the jitter amount varies (increases / decreases) depending on the operation state of the apparatus, the gain parameter G1 can be increased / decreased in accordance with the variation of the jitter amount. Therefore, the gain parameter G1 suitable for the jitter amount that varies from time to time can be set, and the tracking characteristic of the CDR circuit 2 suitable for the jitter amount can be set.

(Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIG. The same members as those shown in FIGS. 1 to 8 are given the same reference numerals, and detailed descriptions of these elements are omitted.

As shown in FIG. 9, the receiving device includes a receiver circuit 1, a plurality (n in this example) of CDR circuits C2i (i = 1, 2,..., N), and a gain setting unit 3b.
Each of the plurality of CDR circuits C2i includes a phase comparison circuit 10i, a filter circuit 11i, and a phase correction control circuit 12i, similarly to the CDR circuit 2 of the first embodiment. Different fixed gain parameters G1i are set in the filter circuits 11i in the CDR circuits C2i. Therefore, each of these CDR circuits C2i generates clock signals CLKi having different phases based on the received data D1 from the receiver circuit 1. Specifically, the first CDR circuit C21 generates the clock signal CLK1 according to the tracking characteristic determined by the gain parameter G11, and the second CDR circuit C22 generates the clock signal CLK2 according to the tracking characteristic determined by the gain parameter G12. These clock signals CLKi are supplied to the selector 52 in the gain setting unit 3b.

  Further, since the phases of the clock signals CLKi generated by the phase correction control circuits 12i are different from each other, each of the phase comparison circuits 10i generates phase difference information D2i indicating different phase differences. Specifically, the phase comparison circuit 101 in the first CDR circuit C21 generates phase difference information D21 indicating the phase difference between the reception data D1 and the clock signal CLK1. In addition, the phase comparison circuit 102 in the second CDR circuit C22 generates phase difference information D22 indicating the phase difference between the reception data D1 and the clock signal CLK2. The phase difference information D2i is supplied to the arithmetic circuit 21i in the gain setting unit 3b.

  Based on the phase difference information D2i from the plurality of CDR circuits C2i, the gain setting unit 3b selects the CDR circuit C2i having the smallest phase difference amount, and extracts the clock signal CLKi generated by the selected CDR circuit C2i. Output as CLK. The extracted clock CLK is supplied to the D-FF circuit 4 and the logic unit 5 shown in FIG.

The gain setting unit 3b includes n arithmetic circuits 21i corresponding to the CDR circuits C2i, a comparison number register 22, a determination circuit 51, and a selector 52.
Each arithmetic circuit 21 i receives the phase difference information D 2 i from the phase comparison circuit 10 i in the corresponding CDR circuit C 2 i and the set number M from the comparison number register 22. Similar to the arithmetic circuit 21, these arithmetic circuits 21 i calculate average values AEi of the phase difference information D 2 i for M times (for example, ten times), respectively, and output the average value AEi to the determination circuit 51. . Specifically, the arithmetic circuit 211 calculates an average value AE1 for the set number M times of the phase difference information D21 from the phase comparison circuit 101 in the first CDR circuit C21. Further, the arithmetic circuit 212 calculates an average value AE2 for the set number of times of the phase difference information D22 from the phase comparison circuit 102 in the second CDR circuit C22. The average values AE1 and AE2 are supplied to the determination circuit 51.

  The determination circuit 51 determines the average value AEi having the smallest phase difference amount by comparing a plurality of average values AEi input from the respective arithmetic circuits 21i. Based on the determination result, the determination circuit 51 generates a selection signal S1 for selecting the CDR circuit C2i corresponding to the arithmetic circuit 21i that generated the average value AEi having the smallest phase difference amount, and selects the selection signal S1. The signal S1 is output to the selector 52. The selector 52 selects any one of the clock signals CLKi from the CDR circuit C2i according to the selection signal S1, and outputs the selected clock CLK.

  Specifically, when the determination circuit 51 determines that the average value AE1 has the smallest amount of phase difference among the average values AE1 to AEn, the selector 52 selects the first CDR circuit C21. A selection signal S1 is supplied. In response to the selection signal S1, the selector 52 selects the clock signal CLK1 generated by the first CDR circuit C21 from the clock signals CLK1 to CLKn, and outputs the clock signal CLK1 as the extracted clock CLK. As a result, the clock signal CLK1 generated by the first CDR circuit C21 having the gain parameter G11 having the smallest phase difference amount can be output as the extracted clock CLK. That is, the clock signal CLK1 generated according to the tracking characteristic determined by the gain parameter G11 most suitable for the jitter amount of the received data D1 at that time can be output as the extracted clock CLK.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) and (5) of the first embodiment.
(7) The clock signal CLKi generated by the CDR circuit C2i having the smallest average value AEi (phase difference amount) is output as the extracted clock CLK. Here, the smallest phase difference amount means that the relationship between the jitter amount of the received data D1 at that time and the gain parameter G1i (following characteristic of the CDR circuit C2i) is most appropriate. For this reason, according to the above configuration, even if the jitter amount fluctuates (increases / decreases) depending on the operating state of the apparatus, the extracted clock CLK is output by the CDR circuit having the gain parameter G1i most suitable for the jitter amount at that time It can be changed to the generated clock signal CLKi. Since this change (update) is executed every set number of times M, it is possible to always generate the optimum extraction clock CLK.

  Furthermore, the gain parameter G1i and the follow-up characteristics of the CDR circuit C2i can be changed only by selecting the CDR circuit C2i having the smallest average value AEi. For this reason, when the jitter amount of the reception data D1 varies, the optimum gain parameter G1i and the tracking characteristic of the CDR circuit C2i can be quickly set for the jitter amount after the variation.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description of these elements is omitted.

As illustrated in FIG. 10, the reception device includes a receiver circuit 1, a CDR circuit 2, a D-FF circuit 4, a logic unit 5, a jitter measurement circuit 6, and a timer 7.
The reception data D1 output from the receiver circuit 1 is supplied to the CDR circuit 2, the D-FF circuit 4, and the jitter measurement circuit 6. A predetermined measurement period Ta is also input from the timer 7 to the jitter measurement circuit 6.

  The jitter measuring circuit 6 measures the jitter amount of the received data D1, and sets the gain parameter G1 of the filter circuit 11 in the CDR circuit 2 according to the jitter amount. Specifically, the jitter measurement circuit 6 measures the maximum amount of jitter in the measurement period Ta, and sets the gain parameter G1 so as to have an appropriate tracking characteristic for the maximum amount of jitter.

Next, an example of the internal configuration of the jitter measurement circuit 6 will be described with reference to FIG.
The jitter measuring circuit 6 is connected to a CDR circuit 61, a plurality of (here, m) D-FF circuits Aj (j = 1, 2,..., M), and a plurality of stages (here, m−1 stages) in series. Buffer circuit Bk (k = 2, 3,..., M). The jitter measuring circuit 6 includes m-1 exclusive OR (EOR) circuits Cxy (x = 1, 2,..., M−1, y = 2, 3,..., M), and m−1. Each D-FF circuit Exy, a maximum jitter amount determination circuit 62, a maximum jitter amount storage circuit 63, and a conversion table 64 are included.

  Although not shown, the CDR circuit 61 includes a phase comparison circuit, a filter circuit in which a fixed gain parameter is set, and a phase correction control circuit. The CDR circuit 61 generates two clock signals CK1 and CK21 having different phases based on the reception data D1 from the receiver circuit 1. Specifically, as shown in FIG. 12, the CDR circuit 61 has an edge (rising edge in this example) at the center position of the reception data D1 so that the setup time and the hold time can be secured for the reception data D1. An incoming clock signal CK1 is generated. Further, as shown in FIG. 12, the CDR circuit 61 generates a clock signal CK21 having a rising edge at the data transition point of the reception data D1. Thus, the CDR circuit 61 generates the clock signals CK1 and CK21 whose phases are shifted from each other by approximately 180 degrees. Then, as shown in FIG. 11, the CDR circuit 61 outputs the clock signal CK1 to the clock terminal of the D-FF circuit Exy and at the same time outputs the clock signal CK21 as the clock signal CK2j to the clock terminal and buffer circuit of the D-FF circuit A1. Output to the first buffer circuit B2 of Bk.

The buffer circuit B2 generates a clock signal CK22 obtained by delaying the clock signal CK21 by a predetermined time, and outputs the clock signal CK22 to the clock terminal of the D-FF circuit A2 and the buffer circuit B3 at the next stage. The subsequent buffer circuit Bk generates a clock signal CK2j obtained by delaying the clock signal CK2 (j-1) input from the preceding buffer circuit B (k-1) by a predetermined time, and the clock signal CK2j is D-FF. The data is output to the clock terminal of the circuit Aj and the buffer circuit B (k + 1) at the next stage. Then, the last stage buffer circuit Bm generates a clock signal CK2m obtained by delaying the clock signal CK2 (m-1) input from the preceding stage buffer circuit B (m-1) by a predetermined time, and the clock signal CK2m is generated. Output to the clock terminal of the D-FF circuit Am. As described above, the CDR circuit 61 and the plurality of buffer circuits Bk generate the m-stage clock signal CK2j whose phase is delayed by a predetermined time. These clock signals CK2j are generated so that the clock signal CK2m generated by the final stage buffer circuit Bm rises earlier than the rising edge of the clock signal CK1 (see FIG. 12).

  Each D-FF circuit Aj receives reception data D1 at its data terminal, and receives a clock signal CK2j at its clock terminal. The D-FF circuit Aj outputs a signal having the level of the reception data D1 input to the data terminal in synchronization with the rising edge of the clock signal CK2j as data D1j. That is, these D-FF circuits Aj sample the received data D1 with the clock signal CK2j whose phase is shifted by a predetermined delay time, and output the sampled data as data D1j. The output terminals of adjacent D-FF circuits Ax, Ay (y = x + 1) in the D-FF circuit Aj are connected to the first and second input terminals of one EOR circuit Cxy, respectively. Therefore, the data D1x and D1y output from the adjacent D-FF circuits Ax and Ay are supplied to one EOR circuit Cxy. In other words, the data D1x sampled with the clock signal CK2x and the data D1y sampled with the clock signal CK2y are supplied to one EOR circuit Cxy. More specifically, data D11 output from the D-FF circuit A1 (sampled by the clock signal CK21) and data D12 output from the D-FF circuit A2 (sampled by the clock signal CK22). It is supplied to the EOR circuit C12. Further, the data D12 output from the D-FF circuit A2 and the data D13 output from the D-FF circuit A3 are supplied to the EOR circuit C23.

  The EOR circuit Cxy compares data D1x and D1y input from adjacent D-FF circuits Ax and Ay. The EOR circuit Cxy outputs the L-level signal CMxy to the data terminal of the D-FF circuit Exy when the values of the data D1x and D1y match, while the values of the data D1x and D1y are different. In this case, the H level signal CMxy is output to the data terminal of the D-FF circuit Exy.

  Each of the D-FF circuits Exy receives the signal CMxy from the EOR circuit Cxy at its data terminal, and receives the clock signal CK1 from the CDR circuit 61 at its clock terminal. The D-FF circuit Exy outputs a signal CMRxy having the level of the signal CMxy input to the data terminal in synchronization with the rising edge of the clock signal CK1 to the maximum jitter amount determination circuit 62.

  Here, when there is a data transition in the reception data D1, the output value of the D-FF circuit Aj changes according to the jitter amount of the reception data D1, that is, the clock signals CK2x and CK2y rise before and after the timing according to the jitter amount. The output value changes between the sampled D-FF circuits Ax and Ay. Therefore, whether or not data transition has occurred between the edges of the clock signal CK2x and the clock signal CK2y is determined by determining whether or not the values of the output data D1x and D1y of the adjacent D-FF circuits Ax and Ay match. Can be determined. Furthermore, it can be determined that the time from the rising edge of the clock signal CK21 to the rising edge of the clock signal CK2y where the data transition occurs corresponds to the jitter amount.

  This point will be described with reference to FIGS. 12 shows the operation of the jitter measurement circuit 6 when the reception data D1 contains no jitter, and FIG. 13 shows the operation of the jitter measurement circuit 6 when the reception data D1 contains jitter. . In the figure, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  Referring to FIG. 13, when reception data D1 includes jitter, reception data D1 transitions from (N−1) to (N) between edges of clock signal CK22 and clock signal CK23. explain.

  In this case, as shown in FIG. 13, the clock signals CK21 and CK22 rise before time t2, which is the actual data transition point of the received data D1, and the clock signals CK23 to CK2m rise after time t2. Therefore, the D-FF circuit A1 outputs data D11 having the level (N-1) of the reception data D1 at that time to the EOR circuit C12 in synchronization with the rising edge of the clock signal CK21. The D-FF circuit A2 outputs data D12 having the level (N-1) of the received data D1 at that time to the EOR circuits C12 and C23 in synchronization with the rising edge of the clock signal CK22. On the other hand, the D-FF circuit A3 outputs data D13 having the level (N) of the reception data D1 at that time to the EOR circuits C23 and C34 in synchronization with the rising edge of the clock signal CK23.

  Therefore, the EOR circuit C12 receives the L-level signal CM12 from the D-FF circuit E12 because the values of the input data D11 and D12 match after the data D12 of level (N-1) is input. Output to.

  On the other hand, after the data D13 having the level (N) is input to the EOR circuit C23, the data D12 having the level (N-1) and the data D13 having the level (N) are input. For this reason, the EOR circuit C23 outputs an H-level signal CM23 to the D-FF circuit E23 because the values of the input data D12 and D13 do not match. The H level signal CM23 is output to the vicinity of the next data transition point where the levels of the data D12 and D13 change. The EOR circuit Cxy subsequent to the EOR circuit C23 has the L level signal CMxy because the data D1x and D1y input after the data (D1y) having the level (N) coincide with each other. Is output to the D-FF circuit Exy.

  Subsequently, in the D-FF circuit Exy, only the D-FF circuit E23 to which the H-level signal CM23 is input to the data terminal outputs the H-level signal CMR23 in synchronization with the rising edge of the clock signal CK1. The D-FF circuit Exy other than the D-FF circuit E23 outputs the L level signal CMRxy in synchronization with the rising edge because the L level signal CMxy is input at the rising edge of the clock signal CK1. .

  When there is a data transition of the received data D1 between the edges of the clock signal CK22 and the clock signal CK23 as in this example, the output data of the D-FF circuits A2 and A3 sampled by the clock signals CK22 and CK23. The values of D12 and D13 are different. In other words, when the values of the output data D12 and D13 of the adjacent D-FF circuits A2 and A3 are different, it is determined that the data transition of the reception data D1 has occurred between the edges of the corresponding clock signals CK22 and CK23. it can. On the other hand, when the values of the data D1x and D1y output from the adjacent D-FF circuits Ax and Ay match, it is determined that there is no data transition of the received data D1 between the edges of the corresponding clock signals CK2x and CK2y. can do.

  Here, in the D-FF circuit Exy, since the values of the data D1x and D1y output from the adjacent D-FF circuits Ax and Ay are different, the D-FF connected to the EOR circuit Cxy that outputs the H level signal CMxy. An H level signal CMRxy is output only from the FF circuit Exy. Therefore, by detecting the H-level signal CMRxy, it can be determined that the reception data D1 has transitioned between the edges of the clock signal CK2x and the clock signal CK2y. Therefore, in this example, since the H level signal CMR23 is detected, it can be determined that the reception data D1 has transitioned between the edges of the clock signal CK22 and the clock signal CK23. Further, when there is a data transition in the reception data D1 as described above, an output value is obtained between the D-FF circuits A2 and A3 sampled by the clock signals CK22 and CK23 that rise before and after the timing according to the jitter amount of the reception data D1. Changes. Therefore, in this example, it can be determined that the time from the rising edge of the clock signal CK21 to the rising edge of the clock signal CK23 is substantially equivalent to the jitter amount.

  Note that when the received data D1 does not include jitter (see FIG. 12), the timing of the actual data transition point of the received data D1 and the rising edge of the clock signal CK21 substantially coincide with each other, so that all the EOR circuits The values of both data D1x and D1y input to Cxy match. Alternatively, only the values of the data D11 and D12 input to the first-stage EOR circuit C12 are different. Therefore, in this case, the L-level signal CMRxy is output from all the D-FF circuits Exy, or the H-level signal CMR12 is output only from the first-stage D-FF circuit E12.

  The maximum jitter amount determination circuit (determination circuit) 62 shown in FIG. 11 includes the maximum jitter amount stored in the maximum jitter amount storage circuit (storage circuit) 63 together with the signal CMRxy output from each D-FF circuit Exy. Quantity is supplied. The determination circuit 62 detects a signal at H level among the plurality of signals CMRxy, and determines the jitter amount based on the signal. Specifically, when the signal CMR23 input from the EOR circuit C23 is at the H level as described above, the determination circuit 62 determines the time from the rising edge of the clock signal CK21 to the rising edge of the clock signal CK23 as the jitter amount. . Then, the determination circuit 62 compares the jitter amount determined from the H-level signal CMRxy with the maximum jitter amount from the storage circuit 63, and if the former is larger than the latter, the former jitter amount is set as a new maximum jitter. The quantity is output to the storage circuit 63.

  Each time the measurement period Ta supplied from the timer 7 shown in FIG. 10 elapses, the storage circuit 63 outputs the maximum jitter amount stored at that time to the conversion table 64 and stores the stored information (maximum Reset the jitter amount.

  If the measurement period Ta is from time t1 to t4 in FIG. 13, the jitter amount determined by the H level signal CMR23 is first stored in the storage circuit 63 as the maximum jitter amount at time t2 to t3. Thereafter, at time t3 to t4, the data transition of the reception data D1 occurs between the edges of the clock signal CK23 and the clock signal CK24 (time t3), so that the output data D13 and D14 of the adjacent D-FF circuits A3 and A4 The value will be different. Then, the H level signal CM34 is output from the EOR circuit C34, and the H level signal CMR34 is output from the D-FF circuit E34 in synchronization with the rising edge of the first clock signal CK1. In this case, the determination circuit 62 determines the time from the rising edge of the clock signal CK21 to the rising edge of the clock signal CK24 as the jitter amount based on the H-level signal CMR34. Further, the determination circuit 62 determines that the jitter amount based on the H level signal CMR 34 is larger than the maximum jitter amount (jitter amount based on the H level signal CMR 23) input from the storage circuit 63, and determines the jitter amount. The new maximum jitter amount is output to the storage circuit 63. For this reason, the storage circuit 63 of this example outputs the jitter amount based on the H level signal CMR 34 to the conversion table 64 as the maximum jitter amount.

  The conversion table 64 shown in FIG. 11 converts the maximum jitter amount output from the storage circuit 63 into the gain parameter G1, and outputs the gain parameter G1 to the filter circuit 11 in the CDR circuit 2 shown in FIG. Specifically, the conversion table 64 stores a table in which the jitter amount of the reception data D1 is associated with the gain parameter G1. For example, as shown in FIG. 4B, the conversion table 64 stores a table in which the gain parameter G1 increases as the jitter amount of the reception data D1 increases. Thereby, the gain parameter G1 can be changed (updated) in accordance with the jitter amount of the reception data D1 that varies from time to time.

Next, a method for setting the gain parameter G1 (tracking characteristics of the CDR circuit 2) in the receiving apparatus configured as described above will be described with reference to FIG.
First, before starting communication, the gain parameter G1, the jitter measurement circuit 6, and the timer 7 are initialized (step S31). Then, it waits until communication is started (step S32). When communication is started (YES in step S32), a count operation of a timer for counting the measurement period Ta is started (step S33).

  Subsequently, the jitter measurement circuit 6 starts measuring the jitter amount of the received data D1 (step S34). Next, it is determined whether or not the measurement period Ta has elapsed (step S35), and the measurement of the maximum jitter amount of the reception data D1 is continued until the measurement period Ta has elapsed (steps S34 and S35). On the other hand, when the measurement period Ta elapses (YES in step S35), the gain parameter G1 corresponding to the maximum jitter amount in the measurement period Ta is set (step S36). That is, in the conversion table 64, the maximum jitter amount output from the storage circuit 63 is converted into the gain parameter G1. The gain parameter G1 is set in the filter circuit 11. Thereby, the gain parameter G1 suitable for the jitter amount of the reception data D1 can be set. As a result, it is possible to set the tracking characteristic of the CDR circuit 2 suitable for the jitter amount of the received data D1.

  Next, the jitter measurement circuit 6 and the timer 7 are reset (step S37), and the process returns to step S33. Then, the count operation of the timer 7 is started again (step S33), and the gain parameter G1 corresponding to the maximum jitter amount in the measurement period Ta is set again (steps S34 to S37). Through such a series of processes, the gain parameter G1 is changed for each measurement period Ta according to the jitter amount at that time. As a result, it is possible to always set the optimum tracking characteristic of the CDR circuit 2 with respect to the jitter amount that varies depending on the operation state of the apparatus.

  For example, in a serial interface such as IEEE1394-2008, as shown in FIG. 15, actual data communication is performed at a high speed of 125 Mbps to 4 Gbps. On the other hand, before starting data communication, connection confirmation between devices and communication speed confirmation by transmission / reception of tone signals are performed at a low speed. By performing jitter measurement (steps S3 to S5) by the jitter measurement circuit 6 during such a low-speed communication period, the jitter amount of the received data D1 is measured and the gain parameter G1 (step S6) is set. It can be executed reliably. Since the low-speed communication uses a clock signal of 48 MHz to 64 MHz, the CDR circuit 61 in the jitter measurement circuit 6 in this case is a circuit that generates clock signals CK1 and CK21 of 48 MHz to 64 MHz.

According to the embodiment described above, in addition to the function and effect (1) of the first embodiment, the following effects are obtained.
(8) The jitter amount of the received data D1 is measured based on the received data D1, and the gain parameter G1 corresponding to the measured jitter amount is set. According to this, since the gain parameter G1 is changed according to the jitter amount itself of the reception data D1, the accuracy of the change control of the gain parameter G1 can be improved.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In the first embodiment, the initial value of the gain parameter G1 is set low so that the tracking characteristic of the CDR circuit 2 is small. For example, the initial value of the gain parameter G1 may be set high so that the tracking characteristic of the CDR circuit 2 is increased. In this case, when the average value AVE is greater than or equal to the reference value T1, the determination circuit 24 decreases the gain parameter G1 so that the average value AVE becomes small.

  The initial value of the gain parameter G1a in the second embodiment may be set low so that the tracking characteristic of the CDR circuit 2 is small, or may be set high so that the tracking characteristic of the CDR circuit 2 is large. .

  In the first to third embodiments, the average values AVE and AEi of the phase difference information D2 and D2i generated by the phase comparison circuits 10 and 10i are monitored as the jitter amount of the reception data D1. That is, in the first and second embodiments, the average value AVE of the phase difference information D2 generated by the phase comparison circuit 10 is compared with the reference value T1. For example, the phase difference information D2 generated by the phase comparison circuit 10 may be compared with the reference value T1.

  In the third embodiment, the CDR circuit C2i having the smallest phase difference amount is determined by comparing the average value AEi of the phase difference information D2i generated by the phase comparison circuit 10i. Not limited to this, the CDR circuit C2i with the smallest phase difference amount may be determined by comparing the phase difference information D2i generated by the phase comparison circuit 10i.

  In the change control of the gain parameter G1 in the first and second embodiments, the change width (the rate of increase or decrease) when changing the gain parameter G1 may be changed. For example, the change range of the gain parameter G1 may be changed in accordance with the magnitude of the average value AVE (or phase difference information D2) of the phase difference information D2, specifically the amount of difference from the reference value T1. In the first embodiment, in the determination circuit 24, when the average value AVE is equal to or greater than the reference value T1, the change range when the gain parameter G1 is increased as the difference amount between the average value AVE and the reference value T1 increases. You may make it enlarge. As a result, the gain parameter G1 can be quickly brought close to an appropriate value.

Or you may make it change the change range of the above-mentioned gain parameter G1 according to a communicating party.
In the above embodiments, the reference value T1, the set number M, and the measurement period Ta may be set from the outside of the apparatus.

  The internal configuration of the jitter measurement circuit 6 in the fourth embodiment is not particularly limited to the circuit shown in FIG. As long as the jitter measurement circuit 6 is a circuit that can measure the jitter amount of the received data D1, the same effect as (8) of the fourth embodiment can be obtained.

The internal configuration of the CDR circuits 2 and 2i in the above embodiments is not particularly limited. For example, the filter circuits 11 and 11i may be changed to analog filters.
The data input to the receiver circuit 1 of each of the above embodiments is not limited to differential serial data. For example, single-ended serial data may be input to the receiver circuit 1.

The following notes are disclosed regarding the above embodiments.
(Appendix 1)
A clock data recovery circuit that generates a clock based on received data;
A receiving apparatus comprising: a setting unit configured to set a gain of a filtering process for filtering a phase difference between the received data and the clock in the clock data recovery circuit according to a jitter amount of the received data.
(Appendix 2)
The receiving apparatus according to claim 1, wherein the setting unit monitors the phase difference as the jitter amount and sets a gain of the filtering process.
(Appendix 3)
The receiving apparatus according to claim 1, wherein the setting unit monitors an average value of the phase differences for a predetermined number of times as the jitter amount and sets a gain of the filtering process.
(Appendix 4)
The setting unit changes the gain of the filtering process so that the phase difference is reduced based on an initial setting of the gain of the filtering process when the phase difference is greater than or equal to a reference. 4. The receiving device according to 3.
(Appendix 5)
When the phase difference is greater than or equal to a reference, the setting unit performs the filtering process so that the phase difference is reduced based on a change in the phase difference between the received data and the clock before and after the gain of the filtering process is changed. 4. The receiving apparatus according to appendix 2 or 3, wherein the gain is changed.
(Appendix 6)
The setting unit sets the gain of the filtering process relative to the first gain, rather than the first phase difference between the received data and the clock when the gain of the filtering process is set to the first gain. If the second phase difference between the received data after changing to the second gain having a difference in the first direction and the clock is small, the second gain has a difference in the first direction with respect to the second gain. The receiving apparatus according to appendix 5, wherein a gain of 3 is set as a gain of the filtering process.
(Appendix 7)
The setting unit sets the gain of the filtering process relative to the first gain, rather than the first phase difference between the received data and the clock when the gain of the filtering process is set to the first gain. If the second phase difference between the received data and the clock after changing to the second gain having the difference in the first direction is large, the second gain is set in the second direction opposite to the first direction. The receiving apparatus according to appendix 5 or 6, wherein a fourth gain changed in a direction is set as a gain of the filtering process.
(Appendix 8)
The receiving apparatus according to appendix 7, wherein the fourth gain is a gain having a difference in the second direction with respect to the first gain.
(Appendix 9)
The clock data recovery circuit includes a plurality of clock data recovery circuits having different gains for the filtering process.
The reception according to claim 2 or 3, wherein the setting unit includes a selection circuit that selects a clock generated by the clock data recovery circuit having the smallest phase difference among the plurality of clock data recovery circuits. apparatus.
(Appendix 10)
The appendix 1 includes a jitter measurement circuit that measures a jitter amount of the received data based on the received data and sets a gain of the filter processing according to the measured jitter amount. The receiving device described.
(Appendix 11)
The jitter measurement circuit includes:
A clock data recovery circuit that outputs a first clock and a second clock based on the received data;
A plurality of flip-flop circuits that respectively sample the received data with a plurality of clocks obtained by delaying the second clock by a predetermined time;
A logic circuit that performs an exclusive OR operation on the output values of adjacent flip-flop circuits;
By sampling the output value of the logic circuit with the first clock, the circuit detects the timing at which the output value of the adjacent flip-flop circuit changes, and measures the jitter amount based on the detected timing;
The receiving apparatus according to claim 10, further comprising: a conversion table that converts the measured jitter amount into a gain of the filtering process.
(Appendix 12)
A gain of a filtering process for filtering a phase difference between the received data and the clock in a clock data recovery circuit that generates a clock based on the received data, according to a jitter amount of the received data Setting method.

DESCRIPTION OF SYMBOLS 1 Receiver 2 Clock data recovery circuit C21-C2n Clock data recovery circuit 3, 3a, 3b Gain setting part (setting part)
6 Jitter measurement circuit (setting unit)
11, 111 to 11n Filter circuit 52 Selector (selection circuit)
61 Clock data recovery circuit 62 Maximum jitter amount determination circuit 63 Maximum jitter amount storage circuit 64 Conversion table A1 to Am D-flip flop circuit (flip flop circuit)
C12 to C (m-1) m exclusive OR circuit (logic circuit)
E12 to E (m-1) m D-flip flop circuit CLK extraction clock (clock)
D1 Received data D2 Phase difference information (phase difference)
G1 Gain parameter (gain)

Claims (10)

A clock data recovery circuit that generates a clock based on received data;
A receiving apparatus comprising: a setting unit configured to set a gain of a filtering process for filtering a phase difference between the received data and the clock in the clock data recovery circuit according to a jitter amount of the received data.   The receiving apparatus according to claim 1, wherein the setting unit monitors the phase difference as the jitter amount and sets a gain of the filtering process.   The said setting part changes the gain of the said filter process so that the said phase difference may become small based on the initial setting of the gain of the said filter process, when the said phase difference is more than a reference | standard. The receiving device described in 1.   When the phase difference is greater than or equal to a reference, the setting unit performs the filtering process so that the phase difference is reduced based on a change in the phase difference between the received data and the clock before and after the gain of the filtering process is changed. The receiving apparatus according to claim 2, wherein the gain is changed.   The setting unit sets the gain of the filtering process relative to the first gain, rather than the first phase difference between the received data and the clock when the gain of the filtering process is set to the first gain. If the second phase difference between the received data after changing to the second gain having a difference in the first direction and the clock is small, the second gain has a difference in the first direction with respect to the second gain. The receiving apparatus according to claim 4, wherein a gain of 3 is set as a gain of the filtering process.   The setting unit sets the gain of the filtering process relative to the first gain, rather than the first phase difference between the received data and the clock when the gain of the filtering process is set to the first gain. If the second phase difference between the received data and the clock after changing to the second gain having the difference in the first direction is large, the second gain is set in the second direction opposite to the first direction. The receiving apparatus according to claim 4 or 5, wherein a fourth gain changed in a direction is set as a gain of the filtering process. The clock data recovery circuit includes a plurality of clock data recovery circuits having different gains for the filtering process.
The receiving apparatus according to claim 2, wherein the setting unit includes a selection circuit that selects a clock generated by the clock data recovery circuit having the smallest phase difference among the plurality of clock data recovery circuits. .   The said setting part has a jitter measurement circuit which measures the jitter amount of this received data based on the said received data, and sets the gain of the said filter process according to the measured jitter amount. The receiving device described in 1. The jitter measurement circuit includes:
A clock data recovery circuit that outputs a first clock and a second clock based on the received data;
A plurality of flip-flop circuits that respectively sample the received data with a plurality of clocks obtained by delaying the second clock by a predetermined time;
A logic circuit that performs an exclusive OR operation on the output values of adjacent flip-flop circuits;
By sampling the output value of the logic circuit with the first clock, the circuit detects the timing at which the output value of the adjacent flip-flop circuit changes, and measures the jitter amount based on the detected timing;
The receiving apparatus according to claim 8, further comprising: a conversion table that converts the measured jitter amount into a gain of the filtering process.   A gain of a filtering process for filtering a phase difference between the received data and the clock in a clock data recovery circuit that generates a clock based on the received data, according to a jitter amount of the received data Setting method.

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