JP2014170779A - Method for constituting dynamic reconfigurable logic element accompanying chaos to state transition region - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for constituting a dynamic reconfigurable logic element accompanying chaos to a state transition region, in which chaotic behavior is found in all the transition region, the reconfiguration of various logic functions is achieved only by switching a circuit parameter, and the logic element accompanying the chaos to the state transition and capable of being dynamically reconfigured can be achieved.SOLUTION: In a method for constituting a dynamic reconfigurable logic element accompanying chaos to a state transition region, the logic element is achieved which accompanies chaos to the state transition and enables dynamic reconfiguration by one chaos neuron (1) and three section linear functions (2,2,2).

Description

  The present invention relates to a method for configuring a dynamically reconfigurable logic element with chaos in a state transition region.

  In recent years, research on information processing systems using complex systems, particularly chaotic dynamical systems, has been actively conducted (see Non-Patent Documents 1 to 3 below). In these studies, we aim to realize real number calculation by complex systems by actively using analog dynamics as continuous systems. On the other hand, in the field of digital computers, research on hardware that can be reconfigured, such as FPGA, has been actively conducted, and in particular, dynamic reconfiguration of logic function circuits has attracted attention.

  Under such circumstances, a dynamic theoretical element that can dynamically change a logical function by utilizing the nonlinearity of the element has been proposed (see Non-Patent Document 4 below). In addition, using a chaotic neuron model (see Non-Patent Document 5 below), chaos is accompanied by analog state transitions between logical values, and the logic function can be dynamically switched by changing the threshold value or coupling coefficient. A logical element has also been proposed at the same time (see Non-Patent Document 4 below). In addition, this dynamic theoretical element is mounted on a circuit using a switched capacitor circuit technique, and its basic operation has been confirmed (see Non-Patent Document 6 below).

However, when the OR, AND, NOR, NAND and EX-OR are realized with the dynamic theoretical elements proposed in the following Non-Patent Documents 4 and 6, the number of neurons required for each logical function is different. It was necessary to add or delete neurons when switching logical functions dynamically. Furthermore, there existed state transitions without chaotic behavior depending on the input value.
On the other hand, a configuration method of a dynamic logic element with chaos in all state transition regions has been proposed without changing the number of necessary neurons (see Non-Patent Document 7 below). Furthermore, a configuration method using a simple piecewise linear element instead of a chaotic neuron has been proposed (see Non-Patent Documents 8 and 9 below).

  FIG. 20 is a diagram showing a conventional configuration method of a logic circuit that can be dynamically reconfigured with chaos in the state transition region. In this figure, CN indicates a chaos neuron 101, PWL indicates a piecewise linear circuit 102, + indicates an adder 104, and 2 indicates a double coefficient unit 103. In this configuration method, as shown in FIG. 20, by combining one chaotic neuron and five piecewise linear functions, two-input OR, AND, NOR, NAND, EX-OR, and EX-NOR logic can be realized. All state transition regions are accompanied by chaotic behavior. That is, it operates as a chaotic element for an analog input and as a dynamically reconfigurable logic element for a digital (logic) input. However, considering actual circuit mounting, the circuit scale becomes large due to the large number of elements, which is not practical.

K. Aihara, “Chaos engineering and its applications to parallel distributed processing with chaotic neural networks,” Proceedings of the IEEE, vol. 90, no. 5, pp. 919-930, 2002. Y. Horio, and K.H. Aihara, “Analog computation through high-dimensional physical chaotic neuro-dynamics,” Physica-D, vol. 237, no. 9, pp. 1215-1225, 2008. Yoshihiko Horio, Hiroyasu Ando, Kazuyuki Aihara, “Basic Technology of Complex Computing Systems,” IEICE Fundamentals Review, vol. 3, no. 2, pp. 34-44, 2009. T. T. et al. Munaka, J .; Takahashi, M .; Sekikawa, and K.K. Aihara, “Chaos computing: A unified-view,” International Journal of Parallel, Emergence and Distributed Systems, vol. 25, issue 1, pp. 3-16, 2010. K. Aihara. T. T. et al. Takabe, and M.M. Toyoda, “Chaotic neural networks,” Physics Letters A, vol. 144, pp. 333-340, 1990. Noriyoshi Ishimura, Jun Takahashi, Yoshihiko Horio, Kazuyuki Aihara, “Implementation of Dynamic Logic Circuits with Chaotic States by Switched Capacitor Chaotic Neuron Circuits,” IEICE Technical Report, vol. 110, no. 387, pp. 13-18 (NLP2010-127), Jan. 24, 2011. Masayoshi Ikeda, Yoshihiko Horio, Kazuyuki Aihara, “Improvement of dynamic logic elements with chaos in transition region,” IEICE technical report, vol. 111, no. 339, pp. 35-40 (NLP2011-123), Dec. 15, 2011. M.M. Ikeda, Y .; Horio, and K.H. Aihara, "Improved dynamical logic element with chaotic state transitions using switched-capacitor chaotic neuron circuit," RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, CD-ROM, Honolulu, Hawaii, USA, March 4-6,2012. M.M. Ikeda, Y .; Horio, and K.H. Aihara, “Improved dynamical logic element with chaotic state transitions using switched-capacitor chaotic neurological circuit,” Journal of Prosigning. 16, no. 4, pp. 291-294, 2012.

  In view of the above situation, the present invention has a chaos behavior in a state transition region in which all transition regions have chaotic behavior and various logic functions can be reconfigured simply by switching circuit parameters. It is an object of the present invention to provide a method for configuring a reconfigurable logic element.

In order to achieve the above object, the present invention provides
[1] In a method of configuring a dynamically reconfigurable logic element with chaos in the state transition region, all transition regions have chaotic behavior, and various logic functions can be reconfigured simply by switching circuit parameters. It is characterized by.
[2] In the method of configuring a dynamically reconfigurable logic element with chaos in the state transition region described in [1] above, used as a basic component of a logic function circuit system for reconfiguring a logic function during operation It is characterized by.

[3] In the method for constructing a dynamically reconfigurable logic element with chaos in the state transition region described in [1] above, real number arithmetic by analog dynamics using chaotic behavior of the transition region can be simultaneously implemented. It is characterized by that.
[4] In the method for configuring a dynamically reconfigurable logic element with chaos in the state transition region described in [3] above, the method is effective for implementation by a hybrid dynamical system or an analog / digital hybrid calculation. To do.

[5] In the method of constructing a dynamically reconfigurable logic element with chaos in the state transition region described in [1] or [2] above, the state transition is accompanied by chaos by one chaotic neuron and three piecewise linear functions. It is characterized by realizing a dynamically reconfigurable logic element.
[6] In the method of constructing a dynamically reconfigurable logic element with chaos in the state transition region described in [5] above, two-input OR logic, AND logic, NOR logic, NAND logic, EX-OR logic, EX -Realize NOR logic.

According to the present invention, the following effects can be achieved.
(1) A dynamic logic circuit system in which various logic functions can be reconfigured simply by switching circuit parameters, and the parameters can be set to values that can be easily realized. In particular, it is very useful as a basic component of a logic function circuit system that dynamically reconfigures a logic function according to the value of an environment variable.

(2) In addition, real number arithmetic by analog dynamics using chaotic behavior of transition region can be implemented at the same time, which is useful for complex system information processing, especially implementation by hybrid dynamic system and analog / digital hybrid calculation. .
(3) In the present invention, it is possible to reduce the size by one chaotic neuron and three piecewise linear functions, and to realize a logic element that can be dynamically reconfigured with chaos in the state transition.

It is a figure which shows the structural method of the logic circuit which can be dynamically reconfigure | reconstructed with chaos in the state transition area | region which shows 1st Example of this invention. It is an input-output characteristic figure of piecewise linear function g (*) in case of CNT = 1. 2 is an input / output characteristic diagram of FIG. 1 according to an OR parameter set of Table 1. FIG. 2 is an input / output characteristic diagram of FIG. 1 according to an AND parameter set of Table 1. FIG. 2 is an input / output characteristic diagram of FIG. 1 according to the NOR parameter set of Table 1. FIG. 2 is an input / output characteristic diagram of FIG. 1 according to the NAND parameter set of Table 1. FIG. 2 is an input / output characteristic diagram of FIG. 1 according to the EX-OR parameter set of Table 1. FIG. 2 is an input / output characteristic diagram of FIG. 1 according to the EX-NOR parameter set of Table 1. FIG. It is a figure which shows the example which mounted the structure method of 1st Example of this invention with the electronic circuit. 10 is an input / output characteristic diagram obtained by SPICE simulation from the circuit of FIG. 9 when the circuit parameter set of Table 4 is used. It is a figure which shows the structural method of the logic circuit which can be dynamically reconfigure | reconstructed with chaos in the state transition area | region which shows 2nd Example of this invention. FIG. 11 is an input / output characteristic diagram of FIG. 10 according to the OR parameter set of Table 5. FIG. 11 is an input / output characteristic diagram of FIG. 10 according to the AND parameter set of Table 5. 10 is an input / output characteristic diagram of FIG. 10 according to the NOR parameter set of Table 5. FIG. 10 is an input / output characteristic diagram of FIG. 10 according to the NAND parameter set of Table 5. FIG. 10 is an input / output characteristic diagram of FIG. 10 according to the EX-OR parameter set of Table 5. FIG. FIG. 11 is an input / output characteristic diagram of FIG. 10 according to the EX-NOR parameter set of Table 5. It is a figure which shows the example which mounted the structure method of 2nd Example of this invention with the electronic circuit. FIG. 19 is an input / output characteristic diagram obtained by SPICE simulation from the circuit of FIG. 18 in the case of the circuit parameter set of Table 7. It is a figure which shows the conventional structure method of the logic circuit which can be dynamically reconfigure | reconstructed with chaos in a state transition area | region.

  The method of configuring a dynamically reconfigurable logic element with chaos in the state transition region has chaotic behavior in all of the transition regions, and realizes reconfiguration of various logic functions only by switching circuit parameters.

Hereinafter, embodiments of the present invention will be described in detail.
FIG. 1 is a diagram showing a configuration method of a logic circuit that can be dynamically reconfigured with chaos in the state transition region according to the first embodiment of the present invention.
In this figure, CN indicates a chaotic neuron 1, PWL indicates a piecewise linear circuit 2, + indicates an adder 4, and 2 indicates a double coefficient unit 3. That is, this figure shows the case of 2 inputs and 1 output. That is, P (t) and Q (t) are inputs, and R (t + 1) is an output. Here, t is a discrete time related to the state update of the chaotic neuron.

Ｒ（ｔ＋１）＝ｆ〔ｘ（ｔ＋１）〕 …（２）
ここで、ｋ（０＜ｋ≦１）は内部状態の減衰定数、α（０＜α≦１）は不応性のスケーリングパラメータ、θは閾値、ｖ_j はｊ番目の外部入力ａ_j （ｔ）との結合係数、Ｎは外部入力の総数である。また、ｘ（ｔ），Ｒ（ｔ）はそれぞれ、離散時間ｔにおけるカオスニューロンの内部状態および出力である。出力関数ｆ〔・〕は単調な非線形関数であるが、回路化の観点から、以下では次式で与えられるバイポーラ型の出力関数を用いる。 CN represents the chaotic neuron 1 (see Non-Patent Document 5 above), and its operation is described by the following equation.

R (t + 1) = f [x (t + 1)] (2)
Here, k (0 <k ≦ 1) is an internal state attenuation constant, α (0 <α ≦ 1) is a refractory scaling parameter, θ is a threshold value, and v _j is a _jth external input a _j (t). And N is the total number of external inputs. X (t) and R (t) are the internal state and output of the chaotic neuron at the discrete time t, respectively. The output function f [•] is a monotonic nonlinear function, but from the viewpoint of circuitization, a bipolar output function given by the following equation is used below.

ここで、ｘは区分線形関数の入力、ＣＮＴは区分線形関数の中間の線形部分の中央値を与え、また、中間部分の傾きは１である。このような、中間部分のゲインが１で、飽和値が−１と１である区分線形関数は、電子回路の実装が非常に容易である。例として、ＣＮＴ＝１の時のｇ（・）の入出力特性を図２に示す。この場合、ｘ＜０でｇ（ｘ）＝−１，ｘ＞２でｇ（ｘ）＝１、０≦ｘ≦２ではｇ（ｘ）＝ｘ−１となる。 f (x) = {[2 / [1 + exp (−x / ε)]} − 1 (3)
Here, ε is a gain parameter.
Further, PWL in FIG. 1 is a piecewise linear function g (•) given by the following equation.

Here, x is the input of the piecewise linear function, CNT is the median value of the middle linear part of the piecewise linear function, and the slope of the middle part is 1. Such a piecewise linear function with an intermediate gain of 1 and saturation values of −1 and 1 is very easy to implement an electronic circuit. As an example, FIG. 2 shows the input / output characteristics of g (•) when CNT = 1. In this case, g (x) = − 1 when x <0, g (x) = 1 when x> 2, and g (x) = x−1 when 0 ≦ x ≦ 2.

  Table 1 shows a parameter set for realizing the 2-input OR, AND, NOR, NAND, EX-OR, and EX-NOR logics with the configuration of FIG.

表１のパラメータセットを用いた時の、図１の入出力特性を図３から図８に示す。なお、カオスニューロンとの結合での増幅を避けるために、表２のように｜ｖ_i ｜≦１としてパラメータを設定することも可能である。

The input / output characteristics of FIG. 1 when the parameter set of Table 1 is used are shown in FIGS. In order to avoid amplification due to coupling with chaotic neurons, it is also possible to set parameters as | v _i | ≦ 1 as shown in Table 2.

次に、論理関数としての特性について説明する。
−１を論理偽（ｆａｌｅｓ）、１を論理真（ｔｒｕｅ）とし、図３から図８において、Ｐ（ｔ）、Ｑ（ｔ）およびＲ（ｔ＋１）がこれらの論理値だけを取る場合を考える。すなわち、図１をディジタル論理回路として用いる場合に限定して考察する。従って、この場合、｛Ｐ（ｔ）、Ｑ（ｔ）｝は、｛−１，−１｝、｛−１，１｝、｛１，−１｝、｛１，１｝の４通りの離散値を取る。図３から図８において、これらの４通りのＰ（ｔ）、Ｑ（ｔ）についてのＲ（ｔ＋１）の真理値表を作成すると表３を得ることができる。

Next, characteristics as a logical function will be described.
-1 is a logical false (false), 1 is a logical true (true), and P (t), Q (t) and R (t + 1) take only these logical values in FIGS. . That is, the case where FIG. 1 is used as a digital logic circuit is considered. Therefore, in this case, {P (t), Q (t)} are four discretes of {-1, -1}, {-1, 1}, {1, -1}, {1, 1}. Take the value. 3 to 8, when the truth table of R (t + 1) for these four types of P (t) and Q (t) is created, Table 3 can be obtained.

表３より、図３の特性がＯＲ論理を、図４の特性がＡＮＤ論理を、図５の特性がＮＯＲ論理を、図６の特性がＮＡＮＤ論理を、図７の特性がＥＸ−ＯＲ論理を、図８の特性がＥＸ−ＮＯＲ論理を、それぞれ実現していることが確認できる。すなわち、図１をディジタル論理回路として用いる場合には、回路パラメータを表１のように設定することで、１つの回路構成により、動的に論理関数が再構成できることが確認できる。この時変更する回路バラメータはθとｖ_i であり、表に示すようにこれらは整数値に設定できるため、容易に回路化できる。

From Table 3, the characteristics of FIG. 3 are OR logic, the characteristics of FIG. 4 are AND logic, the characteristics of FIG. 5 are NOR logic, the characteristics of FIG. 6 are NAND logic, and the characteristics of FIG. 7 are EX-OR logic. It can be confirmed that the characteristics of FIG. 8 realize the EX-NOR logic. That is, when FIG. 1 is used as a digital logic circuit, it can be confirmed that a logic function can be dynamically reconfigured by one circuit configuration by setting circuit parameters as shown in Table 1. The circuit parameters to be changed at this time are θ and v _i , and these can be set to integer values as shown in the table.

Here, FIGS. 3 to 8 will be described in detail.
In FIG. 3, FIG. 3 (a): P (t) is changed to −1⇔1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔−1, FIG. 3B: Q (t) = − 1 fixed, P (t) is changed to −1⇔1, and P (t) = 1. When Q (t) is fixed and changed to 1⇔−1, FIG. 3C: P (t) = − 1 fixed and Q (t) is changed to −1⇔1 and In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 4, FIG. 4 (a): P (t) is changed to −1⇔1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔−1, FIG. 4 (b): Q (t) = − 1 fixed, P (t) is changed to −1⇔1, and P (t) = 1. Fig. 4 (c): P (t) = -1 fixed and Q (t) changed to -1 -1 when Q (t) is changed to 1 -1 In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 5, FIG. 5 (a): P (t) is changed from −1⇔1 and Q (t) to −1⇔1, and P (t) is changed from −1⇔1, Q (t ) Is changed to 1⇔−1, FIG. 5B: Q (t) = − 1 fixed, P (t) is changed to −1⇔1, and P (t) = 1. Fig. 5 (c): P (t) = -1 fixed and Q (t) changed to -1 ⇔1 when Q (t) is changed to -1⇔-1 In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 6, FIG. 6 (a): P (t) is changed to −1⇔1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔-1, FIG. 6B: Q (t) = − 1 fixed, and P (t) is changed to −1⇔1, and P (t) = 1. Fig. 6 (c): P (t) = -1 fixed and Q (t) changed to -1 -1 when Q (t) is changed to 1 -1; In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  7 (a): P (t) is changed to −1⇔1, Q (t) is changed to −1） 1, and P (t) is changed to −1） 1, Q (t ) Is changed to 1⇔−1, FIG. 7B: Q (t) = − 1 fixed, P (t) is changed to −1⇔1, and P (t) = 1. FIG. 7 (c): P (t) = − 1 fixed and Q (t) changed to −1⇔1 when Q (t) 1⇔−1 is fixed and Q (t) 1⇔−1 In this example, (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 8, FIG. 8 (a): P (t) is changed to −1⇔1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔−1, FIG. 8B: Q (t) = − 1 fixed and P (t) is changed to −1⇔1, and P (t) = 1. When Q (t) is fixed and changed to 1⇔−1, FIG. 8 (c): P (t) = − 1 fixed and Q (t) is changed to −1⇔1 and In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

Next, a response to an analog input will be described.
In FIG. 1, let us consider a case where inputs P (t) and Q (t) take continuous values [−1, 1]. In this case, from FIG. 3 to FIG. 8, the output R (t + 1) also takes a continuous value, and as P (t) or Q (t) changes from −1 to 1, complex branches including periodic solutions and chaotic solutions It can be confirmed that the characteristics are exhibited. That is, FIG. 1 shows a complex behavior including chaos for an analog input. This is a useful and essential characteristic in information processing using chaos (see Non-Patent Documents 1 to 3 above).

  On the other hand, when the characteristics as a logic function and the response to the above analog input are combined, the circuit of FIG. 1 operates as a logic function circuit that can be dynamically reconfigured with respect to the digital input. It can be seen that in the state transition region at the time of transition to a value, it operates as an analog arithmetic element with chaos. That is, the circuit of FIG. 1 is useful as a basic component of an analog / digital hybrid information processing apparatus.

  FIG. 9 is a diagram showing an example in which the configuration method of FIG. 1 of the present invention is implemented by an electronic circuit, and Table 4 shows examples of electronic circuit components.

図１０は表４の回路パラメータセットの時、図９の回路からＳＰＩＣＥシミュレーションにより得られた入出力特性図である。
図１０においては、図１０（ａ）：Ｐ（ｔ）を−１Ｖ⇔１Ｖ，Ｑ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合と、Ｐ（ｔ）を−１Ｖ⇔１Ｖ，Ｑ（ｔ）を１Ｖ⇔−１Ｖと変化させた場合、図１０（ｂ）：Ｑ（ｔ）＝−１Ｖ固定で、Ｐ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合と、Ｐ（ｔ）＝１Ｖ固定で、Ｑ（ｔ）を１Ｖ⇔−１Ｖと変化させた場合、図１０（ｃ）：Ｐ（ｔ）＝−１Ｖ固定で、Ｑ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合と、Ｑ（ｔ）＝１Ｖ固定で、Ｐ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合を示している。

10 is an input / output characteristic diagram obtained by SPICE simulation from the circuit of FIG. 9 when the circuit parameter set of Table 4 is used.
10 (a): P (t) is changed to −1V−１1V, Q (t) is changed to −1V⇔1V, and P (t) is changed to −1V⇔1V, Q (t ) Is changed to 1V⇔-1V, FIG. 10 (b): Q (t) =-1V fixed, P (t) is changed to -1V⇔1V, and P (t) = 1V When Q (t) is fixed and changed to 1VＶ-1V, FIG. 10 (c): P (t) = − 1V is fixed and Q (t) is changed to −1V⇔1V, In this example, Q (t) = 1V is fixed and P (t) is changed to -1V⇔1V.

FIG. 11 is a diagram showing a configuration method of a logic circuit that can be dynamically reconfigured with chaos in the state transition region according to the second embodiment of the present invention. That is, a more compact configuration method is shown as compared to the first embodiment using a coefficient unit.
In FIG. 11, CN indicates a chaos neuron 11, PWL indicates a piecewise linear circuit 12, and + indicates a adder 13.

  Table 5 shows a parameter set for realizing OR, AND, NOR, NAND, EX-OR, and EX-NOR logic with this configuration.

表５中、｜ｖ_i ｜＝０．５の場合があるが、これは１／２であるため、実際の回路ではキャバシタの容量比や抵抗の抵抗比によって容易に実現できる。（これは、表２についても同様である。）
表５のパラメータセットを用いた時の、図１１の入出力特性を図１２から図１７に示す。

In Table 5, there are cases where | v _i | = 0.5, but since this is 1/2, in an actual circuit, it can be easily realized by the capacitance ratio of the capacitor and the resistance ratio of the resistor. (This also applies to Table 2.)
The input / output characteristics of FIG. 11 when the parameter set of Table 5 is used are shown in FIGS.

  The characteristics as a logical function will be described. Table 6 shows a truth table in the case where -1 is logic false and 1 is logic true, and P (t), Q (t) and R (t + 1) take only these logic values in FIGS. Show.

表６より、図１２の特性がＯＲ論理を、図１３の特性がＡＮＤ論理を、図１４の特性がＮＯＲ論理を、図１５の特性がＮＡＮＤ論理を、図１６の特性がＥＸ−ＯＲ論理を、図１７の特性がＥＸ−ＮＯＲ論理を、それぞれ実現していることが確認できる。すなわち、図１１をディジタル論理回路として用いる場合には、回路パラメータを表５のように設定することで、１つの回路構成により、動的に論理関数が再構成できることが確認できる。

From Table 6, the characteristics of FIG. 12 are OR logic, the characteristics of FIG. 13 are AND logic, the characteristics of FIG. 14 are NOR logic, the characteristics of FIG. 15 are NAND logic, and the characteristics of FIG. 16 are EX-OR logic. It can be confirmed that the characteristics of FIG. 17 realize the EX-NOR logic. That is, when FIG. 11 is used as a digital logic circuit, it can be confirmed that a logic function can be dynamically reconfigured by one circuit configuration by setting circuit parameters as shown in Table 5.

Here, FIGS. 12 to 17 will be described in detail.
In FIG. 12, FIG. 12 (a): P (t) is changed from −1⇔1, Q (t) to −1⇔1, and P (t) is changed from −1⇔1, Q (t ) Is changed to 1⇔-1, FIG. 12B: when Q (t) = − 1 is fixed and P (t) is changed to −1⇔1, and P (t) = 1. Fig. 12 (c): P (t) = -1 fixed and Q (t) changed to -1 ⇔1 when Q (t) is changed to -1⇔-1 In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 13, FIG. 13 (a): P (t) is changed to −1 を 1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔-1, FIG. 13B: Q (t) = − 1 fixed, P (t) is changed to −1⇔1, and P (t) = 1. Fig. 13 (c): P (t) is fixed to -1 and Q (t) is changed to -1⇔1 when Q (t) is changed to 1⇔-1. In this example, Q (t) 1 = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 14, FIG. 14 (a): P (t) is changed to −1） 1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔-1, FIG. 14B: when Q (t) = − 1 is fixed and P (t) is changed to −1⇔1, and P (t) = Fig. 14 (c): P (t) = -1 fixed and Q (t) changed to -1 ⇔1 when Q (t) is changed to 1⇔-1 with 1 fixed , Q (t) = 1 is fixed, and P (t) is changed to −1⇔1.

  15, FIG. 15 (a): P (t) is changed to −1⇔1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔−1, FIG. 15B: Q (t) = − 1 is fixed, and P (t) is changed to −1⇔1, and P (t) = 1. Fig. 15 (c): P (t) = -1 fixed and Q (t) changed to -1 ⇔1 when Q (t) is changed to -1⇔-1 In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 16, FIG. 16 (a): P (t) is changed to −1） 1, Q (t) is changed to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔−1, FIG. 16B: Q (t) = − 1 is fixed, and P (t) is changed to −1⇔1, and P (t) = 1. When Q (t) is fixed and changed to 1 で −1, FIG. 16 (c): P (t) = − 1 fixed and Q (t) is changed to −1⇔1 and In this example, Q (t) = 1 is fixed and P (t) is changed to −1⇔1.

  In FIG. 17A, FIG. 17A shows a case where P (t) is changed to −1 （1, Q (t) to −1⇔1, and P (t) is changed to −1⇔1, Q (t ) Is changed to 1⇔-1, FIG. 17B: Q (t) = − 1 fixed, P (t) is changed to −1⇔1, and P (t) = 1. When Q (t) is fixed and changed to 1 で -1, FIG. 17 (c): P (t) = 1 fixed and Q (t) is changed to −1⇔1, In this example, (t) = 1 is fixed and P (t) is changed to −1⇔1.

Next, a response to an analog input will be described.
In FIG. 11, when inputs P (t) and Q (t) take continuous values [−1, 1], P (t) and Q (t) change from −1 to 1 from FIGS. 12 to 17. It can be seen that the output R (t + 1) exhibits complex branching characteristics including periodic solutions and chaotic solutions. That is, FIG. 11 shows a complex behavior including chaos, which is a useful and essential characteristic for information processing using chaos for analog input (see Non-Patent Documents 1 to 3 above).

  Furthermore, when the characteristics as a logic function and the response to the above analog input are combined, the circuit of FIG. 11 operates as a logic function circuit that can be dynamically reconfigured with respect to the digital input, and the input is set to another value. In the state transition region at the time of transition, it can be seen that it operates as an analog arithmetic element with chaos. That is, the circuit of FIG. 11 is useful as a basic component of the analog / digital hybrid information processing apparatus.

  FIG. 18 is a diagram showing an example in which the configuration method of FIG. 11 of the present invention is implemented by an electronic circuit, and Table 7 shows examples of electronic circuit components.

図１９は表７の回路パラメータセットの時、図１８の回路からＳＰＩＣＥシミュレーションにより得られた入出力特性図である。
図１９においては、図１９（ａ）：Ｐ（ｔ）を−１Ｖ⇔１Ｖ，Ｑ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合と、Ｐ（ｔ）を−１Ｖ⇔１Ｖ，Ｑ（ｔ）を１Ｖ⇔−１Ｖと変化させた場合、図１９（ｂ）：Ｑ（ｔ）＝−１Ｖ固定で、Ｐ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合と、Ｐ（ｔ）＝１Ｖ固定で、Ｑ（ｔ）を１Ｖ⇔−１Ｖと変化させた場合、図１９（ｃ）：Ｐ（ｔ）＝−１Ｖ固定で、Ｑ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合と、Ｑ（ｔ）＝１Ｖ固定で、Ｐ（ｔ）を−１Ｖ⇔１Ｖと変化させた場合を示している。

19 is an input / output characteristic diagram obtained by SPICE simulation from the circuit of FIG. 18 when the circuit parameter set of Table 7 is used.
In FIG. 19, FIG. 19 (a): P (t) is changed to -1V−１1V, Q (t) is changed to -1V⇔1V, and P (t) is changed to -1V⇔1V, Q (t ) Is changed to 1V⇔-1V, FIG. 19 (b): Q (t) =-1V fixed, P (t) is changed to -1V⇔1V, and P (t) = 1V When Q (t) is fixed and changed to 1VＶ-1V, FIG. 19 (c): P (t) = − 1V is fixed and Q (t) is changed to −1V⇔1V, In this example, Q (t) = 1V is fixed and P (t) is changed to -1V⇔1V.

  According to the present invention, since various logic functions can be reconfigured simply by switching circuit parameters, and the parameters can be set to values that can be easily realized, a logic function circuit system that reconfigures a logic function during operation. It is very useful as a basic component. Furthermore, not only logic operations but also real number operations by analog dynamics using chaotic behavior in the transition region can be implemented at the same time, for complex information processing, especially for operations by hybrid dynamical systems and analog / digital hybrid calculations. Useful. According to such a hybrid system, dynamic memory, solution of optimization problem, autonomous escape from deadlock state, dynamic information processing system whose function changes autonomously depending on environment variable and state, etc. It can be applied to. In particular, autonomous escape from a deadlock state is widely applied to optimal operation of various networks such as a wireless communication network, a computer network, a traffic flow network, and a power network, and avoiding a function stop.

The elements composing the proposed logic element are chaotic neurons and piecewise linear functions. The chaos neuron has already been integrated into an integrated circuit by the inventors of the present application, and it has been shown that it is sufficiently small and can operate at low power consumption and high speed.
In addition, the piecewise linear function used in the present invention is very easy to implement in an integrated circuit or the like, and can be miniaturized.

Therefore, the present invention can be immediately put into practical use with an integrated circuit or the like.
In the configuration method of the present invention, since various logic functions can be reconfigured simply by switching the circuit parameters, it can be used for implementation by a hybrid dynamical system or an analog / digital hybrid calculation, and cannot be easily solved only by logic operations. It can be applied to various problems such as problems.

  In addition, this invention is not limited to the said Example, Based on the meaning of this invention, a various deformation | transformation is possible and these are not excluded from the scope of the present invention.

  The configuration method of dynamically reconfigurable logic elements with chaos in the state transition region of the present invention has chaotic behavior in all of the transition regions, and realizes reconfiguration of various logic functions just by switching circuit parameters It can be used as a method for configuring a dynamically reconfigurable logic element with chaos in the state transition region.

1,11 Chaotic neuron (CN)
2,12 Piecewise linear circuit (PWL)
3 Coefficient multiplier 4, 13 Adder P (t), Q (t) Input R (t + 1) Output t Discrete time for state update of chaotic neuron

Claims (6)

  In the method of configuring a dynamically reconfigurable logic element with chaos in the state transition region, all transition regions have chaotic behavior, and various logic functions can be reconfigured simply by switching circuit parameters. A method for configuring a dynamically reconfigurable logic element with chaos in a characteristic state transition region.   2. The method for configuring a dynamically reconfigurable logic element with chaos in the state transition region according to claim 1, wherein the logic element is used as a basic component of a logic function circuit system for reconfiguring a logic function during operation. A method for configuring a dynamically reconfigurable logic element with chaos in a state transition region.   The method of configuring a dynamically reconfigurable logic element with chaos in the state transition region according to claim 1, wherein real number arithmetic by analog dynamics using chaotic behavior of the transition region can be simultaneously implemented. Of dynamically reconfigurable logic element with chaos in the state transition region to be performed.   4. A method of constructing a dynamically reconfigurable logic element with chaos in a state transition region according to claim 3, wherein the state transition region is effective for implementation by a hybrid dynamical system or an analog / digital hybrid calculation. Of dynamically reconfigurable logic elements with chaos.   3. The method of constructing a dynamically reconfigurable logic element with chaos in the state transition region according to claim 1 or 2, wherein the state transition can be dynamically reconfigured with chaos by one chaotic neuron and three piecewise linear functions. A method for configuring a dynamically reconfigurable logic element with chaos in a state transition region, characterized by realizing a simple logic element.   6. The method of configuring a dynamically reconfigurable logic element with chaos in the state transition region according to claim 5, wherein two-input OR logic, AND logic, NOR logic, NAND logic, EX-OR logic, and EX-NOR logic A configuration method of a logic element that can be dynamically reconfigured with chaos in a state transition region, characterized in that it is realized.

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