JP2014170361A - Information processor, bus division method and bus division program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the availability of a circuit in a two-wire serial bus.SOLUTION: An information processor consists of a two-wire serial bus system 100, and includes a plurality of master devices 10; one or more slave devices 20 and a switch 30 for dividing a bus into a plurality of buses such that at least one master device 10 exists on the respective divided buses. The master devices 10 are configured to operate as masters on the respective divided buses such that those master devices are allowed to operate in parallel as multi-masters. Also, the switch 30 is configured to emulate the functions of the master devices or slave devices.

Description

  The present invention relates to a two-wire serial bus system, and more particularly to a bus division technique.

  As an interface for transmitting information between devices, an I2C (Inter Integrated Circuit) bus or the like is known. I2C is a communication method that enables communication using two data lines and a clock line. Since it is simple and can reduce the manufacturing cost, it is often used when the speed is not so high. Furthermore, in recent years, it has been used for various purposes because of the advantage that the number of wirings can be reduced. Now, the communication speed in the standard is expanded and the communication speed is gradually increased.

  However, in I2C, waveform rounding due to the wiring length also occurs, so it is not suitable for long wiring, and in reality, there are severe restrictions on using high-speed communication. In addition, although it supports multi-master, it is connected by daisy chain, so if multiple devices do not become masters at the same time, but try to start communication at the same time, the collision detection function and arbitration function will destroy the data. It is something that prevents and coexists. In the communication system based on I2C, only one-to-one communication or one-to-multiple communication can be performed when viewed in terms of time.

  Here, as a related technique, Patent Document 1 discloses a technique in which MBUS and SBUS are divided and a bus master is mounted on any bus to form a multi-bus master configuration.

JP-A-6-060015

  FIG. 9 shows a schematic diagram of a two-wire serial bus system known in the background art. In the case of such a general multi-master, one of them operates as a master device and cannot operate as a master device at the same time.

  Here, FIG. 10 shows a timing chart of the basic operation of communication using the two-wire serial bus. In FIG. 10, the master device first declares the start of communication in the START state, and subsequently transmits data. Thereafter, upon receiving an acknowledge from the receiving side, the master device terminates communication in the STOP state. In a two-wire serial bus system known in the background art, during communication, this state occupies the bus line, so that devices can communicate only in a one-to-one correspondence.

(Object of invention)
An object of the present invention is to provide an information processing apparatus, a bus division method, and a bus division program capable of solving the above-described problems and increasing the availability of a circuit in a two-wire serial bus.

  A first information processing apparatus according to the present invention is an information processing apparatus configured by a two-wire serial bus system, and includes at least one master device, one or more slave devices, and each divided bus. A switch is provided that divides the bus into a plurality of buses so that there is one master device, and the master device operates as a master on each of the divided buses, thereby operating in parallel as a multi-master.

  A second information processing apparatus according to the present invention is an information processing apparatus configured by a two-wire serial bus system, and includes one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of devices. The switch includes an emulating unit that functions as a master device or a slave device.

  A first bus division method according to the present invention is a bus division method in an information processing apparatus configured by a two-wire serial bus system and including a plurality of master devices, one or more slave devices, and a switch. However, the step of dividing the bus into a plurality of buses so that there is at least one master device on each divided bus, and the master device operates as a master on each divided bus. And operating as a master in parallel.

  A second bus division method of the present invention is an information processing apparatus that is configured by a two-wire serial bus system and includes one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of buses. In the bus division method, the emulation means included in the switch includes an emulation step that functions as a virtual master device or a slave device.

  The first bus division program of the present invention is a bus that is configured by a two-wire serial bus system and that operates on a computer that constitutes an information processing apparatus including a plurality of master devices, one or more slave devices, and a switch. A division program that causes a switch to execute a process of dividing a bus into a plurality of buses so that at least one master device exists on each divided bus, and the master device on each divided bus By operating as a master, a process that operates in parallel as a multi-master is executed.

  A second bus division program according to the present invention is an information processing apparatus that includes a two-wire serial bus system and includes one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of buses. It is a bus division program, and causes the emulation means provided in the switch to execute an emulation process that functions as a virtual master device or slave device.

  According to the present invention, the availability of a circuit in a two-wire serial bus can be increased.

1 is a block diagram showing a configuration of a two-wire serial bus system according to a first embodiment of the present invention. It is a block diagram which shows the internal structure of the switch by the 1st Embodiment of this invention. It is a flowchart which shows the data reception flow of the switch by the 1st Embodiment of this invention. It is a flowchart which shows the data transmission flow of the switch by the 1st Embodiment of this invention. It is a figure which shows the state of the bus division | segmentation by the 1st Embodiment of this invention. It is a figure which shows the operation | movement folk tool in the multi master by the 1st Embodiment of this invention. It is a figure which shows the state of the bus division | segmentation by the 1st Embodiment of this invention. It is a block diagram which shows the hardware structural example of the information processing apparatus of this invention. It is a block diagram which shows the structure of the two-wire serial bus system by background art. It is a figure which shows the timing chart of communication by the two-wire serial bus system by background art.

  In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In addition to the above-described object of the present invention, other technical problems, means for solving the technical problems, and operational effects thereof will become apparent from the disclosure of the following embodiments. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
A first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a two-wire serial bus system 100 according to the first embodiment of the present invention. Although not shown, the two-wire serial bus system 100 is configured on the information processing apparatus 200.

  The two-wire serial bus system 100 according to the present embodiment includes a master device 10-1, a master / slave device 40, slave devices 20-2 to 20-4, and a switch 30. The master / slave device 40 functions as the master device 10-2 or the slave device 20-1. FIG. 1 is an exemplification, and does not limit the system configuration.

  The two-wire serial bus system 100 according to the present embodiment includes a switch 30 that monitors the communication state of the transmission line and controls data input / output in addition to the known two-wire serial bus system according to the background art. And

  The switch 30 has a function of dividing or connecting a circuit. The switch 30 has a function of emulating the operations of the master device and the slave device on the serial bus. When communication between the buses divided by the switch 30 is performed, this switch is used. The switch 30 itself is also controlled via a serial bus.

  The internal configuration of the switch 30 is shown in FIG. The switch 30 includes a memory 31, an emulating unit 32 serving as the master device 10 or the slave device 20 in each bus, and a switch switching unit 33 for switching the state of the switch 30.

  The memory 31 stores or provides data received from the master device 10 on the serial bus or received from the slave device 20 on the serial bus connected in a chain.

  The switch switching unit 33 has a function of switching the operation of the emulation unit 32 as a master device and a slave device between on and off.

  By incorporating this switch 30 into the bus, each bus can be separated as shown in FIG. 5 and operated in parallel as a multi-master. Further, in order to switch the state of the switch 30, a switch switching means 33 is provided as a slave device on the serial bus.

  The bus is divided into two or more by the switch 30, and each can have a master as its own bus.

  The present invention has the above-described configuration, and when using a serial bus, a memory and a switch 30 for emulating an arbitrary master device 10 or slave device 20 are inserted so that a plurality of masters can be used simultaneously. By increasing the availability of the circuit. That is, the communication state of the transmission path is monitored, data input / output is controlled, a switch 30 for dividing or connecting the circuit is inserted, and a bus is constructed for each master. The switch 30 is a digital state machine that can operate as either the master device 10 or the slave device 20 on a serial bus chained to each bus.

(Description of the operation of the first embodiment)
Next, the operation of the two-wire serial bus system 100 according to the present embodiment will be described in detail with reference to the drawings.

  There are two states of the switch 30, and the state can be changed by serial bus communication. This is because the switch switching means 33 in the switch 30 has an address on the serial bus, which operates as the slave device 20 on the bus and emulates the Enb signal from the switch switching means 33 as shown in FIG. By sending means 32, switching is possible.

  The two-wire serial bus in the present invention is an open drain system in which the nominal voltage on the bus is High (logic 1) and the device pulls the voltage to the low (logic 0) side. A pull-up resistor is used to connect to the voltage source. The pull-up resistor assists these circuits to maintain a high (logic 1) state when not pulled down by the master device 10 and slave device 20 on the two-wire serial bus.

  The transaction operation of the two-wire serial bus starts with the issuance of the START state. The master device 10 can transmit an address and a READ / WRITE (R / W) signal. The slave device 20 having the address responds with an acknowledge signal. Next, the data word is transmitted, and in the READ transaction, the slave device 20 transmits the data word to the master device 10. The data word may be any number of bits, such as an 8-bit word.

  In the WRITE transaction, the master device 10 can transmit a data word, and the slave device 20 can transmit an acknowledge signal. Further data words and acknowledge signals are repeatable until all data has been transmitted. In other embodiments, the data word may be a data stream that is not divided into separate packets.

  After the data is transmitted, the master device 10 issues a STOP state. As a specific operation, the clock line starts clock transmission after the START state. First, the master device 10 transmits an address, the slave device 20 receives this address, and compares this address with its own address. If the addresses do not match, the slave device 20 waits in the STOP state. If the addresses match, the slave device 20 prepares to receive data.

  Next, the master device 10 transmits a signal to notify the slave device 20 that the transaction is a WRITE operation and not a READ operation. In one embodiment, the READ / WRITE signal is a single bit notification. After receiving the address, the slave device 20 transmits an acknowledge signal.

  The master device 10 can then start transmitting a byte-sized data word to the slave device 20. The slave device 20 can transmit an acknowledge signal after each data word. The transmission of the data word can be continued until all data is transmitted from the master device 10 to the slave device 20.

  When the data transmission is successfully completed, the master device 10 issues a STOP state. In one embodiment, the STOP state is realized when the master device allows the data line to be high when the clock is high. At this point, the serial bus is released and all devices will wait to issue further START states.

  In the READ operation, the master device 10 can transmit a READ bit. The slave device 20 transmits a byte-sized data word to the master device 10. Master device 10 transmits an acknowledge signal after each data word. When reception of all data is completed, the master device issues a STOP state.

  A special switch capable of emulating the operation of the above master device and slave device is inserted into the serial bus. This switch divides the bus into two or more, and each can have a master as its own bus.

  In the divided bus, data received from one or more slave devices 20 is stored in the memory 31 in the switch 30 using the same address, offset, and other formats according to the flowchart of FIG. Is done. The update of the memory 31 can be performed at any timing and at any interval that ensures that the memory 31 accurately reflects the data stored on one or more buses.

  When the master device 10 of a certain bus accesses the slave device 20 of the adjacent bus, the switch 30 receives the device address and compares this address with the address stored in the memory. When the address matches the address in the memory 31, the switch 30 transmits an acknowledge signal. Next, the switch 30 reads appropriate data from the memory 31 that is regularly updated, and starts transmitting this data to the master device 10. This flowchart is shown in FIG.

  Referring to FIG. 4, first, the emulation unit 32 receives a read request from the master device 10 to the slave device 20 existing on a bus different from the master device 10 (step S401).

  Next, the emulation unit 32 determines the address of the slave device 20 to be read (step S402).

  Next, the emulation unit 32 searches the storage location of the requested data in the memory 31 (step S403).

  Next, the corresponding data is extracted from the memory 31 (step S404), and the data is transmitted to the master device 10 (step S405). When there is no data in the memory 31, the operation is shown in FIG.

  In the above operation, the emulation unit 32 functions as a virtual slave device 20 ′ on the bus where the master device 10 exists.

  As a result, the master device 10 obtains target data by communicating with the switch 30 by the same method as that interoperating with the target slave device 20. With the above operation, the switch 30 emulates a two-wire serial bus transaction.

  Next, an operation example of the two-wire serial bus system 100 according to the present embodiment will be described.

  Operation Example 1: When the function of the switch 30 is turned off and the communication between the master and the slave is directly performed between the two systems, this is realized by passing the communication state as it is. As a whole circuit, the operation is the same as in a normal wired state without a switch.

  Operation Example 2: As shown in FIG. 5, the circuit is divided by turning on the switch, and each master device 10 operates as a master in an independent system on bus A and bus B. That is, the master device 10 can be activated in each system surrounded by a dotted line.

Operation Example 3: In FIG. 1, communication between the bus A and the bus B is performed in a state where the function of the switch 30 is turned on and the two systems are separated. At this time, the operation of the switch 30 on the bus B side is the same as that of the master device 10-1, and the master device 10-1 ′ (virtually reproduced master device 10-1) in the switch 30 is connected to the bus B. It communicates with the slave device 20-1.

  In this case, the master on the bus B is the master device 10-1 ′, and the master / slave device 40 functions as the slave device 20-1. When the master device 10-1 receives the data obtained by the master device 10-1 ', communication between the buses becomes possible.

  The operation when the bus A and the bus B are reversed is also possible. In this case, the switch 30 (emulating means 32) operates as the master device 10-2 ′ in the bus A.

  FIG. 3 shows a flowchart when the switch 30 receives data.

  First, the emulation unit 32 receives a read request from the master device 10 to the slave device 20 existing on a different bus from the master device 10 (step S301).

  Next, the emulation unit 32 determines the address of the reading target slave device 20 (step S302).

  Next, the emulation unit 32 transmits a data read request to the target slave device 20 as the virtual master device 10 ′, and transmits the received data to the master device 10 as a result. The address of the device 20 is stored in the memory 31 (steps S303 and S304).

  In the above operation, the emulation unit 32 functions as a virtual master device 10 ′ on the bus where the target slave device 20 exists.

  When parallel operation is enabled as a multi-master, as shown in FIG. 6, when the master device 10-1 and the slave device 20-2, and the master device 10-2 and the slave device 20-3 communicate, Can be shortened from t1 + t2 to a maximum of t1 (assuming t1> t2), and it can be seen that the idle time of the apparatus is reduced and the apparatus can operate simultaneously.

(Effects of the first embodiment)
According to the present embodiment, bidirectional communication that cannot be achieved with a simple bus switch or isolator and simultaneously function as a parallel circuit can be achieved. As described in the operation example 3, the availability of the circuit in the two-wire serial bus can be increased because communication can be performed for each bus while maintaining the small number of wires that is a merit of the serial bus.

  Further, according to the present embodiment, even if polling or the like is performed in one bus system, the other system can be used without making the bus busy.

  In addition, in the case of a daisy chain that connects all devices, the communication speed is limited to the slowest device. However, according to this embodiment, the circuit scale of I2C in one master can be reduced, and as shown in FIG. Slow devices can be selectively disconnected to another bus. Since the portion surrounded by the dotted line is a separate system, the line length restriction is relaxed within this range, and high-speed communication is also possible.

  Further, in addition to the above, high-speed communication that tends to be long wiring in a large-sized device and is difficult to use can be easily used by reducing the circuit scale.

  Here, a minimum configuration capable of solving the problems of the present invention will be described. As shown in FIG. 1, an information processing apparatus 200 is configured by a two-wire serial bus system 100, and includes a plurality of master devices 10, one or more slave devices 20, and at least one master on each divided bus. As the device 10 exists, the device includes a switch 30 that divides the bus into a plurality of buses, and the master device 10 operates as a master on each divided bus, thereby operating in parallel as a multi-master. The problems of the present invention described above can be solved.

  Next, a hardware configuration example of the information processing apparatus 200 configuring the two-wire serial bus system 100 of the present invention will be described with reference to FIG.

  Referring to FIG. 8, an information processing apparatus 200 according to the present invention has a hardware configuration similar to that of a general computer apparatus, and includes data such as a CPU (Central Processing Unit) 801 and a RAM (Random Access Memory). The main storage unit 802 used for the work area and data temporary save area, the communication unit 803 that transmits and receives data via the network, the input device 805, the output device 806, and the storage device 807 are connected to transmit and receive data. An input / output interface unit 804 and a system bus 808 for interconnecting the above-described components are provided. The storage device 807 is realized by, for example, a hard disk device including a non-volatile memory such as a ROM (Read Only Memory), a magnetic disk, and a semiconductor memory.

  Each function of the information processing apparatus 200 according to the present invention is implemented by hardware by mounting circuit components that are hardware components such as LSI (Large Scale Integration) incorporating a program. As another example, a program that provides the function may be stored in the storage device 807, loaded into the main storage unit 802, and executed by the CPU 801 to be realized in software.

  The present invention has been described above with reference to preferred embodiments. However, the present invention is not necessarily limited to the above embodiments, and various modifications can be made within the scope of the technical idea. it can.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, and the like are also effective as an aspect of the present invention.

  The various components of the present invention do not necessarily have to be independent of each other. A plurality of components are formed as a single member, and a single component is formed of a plurality of members. It may be that a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like.

  Moreover, although the several procedure is described in order in the method and computer program of this invention, the order of the description does not limit the order which performs a several procedure. For this reason, when implementing the method and computer program of this invention, the order of the several procedure can be changed in the range which does not interfere in content.

  The plurality of procedures of the method and the computer program of the present invention are not limited to being executed at different timings. For this reason, another procedure may occur during the execution of a certain procedure, or some or all of the execution timing of a certain procedure and the execution timing of another procedure may overlap.

  Further, a part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
An information processing apparatus constituted by a two-wire serial bus system,
Multiple master devices;
One or more slave devices;
A switch that divides the bus into a plurality of buses such that there is at least one master device on each bus after the division,
An information processing apparatus that operates in parallel as a multi-master by operating the master apparatus as a master on each divided bus.

(Appendix 2)
The switch is
The information processing apparatus according to appendix 1, wherein the slave apparatus having a low communication speed is selectively disconnected to another bus.

(Appendix 3)
An information processing apparatus constituted by a two-wire serial bus system,
One or more master devices;
One or more slave devices;
With a switch that divides the bus into multiple parts,
The switch
An information processing apparatus comprising an emulating unit that functions as a master device or a slave device.

(Appendix 4)
The switch is
Receiving means for receiving a read request from the master device to the slave device on another bus;
Determining means for determining an address of a slave device to be read;
A memory for storing data,
The emulating means comprises:
Functions as a virtual master device on the bus where the slave device exists, sends a read request to the slave device to be read, acquires data,
The information processing apparatus according to appendix 3, wherein the acquired data is transmitted to the master apparatus and stored in the memory as a set with the address.

(Appendix 5)
The emulating means comprises:
The supplementary note 4 is characterized in that, when the data stored as a set with the address determined by the determination means is not in the memory, a read request is transmitted to the slave device to be read to acquire the data. Information processing device.

(Appendix 6)
The emulating means comprises:
When data stored as a set with the address determined by the determination means is in the memory, the data functions as a virtual slave device on the bus where the master device exists, and the data stored in the memory is The information processing apparatus according to appendix 5, wherein the information processing apparatus transmits to the master apparatus.

(Appendix 7)
The switch is
The information processing apparatus according to any one of appendix 1 to appendix 6, further comprising: a switch switching unit that switches whether to divide the bus.

(Appendix 8)
A bus dividing method in an information processing apparatus configured by a two-wire serial bus system and including a plurality of master devices, one or more slave devices, and a switch,
Dividing the bus into a plurality of buses such that the switch has at least one master device on each divided bus; and
And a step of operating the master device as a master on each of the divided buses to operate in parallel as a multi-master.

(Appendix 9)
The bus dividing method according to appendix 8, wherein the switch includes a step of selectively separating the slave device having a low communication speed from another bus.

(Appendix 10)
A bus dividing method in an information processing apparatus configured by a two-wire serial bus system and including one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of devices,
The bus dividing method, wherein the emulation means included in the switch includes an emulation step that functions as a virtual master device or a slave device.

(Appendix 11)
A receiving step in which the receiving means included in the switch receives a read request from the master device to the slave device on another bus;
A determination unit included in the switch includes a determination step of determining an address of a slave device that is a target of the read request;
In the emulation step,
Functions as a virtual master device on the bus where the slave device exists, sends a read request to the slave device to be read, acquires data,
The bus division method according to appendix 10, wherein the acquired data is transmitted to the master device and stored in the memory in the switch as a set with the address.

(Appendix 12)
In the emulation step,
The supplementary note 11 is characterized by transmitting a read request to the slave device to be read and acquiring the data when the data stored as a set with the address determined by the determination means is not in the memory. Bus partitioning method.

(Appendix 13)
In the emulation step,
When data stored as a set with the address determined in the determination step is in the memory, the data functions as a virtual slave device on the bus on which the master device exists, and the data stored in the memory is The bus dividing method according to appendix 12, wherein the bus dividing method is transmitted to the master device.

(Appendix 14)
14. The bus dividing method according to any one of appendix 8 to appendix 13, wherein the switch switching means included in the switch includes a switch switching step for switching whether or not to divide the bus.

(Appendix 15)
A bus division program configured on a two-wire serial bus system and operating on a computer constituting an information processing device including a plurality of master devices, one or more slave devices, and a switch,
Causing the switch to execute a process of dividing the bus into a plurality of buses such that at least one master device exists on each divided bus;
A bus division program comprising: executing a process of operating in parallel as a multi-master by causing the master device to operate as a master on each divided bus.

(Appendix 16)
The bus division program according to appendix 15, wherein the switch causes the slave device having a low communication speed to be selectively disconnected from another bus.

(Appendix 17)
A bus division program in an information processing apparatus that is configured by a two-wire serial bus system and includes one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of pieces,
A bus division program that causes an emulation means included in the switch to execute an emulation process that functions as a virtual master device or a slave device.

(Appendix 18)
Causing the receiving means provided in the switch to execute a receiving process for receiving a read request from the master device to the slave device on another bus;
The determination means provided in the switch causes determination processing to determine the address of the slave device that is the target of the read request,
In the emulation process,
Functions as a virtual master device on the bus where the slave device exists, sends a read request to the slave device to be read, acquires data,
18. The bus division program according to appendix 17, wherein the acquired data is transmitted to the master device and is stored in the memory in the switch as a set with the address.

(Appendix 19)
In the emulation process,
Item 18. The supplementary note 18, wherein when the data stored as a set with the address determined by the determination unit is not in the memory, a read request is transmitted to the slave device to be read to acquire the data. Bus partitioning program.

(Appendix 20)
In the emulation process,
When data stored as a set with the address determined in the determination step is in the memory, the data functions as a virtual slave device on the bus on which the master device exists, and the data stored in the memory is The bus division program according to appendix 19, wherein the bus division program is transmitted to the master device.

(Appendix 21)
21. The bus division program according to any one of appendix 15 to appendix 20, wherein the switch switching unit included in the switch executes switch switching processing for switching whether to divide the bus.

  In the case of a large-scale device that connects a number of substrates connected in series, it is not intended for I2C, but is often used for its convenience, and its use may also be an important part such as a diagnostic system. The present invention can be used very effectively in a circuit configuration for performing large-scale high-speed communication in which signals are transmitted many times at high speeds using such a serial bus. For example, when polling with I2C when having a large number of temperature sensor ICs as a slave device in a large-scale device, the time loss due to occupying the bus in one system, the scale of the bus by dividing the bus with the switch according to the present invention And the polling time can be greatly reduced.

10, 10-1, 10-2, 10 ', 10-1': Master device 20, 20-1 to 20-4, 20 ': Slave device 30: Switch 31: Memory 32: Emulation means 33: Switch Switching means 40: Master / slave device 100: Two-wire serial bus system 200: Information processing device 801: CPU
802: Main storage unit 803: Communication unit 804: Input / output interface unit 805: Input device 806: Output device 807: Storage device 808: System bus

Claims (10)

An information processing apparatus constituted by a two-wire serial bus system,
Multiple master devices;
One or more slave devices;
A switch that divides the bus into a plurality of buses such that there is at least one master device on each bus after the division,
An information processing apparatus that operates in parallel as a multi-master by operating the master apparatus as a master on each divided bus. The switch is
The information processing apparatus according to claim 1, wherein the slave device having a low communication speed is selectively disconnected to another bus. An information processing apparatus constituted by a two-wire serial bus system,
One or more master devices;
One or more slave devices;
With a switch that divides the bus into multiple parts,
The switch
An information processing apparatus comprising an emulating unit that functions as a master device or a slave device. The switch is
Receiving means for receiving a read request from the master device to the slave device on another bus;
Determining means for determining an address of a slave device to be read;
A memory for storing data,
The emulating means comprises:
Functions as a virtual master device on the bus where the slave device exists, sends a read request to the slave device to be read, acquires data,
The information processing apparatus according to claim 3, wherein the acquired data is transmitted to the master apparatus and stored in the memory as a set with the address. The emulating means comprises:
5. The data is acquired by transmitting a read request to the slave device to be read when data stored as a set with the address determined by the determination means is not in the memory. The information processing apparatus described. The emulating means comprises:
When data stored as a set with the address determined by the determination means is in the memory, the data functions as a virtual slave device on the bus where the master device exists, and the data stored in the memory is The information processing apparatus according to claim 5, wherein the information processing apparatus transmits the information to the master apparatus. A bus dividing method in an information processing apparatus configured by a two-wire serial bus system and including a plurality of master devices, one or more slave devices, and a switch,
Dividing the bus into a plurality of buses such that the switch has at least one master device on each divided bus; and
And a step of operating the master device as a master on each of the divided buses to operate in parallel as a multi-master. A bus dividing method in an information processing apparatus configured by a two-wire serial bus system and including one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of devices,
The bus dividing method, wherein the emulation means included in the switch includes an emulation step that functions as a virtual master device or a slave device. A bus division program configured on a two-wire serial bus system and operating on a computer constituting an information processing device including a plurality of master devices, one or more slave devices, and a switch,
Causing the switch to execute a process of dividing the bus into a plurality of buses such that at least one master device exists on each divided bus;
A bus division program comprising: executing a process of operating in parallel as a multi-master by causing the master device to operate as a master on each divided bus. A bus division program in an information processing apparatus that is configured by a two-wire serial bus system and includes one or more master devices, one or more slave devices, and a switch that divides the bus into a plurality of pieces,
A bus division program that causes an emulation means included in the switch to execute an emulation process that functions as a virtual master device or a slave device.

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