JP2014153822A - Semiconductor device, communication system, camera shake correction controller, imaging apparatus, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication system of master slave system, by which a slave device can obtain the state of another slave device in a short communication time.SOLUTION: A semiconductor device 20 is used together with (i) a host device 10 having a master I/F circuit 12, and (ii) a slave device 30 having a slave I/F circuit 32 connected to the master I/F circuit 12 via a bus 40 and having a register 34 storing data. A data access section 26 is connected to the bus 40, and monitors data stream transmitted through the bus 40 to thereby obtain data stored in a predetermined word address of the register 34 of the slave device 30. The data access section 26, when the data stream transmitted through the bus 40 includes device address of the slave device 30 and the predetermined word address, configures data following the data stream to be extractable.

Description

  The present invention relates to master-slave serial data communication.

In master-slave serial data communication such as I ² C, a plurality of slave devices may be connected to one master device. FIG. 1A is a block diagram showing a configuration of a communication system examined by the present inventor, and FIG. 1B is a time chart showing its operation.

  The communication system 202 in FIG. 1A includes a host device 210, a first slave device 220, a second slave device 230, and a bus 240. The host device 210 includes a master interface (I / F) circuit 212, and the first slave device 220 and the second slave device 230 include slave I / F circuits 222 and 232, and registers 224 and 234 for storing data, respectively. .

The master I / F circuit 212 and the slave I / F circuits 222 and 232 are connected via a common bus 240. In a 2-wire serial interface such as an I ² C bus, the bus 240 includes a data line and a clock line, but is shown here as a single bus. Predetermined device addresses ADR1 and ADR2 are assigned to the slave I / F circuits 222 and 232, respectively.

  In master-slave data communication, data communication is possible between the master I / F circuit 212 and the slave I / F circuit 222, and between the master I / F circuit 212 and the slave I / F circuit 232. Direct data transmission between the F circuits 222 and 232 is not possible. Specifically, the master I / F circuit 212 can read data from an address designated by one of the internal registers selected from the slave devices 220 and 230 (Read), and the master I / F circuit. 212 can write data to the address designated by the internal register of one of the slave devices 220 and 230 (Write).

In such a communication system 202, a slave device 220 may wish to access data stored in a register 234 of another slave device 230. In this case, first, the master I / F circuit 212 reads data stored in the register 234 via the slave I / F circuit 232. Subsequently, the master I / F circuit 212 writes the data read from the register 234 to the register 224 via the slave I / F circuit 222. FIG. 1B shows a time chart at this time. Here, an I ² C communication data format is used.

  The first packet PCKT1 indicates a read operation from the slave device 230 to the host device 210, and the subsequent packet PCKT2 indicates a write operation from the host device 210 to the slave device 220.

  The packet PCKT1 will be described. The host device 210 transmits a device address ADR2 that designates the slave device 230 that is a read source, and then transmits a bit indicating a read operation (Read). In response to this, an acknowledge is returned from the slave device 230. Subsequently, the host device 210 transmits a word address adr2 indicating the access destination of the register 234 in the slave device 230. Subsequently, an acknowledge is returned from the slave device 230. Subsequently, the data stored in the address adr2 of the register 234 is transmitted from the slave device 230 to the host device.

  Subsequently, the host device 210 transmits a device address ADR1 designating the slave device 220 that is the write destination, and then transmits a bit indicating a write operation (Write). In response to this, an acknowledge is returned from the slave device 230. Subsequently, the host device 210 transmits a word address adr1 indicating the access destination of the register 224 in the slave device 220. Subsequently, an acknowledge is returned from the slave device 220. Subsequently, data is transferred from the host device to the slave device 220, and the data is written to the address adr 1 of the register 234.

  As described above, in the system of FIG. 1A, there is a problem that it takes a long communication time because communication occurs twice.

  2A is a block diagram showing another communication system 302 examined by the present inventor, and FIG. 2B is a time chart showing the operation thereof.

  The communication system 302 in FIG. 2A includes a host device (Integrated Circuit) 310, a first slave device 320, a second slave device 330, a first bus 340, and a second bus 350. The host device 310 includes a master I / F circuit 312. The first slave device 320 includes a master I / F circuit 326 in addition to the slave I / F circuit 322 and the register 324. The second slave device 330 includes a slave I / F circuit 336 in addition to the slave I / F circuit 332 and the register 334. The master I / F circuit 326 and the slave I / F circuit 336 are connected via the second bus 350. A predetermined device address ADR3 is assigned to the slave I / F circuit 336.

FIG. 2B shows an operation when the first slave device 320 accesses the data stored in the register 334 of the second slave device 330 in the communication system 302 of FIG.
The master I / F circuit 326 of the first slave device 320 transmits the device address ADR3 to the slave I / F circuit 332 of the second slave device 330, and then transmits a bit indicating a read operation. In response to this, an acknowledge is returned from the slave device 330. Subsequently, the master I / F circuit 326 transmits a word address adr2 indicating the access destination of the register 334 in the slave device 330. In response to this, an acknowledge is returned from the slave device 230. Subsequently, the data stored in the address adr2 of the register 334 is transmitted from the slave I / F circuit 336 of the slave device 330 to the master I / F circuit 326 of the slave device 320.

  As described above, according to the communication system 302 in FIG. 2A, the data of the slave device 330 can be transmitted to the slave device 320 by one data communication. However, since the I / F circuits 326 and 336 need to be added to the slave devices 320 and 330, and the bus 350 needs to be added, the circuit area increases.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary purposes of one aspect thereof is a master-slave communication in which a slave device can acquire the status of another slave device in a short communication time. In providing the system.

  A semiconductor device according to an aspect of the present invention includes (i) a host device having a master interface circuit, (ii) a first slave interface circuit connected to the master interface circuit via a bus, a register for storing data, The present invention relates to a semiconductor device used together with a slave device having a master-slave communication system. The semiconductor device has a second slave interface circuit connected to the master interface circuit via the bus, and a predetermined word in the register of the slave device by monitoring the data stream connected to the bus and transmitted via the bus. A data access unit that acquires data stored in the address. The data access unit is configured to be able to extract data following the data stream when the data stream transmitted via the bus includes a device address of the slave device and a predetermined word address.

  According to this aspect, by monitoring data communication between the host device and the slave device by the data access unit, the data stored in the predetermined address of the slave device register from the semiconductor device while suppressing an increase in circuit area. Can be obtained.

The data access unit may extract data following the data stream when the data stream includes a control instruction instructing reading.
According to this aspect, when the slave device autonomously updates the data stored in the predetermined word address, the semiconductor device can acquire the value of the data.

The data access unit may extract data following the data stream when the data stream includes a control instruction that instructs writing.
According to this aspect, when the data stored in the predetermined word address of the slave device is updated by the host device, the semiconductor device can acquire the value of the data.

  The semiconductor device according to an aspect may further include an address register. Immediately after activation of the communication system, the master interface circuit of the host device may write the device address of the slave device and a predetermined word address to the address register via the second slave interface circuit of the semiconductor device.

  The semiconductor device according to an aspect may further include a nonvolatile memory that stores a device address of the slave device and a predetermined word address.

  Another aspect of the invention relates to a communication system. The communication system includes: (i) a host device having a master interface circuit; (ii) a first slave interface circuit connected to the master interface circuit via a bus; and a slave device having a register for storing data; (Iii) Any one of the semiconductor devices described above may be provided.

  Another embodiment of the present invention relates to an electronic device. This electronic apparatus includes the above-described communication system.

  Another embodiment of the present invention relates to a camera shake correction controller used in an image pickup apparatus with a camera shake correction mechanism or an image pickup apparatus using the same. The image pickup apparatus includes a camera shake correction controller that controls an actuator for positioning a camera shake correction lens, a gyro sensor, a host processor that controls the image pickup apparatus in an integrated manner, and a camera shake correction controller and a gyro sensor using the host processor as a host device. A bus connected as a slave device. The host processor has a master interface circuit connected to the bus. The gyro sensor includes a first slave interface circuit connected to the master interface circuit via a bus, and a register that stores detected angular velocity data. The image stabilization controller is stored in the register of the gyro sensor by monitoring the second slave interface circuit connected to the master interface circuit via the bus and the data stream connected to the bus and transmitted via the bus. A data access unit for acquiring angular velocity data. The data access unit is configured to be able to extract data following the data stream when the data stream transmitted via the bus includes a device address of the gyro sensor and a word address indicating an address where the angular velocity data is stored. The

  Another embodiment of the present invention relates to an electronic device. This electronic apparatus includes the above-described imaging device.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the communication system of the present invention, a semiconductor device can acquire the state of another slave device in a short communication time.

FIG. 1A is a block diagram showing a configuration of a communication system examined by the present inventor, and FIG. 1B is a time chart showing its operation. 2A is a block diagram showing another communication system examined by the present inventor, and FIG. 2B is a time chart showing the operation thereof. It is a block diagram which shows the structure of the communication system which concerns on embodiment. It is a time chart which shows operation | movement of the communication system of FIG. It is a block diagram of an imaging device with a shake mechanism using a communication system. It is a block diagram which shows an example of an electronic device.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 3 is a block diagram showing a configuration of the communication system 2 according to the embodiment. The communication system 2 includes a host device 10, a semiconductor device 20, and a slave device 30.
The host device 10 includes a master I / F circuit 12. The host device 10 is configured to control the entire communication system 2 as a whole, access registers in the semiconductor device 20 or the slave device 30, and read / write data.

  The slave device 30 includes a slave I / F circuit 32 connected to the master I / F circuit 12 via a bus 40, and a register 34 for storing various data. The device address of the slave device 30 is ADR2. The register 34 also includes word addresses adr2_1, adr2_2,.

  The semiconductor device 20 according to the embodiment is used together with the host device 10 and the semiconductor device 20, and constitutes a master-slave communication system 2.

The semiconductor device 20 includes a slave I / F circuit 22, a register 24, and a data access unit 26. The slave I / F circuit 22 is connected to the master I / F circuit 12 of the host device 10 via the bus 40. The master I / F circuit 12, the slave I / F circuit 22, and the slave I / F circuit 32 may conform to, for example, an I ² C bus format.

  The data access unit 26 is connected to the bus 40, and monitors a data stream transmitted between the host device 10 and the slave device 30 via the bus 40, so that a predetermined word address of the register 34 of the slave device 30 is obtained. Data DATA_X stored in (i-th adr2_i) is acquired.

  When the data stream transmitted via the bus 40 includes a device address ADR2 of the slave device 30 and a predetermined word address adr2_i, the data access unit 26 is configured to be able to extract data DATA_X following the data stream. .

  For example, the data access unit 26 includes a data extraction unit 28 and an address reference unit 29. The register 24 includes a data register 24a and an address register 24b. Data indicating the device address ADR2 and the word address adr2_i of the slave device 30 is stored in the address register 24b.

  The host device 10 knows the device addresses of the semiconductor device 20 and the slave device 30. It also knows the word address of the register 24 of the semiconductor device 20 and the word address of the register 34 of the slave device 30.

  Therefore, immediately after the communication system 2 is started, the master I / F circuit 12 of the host device 10 sends the device address ADR2 of the slave device 30 and a predetermined word to the address register 24b via the slave I / F circuit 22. The address adr2_i may be written.

The address reference unit 29 compares the device address and the word address included in the data stream transmitted through the bus 40 with the device address and the word address stored in the address register 24b, and determines whether or not they match. The determination signal S1 is asserted (for example, high level).
When the determination signal S1 is asserted, in other words, when the coincidence determination is made by the address reference unit 29, the data extraction unit 28 extracts the data DATA_X following the word address and stores it in the data register 24a.

  When the data stream transmitted through the bus 40 includes a control command (Read) that instructs reading, the data access unit 26 extracts data DATA_X that follows the data stream.

The above is the configuration of the communication system 2. Next, the operation will be described.
FIG. 4 is a time chart showing the operation of the communication system 2 of FIG.
For example, it is assumed that the semiconductor device 20 wants to acquire the data DATA_X of the address adr2_i of the slave device 30 at a predetermined cycle. In this case, the host device 10 outputs the first data stream DS1 shown in FIG. 4 to the slave device 30 at the same cycle. The first data stream DS1 includes a device address ADR2 of the slave device 30 and a read command Read. In response to the first data stream DS1, the slave device 30 returns an acknowledge. The host device 10 that has received the acknowledgment subsequently outputs the second data stream DS2 including the word address adr2_i. In response to this, the slave device 30 returns an acknowledge, and then transmits the data DATA_X stored in the word address adr2_i to the host device 10.

  During this time, the address reference unit 29 of the data access unit 26 detects that the device address included in the first data stream DS1 matches the device address ADR2 of the slave device 30, and the control command is Read. Further, the address reference unit 29 of the data access unit 26 detects that the word address included in the subsequent second data stream DS2 matches the predetermined word address adr2_i, and asserts the determination signal S1. When the determination signal S1 is asserted, the data extraction unit 28 extracts the data DATA_X included in the third data stream DS3 and stores it in the data register 24a.

The above is the operation of the communication system 2.
According to the communication system 2, the semiconductor device 20 can acquire the data of the slave device 30 by one data access from the host device 10 to the slave device 30. In this communication system 2, since the two data accesses shown in FIG. 1B are shortened to one time, the communication time can be shortened. Further, since the bus 350 as shown in FIG. 2A is unnecessary, an increase in circuit area can be suppressed.

The above processing can be used in the following two cases.
The first case is a case where the host device 10 itself needs data DATA_X. In this case, the data access by the host device 10 may be unrelated to the operation of the semiconductor device 20.

  The second case is a case where the host device 10 itself does not need the data DATA_X, and only the semiconductor device 20 needs the data DATA_X. In this case, the host device 10 performs the data access of FIG. 4 in order to cause the semiconductor device 20 to acquire the data DATA_X of the slave device 30.

  Next, the use of the communication system 2 will be described. The communication system 2 is used for various electronic devices equipped with a master-slave data communication system, such as a mobile phone terminal, a smart phone, a tablet PC, a digital camera, an audio player, a PC (Personal Computer), a television, and a hard disk recorder. Can do.

FIG. 5 is a block diagram of an imaging apparatus with a shake mechanism using a communication system.
The imaging apparatus 500 includes an imaging unit 501, a camera shake correction lens 502, an actuator 504, a host controller 510, a camera shake correction controller 520, a gyro sensor unit 530, and a bus 540. The host controller 510, the camera shake correction controller 520, and the gyro sensor unit 530 correspond to the host device 10, the semiconductor device 20, and the slave device 30 in FIG.

  The imaging unit 501 is a CMOS sensor or a CCD, and generates image data. The imaging unit 501 is connected to the host controller 510 via the bus 540 and can be controlled from the host controller 510.

  The actuator 504 positions the camera shake correction lens 502. The gyro sensor unit 530 detects an angular velocity around at least one axis of the imaging apparatus 500. The camera shake correction controller 520 controls the actuator 504 based on the angular velocity data detected by the gyro sensor unit 530.

  The gyro sensor unit 530 includes a gyro sensor 36 in addition to the slave I / F circuit 32 and the register 34. The gyro sensor 36 detects the angular velocity at a predetermined cycle, and updates the angular velocity data DATA_X stored in the address adr2_1 of the register 34.

  The camera shake correction controller 520 includes an actuator driver 21 in addition to the slave I / F circuit 22, the register 24, and the data access unit 26. The data access unit 26 monitors the data stream transmitted via the bus 540, acquires the angular velocity data DATA_X stored in the address adr2_1 of the register 34 in the gyro sensor unit 530, and writes it into the data register 24a. The actuator driver 21 controls the actuator 504 based on the angular velocity data DATA_X stored in the data register 24a.

  FIG. 6 is a block diagram illustrating an example of the electronic device 600. The electronic device 600 is a digital camera including an imaging device 500 with a camera shake correction mechanism. The electronic device 600 includes a housing 602, a shutter button 604, a grip 606, a lens 608, and the like. Inside the housing 602, the above-described imaging device 500 with camera shake correction is built.

  The electronic device 600 may be a digital video camera, a mobile phone terminal with an imaging function, a smart phone, a tablet PC, or an audio player.

  By using the communication system 2 of FIG. 3, in such an electronic apparatus, a certain device can acquire the state of another device in a short communication time. By shortening the communication time, the number of times data is acquired can be increased.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(Modification 1)
In the embodiment, the case has been described in which the data access unit 26 acquires the data DATA_X when the data stream transmitted through the bus 40 includes the control command READ instructing reading. However, the present invention is not limited to this. .
In some cases, the data DATA_X stored in the register 34 of the slave device 30 can be updated by writing from the host controller 510. In this case, the data access unit 26 may acquire the data DATA_X when the data stream transmitted through the bus 40 includes a control command WRITE instructing writing.

(Modification 2)
In the embodiment, the case where the host device 10 notifies the semiconductor device 20 of the device address and the word address of the slave device 30 when the communication system 2 is activated has been described, but the present invention is not limited thereto.
For example, when the designer of the semiconductor device 20 knows the device address of the slave device 30 and the predetermined word address adr2_i in advance, they may be stored in a nonvolatile memory inside the semiconductor device 20. . Alternatively, the device address of the slave device 30 and the predetermined word address may be supplied from another control pin of the semiconductor device 20 without going through the slave I / F circuit 22.

(Modification 3)
In the embodiments, the I2C bus has been described as an example. However, the present invention is not limited thereto, and is applied to other serial data transmission systems such as SPI (System Packet Interface) and I ² S (Inter IC Sound). be able to.

(Modification 4)
In the embodiment, the case where the semiconductor device 20 acquires data of a single word address of the register 34 of the single slave device 30 has been described, but the present invention is not limited to this. For example, the semiconductor device 20 may acquire data DATA_X, DATA_Y,... Of a plurality of word addresses adr2_i, adr2_j,. In this case, a plurality of word addresses adr2_i and adr2_j may be stored in the address register 24b of the semiconductor device 20.
Alternatively, as shown in FIG. 5, when a plurality of slave devices (501, 530) are connected to the host device (host controller 510), the semiconductor device (camera shake correction controller 520) is connected to the first slave device (501). ) Register data and the second slave device (530) register data. In this case, a plurality of device addresses may be stored in the address register 24b of the semiconductor device 20.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 2 ... Communication system, 10 ... Host device, 12 ... Master I / F circuit, 20 ... Semiconductor device, 22 ... Slave I / F circuit, 24 ... Register, 24a ... Data register, 24b ... Address register, 26 ... Data Access unit 28 ... Data extraction unit 29 ... Address reference unit 30 ... Slave device 32 ... Slave I / F circuit 34 ... Register 40 ... Bus 500 ... Electronic device 510 ... Host controller 520 ... Shake correction Controller, 530 ... Gyro sensor unit.

Claims (15)

(I) a host device having a master interface circuit; (ii) a first slave interface circuit connected to the master interface circuit via a bus; and a slave device having a register for storing data. A semiconductor device constituting a master-slave communication system,
The semiconductor device is:
A second slave interface circuit connected to the master interface circuit via the bus;
A data access unit connected to the bus and acquiring data stored in a predetermined word address of the register of the slave device by monitoring a data stream transmitted through the bus;
With
The data access unit is configured to be able to extract data following the data stream when the data stream transmitted via the bus includes a device address of the slave device and the predetermined word address. A featured semiconductor device.   The semiconductor device according to claim 1, wherein the data access unit extracts data following the data stream when the data stream includes a control command instructing reading.   The semiconductor device according to claim 1, wherein the data access unit extracts data following the data stream when the data stream includes a control instruction instructing writing. An address register;
Immediately after activation of the communication system, the master interface circuit of the host device receives the device address of the slave device and the predetermined word in the address register via the second slave interface circuit of the semiconductor device. 4. The semiconductor device according to claim 1, wherein an address is written.   4. The semiconductor device according to claim 1, further comprising a control pin that receives a device address of the slave device and data indicating the predetermined word address. 5.   4. The semiconductor device according to claim 1, further comprising a non-volatile memory that stores a device address of the slave device and the predetermined word address. A host device having a master interface circuit;
A slave device having a first slave interface circuit connected to the master interface circuit via a bus, and a register for storing data;
A semiconductor device according to any one of claims 1 to 6;
A communication system comprising:   An electronic apparatus comprising the communication system according to claim 7. A camera shake correction controller for controlling an actuator for positioning a camera shake correction lens used in an imaging apparatus with a camera shake correction mechanism,
In addition to the camera shake correction controller, the imaging device includes:
Gyro sensor,
A host processor for overall control of the imaging device;
A bus for connecting the image stabilization controller and the gyro sensor as a slave device with the host processor as a host device;
With
The host processor has a master interface circuit connected to the bus,
The gyro sensor has a first slave interface circuit connected to the master interface circuit via the bus, and a register for storing detected angular velocity data,
The image stabilization controller is
A second slave interface circuit connected to the master interface circuit via the bus;
A data access unit connected to the bus and acquiring the angular velocity data stored in the register of the gyro sensor by monitoring a data stream transmitted via the bus;
With
When the data stream transmitted via the bus includes a device address of the gyro sensor and a word address indicating an address where the angular velocity data is stored, the data access unit extracts data following the data stream. An image stabilization controller that is configured to be capable of being used.   The camera shake correction controller according to claim 9, wherein the data access unit extracts data following the data stream when the data stream includes a control command for instructing reading. The image stabilization controller further includes an address register,
Immediately after activation of the communication system, the master interface circuit of the host device receives the device address of the slave device and the predetermined word in the address register via the second slave interface circuit of the semiconductor device. The camera shake correction controller according to claim 9 or 10, wherein an address is written. An imaging device with a camera shake correction mechanism,
A camera shake correction controller for controlling an actuator for positioning the camera shake correction lens;
Gyro sensor,
A host processor for overall control of the imaging device;
A bus for connecting the image stabilization controller and the gyro sensor as a slave device with the host processor as a host device;
With
The host processor has a master interface circuit connected to the bus,
The gyro sensor has a first slave interface circuit connected to the master interface circuit via the bus, and a register for storing detected angular velocity data,
The image stabilization controller is
A second slave interface circuit connected to the master interface circuit via the bus;
A data access unit connected to the bus and acquiring the angular velocity data stored in the register of the gyro sensor by monitoring a data stream transmitted via the bus;
With
When the data stream transmitted via the bus includes a device address of the gyro sensor and a word address indicating an address where the angular velocity data is stored, the data access unit extracts data following the data stream. An imaging device characterized by being configured.   The imaging apparatus according to claim 12, wherein the data access unit extracts data following the data stream when the data stream includes a control command for instructing reading. The image stabilization controller further includes an address register,
Immediately after activation of the communication system, the master interface circuit of the host device receives the device address of the slave device and the predetermined word in the address register via the second slave interface circuit of the semiconductor device. 14. The imaging apparatus according to claim 12, wherein an address is written.   An electronic apparatus comprising the imaging device according to claim 12.

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