JP2014150573A - Information reproducing device and information reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system which realizes flexible correspondence in accordance with received video information, has high in operation rate and efficiency.SOLUTION: A video signal display device includes two systems from a tuner portion to a demultiplexer. The device receives an RF signal including a plurality of transport streams. When at least one of first compression video data and second compression video data is large throughput per unit time based on a profile and a level, the first compression video data and the second compression video data are extracted in parallel and desired video is displayed.

Description

The present invention relates to a video signal processing apparatus, and more particularly to decoding of MPEG2 compressed video data and the like.

FIG. 4 is a diagram showing a conventional video signal processing apparatus described on page 66 of the Nikkei Microdevice May 1997 issue. In FIG. 4, 1 is an antenna, 2 is a tuner, 3 is a demodulator,
4 is a demultiplexer, 51 and 52 are decoders, 6 is a display processor, and 7 is a video output.

FIG. 10 is a diagram showing a conventional demultiplexer 4. In FIG. 10, reference numeral 400 denotes a distributor for separating transport stream packets, 402 denotes a transport stream input, 403 denotes compressed audio data output, 404 denotes other data output, and 405 denotes compressed video data output.

FIG. 11 is a diagram showing a conventional display processor 6. In FIG. 11, 7 is a video output, 620 is a switch, 621 is a determination unit for determining a decoding area, 631 and 63
Reference numeral 2 denotes an input of decoding results of the decoders 51 and 52, and reference numerals 641 and 642 denote memories for storing decoded data.

The antenna 1 outputs the received RF signal to the tuner 2. However, when the antenna 1 is a satellite broadcast antenna, an IF signal is output from a converter attached to the satellite broadcast antenna. The tuner 2 performs channel selection by performing frequency selection processing on the RF signal or IF signal. The extracted signal is restored to a transport stream by the demodulator 3. Further, the restored transport stream is separated by the distributor 400 of the demultiplexer 4 into data constituting the transport stream, for example, compressed video and compressed audio data. The separated video data is output to the decoders 51 and 52. The reason why the two decoders are provided is that high-definition video requires a large amount of processing to decode the high-definition video, and cannot be decoded with only one decoder currently in practical use.

If the received video data is a high-definition video (in this case, 1080i), the decoders 51 and 52 share and decode the video data. For example, the screen is divided into upper and lower parts, and the upper half is decoded on the one hand and the lower half on the other hand. If the received video data is a standard video (here, 480i), decoding is performed by only one decoder. The decryption result is
Passed to the display processor 6. In this case, the decoder 51 passes information indicating the video format together with the decoded video data to the display processor 6 as a decoding result.

The display processor 6 stores the decoding results passed from the decoders 51 and 52 in the memories 641 and 642, respectively. Then, by reading the decoding results stored in the memories 641 and 642, one screen is configured. The reading method in this case is the type of video at that time,
It depends on the display mode.

When the video at this time is a high-definition video (1080i), one screen is configured by combining the decoding results stored in the memory 641 and the memory 642. This combination is realized by switching the memory from which the video data is read at a predetermined timing by the switch 620. For example, the switch 620 is switched so that reading from the memory 641 is performed when data on the upper half of the screen is output, and reading is performed from the memory 642 when data at the lower half of the screen is output.

On the other hand, when the video at this time is the standard video (480i), the decoding result is output only from the decoder 51. The display processor 6 stores this in the memory 641 and
This is read as it is to constitute one screen. In this case, the switch 620 is always in the state where the memory 641 is selected.

Note that the selection state of the switch 620, that is, the type of video at this time is determined as follows. That is, the decoding result output from the decoder 51 and stored in the memory 641 includes information indicating the video format of the video. The determination unit 621 in the display processor 6 reads out this information and determines the content thereof.
The type of video at that time is determined. Then, the switch 620 is switched according to the determination result.

In the conventional video signal processing device, when the high-definition video is not decoded, one decoder,
In the above-described example, the decoder 52 is not used at all and is wasted. In addition, when high-definition video is not transmitted, there is a possibility that only one of the videos can be viewed even though a plurality of 480i or 480p video signals are likely transmitted. . In order to view two images at the same time, it is necessary to provide two systems of the entire circuit shown in FIG. 9, which is difficult to realize in terms of cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing apparatus that has a high decoder operation rate and that can enjoy a number of digital video images on a single screen.

The present invention has been made to achieve the above object, and information reproduction for reproducing a digital video signal based on an input signal including a high-definition digital video signal or a plurality of standard digital video signals. A transport stream comprising a packet including an ID signal for identifying a data type, wherein the input signal includes information indicating a profile and level defined in MPEG2 or a video format. The first reproduction means for reproducing the first digital video signal among the plurality of types of digital video signals, and the second reproduction unit different from the first digital video signal among the plurality of types of digital video signals. Second reproduction means for reproducing a digital video signal, and either the first digital video signal or the second digital video signal And separating means for outputting each digital video signal to the first reproduction means or the second reproduction means, and the separation means separates the packet from the transport stream and provides a plurality of types of digital signals. A video signal is formed, and a predetermined digital video signal is selected from a plurality of types of digital video signals based on information indicating a video format.
Or a predetermined output port, and the input signal includes a determination signal for determining whether the separation means is the first digital video signal or the second digital video signal, The determination signal includes video-related information that is information corresponding to the profile and level of the digital video signal or the video format, and includes first video-related information corresponding to the first digital video signal and a second digital video signal. There is provided an information reproducing apparatus characterized in that the corresponding second video related information is different.

According to the video signal processing apparatus of the present invention, it is possible to flexibly cope with the received video information. In addition, it is possible to provide a system with a high operating rate and no waste.

Furthermore, it is possible to arbitrarily select and decode compressed video data from a plurality of transport streams. Therefore, it is possible to process a plurality of videos sent through different physical channels or broadcast networks at a time.

When the display processing unit further includes a configuration for simultaneously displaying a plurality of videos on one screen, the plurality of videos decoded in parallel can be displayed on one screen at a time.

It is a block diagram which shows the structure of the video signal processing apparatus in Embodiment 1 of this invention. 3 is a block diagram illustrating a configuration of a demultiplexer according to Embodiment 1. FIG. 3 is a block diagram illustrating a configuration of a display processor according to Embodiment 1. FIG. It is a block diagram which shows the structure of the conventional video signal processing apparatus. It is a block diagram which shows the structure of the video signal processing apparatus in Embodiment 2 of this invention. 6 is a block diagram illustrating a configuration of a demultiplexer according to Embodiment 2. FIG. 6 is a block diagram illustrating a configuration of a display processor in Embodiment 2. FIG. It is a block diagram which shows the structure of the video signal processing apparatus in Embodiment 3 of this invention. It is a block diagram which shows the structure of the video signal processing apparatus in Embodiment 4 of this invention. It is a block diagram which shows the structure of the conventional demultiplexer. It is a block diagram which shows the structure of the conventional display processor.

Embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG. The first embodiment is MPEG2 (Moving Picture Exp.)
This is a video signal processing device that processes video data in conformity with erts Group Phase 2). In particular, in the present embodiment, a video signal having a large processing amount per unit time required for decoding is decoded and shared by a plurality of decoders, while a plurality of video signals having a small processing amount per unit time required for decoding are provided. When included, the main feature is that each video signal is decoded by each decoder. The processing amount per unit time required for decoding is basically larger as the image resolution is higher. But,
This amount of processing is not determined only by the resolution, but also varies depending on the transmission rate at the time of transmission, the compression method, and the like. In this embodiment, before decoding, it is based on the profile and level defined in MPEG2. In addition, after the decoding, the sharing method is set in advance based on the video format.

Hereinafter, the first embodiment will be described in detail with reference to FIG. 1, FIG. 2, and FIG.

As shown in FIG. 1, the video signal processing apparatus according to the first embodiment includes a demultiplexer 4, decoders 51 and 52, and a display processor 6. In addition, the same code | symbol is attached | subjected to the same function structural part as a prior art example, and description is abbreviate | omitted. The antenna 1, the tuner 2 and the demodulator 3 are the same as in the prior art.

The demultiplexer 4 is based on the information included in the packet of the transport stream input from the demodulator 3, the content of the transmitted data, for example, whether it is a video,
Also, the resolution of the video is discriminated, and each is output separately. In MPEG2, an ID number for identifying a packet is assigned to the header portion of the packet. As information for identifying whether the content of each packet is video or audio, the program association table is also included in the packet with ID = 0, and ID
= 1 is provided with a program map table. The demultiplexer 4 performs the above-described determination based on information described in the program association table and the program map table. The structure of the video data separated by the demultiplexer 4 has a hierarchical structure defined by MPEG2. That means
The sequence header and sequence extension provided at the beginning describe the profile and level that define the capability required of the decoder, and information indicating the video format, for example, the number of pixels in the horizontal direction and the number of scanning lines.

Specifically, the demultiplexer 4 in the present embodiment includes a distributor 4 as shown in FIG.
00, a switch 401 is provided. As outputs, a compressed audio data output 403, other data outputs 404, and compressed video data outputs 405 and 406 are provided.

A switch 401 in FIG. 2 is for switching compressed video data output from the outputs 405 and 406. In particular, in the first embodiment, what kind of compressed video data is output from the outputs 405 and 406 is actually set in advance in the demultiplexer 4 in accordance with the profile and level defined in MPEG2. Has been. In the present embodiment, in the case of high definition video, the same compressed video data is output from both the output 405 and the output 406. When a plurality of standard videos (480i) and 480p videos are included, the demultiplexer 4 selects two of them and outputs 40
5 and 406 are output separately. The output 405 is output to the decoder 51.
On the other hand, the output 406 is input to the decoder 52.

The decoders 51 and 52 are for decoding the compressed video data input from the demultiplexer 4. The decoders 51 and 52 have a function of determining by themselves the data area to be decoded according to the video format described in the sequence header of the input compressed video data. Which area is to be decoded is preset in the decoders 51 and 52 in accordance with the video format of the video. In particular,
The decoder 51 decodes only the upper half when high definition video (1080i or 720p in the present embodiment) is input, and decodes the whole when a normal standard image is input. Is set to On the other hand, the decoder 52 is set to decode only the lower half when a high-definition video is input, and to decode the whole when a normal standard image is input. . That is, the decoders to which the same compressed video data is input have a decoding area set so that the compressed video data is shared and decoded. Each of the decoders 51 and 52 has a necessary and sufficient capability for decoding at least half of the high-definition video.

The correspondence between the decoder capability (profile and level) and video data compliant with MPEG2 is as follows. That is, the main profile @ main level is 4
It corresponds to 80i video. Main profile @ high level (1440) corresponds to a 480p video. Main profile @ high level high definition video (1080i, 720p)
Corresponds to the video.

The decoders 51 and 52 output the decoding result to the display processor 6. The decoding result includes the video format included in the above-described sequence header and the like in addition to the decoded video data.

The display processor 6 receives the decoding results from the decoders 51 and 52, and constitutes one screen by the video data included in the decoding results. As shown in FIG. 3, the display processor 6 includes memories 641 and 642, a determination unit 621, a switch 620, and filters 650 and 651.

The memory 641 stores the decoding result sent from the decoder 51. The memory 642 accumulates the decoding result sent from the decoder 52.

The determination unit 621 and the switch 620 determine the source of the data to be read at that time (memory 641 according to the video format included in the decoding results accumulated in the memories 641 and 642).
, Memory 642). Depending on how the determination unit 621 and the like operate, one screen is configured, for example, one image is displayed on the entire screen, or one screen is divided into two left and right to display different images in the respective areas. It will be decided. These operation methods, that is, switching of the switch 620 is preset in the display processor 6 in accordance with the video format.

Filters 650 and 651 perform pixel interpolation of video data. These filters 6
By performing pixel interpolation with 50 and 651, even when the resolution of the video data is different from the resolution of the display device, the video can be displayed on the entire screen of the display device.

The “separator” in the claims corresponds to the demultiplexer 4 in the present embodiment. The “decoding unit” corresponds to the decoders 51 and 52. The “display processing unit” corresponds to the display processor 6. The “multiplexed compressed video signal” corresponds to a transport stream. The “output port” corresponds to the outputs 405 and 406 of the demultiplexer 4. “Decoded video data” corresponds to a decoding result output from the decoders 51 and 52.

Next, the operation will be described.

An RF signal received by the antenna 1 is output to the tuner 2. However, when the antenna 1 is a satellite broadcast antenna, an IF signal from a converter attached to the satellite broadcast antenna is output to the tuner 2. The tuner 2 performs frequency selection processing, that is, channel selection, on the RF signal or IF signal. The extracted signal is restored to a transport stream by the demodulator 3. This transport stream is output to the input 402 of the demultiplexer 4.

The demultiplexer 4 separates video data, audio data, and the like from the transport stream packet input from the demodulator 3. Each separated data is distributed by the distributor 400 and output from the corresponding outputs 403, 404, and the like. in this case,
As for the compressed video data, the switch 401 is switched according to the profile and level of the compressed video data, so that the compressed video data output from the outputs 405 and 406 is switched. Specifically, when the data is a high definition video, the same compressed video data is output from both the output 405 and the output 406. On the other hand, standard video (480i) and 48
When a plurality of 0p videos are included, the demultiplexer 4 selects two of them,
Output from outputs 405 and 406 separately. In this case, the structure of the video data separated by the demultiplexer 4 has a hierarchical structure defined by MPEG2, and the sequence header and sequence extension include information indicating the profile, level, and video format (for example, horizontal direction). Number of pixels, number of scanning lines, aspect ratio, frame rate, interlace /
Progressive) etc. are described.

The decoders 51 and 52 confirm the video format of the video by checking the sequence header of the video data input from the demultiplexer 4 at that time. Then, only the area set in advance according to the video format is decoded. When high-definition video is input, areas set to be decoded are different between the decoder 51 and the decoder 52. Therefore, as a result, the decoder 51 and the decoder 52 share each other and decode the entire high-definition video. The decoders 51 and 52 output the decoding result including the decoded video data and the video format to the display processor 6.

The display processor 6 stores the decoding results input from the decoders 51 and 52 in the memory 641 and the memory 642, respectively. Determination unit 621 of display processor 6
Determines the video format included in the decoding result, and configures one video by switching the switch 620 at a predetermined timing according to the determination result. That is, when the original video is one high-definition video, the switch 620 is switched at a half position of one field to configure one screen as in the conventional example. On the other hand, when the decoder 51 and the decoder 52 are decoding different videos, the switch 620 is switched at a half position of one line. Thereby, it can divide | segment into the area | region of the right half and the area | region of the left half of one screen, and can display a different image | video for every area | region. Note that when a selection instruction from the user is received in an operation unit (not shown), only one of the plurality of videos selected is displayed.

When two video signals are displayed on the left and right of one screen, the video data and the resolution of the display may not match. For example, when two standard images composed of horizontal 720 pixels and vertical 480 lines are displayed on a high-definition display having horizontal 1920 pixels and vertical 1080 lines, they are not displayed on the full screen. However, if pixel interpolation is performed by the filters 650 and 651, the image can be displayed on the entire screen. If the decoder is decoding high-definition video,
The filters 650 and 651 are disabled. However, when one standard video is displayed on the entire screen, or when two standard videos are displayed side by side on the same screen, the input standard is obtained by the pixel interpolation by the filter 650 or the like. The video is converted into a 1920 × 1080 image.

When two or more videos are displayed at a time, selection by the user is accepted for audio, and only the compressed audio data of the selected video is separated and output from the audio data output 403 by the distributor 400.

According to the video signal processing apparatus of the first embodiment described above, when a video signal having a large processing amount per unit time required for decoding is decoded using a plurality of decoders, processing per unit time required for decoding is performed. When a plurality of video signals having a small amount are included, each video signal is decoded by each decoder. In addition, the display processor can display one or a plurality of decoded video signals on one screen or one or a divided screen. Therefore, a decoder or the like can be used more effectively.

In the present embodiment, by setting the decoding area for each decoder in advance, each decoder performs the decoding without sharing each other. But,
The sharing method is not limited to the present embodiment. For example, an independent control unit may be provided, and after the control unit determines the video format, an area to be assigned to each decoder for decoding may be indicated each time.

Embodiment 2. FIG. The main feature of the second embodiment is that it includes four decoders and uses them according to the profile and level of video data, the video format, and the like.
The configuration of the second embodiment corresponds to the provision of four decoders, except that the output of the demultiplexer 4 and the memory in the display processor 6 are divided into four systems. It is the same. Therefore, the following description will be focused on points different from the first embodiment.

FIG. 5 is a block diagram showing an outline of the video signal processing apparatus according to the second embodiment. FIG. 6 is a block diagram showing a configuration of the demultiplexer 4 in the second embodiment. FIG.
6 is a block diagram illustrating a configuration of a display processor 6 according to Embodiment 2. FIG. In FIG. 5, reference numerals 51, 52, 53 and 54 denote decoders. In FIG. 6, 400 is a, b, c, d4.
A distributor with a system output. Reference numeral 401 denotes a switch for switching compressed video data to be output from the outputs 405, 406, 407, and 408 among the data output from the systems a, b, c, and d. The setting state of the switch 401 is determined in advance according to the profile and the level, and specifically, as shown in Table 1. In FIG. 7, 631, 632, 633, 634 are decoding result inputs from the decoder, 641, 64
2, 643 and 644 are memories, 661 and 662 are switches, and 671 and 672 are memories.

The demultiplexer 4 is basically the same as that of the first embodiment except that it includes four systems (a, b, c, d) for outputting compressed video data.

In the demultiplexer 4, the internal distributor 400 and the switch 401 operate in cooperation to output predetermined compressed video data from a predetermined system.

If the separated compressed video data is for one high-definition video, distributor 400 outputs this to system a. As shown in Table 1, the state of the switch 401 changes according to the format of the input video. As shown in Table 1, in this case, the output 40
The compressed video data of system a is output to all of 5,406, 407, and 408.

If the separated compressed video data is for two 480p line-sequential videos, distributor 400 outputs one compressed video data to system a and the other compressed video data to system c. In this case, as shown in Table 1, the switch 401 outputs the compressed video data input to the system a to the outputs 405 and 406, and the compressed video data input to the system c to the output 4
07, 408.

If the separated compressed video data is for one 480p line-sequential video and two standard videos, the distributor 400 sends the compressed video data of 480p line-sequential video to the system a, The compressed video data of one standard video is output to the system c, and the compressed video data of the other standard video is output to the system d. In this case, as shown in Table 1, switch 40
1 outputs to the outputs 405 and 406 the compressed video data of 480p line-sequential video input to the system a. Also, the standard video signal of 480i input to the system c is output 407,
The compressed video data of the standard video of 480i input to the system d is output to the output 408.

If the separated compressed video data is for four standard videos, distributor 400
One compressed video data of a standard video is assigned to each of the systems a, b, c, and d and output. In this case, as shown in Table 1, the switch 401 causes the output 405 to output the compressed video data of the standard video input to the system a. Similarly, the compressed video data of the standard video input to the system b is output to the output 406, and the compressed video data of the standard video input to the system c is output 4
In addition, the compressed video data of the standard video input to the system d is output to the output 408.

The compressed video data output from the outputs 405, 406, 407, and 408 are input to the decoders 51, 52, 53, and 54, respectively, where they are decoded. In this case, the compressed video data output to the output 405 is output to the decoder 51, the compressed video data output to the output 406 is output to the decoder 52, and the compressed video data output to the output 407 is output to the decoder 53 and the output 408. The compressed video data is input to the decoder 54.

In this case, the division of the decoding area among the decoders is as follows. If the compressed video data is for high-definition video, the video is divided into four in the vertical direction,
Each section is assigned to each of the decoders 51, 52, 53, and 54. Also, in the case of 480p line sequential video, the video is divided into two in the vertical direction, with one decoder serving the upper half and the other decoder serving the lower half. Which section each decoder decodes is preset in accordance with the video format in each decoder. Each decoder can decode the standard video signal (480i) with a margin as long as it has the ability to decode a quarter of the 1080i video. The video data decoded in this way is output to the display processor 6.

The display processor 6 configures a screen according to the original video format from the decoding results input from the four decoders 51, 52, 53, and 54. Hereinafter, the operation in the display processor 6 will be described in detail with reference to FIG.

The decoding result output from the decoder 51 is input to the input 631 of the display processor 6, and the input data is stored in the memory 641. Similarly, the decoding result of the decoder 52 is stored in the memory 642 through the input 632. The decoding result of the decoder 53 is stored in the memory 643 through the input 633. The decoding result of the decoder 54 is stored in the memory 644 through the input 634.

The display processor 6 configures one screen by switching the switches 661, 662, and 620 according to the video format of the video input at this time. Switch 66
Table 2 shows the setting contents of 1,662,620.

For example, if the video data at this time is for high-definition video, the memory 641 stores
The upper quarter of one image is accumulated. Similarly, in the memories 642, 643, and 644, one-fourth of one image is sequentially stored. Therefore, the upper half of the screen is configured by switching the switch 661 so that data is continuous from the memory 641 to the memory 642. Then, the constructed upper half image is stored in the memory 671. Similarly, switch 6
By switching 62 from the memory 643 to the memory 644, the lower half of the screen is configured. The constructed lower half image is stored in the memory 672. Further, similarly to the first embodiment, one screen is configured by switching the switch 620 at a half position of the field. The switches 661, 662, and 62 are switched based on the result of the determination unit 621 determining the video format included in the decoding result.

If the video data at this time is for two different 480p line sequential videos, the screen is divided into left and right, and each video is displayed side by side. In this case, the upper half of one video is stored in the memory 641 and the lower half is stored in the memory 642. Therefore, switch 661
Is switched at half the position of the field to configure one screen, and the configured screen is stored in the memory 671. As for the other video, the upper half is stored in the memory 643 and the lower half is stored in the memory 644. Accordingly, similarly, one screen is formed by switching the switch 662 at a half position of the field, and the constructed video is stored in the memory 672. Further, by switching the switch 620 at a position half of one line, the video stored in the memory 671 and the video stored in the memory 672 are displayed separately on the left and right sides of the screen.

If the video data at this time is for a total of three of one 480p line sequential video and two different 480i line sequential videos, one or two of them are selected and displayed. When two images are displayed, the screen is divided into left and right parts, and the two images are displayed side by side. In this case, the upper half of the 480p video is stored in the memory 641, and the lower half is stored in the memory 642. Accordingly, one image is formed by switching the switch 661 at a half position of the field, and the formed image is stored in the memory 671. Two 480i
One of these images is stored in the memory 643 and the other is stored in the memory 644. Therefore, by setting either the memory 643 or the memory 644 with the switch 662, only one of the videos is read and stored in the memory 672. Further, by switching the switch 620 at a position half of one line, the video stored in the memory 671 and the video stored in the memory 672 are displayed separately on the left and right sides of the screen. In this case, the video accumulated in the memory 672 is processed by the filter 651 so that 480 is obtained.
It is converted to p and output.

If the video data at this time is for four 480i standard videos, the memory 6
41, 642, 643, and 644 each store one standard video. Therefore,
In this case, the screen is divided into upper, lower, left and right, and one image is displayed in each area. Such a display can be performed by switching the switch 661 and the switch 662 at half the position of the field and switching the switch 620 at the half of one line. Or, conversely, the switch 661 and the switch 662 can be switched by half of one line, and the switch 620 can be switched by half of the field.

However, it goes without saying that in any of the above cases, only one video can be displayed according to the user's selection.

Embodiment 3 FIG. The third embodiment is different from the above-described embodiment in that not only the decoder but also a plurality of demultiplexers are provided so that video data is separately extracted from a plurality of transport streams and further decoded by the decoder. Different. In addition, the correspondence between the demultiplexer and the decoder can be changed by a switch 8 described later. Details will be described below.

FIG. 8 is a block diagram showing the third embodiment. In FIG. 8, 41 and 42 are demultiplexers, and 8 is a switch. Further, the demodulator 3 according to the third embodiment has a capability of outputting two transport streams from one physical channel.

When two or more transport streams are included in one physical channel, the demodulator 3 separates a predetermined number (two in this embodiment) of transport streams, and separates each transport stream into a separate demultiplexer. Output to multiplexers 41 and 42. At this time, high-definition video having a large processing amount per unit time required for decoding is output to the demultiplexer 41 side. Actually, the output destination is preset in the demodulator 3 according to the profile and level defined in MPEG2, and the output destination is selected according to the setting.

The demultiplexers 41 and 42 are the same demultiplexers as shown in FIG.
Separate and output compressed video data.

Normally, the switch 8 connects the decoder 52 to the demultiplexer 41. However, only when the control signal 501 is output from the decoder 51, the state is switched so that the decoder 52 is connected to the demultiplexer 42 side. When the output of the demultiplexer 41 is compressed video data for high-definition video, the decoder 51 does not output the control signal 501. Accordingly, both the decoder 51 and the decoder 52 are supplied with compressed video data of high-definition video that is the output of the demultiplexer 41. On the other hand, when the output of the demultiplexer 41 is compressed video data for the standard video (480i), the decoder 51 outputs a control signal 501 to the switch 8. Switch 8 responds accordingly.
Switch to the demultiplexer 41 side. As a result, the decoder 51 receives the output of the demultiplexer 41, while the decoder 52 receives the output of the demultiplexer 42. Thereafter, the outputs of the decoders 51 and 52 are processed in the same manner as in the first embodiment and output from the video output 7.

In the present embodiment, the “switching means” referred to in the claims is realized by the decoder 51 and the switch 8.

Embodiment 4 FIG. The video signal processing apparatus according to the fourth embodiment is an example in which a plurality of tuners, demodulators, and demultiplexers are provided.

FIG. 9 is a block diagram showing the fourth embodiment. In FIG. 9, 21 and 22 are tuners,
Reference numerals 31 and 32 denote demodulators, and the other parts have the same configuration as in the third embodiment.

When receiving a plurality of transport streams from a plurality of physical channels (including cases where the networks such as BS and CS are different), a plurality of (two in the figure) are passed through different tuners, demodulators, and demultiplexers, respectively. Get compressed video data. The subsequent steps are the same as in the third embodiment.

In the embodiment described above, two or four demultiplexers and decoders are provided. However, the number of these is not limited to this.

In the above-described embodiment, an apparatus for processing video data compliant with MPEG2 has been described. However, the application of the present invention is not limited to apparatuses that process video data compliant with MPEG2. Further, the number of decoders assigned to one compressed video data is not limited to the above example. What is necessary is just to set according to the processing amount per unit time required for the decoding of the compressed video data, and the processing capacity of the decoder.

1 antenna, 2 tuner, 3 demodulator, 4 demultiplexer, 6 display processor, 8 switch, 21, 22 tuner, 31,32 demodulator,
41, 42 Demultiplexer, 51, 52, 53, 54 Decoder, 400 Distributor, 401 switch, 620 switch, 621 determination unit, 641, 642, 6
43,644,671,672 memory, 661,662 switch, 650,65
1 Filter.

Claims (2)

An information reproducing apparatus for reproducing the digital video signal based on an input signal configured to include a high-definition digital video signal or a plurality of standard digital video signals,
The input signal is a transport stream that includes information indicating a profile and level defined in MPEG2 or a video format, and includes a packet having an ID number for identifying a data type in a header portion,
First reproducing means for reproducing a first digital video signal of the plurality of types of digital video signals;
Of the plurality of types of digital video signals, a second different from the first digital video signal
Second reproduction means for reproducing the digital video signal of
Determining whether the first digital video signal or the second digital video signal;
Separating means for outputting each digital video signal to the first reproduction means or the second reproduction means,
The separation unit separates the packet from the transport stream to form the plurality of types of digital video signals, and among the plurality of types of digital video signals, the number of pixels in the horizontal direction, the number of scanning lines, or the aspect Based on the information on the ratio, a predetermined digital video signal is output from a predetermined output port of 1 or 2,
The input signal is the first digital video signal or the second digital signal in the separation means.
Including a determination signal for determining whether the digital video signal is
The determination signal includes video-related information that is information corresponding to the profile and level of the digital video signal, or a video format,
An information reproducing apparatus, wherein the first video related information corresponding to the first digital video signal and the second video related information corresponding to the second digital video signal are different. An information reproduction method for reproducing the digital video signal based on an input signal including a high-definition digital video signal or a plurality of standard digital video signals,
The input signal is a transport stream that includes information indicating a profile and level defined in MPEG2 or a video format, and includes a packet having an ID number for identifying a data type in a header portion,
Separating the packet from the transport stream of the plurality of types of digital video signals, and playing back the configured first digital video signal in a first playback means;
Among the plurality of types of digital video signals, the packets are separated from the transport stream to form the plurality of types of digital video signals, and among the plurality of types of digital video signals, the number of pixels in the horizontal direction and the scanning line Based on number or aspect ratio information,
A predetermined digital video signal is output from one or two predetermined output ports, and a second digital video signal different from the configured first digital video signal is reproduced in the second reproduction means;
When reproducing the first digital video signal or the second digital video signal, determining whether the first digital video signal or the second digital video signal;
Based on the determination result, each digital video signal is converted into the first reproduction means or the second reproduction means.
Output to the playback means,
The input signal includes a determination signal for determining whether the input signal is the first digital video signal or the second digital video signal;
The determination signal includes video-related information that is information corresponding to the profile and level of the digital video signal, or a video format,
An information reproducing method, wherein the first video related information corresponding to the first digital video signal is different from the second video related information corresponding to the second digital video signal.

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