JP2014131073A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of which malfunctions and variations of operation characteristics are reduced by reducing a gain of a parasitic bipolar transistor, and a manufacturing method of the semiconductor device.SOLUTION: On a top surface of a silicon layer 3, a silicone oxide film 6 is partially formed. On the silicone oxide film 6, a gate electrode 7 composed of polysilicon is partially formed. A part of the silicone oxide film 6 which exists below the gate electrode 7 functions as a gate insulating film. On a side surface of the gate electrode 7, a silicon nitride film 9 is formed with a silicone oxide film 8 sandwiched between them. The silicone oxide film 8 and the silicon nitride film 9 are formed on the silicone oxide film 6. A width W1 of the silicone oxide film 8 of a gate length direction is larger than a film thickness T1 of the silicone oxide film 6.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.

  As a device having a high operating speed and low power consumption, a semiconductor device (SOI device) using an SOI substrate has attracted attention. The SOI substrate is a substrate having a structure in which a semiconductor substrate, an insulating layer, and a semiconductor layer are stacked in this order. An SOI device having a semiconductor layer thinned to about several μm (referred to as a “thin film SOI device”) has recently attracted particular attention and is expected to be applied to LSIs for portable devices.

  FIG. 44 is a cross-sectional view showing the structure of a conventional semiconductor device. The SOI substrate 104 has a structure in which a silicon substrate 101, a BOX (Burried OXide) layer 102, and a silicon layer 103 are laminated in this order. In the silicon layer 103, an element isolation insulating film 105 made of a silicon oxide film is partially formed. The element isolation insulating film 105 is formed so as to reach from the upper surface of the silicon layer 103 to the upper surface of the BOX layer 102. Such an element isolation insulating film is called a “complete isolation type element isolation insulating film”.

  A MOSFET is formed in the element formation region defined by the element isolation insulating film 105. Specifically, it is as follows. A silicon oxide film 106 is partially formed on the upper surface of the silicon layer 103. A gate electrode 107 made of polysilicon is partially formed on the silicon oxide film 106. A portion of the silicon oxide film 106 existing below the gate electrode 107 functions as a gate insulating film. A silicon nitride film 109 is formed on the side surface of the gate electrode 107 with the silicon oxide film 108 interposed therebetween. The silicon oxide film 108 is formed not only between the side surface of the gate electrode 107 and the side surface of the silicon nitride film 109 but also between the upper surface of the silicon oxide film 106 and the bottom surface of the silicon nitride film 109.

  A pair of source / drain regions 110 are formed in the silicon layer 103. A region sandwiched between the paired source / drain regions 110 is defined as a body region 112. The source / drain region 110 has an extension 111 extending below the gate electrode 107 in the upper surface of the silicon layer 103.

  FIG. 45 is a cross-sectional view showing the structure of another conventional semiconductor device. Instead of the complete isolation type element isolation insulating film 105 shown in FIG. 44, an element isolation insulating film 130 made of a silicon oxide film is formed. The bottom surface of the element isolation insulating film 130 does not reach the top surface of the BOX layer 102. Such an element isolation insulating film is called a “partial isolation type element isolation insulating film”. Other structures of the semiconductor device shown in FIG. 45 are the same as those of the semiconductor device shown in FIG.

  FIG. 46 is a top view schematically showing a top structure of the semiconductor device shown in FIG. By employing the partial isolation type element isolation insulating film 130, the potential of the body region 112 from the body contact region 150 through the silicon layer 103 between the bottom surface of the element isolation insulating film 130 and the upper surface of the BOX layer 102. Can be fixed. As a result, it is possible to suppress a so-called substrate floating effect such as occurrence of a kink phenomenon or fluctuation in delay time depending on the operating frequency.

  44 and 45, the width W101 of the silicon oxide film 108 in the gate length direction (left and right direction on the paper surface) is the total film thickness T101 of the silicon oxide film 106 and the silicon oxide film 108. Smaller than. However, the silicon oxide film 106 other than the portion functioning as the gate insulating film (that is, the portion of the silicon oxide film 106 existing between the bottom surface of the silicon oxide film 108 and the top surface of the silicon layer 103 in FIG. 44) is etched during gate etching. In some cases, W101 is equal to T101. That is, in the conventional semiconductor device, W101 is T101 or less.

  However, according to such a conventional semiconductor device, since the width W101 of the silicon oxide film 108 is relatively narrow, the distance between the paired source / drain regions 110 (specifically, the distance between the paired extensions 111). ) L101 is also relatively narrow.

  Incidentally, the semiconductor device shown in FIGS. 44 and 45 includes a parasitic bipolar transistor having the source / drain region 110 as an emitter and a collector and the body region 112 as a base. The fact that the distance L101 between the paired source / drain regions 110 is narrow means that the base width of the parasitic bipolar transistor is narrow, so that the gain of the parasitic bipolar transistor increases. As a result, the conventional semiconductor device has a problem that a malfunction may occur in the MOSFET or an operation characteristic may vary due to the high gain of the parasitic bipolar transistor.

  The present invention has been made to solve such a problem, and an object of the present invention is to obtain a semiconductor device with less malfunctions and fluctuations in operating characteristics by reducing the gain of a parasitic bipolar transistor and a method for manufacturing the same. It is.

  According to a first aspect of the present invention, a semiconductor device includes: a substrate; and (a) a gate electrode formed on a main surface of the substrate with a gate insulating film interposed therebetween and extending along a predetermined direction; A) a first sidewall formed on the side surface of the gate electrode; (c) a body region formed in the substrate below the gate electrode; and (d) a pair formed between the body region and sandwiching the body region. A semiconductor element having a source / drain region to be formed, an interlayer insulating film formed on the substrate so as to cover the semiconductor element, and formed in the interlayer insulating film extending in a predetermined direction while being in contact with the upper surface of the gate electrode; And a gate wiring having a dimension in the gate length direction of the gate electrode larger than the gate length of the gate electrode.

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the second sidewall formed on the side surface of the gate electrode with the first sidewall interposed therebetween. Furthermore, it is characterized by providing.

  According to a third aspect of the present invention, the semiconductor device according to the second aspect is the semiconductor device according to the second aspect, wherein the dimension of the second side wall in the gate length direction is the first side wall in the gate length direction. It is characterized in that it is larger than the dimension.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the semiconductor device is formed in an interlayer insulating film connected to a source / drain region. The contact plug is further provided, and the size of the gate wiring in the gate length direction is smaller than the size of the contact plug in the gate length direction.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: (a) a step of preparing a substrate; and (b) a gate electrode extending along a predetermined direction with a gate insulating film interposed therebetween. Forming on the main surface of the substrate; (c) forming a first sidewall on the side surface of the gate electrode; and (d) covering the gate electrode and the first sidewall to cover the substrate with interlayer insulation. A step of forming a film; and (e) a gate wiring having a dimension in the gate length direction of the gate electrode larger than the gate length of the gate electrode and extending in a predetermined direction while being in contact with the upper surface of the gate electrode. And forming the step.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth aspect of the present invention, wherein the method is performed before step (d), The method further includes the step of forming a second sidewall on the side surface of the gate electrode with the sidewall interposed therebetween.

  According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the sixth aspect, wherein in the step (f), the dimension in the gate length direction is the gate length. A second sidewall that is larger than the dimension of the first sidewall in the direction is formed.

  According to an eighth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any one of the fifth to seventh aspects, wherein: (s) below the gate electrode And forming a pair of source / drain regions in the substrate with the body region sandwiched therebetween, and (t) a step connected to the source / drain region and the dimension in the gate length direction. However, the method further includes a step of forming a contact plug larger than the dimension of the gate wiring in the gate length direction in the interlayer insulating film.

  According to the first aspect of the present invention, the gate resistance can be reduced and the maximum oscillation frequency of the semiconductor element can be increased.

  According to the second aspect of the present invention, the margin of misalignment can be improved in the manufacturing process of the semiconductor device by forming the second sidewall.

  According to the third aspect of the present invention, the margin of misalignment can be further improved in the semiconductor device manufacturing process.

  According to a fourth aspect of the present invention, in the manufacturing process of a semiconductor device, when the contact hole for the contact plug and the wiring groove for the gate wiring are formed in the same etching process, the etching is performed. The difference in speed can be reduced.

  According to the fifth aspect of the present invention, since the gate resistance is reduced, a semiconductor device with an improved maximum oscillation frequency can be obtained.

  According to the sixth aspect of the present invention, the margin of misalignment can be improved in the step of forming the wiring trench for the gate wiring by forming the second sidewall.

  According to the seventh aspect of the present invention, the margin of misalignment can be further improved.

  According to the eighth aspect of the present invention, when a contact hole for a contact plug and a wiring groove for a gate wiring are formed in the same etching process, a difference in etching rate is reduced. Can do.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the aspect by which NMOSFET and PMOSFET which concern on Embodiment 1 of this invention were formed on the same SOI substrate. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view which shows the 1st modification of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view which shows the 2nd modification of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 10 is a circuit diagram showing a simplified equivalent circuit of a transistor with respect to Embodiment 3 of the present invention. It is a graph which shows the result of having measured the relationship between the width | variety of a silicon oxide film, the cutoff frequency, and the maximum oscillation frequency for the transistor whose gate length is 70 nm. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention in order of a process. It is sectional drawing which shows the 1st modification of the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the 2nd modification of the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the 3rd modification of the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the other semiconductor device which concerns on Embodiment 5 of this invention. It is a graph which shows the result of having measured the relationship between the width | variety and the delay time of the insulating film for offsets for the transistor whose gate length is 70 nm. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention in order of a process. It is a top view which shows typically the structure of the semiconductor device which concerns on Embodiment 7 of this invention. FIG. 37 is a cross-sectional view showing a cross-sectional structure related to a position along line segment A1-A1 shown in FIG. 36. FIG. 37 is a cross-sectional view showing a cross-sectional structure related to a position along line segment A2-A2 shown in FIG. 36. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention in order of a process. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows the structure of the other conventional semiconductor device. FIG. 46 is a top view schematically showing a top surface structure of the semiconductor device shown in FIG. 45.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. The SOI substrate 4 has a structure in which a silicon substrate 1, a BOX layer 2, and a single crystal silicon layer 3 are laminated in this order. However, a polycrystalline or amorphous silicon layer may be formed instead of the single crystal silicon layer 3. A complete isolation type element isolation insulating film 5 made of a silicon oxide film is partially formed in the silicon layer 3. The element isolation insulating film 5 is formed so as to reach from the upper surface of the silicon layer 3 to the upper surface of the BOX layer 2.

  A MOSFET is formed in the element formation region defined by the element isolation insulating film 5. Specifically, it is as follows. A silicon oxide film 6 is partially formed on the upper surface of the silicon layer 3. On the silicon oxide film 6, a gate electrode 7 made of polysilicon is partially formed. A portion of the silicon oxide film 6 existing below the gate electrode 7 functions as a gate insulating film. A silicon nitride film 9 is formed on the side surface of the gate electrode 7 with the silicon oxide film 8 interposed therebetween. The silicon oxide film 8 and the silicon nitride film 9 are formed on the silicon oxide film 6. The width W1 of the silicon oxide film 8 in the gate length direction (left and right direction in the drawing) is larger than the film thickness T1 of the silicon oxide film 6.

  With respect to the silicon oxide film 8, in this specification, a side surface that contacts the side surface of the gate electrode 7 is defined as an “inner side surface”, and a side surface that does not contact the side surface of the gate electrode 7 is defined as an “outer surface”. Further, regarding the silicon nitride film 9, in this specification, the side surface that contacts the outer surface of the silicon oxide film 8 is the “inner surface”, and the side surface that does not contact the outer surface of the silicon oxide film 8 is the “outer surface”. Is defined.

  A pair of source / drain regions 10 are formed in the silicon layer 3. A region sandwiched between the paired source / drain regions 10 is defined as a body region 12. The source / drain region 10 includes an extension 11 (also referred to as “LDD” when the impurity concentration is relatively low) 11 formed to extend from below the outer surface of the silicon oxide film 8 toward the body region 12. It has in the upper surface.

  FIG. 2 is a cross-sectional view showing an aspect in which the NMOSFET and the PMOSFET according to the first embodiment are formed on the same SOI substrate 4. In FIG. 2, an NMOSFET is formed in an element formation region defined by the leftmost element isolation insulating film 5 and the central element isolation insulating film 5, and the rightmost element isolation insulating film 5 and the central element isolation insulating film are formed. PMOSFET is formed in the element formation region defined by 5. Each of the NMOSFET and the PMOSFET has the same structure as that shown in FIG.

3 to 12 are cross-sectional views showing the method of manufacturing the semiconductor device shown in FIG. Referring to FIG. 3, first, after preparing SOI substrate 4, element isolation insulating film 5 is formed in silicon layer 3. Next, a silicon oxide film 13 is formed on the entire upper surface of the silicon layer 3 and the upper surface of the element isolation insulating film 5 by CVD or thermal oxidation. However, instead of the silicon oxide film 13, a silicon oxynitride film, a metal oxide film such as Al ₂ O ₃ , and a ferroelectric film such as Ta ₂ O ₅ or BST may be formed. Next, a polysilicon film 14 having a thickness of about 100 to 400 nm is formed on the entire upper surface of the silicon oxide film 13 by LPCVD. However, impurities such as P and B may be introduced into the polysilicon film 14. Further, instead of the polysilicon film 14, a metal film such as W, Ta, or Al may be formed. Next, photoresists 15a and 15b are partially formed on the upper surface of the polysilicon film 14 by photolithography. The photoresists 15a and 15b are formed above the regions where the gate electrodes 7a and 7b are to be formed.

  Referring to FIG. 4, next, using photoresists 15a and 15b as etching masks, the etching rate is high in the depth direction of SOI substrate 4, such as RIE (Reactive Ion Etching) or ECR (Electron Cyclotron Resonance). The polysilicon film 14 is etched by anisotropic dry etching. As a result, the polysilicon film 14 in the portion located below the photoresists 15a and 15b remains without being etched, and the gate electrodes 7a and 7b are formed. By this anisotropic dry etching, the upper surface of the silicon oxide film 13 is also slightly etched. Thereafter, the photoresists 15a and 15b are removed. However, after forming an insulating film on the upper surface of the polysilicon film 14 and patterning the insulating film by photolithography and etching, the polysilicon film 14 is anisotropic using the patterned insulating film as a hard mask. The gate electrodes 7a and 7b may be formed by reactive etching.

  Referring to FIG. 5, next, a silicon oxide film 16 is entirely formed by a CVD method or a thermal oxidation method. However, instead of the silicon oxide film 16, an HTO film, an LTO film, a TEOS film, or a plasma oxide film may be formed.

  Next, referring to FIG. 6, the silicon oxide film 16 is etched by anisotropic dry etching with a high etching rate in the depth direction of the SOI substrate 4. Thereby, silicon oxide films 8a and 8b are formed on the side surfaces of the gate electrodes 7a and 7b. At this time, the etching is stopped before the upper surface of the silicon oxide film 13 and the upper surfaces of the gate electrodes 7a and 7b are exposed, so that the silicon oxide film is formed on the upper surface of the silicon oxide film 13 and the upper surfaces of the gate electrodes 7a and 7b. 16 may be left thin.

Referring to FIG. 7, next, a photoresist 17 is formed on the region where the PMOSFET is to be formed by photolithography. Next, using the photoresist 17 as an implantation mask, p-type impurities such as B, BF ₂ , and In are ion-implanted under conditions of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² to form an NMOSFET. A pocket region (not shown) is formed in the silicon layer 3 in the planned region. The pocket region is formed in order to suppress a short channel effect due to device miniaturization. Next, n-type ions 18 such as As, P, and Sb are ion-implanted under conditions of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² , so that the silicon layer 3 in the formation region of the NMOSFET is An extension 11a is formed. At this time, the photoresist 17, the gate electrode 7a, the silicon oxide film 8a, and the element isolation insulating film 5 function as an implantation mask. As a result, the extension 11a is formed in the upper surface of the silicon layer 3 where the gate electrode 7a, the silicon oxide film 8a, and the element isolation insulating film 5 are not formed, but at its end (on the gate electrode 7a side). The end portion is present inside the outer surface of the silicon oxide film 8a.

  After obtaining the structure shown in FIG. 6, before forming the photoresist 17, a silicon oxide film having a predetermined thickness is formed on the entire surface by the CVD method, so that a pocket region is formed in the silicon layer 3. And the location where the extension 11a is formed can also be adjusted. When the short channel effect is suppressed by adjusting the source / drain junction depth, the thickness of the gate insulating film, or the like, the pocket region need not be formed.

Referring to FIG. 8, next, after removing the photoresist 17, a photoresist 19 is formed on the formation region of the NMOSFET by photolithography. Next, using the photoresist 19 as an implantation mask, n-type impurities such as As, P, and Sb are ion-implanted under conditions of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² to form a PMOSFET. A pocket region (not shown) is formed in the silicon layer 3 in the region. Next, p-type ions 20 such as B, BF ₂ , and In are ion-implanted under the conditions of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , so that the silicon layer 3 in the formation region of the PMOSFET is formed. The extension 11b is formed. At this time, the photoresist 19, the gate electrode 7b, the silicon oxide film 8b, and the element isolation insulating film 5 function as an implantation mask. As a result, the extension 11b is formed in the upper surface of the silicon layer 3 where the gate electrode 7b, the silicon oxide film 8b, and the element isolation insulating film 5 are not formed, but at its end (on the gate electrode 7b side). The end portion is present inside the outer surface of the silicon oxide film 8b. In the same manner as described above, the location where the pocket region and the extension 11b are formed in the silicon layer 3 can also be adjusted. Further, similarly to the above, the formation of the pocket region can be omitted.

  Referring to FIG. 9, next, after removing the photoresist 19, a silicon nitride film 21 is formed over the entire surface by CVD. Referring to FIG. 10, next, the silicon nitride film 21 and the silicon oxide film 13 are formed by anisotropic dry etching with a high etching rate in the depth direction of the SOI substrate 4 until the upper surface of the silicon layer 3 is exposed. Etching is performed in this order. As a result, silicon nitride films 9a and 9b as sidewall insulating films are formed on the outer surfaces of the silicon oxide films 8a and 8b. Silicon nitride films 9a and 9b are formed on silicon oxide films 6a and 6b.

Referring to FIG. 11, next, a photoresist 22 is formed on the formation region of the PMOSFET by photolithography. Next, by using the photoresist 22 as an implantation mask, n-type ions 23 such as As, P, and Sb are ion-implanted under the conditions of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² , thereby Source / drain regions 10a are formed in the silicon layer 3 in the formation region. The extension 11a becomes a part of the source / drain region 10a.

Referring to FIG. 12, next, after removing the photoresist 22, a photoresist 24 is formed on the formation region of the NMOSFET by photolithography. Next, by using the photoresist 24 as an implantation mask, p-type ions 25 such as B, BF ₂ , and In are ion-implanted under conditions of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² , thereby causing PMOSFETs. A source / drain region 10b is formed in the silicon layer 3 in the formation planned region. The extension 11b becomes a part of the source / drain region 10b.

  Finally, after removing the photoresist 24, annealing is performed at about 800 to 1150 ° C. in order to activate the impurities introduced into the silicon layer 3. Then, a semiconductor device is completed through a process of forming metal silicide on the upper surfaces of the source / drain regions 10a and 10b and the gate electrodes 7a and 7b and a wiring process.

  As described above, according to the method of manufacturing the semiconductor device according to the first embodiment, after the relatively wide silicon oxide films 8a and 8b are formed on the side surfaces of the gate electrodes 7a and 7b in the step shown in FIG. In the steps shown in FIGS. 7 and 8, extensions 11a and 11b are formed. Therefore, as shown in FIG. 1, the distance between the paired source / drain regions 10 (specifically, the distance between the paired extensions 11) L1 is set to the distance L101 in the conventional semiconductor device (see FIG. 44). ).

  As a result, since the base width of the parasitic bipolar transistor is widened, the gain of the parasitic bipolar transistor is reduced, and the malfunction of the MOSFET and the fluctuation of the operating characteristics can be suppressed.

  In addition, since the degree of overlap between the gate electrode 7 and the extension 11 in plan view is reduced, the gate overlap capacitance is suppressed, and the operation speed can be increased and the power consumption can be reduced. Moreover, in the semiconductor device according to the first embodiment, an SOI substrate 4 is used instead of a normal bulk substrate. As shown in FIG. 1, in the semiconductor device using the SOI substrate 4, since the bottom surface of the source / drain region 10 is in contact with the BOX layer 2, the junction capacitance at the source / drain is small. For this reason, the semiconductor device using the SOI substrate 4 has a smaller total parasitic capacitance than the semiconductor device using the bulk substrate. Therefore, when trying to obtain an equivalent current drive capability, the silicon device manufacturing method according to the first embodiment has a wider silicon oxide film than the case of manufacturing a semiconductor device using a bulk substrate. 8 can be formed in contact with the side surface of the gate electrode 7. As a result, even when the gate length of the gate electrode 7 is shortened by miniaturization of the device, the gate electrode 7 can be effectively prevented from falling due to the ashing process or the RCA cleaning process.

  44 and 45 relating to the prior art, the interval L101 can be increased even if the thickness of the silicon oxide film 108 is simply increased. In this case, ion implantation for forming the extension 111 is performed. In the process, it is necessary to increase the implantation energy. Therefore, since the range of ions is large, it is difficult to form the extension 111 shallowly in the upper surface of the silicon layer 103, and a short channel effect occurs. On the other hand, according to the method for manufacturing the semiconductor device according to the first embodiment, the extension 11 can be formed shallowly in the upper surface of the silicon layer 3, so that the short channel effect can be suppressed.

Embodiment 2. FIG.
FIG. 13 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. Instead of the complete isolation type element isolation insulating film 5 shown in FIG. 1, a partial isolation type element isolation insulating film 30 is formed. The other structure of the semiconductor device according to the second embodiment is the same as that of the semiconductor device according to the first embodiment shown in FIG. The semiconductor device according to the second embodiment is formed through the steps shown in FIGS. 3 to 12 by forming the element isolation insulating film 30 instead of the element isolation insulating film 5 in the step shown in FIG. can do.

  By employing the partial isolation type element isolation insulating film 30, the body region is formed from the body contact region (not shown) through the silicon layer 3 between the bottom surface of the element isolation insulating film 30 and the upper surface of the BOX layer 2. Twelve potentials can be fixed. As a result, it is possible to suppress a so-called substrate floating effect such as occurrence of a kink phenomenon or fluctuation in delay time depending on the operating frequency.

  According to the semiconductor device according to the second embodiment, in addition to the effects obtained by the semiconductor device according to the first embodiment and the manufacturing method thereof, the following effects are obtained. That is, as a result of the increase in the distance L1, the body resistance in the direction perpendicular to the paper surface of FIG. 13 is also reduced. Therefore, the problem that the threshold voltage of the MOSFET differs depending on the distance from the body contact region can be suppressed.

  FIG. 14 is a top view showing a first modification of the semiconductor device according to the second embodiment. In the semiconductor device shown in FIG. 14, the complete isolation type element isolation insulating film 5 is employed instead of the partial isolation type element isolation insulating film 30. The gate electrode 7 employs an H-shaped gate with both ends widened. In order to fix the potential of the body region 12, body contact regions 31 that are in direct contact with the body region 12 are formed at both ends of the gate electrode 7.

  FIG. 15 is a top view showing a second modification of the semiconductor device according to the second embodiment. In the semiconductor device shown in FIG. 15, the complete isolation type element isolation insulating film 5 is employed instead of the partial isolation type element isolation insulating film 30. The gate electrode 7 employs a T-shaped gate with one end widened. In order to fix the potential of the body region 12, a body contact region 31 that is in direct contact with the body region 12 is formed at the one end of the gate electrode 7.

  14 and 15, the body resistance can be reduced by adopting the cross-sectional structure shown in FIG. 13, and the threshold voltage of the MOSFET varies depending on the distance from the body contact region 31. Can be suppressed.

Embodiment 3 FIG.
In the third embodiment, the relationship between the gate length of the gate electrode 7 and the width W1 of the silicon oxide film 8 in the gate length direction will be described.

FIG. 16 is a circuit diagram showing a simplified equivalent circuit of a transistor. In FIG. 16, R _g is a gate resistance, R _i is a channel resistance, R _s is a source resistance, g _m is a mutual conductance, g _ds is a drain-source conductance, C _gs is a gate-source capacitance, C _gd Is the gate-drain capacitance. In general, there are a cutoff frequency f _t and a maximum oscillation frequency f _{max as} indexes indicating the performance of a transistor. Referring to FIG. 16, the cutoff frequency f _t and the maximum oscillation frequency f _max are represented by the following expressions (1) and (2), respectively.

Increasing the width W1 of the silicon oxide film 8, since the effective channel length is increased, the transconductance g _m is reduced. Therefore, from equation (1), when the width W1 of the silicon oxide film 8 is increased, the cutoff frequency _ft is decreased. When the cut-off frequency _ft is reduced, the maximum oscillation frequency _fmax is also reduced from the equation (2). However, when the width W1 of the silicon oxide film 8 is increased, the gate-drain overlap capacitance (corresponding to the above C _gd ) is reduced and the short channel effect is suppressed, so that the drain-source conductance is reduced. g _ds also decreases. Thus, the cutoff frequency f _t, the gate - overlap capacitance C _gd and drain between the drain - the conductance g _ds between source, there is a trade-off with each other. Therefore, there is an optimum value for the width W1 of the silicon oxide film 8 in order to improve the maximum oscillation frequency _fmax .

FIG. 17 is a graph showing the results of measuring the relationship between the width W1 of the silicon oxide film 8, the cut-off frequency f _t, and the maximum oscillation frequency f _max for a transistor having a gate length of Lg = 70 nm. In order to prevent the gate electrode 7 from falling due to ashing or RCA cleaning, it is desirable that the width W1 of the silicon oxide film 8 is wide. However, as shown in FIG. 17, when the width W1 of the silicon oxide film 8 becomes too large, the maximum oscillation frequency f _max is lowered. Therefore, in view of stably forming the gate electrode 7 and suppressing the decrease in the maximum oscillation frequency _fmax , it is desirable to set the width W1 of the silicon oxide film 8 to about 20 nm. In this case, the ratio between the gate length Lg and the width W1 of the silicon oxide film 8 is 1 to 2/7.

  Next, consider a case where the gate electrode 7 is miniaturized. According to the scaling rule, if the miniaturization progresses and the gate length Lg becomes shorter, the width W1 of the silicon oxide film 8 should be reduced accordingly. However, the implantation energy in ion implantation for forming the extension 11 is still sub-keV even now, and it is difficult to lower the implantation energy any more. As for heat treatment, RTA (Rapid Thermal Annealing) technology is currently used, and it is difficult to further shorten the heat treatment time. For this reason, even if the gate electrode 7 is miniaturized, it is difficult to form the source / drain region 10 shallowly according to the scaling rule, and therefore the source / drain profile is considered not to change so much. Further, when the width W1 of the silicon oxide film 8 is reduced according to the scaling rule, the gate overlap capacitance is increased and the operation speed of the transistor is decreased. For the above reasons, it is considered that the optimum value of the width W1 of the silicon oxide film 8 remains 20 nm even if the device is miniaturized. Therefore, even when the MOS transistor is miniaturized to the shortest gate length (Lg = 20 nm) at which the MOS transistor can operate, the optimum value of the width W1 of the silicon oxide film 8 is about 20 nm. The ratio of Lg to the width W1 of the silicon oxide film 8 is 1: 1.

As described above, according to the semiconductor device according to the third embodiment, the width W1 of the silicon oxide film 8 is set to 2/7 to 1 of the dimension of the gate length Lg of the gate electrode 7, so that the gate electrode 7 is stabilized. And a reduction in the maximum oscillation frequency f _max can be suppressed.

Embodiment 4 FIG.
18 to 22 are cross-sectional views showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps. Referring to FIG. 18, first, gate electrode 7 is formed in the same manner as in the first embodiment, and then silicon oxide film 16 is formed on the entire surface by CVD.

  Referring to FIG. 19, next, the silicon oxide film 16 is etched by anisotropic dry etching having a high etching rate in the depth direction of the SOI substrate 4. Thereby, a silicon oxide film 8 is formed on the side surface of the gate electrode 7. At this time, the upper surface of the silicon layer 3 exposed by etching the silicon oxide film 16 is continuously etched by overetching in anisotropic dry etching for forming the silicon oxide film 8. As a result, defects are generated in the upper surface of the silicon layer 3 due to damage caused by etching.

  Referring to FIG. 20, next, an extension 11 is formed in the upper surface of the silicon layer 3 by ion implantation. Referring to FIG. 21, next, a silicon oxide film and a silicon nitride film are entirely formed in this order by the CVD method. Next, these silicon oxide film and silicon nitride film are etched by anisotropic dry etching with a high etching rate in the depth direction of the SOI substrate 4 until the upper surface of the silicon layer 3 is exposed. Thereby, a silicon oxide film 40 and a silicon nitride film 9 are formed on the outer surface of the silicon oxide film 8. Referring to FIG. 22, next, source / drain regions 10 are formed in the silicon layer 3 by ion implantation.

  Thus, according to the method for manufacturing a semiconductor device according to the fourth embodiment, in the etching for forming silicon oxide film 8, the top surface of silicon layer 3 is etched by etching the top surface of silicon layer 3 together. A defect is formed in the inside. As a result, since this defect acts as a lifetime killer for the parasitic bipolar transistor, the gain of the parasitic bipolar transistor can be reduced. The invention according to the fourth embodiment can be applied to any of the inventions according to the first to third embodiments.

  FIG. 23 is a cross-sectional view showing a first modification of the method of manufacturing a semiconductor device according to the fourth embodiment. In FIG. 21, the silicon nitride film 9 is formed on the upper surface of the silicon layer 3 with the silicon oxide film 40 interposed therebetween. On the other hand, in the first modification of the fourth embodiment, the silicon nitride film 9 is formed directly on the upper surface of the silicon layer 3. The invention according to the first modification of the fourth embodiment can be applied to any invention according to the first to fourth embodiments.

  According to the first modification of the fourth embodiment, more lifetime killer is generated in the upper surface of the silicon layer 3 due to the stress generated at the interface between the bottom surface of the silicon nitride film 9 and the upper surface of the silicon layer 3. Can be made. As a result, the gain of the parasitic bipolar transistor can be further reduced. Thereby, it is possible to suppress the substrate floating effect which is a problem particularly in the SOI device. By suppressing the substrate floating effect, it is possible to obtain the advantage that the transient effect, the kink effect, and the hot carrier effect are suppressed, and the advantage that the current driving capability is improved.

  FIG. 24 is a cross-sectional view showing a second modification of the method of manufacturing a semiconductor device according to the fourth embodiment. 22 and 23, the anisotropic dry etching for forming the silicon nitride film 9 is stopped when the upper surface of the silicon layer 3 is exposed. On the other hand, in the second modification of the fourth embodiment, the upper surface of the silicon layer 3 is etched together by overetching in anisotropic dry etching for forming the silicon nitride film 9. The invention according to the second modification of the fourth embodiment is applied to both the invention according to the first to fourth embodiments and the invention according to the first modification of the fourth embodiment. can do.

  According to the second modification of the fourth embodiment, the upper surface of the silicon layer 3 is etched together when the silicon nitride film 9 is formed. Can be generated. As a result, the gain of the parasitic bipolar transistor can be further reduced.

  FIG. 25 is a cross-sectional view showing a third modification of the method of manufacturing a semiconductor device according to the fourth embodiment. In the third modification of the fourth embodiment, after the source / drain region 10 is formed in the silicon layer 3, the metal silicide layer 45 is formed by silicidizing the upper surface of the source / drain region 10. At this time, the upper surface of the gate electrode 7 is also silicided, and a metal silicide layer 46 is formed. The invention according to the third modification of the fourth embodiment corresponds to any of the inventions according to the first to fourth embodiments and the inventions according to the first and second modifications of the fourth embodiment. Even can be applied.

  According to the third modification of the fourth embodiment, more lifetime killer can be generated in the upper surface of the silicon layer 3 by siliciding the upper surface of the source / drain region 10. As a result, the gain of the parasitic bipolar transistor can be further reduced.

  In the fourth embodiment and the first to third modifications thereof, an object is to generate many lifetime killer in the upper surface of the silicon layer 3 in order to reduce the gain of the parasitic bipolar transistor. However, increasing the lifetime killer has the disadvantage of increasing junction leakage. For this reason, it is necessary to select an optimal structure in consideration of both the advantage of speeding up the operation by suppressing the substrate floating effect and the disadvantage of the increase in power consumption due to an increase in junction leakage.

Embodiment 5 FIG.
In the semiconductor device according to the first embodiment shown in FIG. 2, the width of the silicon oxide film 8a included in the NMOSFET and the width of the silicon oxide film 8b included in the PMOSFET are the same. In the fifth embodiment, semiconductor devices having different widths according to purposes will be described.

  FIG. 26 is a cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment of the present invention. Instead of the silicon oxide film 8b shown in FIG. 2, a silicon oxide film 8bb having a width W3 narrower than the width W1 of the silicon oxide film 8a is formed. As a result, the distance L3 between the paired source / drain regions 10b is narrower than the distance L1 between the paired source / drain regions 10a. The narrow silicon oxide film 8bb can be obtained, for example, by wet etching the silicon oxide film 8b in the process shown in FIG.

  FIG. 27 is a cross-sectional view showing the structure of another semiconductor device according to the fifth embodiment. Instead of the silicon oxide film 8a shown in FIG. 2, a silicon oxide film 8aa having a width W4 narrower than the width W1 of the silicon oxide film 8b is formed. As a result, the distance L4 between the paired source / drain regions 10a is narrower than the distance L1 between the paired source / drain regions 10b. The narrow silicon oxide film 8aa can be obtained, for example, by wet etching the silicon oxide film 8a in the process shown in FIG.

  The problem of the substrate floating effect is more likely to occur with NMOSFETs than with PMOSFETs. This is because the parasitic bipolar transistor is easily operated by holes generated by impact ionization in the vicinity of the drain. Therefore, as in the semiconductor device shown in FIG. 25, the problem of the substrate floating effect in the NMOSFET can be suppressed by increasing the width of the silicon oxide film 8a that the NMOSFET has than the silicon oxide film 8bb that the PMOSFET has. Therefore, it is possible to increase the operation speed and improve the current driving capability.

  Also, the short channel effect is more likely to occur with PMOSFETs than with NMOSFETs. Therefore, as in the semiconductor device shown in FIG. 27, the occurrence of the short channel effect in the PMOSFET can be suppressed by increasing the width of the silicon oxide film 8b included in the PMOSFET rather than the silicon oxide film 8aa included in the NMOSFET. . As a result, the roll-off characteristics of the PMOSFET are improved and an increase in off-current is suppressed, so that power consumption can be reduced.

Embodiment 6 FIG.
FIG. 17 shows the relationship between the width W1 of the silicon oxide film 8 serving as the offset insulating film, the cutoff frequency _ft, and the maximum oscillation frequency _fmax. The cutoff frequency _ft and the maximum oscillation frequency _fmax are as follows. It is used as an index indicating the performance of analog circuits and radio frequency circuits. However, in the following, an analog circuit will be described as a representative. Examples of the analog circuit include a PLL (Phase-locked loop) circuit and a sense amplifier. On the other hand, the delay time t _{pd of the} inverter is often used as an index indicating the performance of the digital circuit. The delay time t _pd is expressed by the following equation (3).

Here, C is the total capacity, V _DD is the power supply voltage, and I is the current driving capability.

FIG. 28 is a graph showing the results of measuring the relationship between the offset insulating film width W1 and the delay time t _pd for a transistor having a gate length of Lg = 70 nm. It can be seen that the delay time t _pd decreases as the width W1 of the offset insulating film decreases.

Referring to equation (3), if the width of the offset insulating film is reduced, the gate overlap capacitance increases and the total capacitance C also increases, so the delay time t _pd should increase. However, when the width of the offset insulating film is narrowed, the effective channel length is shortened and the current driving capability I is increased. This influence acts more than the influence caused by the increase in the total capacity C. As a result, as shown in FIG. 28, the delay time t _pd decreases as the width W1 of the offset insulating film decreases.

From the above, in the digital circuit, as the width of the offset insulating film becomes narrower, the delay time t _pd becomes smaller and the circuit performance improves. That is, the optimum value of the width of the insulating film for offset differs between the transistor constituting the analog circuit (or high frequency circuit) and the transistor constituting the digital circuit. Therefore, in the sixth embodiment, in a semiconductor device in which an analog circuit (or high-frequency circuit) and a digital circuit are mixedly mounted on the same substrate, insulation for offset of a transistor constituting the analog circuit (or high-frequency circuit) is performed. A semiconductor device in which the film width is different from the width of the offset insulating film of the transistor constituting the digital circuit will be described. The structure according to the sixth embodiment can be applied to any of the semiconductor devices of the first to fifth embodiments.

  FIG. 29 is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment. The SOI substrate 4 has a digital circuit formation region in which a digital circuit is formed and an analog circuit formation region in which an analog circuit is formed. The digital circuit formation region and the analog circuit formation region are electrically separated from each other by an element isolation insulating film 50 in which a complete isolation portion 51 is formed on a part of the bottom surface.

  First, regarding the digital circuit formation region, MOSFETs constituting the digital circuit are formed in the element formation region defined by the element isolation insulating films 30 and 50. This MOSFET is formed in the silicon layer 3 below the gate electrode 53 and the gate electrode 53 made of polysilicon formed on the upper surface of the silicon layer 3 with the gate oxide film 52 made of silicon oxide interposed therebetween. Body region 58 and source / drain regions 60 formed in silicon layer 3 and paired with body region 58 interposed therebetween. The source / drain region 60 has a pair of extensions 59 formed in the upper surface of the silicon layer 3 so as to extend below the gate electrode 53.

  A silicon oxide film 54 as an offset insulating film is formed in contact with the side surface of the gate electrode 53. A silicon oxide film 55 is formed outside the silicon oxide film 54, and a sidewall made of a silicon oxide film 56 and a silicon nitride film 57 is formed outside the silicon oxide film 55.

  Next, with respect to the analog circuit formation region, a MOSFET constituting the analog circuit is formed in the element formation region defined by the element isolation insulating films 30 and 50. This MOSFET is formed in the silicon layer 3 below the gate electrode 63 and the gate electrode 63 made of polysilicon formed on the upper surface of the silicon layer 3 with the gate oxide film 62 made of silicon oxide interposed therebetween. Body region 68 and source / drain regions 70 formed in silicon layer 3 and paired with body region 68 interposed therebetween. The source / drain region 70 has a pair of extensions 69 formed in the upper surface of the silicon layer 3 so as to extend below the gate electrode 63. The gate length of the gate electrode 63 is equal to the gate length of the gate electrode 53.

  Further, a silicon oxide film 64 as a first offset insulating film is formed in contact with the side surface of the gate electrode 63. A silicon oxide film 65 as a second offset insulating film is formed outside the silicon oxide film 64. The thickness of the silicon oxide film 64 is equal to the thickness of the silicon oxide film 54, and the thickness of the silicon oxide film 65 is equal to the thickness of the silicon oxide film 55. On the outside of the silicon oxide film 65, a sidewall made of a silicon oxide film 66 and a silicon nitride film 67 is formed.

  The extent to which the gate electrode 53 and the extension 59 overlap (dimension K1) in plan view (that is, when viewed from above the gate electrode) is larger than the extent to which the gate electrode 63 and extension 69 overlap in plan view (dimension K2). wide. As a result, the effective channel length of the MOSFET formed in the digital circuit formation region is shorter than the effective channel length of the MOSFET formed in the analog circuit formation region.

  30 to 35 are cross-sectional views showing the method of manufacturing the semiconductor device according to the sixth embodiment in the order of steps. Referring to FIG. 30, first, after preparing SOI substrate 4, element isolation insulating films 30 and 50 are formed in silicon layer 3.

Referring to FIG. 31, next, a silicon oxide film is formed on the entire upper surface of the silicon layer 3 and the upper surfaces of the element isolation insulating films 30 and 50 by CVD or thermal oxidation. However, instead of the silicon oxide film, a silicon oxynitride film, a metal oxide film such as Al ₂ O _3, or a ferroelectric film such as Ta ₂ O ₅ or BST may be formed. Next, a polysilicon film having a thickness of about 100 to 400 nm is formed on the entire upper surface of the silicon oxide film by LPCVD. However, impurities such as P and B may be introduced into the polysilicon film. Further, a metal film such as W, Ta, or Al may be formed instead of the polysilicon film. Next, the gate electrodes 53 and 63 and the gate oxide films 52 and 62 are formed by patterning the polysilicon film and the silicon oxide film by photolithography and anisotropic dry etching.

  Next, after a silicon oxide film having a thickness of about several nm to several tens of nm is formed on the entire surface, the silicon oxide film is etched by anisotropic dry etching with a high etching rate in the depth direction of the SOI substrate 4. . As a result, the silicon oxide film 54 is formed in contact with the side surface of the gate electrode 53, and the silicon oxide film 64 is formed in contact with the side surface of the gate electrode 63. The silicon oxide film 54 functions as an offset insulating film for forming the extension 59 in a later process. The silicon oxide film 64 functions as a first offset insulating film for forming the extension 69 in a later step.

  Referring to FIG. 32, next, a photoresist 71 is formed on the silicon layer 3 in the analog circuit formation region so as to cover the gate electrode 63 and the silicon oxide film 64 by photolithography. Next, an extension 59 is formed in the upper surface of the silicon layer 3 in the digital circuit formation region by ion implantation of impurities such as As, P, and Sb (when forming an NMOS).

  Referring to FIG. 33, next, after removing photoresist 71, a silicon oxide film having a thickness of about several nm to several tens of nm is formed on the entire surface. Thereafter, the silicon oxide film is etched in the depth direction of the SOI substrate 4 by an anisotropic dry etching method having a high etching rate. As a result, a silicon oxide film 55 is formed outside the silicon oxide film 54 and a silicon oxide film 65 is formed outside the silicon oxide film 64. The silicon oxide film 65 functions as a second offset insulating film for forming the extension 69 in a later process.

  Referring to FIG. 34, next, a photoresist 72 is formed on the silicon layer 3 in the digital circuit formation region so as to cover the gate electrode 53 and the silicon oxide films 54 and 55 by photolithography. Next, an extension 69 is formed in the upper surface of the silicon layer 3 in the analog circuit formation region by ion implantation of impurities such as As, P, and Sb (when forming an NMOS).

  Referring to FIG. 35, after removing photoresist 72, a silicon oxide film and a silicon nitride film are formed on the entire surface in this order. Next, these silicon oxide film and silicon nitride film are removed by anisotropic dry etching until the upper surface of the silicon layer 3 is exposed. As a result, a sidewall made of the silicon oxide film 56 and the silicon nitride film 57 is formed outside the silicon oxide film 55, and a side made of the silicon oxide film 66 and the silicon nitride film 67 is formed outside the silicon oxide film 65. A wall is formed. These sidewalls function as an implantation mask for forming the source / drain regions 60 and 70 in a later step.

  Thereafter, impurities such as As, P, and Sb (when forming an NMOS) are introduced into the silicon layer 3 by ion implantation, thereby forming the source / drain regions 60 and 70. Through the above steps, the structure shown in FIG. 29 is obtained.

As described above, according to the method of manufacturing a semiconductor device according to the sixth embodiment, in the digital circuit formation region, ion implantation for forming the extension 59 is performed using the silicon oxide film 54 as the offset insulating film. Is called. On the other hand, in the analog circuit formation region, ion implantation for forming the extension 69 is performed using the silicon oxide films 64 and 65 as offset insulating films. As a result, in the semiconductor device according to the sixth embodiment, the extent to which the gate electrode 53 and the extension 59 overlap in plan view (dimension K1) is the extent to which the gate electrode 63 and the extension 69 overlap in plan view (dimensions). It is wider than K2). Accordingly, the effective channel length can be shortened for the transistor constituting the digital circuit while the optimum value of the width of the offset insulating film is ensured for the transistor constituting the analog circuit (or high-frequency circuit), and the delay time t. _The performance can be improved by shortening the _pd .

  Note that the short channel effect is likely to occur when the effective channel length is shortened for the transistors constituting the digital circuit. However, in the digital circuit, the influence of the short channel effect is not a problem as in the analog circuit.

  In the above description, the invention according to the sixth embodiment has been described taking the case of forming an NMOS transistor as an example. However, the invention according to the sixth embodiment can be applied to the case of forming a PMOS transistor or a CMOS transistor. Applicable. The same applies to the seventh embodiment described later.

Embodiment 7 FIG.
From the above equation (2), it is found that can increase the maximum oscillation frequency f _max by lowering the gate resistance R _g. In the seventh embodiment, a gate structure capable of reducing gate resistance will be described. The gate structure according to the seventh embodiment can be applied to any of the semiconductor devices of the first to sixth embodiments.

  FIG. 36 is a top view schematically showing the structure of the semiconductor device according to the seventh embodiment of the present invention. A pair of source / drain regions 76 are formed with the gate electrode 75 interposed therebetween. A plurality of contact plugs 77 that are in contact with the source / drain regions 76 are formed.

  37 is a cross-sectional view showing a cross-sectional structure related to the position along the line segment A1-A1 shown in FIG. 36, and FIG. 38 shows a cross-sectional structure related to the position along the line segment A2-A2 shown in FIG. It is sectional drawing shown. Referring to FIG. 37, a polysilicon film 79 is formed on the upper surface of silicon layer 3 via a gate oxide film 78 made of a silicon oxide film. A metal silicide layer 80 is formed on the polysilicon film 79, and the gate electrode 75 is constituted by the polysilicon film 79 and the metal silicide layer 80. A side wall 83 made of a silicon oxide film 81 and a silicon nitride film 82 is formed on the side surface of the gate electrode 75. A side wall 86 made of a silicon oxide film 84 and a silicon nitride film 85 is formed on the side surface of the side wall 83 opposite to the gate electrode 75.

  A body region 88 is formed in the silicon layer 3 below the gate electrode 75. Further, in the silicon layer 3, a source / drain region 76 that forms a pair with the body region 88 interposed therebetween is formed. The source / drain region 76 has a pair of extensions 87 formed in the upper surface of the silicon layer 3 so as to extend below the gate electrode 75. A metal silicide layer 89 is formed on the upper surface of the source / drain region 76 where the sidewalls 83 and 86 are not formed.

  An interlayer insulating film 90 made of a silicon oxide film is formed on the silicon layer 3 so as to cover the MOSFET. A contact plug 77 made of metal is formed in the interlayer insulating film 90 from the upper surface of the interlayer insulating film 90 to the upper surface of the metal silicide layer 89. On the upper surface of the interlayer insulating film 90, a metal wiring 91 made of a metal such as aluminum or copper is formed in contact with the contact plug 77. In the interlayer insulating film 90, a gate wiring 92 made of metal is formed from the upper surface of the interlayer insulating film 90 to the upper surfaces of the metal silicide layer 80 and the sidewall 83. The dimension of the gate wiring 92 in the gate length direction is larger than the gate length of the gate electrode 75.

  Referring to FIG. 38, gate wiring 92 is formed to extend in the direction in which gate electrode 75 extends while in contact with the upper surface of gate electrode 75.

  39 to 43 are cross-sectional views showing the method of manufacturing the semiconductor device according to the seventh embodiment in the order of steps. Referring to FIG. 39, first, after preparing SOI substrate 4, element isolation insulating film 30 is formed in silicon layer 3. Next, the gate oxide film 78 and the polysilicon film 79 are formed on the upper surface of the silicon layer 3 by the method described in the above embodiments. Next, an extension 87 is formed by introducing impurities such as As, P, and Sb (when forming an NMOS) into the upper surface of the silicon layer 3 by ion implantation. At this time, by applying the concept of the invention according to the first to sixth embodiments, an insulating film for offset is formed on the side surface of the polysilicon film 79 before ion implantation is performed. The channel length may be increased.

  Referring to FIG. 40, next, a silicon oxide film and a silicon nitride film are formed on the entire surface in this order by the CVD method. Next, these films are etched by anisotropic dry etching with a high etching rate in the depth direction of the SOI substrate 4 until the upper surface of the silicon layer 3 is exposed. As a result, the silicon oxide film 81 and the silicon nitride film 82 remain on the side surfaces of the polysilicon film 79, and the sidewalls 83 are formed. Next, impurities such as As, P, and Sb (when forming an NMOS) are introduced into the silicon layer 3 by ion implantation to form the source / drain regions 76. The sidewall 83 functions as an implantation mask in the ion implantation process for forming the source / drain regions 76.

  Referring to FIG. 41, next, a silicon oxide film and a silicon nitride film are formed in this order on the entire surface by CVD. Next, these films are etched by anisotropic dry etching with a high etching rate in the depth direction of the SOI substrate 4 until the upper surface of the silicon layer 3 is exposed. As a result, the silicon oxide film 84 and the silicon nitride film 85 remain on the side surface of the sidewall 83, and the sidewall 86 is formed. At this time, the dimension of the sidewall 86 in the gate length direction can be made different from the dimension of the sidewall 83 in the gate length direction by adjusting the thickness of the silicon nitride film, the etching conditions, and the like.

  Referring to FIG. 42, heat treatment is performed after a metal film such as cobalt is formed on the entire surface. As a result, the silicon and metal in the portions in contact with each other react to form metal silicide layers 80 and 89. The metal silicide layer 80 is formed on the polysilicon film 79, whereby the gate electrode 75 is formed. The metal silicide layer 89 is formed on the source / drain region 76. Thereafter, the unreacted metal film is removed.

  Referring to FIG. 43, next, an interlayer insulating film 90 is formed by depositing a silicon oxide film on the entire surface by the CVD method. Next, a photoresist (not shown) having a predetermined opening pattern is formed on the upper surface of the interlayer insulating film 90 by photolithography. Next, using the photoresist as an etching mask, the interlayer insulating film 90 is removed by anisotropic dry etching having a high etching rate in the depth direction of the SOI substrate 4. At this time, it is possible to prevent the upper surface of the sidewall 83 from being etched by performing the etching under the condition that the silicon oxide film is easily etched and the silicon nitride film is not easily etched. As a result, a contact hole 93 is formed on the metal silicide layer 76 and a wiring trench 94 is formed on the gate electrode 75.

  At this time, it is desirable to form the photoresist opening pattern so that the dimension M1 of the contact hole 93 in the gate length direction is larger than the dimension M2 of the wiring groove 94 in the gate length direction. The reason is as follows. That is, since the wiring trench 92 extends along the gate electrode 75, the opening area of each contact hole 93 is smaller than the opening area of the wiring trench 92. Therefore, the etching of the contact hole 93 is less likely to proceed than the etching of the wiring groove 92. Therefore, the difference in etching rate can be reduced by making the dimension M1 larger than the dimension M2.

  Next, a metal film (Al, W, Cu, etc.) is formed on the entire surface with a film thickness that can fill the contact hole 93 and the wiring groove 94, and the metal film is etched back until the upper surface of the interlayer insulating film 90 is exposed. To do. Here, in order to improve the adhesion of the metal film, a barrier metal layer may be formed before the metal film is formed. The material of the barrier metal layer is titanium (Ti), titanium nitride (TiN), a composite film of Ti and TiN, or the like. Thereafter, metal wiring 91 is formed to obtain the structure shown in FIG.

As described above, according to the semiconductor device of the seventh embodiment, the gate electrode 75 extends in the extending direction while being in contact with the upper surface of the gate electrode 75, and the dimension in the gate length direction is the gate electrode 79. A gate wiring 92 larger than the gate length is formed in the interlayer insulating film 90. Therefore, the gate resistance R _g in the above equation (2) is reduced, and the maximum oscillation frequency f _max can be increased.

  Further, according to the method of manufacturing a semiconductor device according to the seventh embodiment, the sidewall 86 is formed outside the sidewall 83. Therefore, even when the formation position of the wiring trench 94 is shifted due to misalignment of the photomask or the like, it is possible to avoid the gate wiring 92 and the metal silicide layer 89 from contacting each other. That is, by forming the sidewall 86, it is possible to improve the margin of misalignment. The larger the dimension of the sidewall 86 in the gate length direction, the greater this effect.

  However, if the dimension of the sidewall 86 in the gate length direction becomes too large, the dimension of the metal silicide layer 76 in the gate length direction becomes small and the source / drain series resistance increases. Therefore, it is necessary to optimize the dimension of the sidewall 86 in the gate length direction by comparing the merit of improving the margin of misalignment with the demerit of increasing the source / drain series resistance.

  Note that the margin of misalignment can be improved by simply increasing the width of the side wall 83 instead of forming the side wall 83 and the side wall 86 separately. However, in this case, the distance between the paired source / drain regions 76 is widened, and the length of the extension 87 is increased, so that the series resistance at that portion is increased and the current driving capability is lowered. On the other hand, when the source / drain region 76 is formed after the sidewall 83 is formed and the sidewall 86 is formed after that, as in the method of manufacturing the semiconductor device according to the seventh embodiment, the length of the extension 87 is increased. The current drive capability can be prevented from being reduced.

  1 silicon substrate, 2 BOX layer, 3 silicon layer, 4 SOI substrate, 6, 8, 54, 55, 64, 65 silicon oxide film, 7, 53, 63, 75 gate electrode, 9 silicon nitride film, 10 source / drain Region, 11, 59, 69 extension, 12 body region, 83, 86 sidewall, 92 gate wiring.

Claims (8)

A substrate,
(A) a gate electrode formed on the main surface of the substrate across a gate insulating film and extending along a predetermined direction; (b) a first sidewall formed on a side surface of the gate electrode; A semiconductor element having a body region formed in the substrate below the gate electrode, and (d) a source / drain region formed in the substrate and paired with the body region interposed therebetween,
An interlayer insulating film formed on the substrate to cover the semiconductor element;
A gate wiring that extends in the predetermined direction while being in contact with the upper surface of the gate electrode and is formed in the interlayer insulating film, wherein a dimension of the gate electrode in a gate length direction is larger than the gate length of the gate electrode; A semiconductor device provided.   The semiconductor device according to claim 1, further comprising a second sidewall formed on the side surface of the gate electrode with the first sidewall interposed therebetween.   The semiconductor device according to claim 2, wherein a dimension of the second sidewall in the gate length direction is larger than a dimension of the first sidewall in the gate length direction. A contact plug connected to the source / drain region and formed in the interlayer insulating film;
4. The semiconductor device according to claim 1, wherein a dimension of the gate wiring in the gate length direction is smaller than a dimension of the contact plug in the gate length direction. (A) preparing a substrate;
(B) forming a gate electrode extending along a predetermined direction across the gate insulating film on the main surface of the substrate;
(C) forming a first sidewall on the side surface of the gate electrode;
(D) forming an interlayer insulating film on the substrate so as to cover the gate electrode and the first sidewall;
(E) A dimension of the gate electrode in the gate length direction is larger than the gate length of the gate electrode, and a gate wiring extending in the predetermined direction while contacting the upper surface of the gate electrode is formed in the interlayer insulating film. A method for manufacturing a semiconductor device.   (F) The method according to claim 5, further comprising a step of forming a second sidewall on the side surface of the gate electrode with the first sidewall interposed therebetween, the step being performed before the step (d). A method for manufacturing a semiconductor device.   7. The semiconductor according to claim 6, wherein in the step (f), the second sidewall having a dimension in the gate length direction larger than a dimension of the first sidewall in the gate length direction is formed. Device manufacturing method. (S) forming a pair of source / drain regions in the substrate across the body region below the gate electrode;
(T) A contact plug that is executed by the same step as the step (e), is connected to the source / drain region, and has a dimension in the gate length direction larger than a dimension of the gate wiring in the gate length direction. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming in the interlayer insulating film.

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