JP2014112907A - Antenna switch circuit and communication terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make compatible allowable power characteristics and insertion loss characteristics, to reduce in size of an antenna switch circuit, and to further stabilize a switching state.SOLUTION: An antenna switch circuit according to the present invention includes: a series transistor circuit connected in series between a transmission port and an antenna port; a parallel transistor circuit connected in parallel between the transmission port and the antenna port; and an impedance conversion circuit provided between the transmission port and the parallel transistor circuit, and reducing a voltage swing of a transmission signal inputted from the transmission port by a predetermined conversion ratio by performing impedance conversion. In the impedance conversion circuit, the predetermined conversion ratio is set so that an inter-terminal voltage outputted to the parallel transistor circuit is less than or equal to the threshold value of the parallel transistor circuit.

Description

  The present invention relates to an antenna switch circuit that switches an antenna connection destination to a transmission port or a reception port. The present invention also relates to a communication terminal equipped with an antenna switch circuit.

  In recent years, a dual-mode (Dual Mode) system equipped with two systems of WCDMA and GSM is becoming mainstream. In this case, when a GSM system is used, since the output is high, it is important to make the antenna switch circuit have two characteristics of allowable power and insertion loss characteristic.

  A technique related to the antenna switch circuit is described in Patent Document 1, for example. Patent Document 1 describes a signal changeover switch in which an impedance conversion circuit is provided between an antenna terminal, a reception terminal, a transmission terminal, and a switch circuit. Then, the signal power propagating through the switch circuit is made by making the impedance smaller than the impedance when the impedance conversion circuit is viewed from the antenna terminal, the reception terminal and the transmission terminal when viewed from the switch circuit. The amplitude of the voltage wave is reduced. With such a configuration, even when a high-power signal is input, the switching state is kept stable to some extent and the maximum transmittable power is improved.

JP-A-10-93471 (paragraphs 0037-0038, FIG. 4)

  The antenna switch circuit generally has the following problems. For example, when GSM900 is used, the maximum output is about +35 dBm, and the voltage amplitude is about ± 17.8 V with a 50Ω load. In order to withstand this large voltage amplitude, FETs are connected in multiple stages in the antenna switch circuit. Therefore, the antenna switch circuit cannot be reduced in size. In general, the nonlinear distortion generated in the antenna switch circuit is caused by the capacitance of the FET that is turned off, and it is known that the linearity of the FET can be secured by reducing the off capacitance.

  For example, in order to obtain good characteristics in an antenna switch circuit, a booster circuit is mounted on the antenna switch circuit. This also makes it impossible to downsize the antenna switch circuit.

  FIG. 7 is an explanatory diagram showing an outline of SPDT (Single Pole Double Throw) of the antenna switch circuit. In the antenna switch circuit, FETs 91 and 92 are connected in multiple stages as shown in FIG. 7 in order to cope with a high output system. As described above, the gate-source voltage is divided by dividing the drain-source voltage applied to each FET, thereby improving the maximum allowable power.

  However, when FETs are connected in multiple stages, a passage loss occurs, and off-capacitance and chip area increase. In addition, even if multiple stages are connected, the power supply voltage of the communication system may not be able to suppress the voltage amplitude below the threshold value of the parallel FET 91, which limits the maximum allowable power.

  In order to improve inconvenience such as limitation of the maximum allowable power as described above, the output of the logic circuit 94 is separately amplified using a booster circuit 93 in the antenna switch circuit as shown in FIG. Yes. With such a configuration, the gate potential applied to the FET can be made larger than the power supply voltage of the communication system, and the gate-source voltage can be kept large. Therefore, even with a high output voltage amplitude, it is possible to operate below the threshold value of the parallel FET 91, and the parallel FET 91 is kept off and the series FET 92 is kept on.

  However, if the booster circuit 93 is provided, a large-scale chip area is required in the antenna switch circuit, which makes it difficult to miniaturize and affects the cost increase. In addition, since the booster circuit includes the oscillation circuit, unnecessary spurious is generated and the reception characteristic of the communication system is affected. Furthermore, current consumption for the booster circuit 93 occurs, leading to an increase in current consumption.

  If the related technique described in Patent Document 1 is used, by providing an impedance conversion circuit, it is possible to secure a certain degree of stabilization of the switching state and improvement of maximum transmittable power when a high-power signal is input. However, Patent Document 1 does not disclose that the operation can be performed below the threshold value of the parallel FET in the signal switching switch even at a high output voltage amplitude, and the switching state is not necessarily stabilized. It ’s not that hard.

  Therefore, the present invention provides an antenna switch circuit and a communication terminal that can achieve both the characteristics of allowable power and insertion loss, can reduce the size of the antenna switch circuit, and can further stabilize the switching state. The purpose is to provide.

  An antenna switch circuit according to the present invention includes a series transistor circuit connected in series between a transmission port and an antenna port, a parallel transistor circuit connected in parallel between the transmission port and the antenna port, and a transmission port in parallel. A first impedance conversion circuit provided between the transistor circuit and performing impedance conversion to reduce a voltage amplitude of a transmission signal input from the transmission port at a predetermined conversion ratio; a series transistor circuit; and an antenna port. And a second impedance conversion circuit for returning the transmission signal whose voltage amplitude is reduced by the first impedance conversion circuit to the original voltage amplitude level. The first impedance conversion circuit is configured using a transformer. The transformer constituting the first impedance conversion circuit is a parallel transformer. Inter-terminal voltage is outputted to the register circuit, characterized in that the predetermined conversion ratio to be equal to or less than the threshold value of the parallel transistor circuit are set.

  A communication terminal according to the present invention includes an antenna switch circuit that switches an antenna connection destination to a transmission port or a reception port. The antenna switch circuit includes a series transistor circuit connected in series between the transmission port and the antenna port, and a transmission A parallel transistor circuit connected in parallel between the port and the antenna port, and a voltage amplitude of the transmission signal input from the transmission port by performing impedance conversion, provided between the transmission port and the parallel transistor circuit. A first impedance conversion circuit that is reduced at a predetermined conversion ratio, and a transmission signal that is provided between the series transistor circuit and the antenna port and whose voltage amplitude is reduced by the first impedance conversion circuit is returned to the original voltage amplitude level. A second impedance conversion circuit, and a first impedance The conversion circuit is configured using a transformer, and the transformer constituting the first impedance conversion circuit has a predetermined conversion ratio set so that the terminal voltage output to the parallel transistor circuit is equal to or less than the threshold value of the parallel transistor circuit. It is characterized by being.

  According to the present invention, the characteristics of allowable power and insertion loss can be made compatible, the antenna switch circuit can be downsized, and the switching state can be further stabilized.

It is a block diagram which shows an example of a structure of the SPDT antenna switch circuit by this invention. It is explanatory drawing for demonstrating the principle of operation of the impedance conversion circuit which the SPDT antenna switch circuit shown in FIG. 1 mounts. It is explanatory drawing for _{demonstrating the} gate source voltage _VGS2 input into parallel FET. It is explanatory drawing for _{demonstrating the} voltage _VGS1 between the gate sources of series FET1. It is a block diagram which shows an example of a structure of the SPDT antenna switch circuit in 2nd Embodiment. It is a block diagram which shows the minimum structural example of a SPDT antenna switch circuit. It is explanatory drawing which shows the outline | summary of SPDT of an antenna switch circuit.

Embodiment 1. FIG.
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of an SPDT antenna switch circuit according to the present invention. In the present embodiment, the SPDT antenna switch circuit is used, for example, to switch the connection destination of the antenna port (ANT port) to the transmission port (Tx port) side or the reception port (Rx port) side. In this embodiment, a case of an SPDT type antenna switch circuit that switches connection between one antenna port and two transmission / reception ports will be described. However, the present invention is also applicable to antenna switch circuits other than SPDT type. is there. For example, the present invention can be applied to an nPnT type antenna switch circuit that switches connection between an antenna port and a transmission / reception port in a system including a plurality of antenna ports and three or more transmission / reception ports.

  In this embodiment, the SPDT antenna switch circuit is applied to a mobile terminal such as a mobile phone equipped with a system such as WCDMA or GSM. The SPDT antenna switch circuit is not limited to a mobile phone, and may be applied to a communication terminal such as a WLAN communication terminal or a mobile terminal communication device using communication means such as Bluetooth.

  As shown in FIG. 1, in the SPDT antenna switch circuit, an impedance conversion circuit 3 is connected to the Tx port side. The impedance conversion circuit 3 includes a circuit element such as a capacitor and is configured not to directly flow a direct current from the Tx port side to the SPDT antenna switch circuit side. The impedance conversion circuit 3 is configured such that field effect transistors (FETs) 1 and 2 arranged adjacent to each other can be biased. In the present embodiment, FETs 1 and 11 connected in parallel between the Tx port, the Rx port, and the ANT port in the SPDT antenna switch circuit are referred to as parallel FETs. The FETs 2 and 10 connected in series between the Tx port and the Rx port and the ANT port are referred to as series FETs.

  The impedance conversion circuit 3 is connected to the source electrode of the parallel FET 1 and the source electrode of the series FET 2. The impedance conversion circuit 3 is provided between the Tx port and the parallel FET 1 and has a function of reducing the voltage amplitude of the transmission signal input from the Tx port by a predetermined conversion ratio by performing impedance conversion. In the present embodiment, the conversion ratio of the impedance conversion circuit 3 is set so that the gate-source voltage output to the parallel FET 1 is equal to or lower than the threshold value of the parallel FET 1.

  In addition, the source electrode and the drain electrode of the FETs 1 and 2 are biased with a voltage having the same potential via a bias resistor, and are stable in a direct current. Further, the drain electrode of the parallel FET 1 is grounded at a high frequency via a capacitor.

Control voltages V _CT1 and V _CT2 generated from the logic circuit 5 are applied to the gate electrodes of the parallel FET 1 and the serial FET ₂ through gate resistors, respectively. Further, gate source voltages V _GS1 and V _GS2 are applied between the gates and sources of the parallel FET 1 and the serial FET ₂ , respectively. Further, the control voltage V _CT1 applied to the parallel FET 1 is also applied to the gate electrode of the series FET 10 connected to the Rx port side. Further, the control voltage V _CT2 applied to the series FET ₂ is also applied to the parallel FET 11 connected to the Rx port side. It is assumed that the operation state of each FET is synchronized with the connection state and the application state of the control voltage.

  Furthermore, an impedance conversion circuit 4 is arranged between the drain electrode of the series FET 2 and the antenna port (ANT port), and impedance matching is performed with a load impedance 12 of a system such as WCDMA or GSM mounted on the portable terminal. That is, in the present embodiment, since the transmission signal whose voltage amplitude is reduced by the impedance conversion circuit 3 is input to the parallel FET 1 and the series FET 2, in order to return to the original voltage amplitude level on the output side from the series FET 2. The impedance conversion circuit 4 is required.

  Similarly, on the Rx port side, the source electrodes of the series FET 10 and the parallel FET 11 are respectively connected to the Rx port. Further, the source electrode and the drain electrode of the FETs 10 and 11 are biased with a voltage having the same potential through a bias resistor, and are stable in terms of DC. The drain electrode of the parallel FET 11 is grounded at a high frequency via a capacitor. Furthermore, the drain electrode of the series FET 10 is connected to an antenna port (ANT port).

  As described above, the SPDT antenna switch circuit is configured. For example, the FET has a symmetrical structure with respect to the gate electrode, not limited to the configuration shown in the present embodiment. Therefore, in the SPDT antenna switch circuit shown in FIG. 1, the source electrode and the drain electrode are arranged in reverse. You may make it comprise.

  In the SPDT antenna switch circuit, an N-type (Nch) FET or a P-type (Pch) FET may be used as the FET. In this embodiment, the FETs 1, 2, 10, and 11 are configured as a single unit. However, the FETs 1, 2, 10, and 11 may be connected in multiple stages using a plurality of FETs.

  Further, in the present embodiment, the case where a circuit configured by using a circuit element such as a capacitor is used as the impedance conversion circuits 3 and 4, but the impedance conversion circuit mounted on the SPDT antenna switch circuit is the present embodiment. It is not limited to what is shown in. For example, the SPDT antenna switch circuit includes a balun (balanced / unbalanced converter), a transformer, an LC matching circuit composed of an inductance L and a capacitance C, and impedance conversion circuits 3 and 4 configured using microstrip lines. May be installed.

  Next, the operation will be described. FIG. 2 is an explanatory diagram for explaining the operating principle of the impedance conversion circuit 3 mounted on the SPDT antenna switch circuit shown in FIG. As shown in FIG. 2, a high-output transmission signal is input to the impedance conversion circuit 3 from a system such as WCDMA or GSM. In the example illustrated in FIG. 2, the impedance conversion circuit 3 is configured using, for example, a transformer that converts the voltage amplitude to n: 1. The impedance conversion circuit 3 impedance-converts the input high-output transmission signal and outputs a signal obtained by converting the voltage amplitude to 1 / n.

  Assuming an ideal state and assuming that the conversion loss is 0, the current amplitude of the transmission signal after conversion is n times, and is stored so that the power does not fluctuate. The transmission signal whose voltage amplitude is converted to 1 / n by the impedance conversion circuit 3 is input to the source electrodes of the serial FET 2 and the parallel FET 1 shown in FIG.

In the present embodiment, a circuit having an appropriate conversion ratio n is used as the impedance conversion circuit 3, and the gate-source voltage V _GS1 input to the parallel FET 1 is always less than or equal to the threshold value of the FET, as shown in FIG. Suppose that it can be suppressed. Therefore, the off state of the parallel FET 1 can be reliably maintained. Accordingly, since the parallel FET 1 is not turned on, a transmission mode in which a transmission signal does not leak to the ground (GND) can be maintained, and insertion loss can be improved.

  In the present embodiment, the gate-source voltage of the parallel FET 1 can be increased (that is, the potential difference between the gate and the source can be increased). Accordingly, the channel immediately under the gate is completely depleted, so that the off-capacitance can be surely reduced. Further, even when a high-output transmission signal is input, it is possible to suppress the off-capacitance from fluctuating due to the voltage. That is, the linearity of the off capacitance can be improved. Therefore, the capacity loss can be reduced by reducing the off-capacitance, and the occurrence of IMD (Inter Modulation Distortion) and harmonic distortion can be suppressed by improving the linearity of the off-capacitance.

Conversely, as shown in FIG. 4, the gate-source voltage V _GS2 of the series FET ₂ can be applied so as to be always equal to or higher than the threshold value of the FET, and the ON state of the series FET 2 can be reliably maintained. . Therefore, since the series FET 2 is not turned off, the on-resistance between the drain and the source can be suppressed from fluctuating depending on the voltage, and insertion loss at the time of transmission signal input can be improved.

  As described above, according to the present embodiment, the SPDT antenna switch circuit includes the impedance conversion circuit 3 on both the input and output sides of the FETs 1 and 2 on the Tx port side. With such a configuration, even when a high-output transmission signal is input, the voltage amplitude of the signal input to the FETs 1 and 2 is converted, so that the operation is stably performed below the threshold voltage of the FET. be able to. Further, by providing the impedance conversion circuit 4, it is possible to return to the impedance of the system such as WCDMA or GMS, and to obtain a transmission signal having a normal voltage amplitude. Therefore, even in the case of using a high-power communication system in an antenna switch circuit of a communication system mounted on a mobile terminal or the like, a booster circuit can be dispensed with, and nonlinear distortion generated in an FET is suppressed and low insertion is achieved. Loss can be secured.

  In other words, according to the present embodiment, the SPDT antenna switch circuit can be configured without the need for a booster circuit, so that the chip area can be reduced, and downsizing and cost reduction can be realized. Further, since a booster circuit is not required, unnecessary spurious can be suppressed and current consumption can be suppressed.

  In addition, according to the present embodiment, it is possible to configure the FET without connecting the FETs more than necessary, so that the insertion loss can be suppressed. Further, since the FETs can be configured without connecting more stages than necessary, the chip area can be reduced, and downsizing and cost reduction can be realized.

  Therefore, the characteristics of the allowable power and the insertion loss can be made compatible, the SPDT antenna switch circuit can be miniaturized, and the switching state can be further stabilized.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing an example of the configuration of the SPDT antenna switch circuit in the second embodiment. In the present embodiment, as shown in FIG. 5, the basic configuration of the SPDT antenna switch circuit is the same as that of the first embodiment, but the impedance conversion circuit is combined with a power amplifier (hereinafter referred to as a power amplifier). It is composed. In the example shown in FIG. 5, the impedance conversion circuit is realized using a capacitor.

  In the present embodiment, a power amplifier is mounted on the SPDT antenna switch circuit. In general, when a power amplifier is used, a power amplifier main body portion and an output matching circuit for performing output matching are often used as a set. In the present embodiment, as shown in FIG. 5, in the SPDT antenna switch circuit, only the power amplifier 41 portion excluding the output matching circuit 42 is connected to the Tx port side.

  In the case of only the power amplifier 41 portion excluding the output control circuit 42, the output impedance of the power amplifier 41 is originally a low value for taking out electric power. Therefore, the maximum output voltage amplitude of the signal output from the power amplifier 41 is about twice the power supply voltage. Therefore, in the present embodiment, the gate-source voltage applied to the FETs 1 and 2 of the antenna switch circuit is matched with the output amplitude of the signal output from the power amplifier 41, and on the output side of the series FET 2 after passing through the FETs 1 and 2. A matching circuit 42 of the power amplifier 41 is arranged. With such a configuration, it is possible to eliminate the necessity of providing the impedance conversion circuit 4 shown in the first embodiment by substituting the output matching circuit 42 of the power amplifier 41 in the SPDT antenna switch circuit. When the amplifier is used, the cost of the SPDT antenna switch circuit can be reduced.

  As described above, according to this embodiment, in addition to the effects shown in the first embodiment, it is not necessary to provide the impedance conversion circuit 4 by substituting the output matching circuit 42 of the power amplifier 41. Thus, the cost of the SPDT antenna switch circuit when using a power amplifier can be reduced.

  Next, the minimum configuration of the SPDT antenna switch circuit according to the present invention will be described. FIG. 6 is a block diagram showing a minimum configuration example of the SPDT antenna switch circuit. As shown in FIG. 6, the SPDT antenna switch circuit includes a series FET 2, a parallel FET 1, and an impedance conversion circuit 3 as minimum components.

  In the SPDT antenna switch circuit, the series FET 2 is connected in series between the Tx port and the ANT port. The parallel FET 1 is connected in parallel between the Tx port and the ANT port. The impedance conversion circuit 3 is provided between the Tx port and the parallel FET 1 and has a function of reducing the voltage amplitude of the transmission signal input from the Tx port by a predetermined conversion ratio by performing impedance conversion. In addition, the impedance conversion circuit 3 has a predetermined conversion ratio set so that the terminal voltage output to the parallel FET 1 is equal to or less than the threshold value of the parallel FET 1.

  According to the SPDT antenna switch circuit having the minimum configuration shown in FIG. 6, the characteristics of allowable power and insertion loss are compatible, the size of the SPDT antenna switch circuit can be reduced, and the switching state can be further stabilized. be able to.

  In each of the embodiments described above, the characteristic configuration of the antenna switch circuit as shown in the following (1) to (6) is shown.

(1) An antenna switch circuit (for example, SPDT antenna switch circuit) is a series transistor circuit (for example, series FET2) connected in series between a transmission port (for example, Tx port) and an antenna port (for example, ANT port). ), A parallel transistor circuit (for example, parallel FET1) connected in parallel between the transmission port and the antenna port, and a transmission port by performing impedance conversion between the transmission port and the parallel transistor circuit. And an impedance conversion circuit (for example, impedance conversion circuit 3) that reduces the voltage amplitude of the transmission signal input from a predetermined conversion ratio (for example, n: 1), and the impedance conversion circuit is output to the parallel transistor circuit. that the inter-terminal voltage (e.g., gate-source voltage _{V GS1)} is brought Wherein the predetermined conversion ratio to be equal to or less than the threshold value of the parallel transistor circuit are set.

(2) The antenna switch circuit includes a power amplifier (for example, power amplifier 41) with a matching circuit (for example, output matching circuit 42), and is an impedance conversion circuit combined with the power amplifier portion excluding the matching circuit. May be provided between the transmission port and the parallel transistor circuit, and the matching circuit may be provided on the output side of the series transistor circuit.

(3) In the antenna switch circuit, the impedance conversion circuit may be configured using a transformer.

(4) In the antenna switch circuit, the impedance conversion circuit may be configured using a balun.

(5) In the antenna switch circuit, the impedance conversion circuit may be configured using a microstrip line.

(6) In the antenna switch circuit, the impedance conversion circuit may be configured using a matching circuit (for example, an LC matching circuit) including an inductance and a capacitance.

  The present invention is applied to a portable terminal such as a cellular phone equipped with a system such as WCDMA or GSM. In addition, the present invention is applied to a communication terminal such as a WLAN communication terminal or a mobile terminal communication device using communication means such as Bluetooth.

1,11 Parallel FET
2,10 series FET
3,4 impedance conversion circuit 5 logic circuit 12 load impedance 41 power amplifier 42 output matching circuit

Claims (4)

A series transistor circuit connected in series between the transmission port and the antenna port;
A parallel transistor circuit connected in parallel between the transmission port and the antenna port;
A first impedance conversion circuit that is provided between the transmission port and the parallel transistor circuit and reduces the voltage amplitude of the transmission signal input from the transmission port by a predetermined conversion ratio by performing impedance conversion;
A second impedance conversion circuit provided between the series transistor circuit and the antenna port for returning a transmission signal whose voltage amplitude is reduced by the first impedance conversion circuit to the original voltage amplitude level;
The first impedance conversion circuit is configured using a transformer,
The transformer constituting the first impedance conversion circuit has the predetermined conversion ratio set so that a voltage between terminals output to the parallel transistor circuit is equal to or less than a threshold value of the parallel transistor circuit. An antenna switch circuit. A power amplifier with a matching circuit,
A first impedance conversion circuit combined with the power amplifier part excluding the matching circuit is provided between the transmission port and the parallel transistor circuit;
The antenna switch circuit according to claim 1, wherein the matching circuit is provided on an output side of the series transistor circuit. An antenna switch circuit that switches the antenna connection destination to the transmission port or the reception port is provided.
The antenna switch circuit is
A series transistor circuit connected in series between the transmission port and the antenna port;
A parallel transistor circuit connected in parallel between the transmission port and the antenna port;
A first impedance conversion circuit that is provided between the transmission port and the parallel transistor circuit and reduces the voltage amplitude of the transmission signal input from the transmission port by a predetermined conversion ratio by performing impedance conversion;
A second impedance conversion circuit provided between the series transistor circuit and the antenna port for returning a transmission signal whose voltage amplitude is reduced by the first impedance conversion circuit to the original voltage amplitude level;
The first impedance conversion circuit is configured using a transformer,
The transformer constituting the first impedance conversion circuit has the predetermined conversion ratio set so that a voltage between terminals output to the parallel transistor circuit is equal to or less than a threshold value of the parallel transistor circuit. Communication terminal. The antenna switch circuit includes a power amplifier with a matching circuit,
A first impedance conversion circuit combined with the power amplifier part excluding the matching circuit is provided between the transmission port and the parallel transistor circuit;
The communication terminal according to claim 3, wherein the matching circuit is provided on an output side of the series transistor circuit.

Images