JP2014109865A - Device for designing logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for designing a logic circuit in which safety, circuit scale, and an operation frequency are considered.SOLUTION: A device for designing a logic circuit corresponding to an input logical formula comprises: input means that inputs the number of registers; and determination means that determines insertion positions of registers for storing intermediate values as many as the number of registers separately from a register for storing an input value to the logic circuit and a register for storing an output value of the logic circuit. The determination means determines the insertion positions of the registers so that a difference in the number of logic elements between registers is equal to or smaller than a predetermined value.

Description

  The present invention relates to a logic circuit design technique considering circuit scale, operating frequency, and resistance to side channel attacks.

  For example, hardware that performs cryptographic processing must be configured to prevent leakage of secret information such as cryptographic keys handled by the hardware due to side channel attacks or the like. Patent Documents 1 and 2 and Non-Patent Documents 1 and 2 disclose safe mounting methods of logic circuits that prevent leakage of information handled by hardware.

JP 2007-334016 A JP 2012-004888 A

Joan Daemen, et al. , “Bitsciphers and Power Analysis Attacks,” Proc. of Fast Software Encryption (FSE2000), Texture Notes in Computer Science 1978, pp.134-149, 2000 Jovan Dj. Golic, et al. , “Universal Masking on Logic Gate Level”, Electronics Letters, Vol. 40, No. 9, April 29, 2004

  However, in the hardware configuration, it is necessary to consider not only the safety against side channel attacks and the like, but also the circuit scale and operating frequency. However, the above prior art does not consider the circuit scale or the operating frequency.

  The present invention provides a logic circuit design device that takes safety, circuit scale, and operating frequency into consideration, and a program that causes a computer to function as the design device.

  According to one aspect of the present invention, there is provided an apparatus for designing a logic circuit corresponding to an input logical expression, input means for inputting the number of registers, a register for storing an input value to the logic circuit, and the logic circuit Apart from a register for storing the output value of the output, a determination means for determining the register insertion position of the number of registers for storing the intermediate value, wherein the determination means has a difference in the number of logical elements between the registers. The insertion position of the register is determined so as to be less than a predetermined value.

  According to one aspect of the present invention, an apparatus for designing a logic circuit corresponding to an input logical expression, the input means for inputting the number of registers and the maximum number of elements, and a register for storing an input value to the logic circuit; In addition to the register for storing the output value of the logic circuit, the register for storing the intermediate value of the logic circuit is inserted by the number of registers input to the input means, whereby the number of elements between the registers is set to the maximum element. It is characterized by comprising determination means for determining whether or not the number can be reduced, and output means for outputting a warning when the maximum number of elements cannot be reduced.

  A logic circuit can be designed in consideration of safety, circuit scale and operating frequency.

Explanatory drawing of the design method of the logic circuit by one Embodiment. Explanatory drawing of the design method of the logic circuit by one Embodiment. Explanatory drawing of the design method of the logic circuit by one Embodiment. Explanatory drawing of the design method of the logic circuit by one Embodiment. Explanatory drawing of the design method of the logic circuit by one Embodiment. Explanatory drawing of the design method of the logic circuit by one Embodiment. Explanatory drawing of the design method of the logic circuit by one Embodiment. 6 is a flowchart of a logic circuit design method according to an embodiment. 1 is a schematic configuration diagram of a logic circuit design device according to an embodiment. FIG.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings. In the following drawings, components that are not necessary for the description of the embodiments are omitted from the drawings.

  A logic circuit that performs some logic operation is realized by combining a plurality of logic elements such as AND gates and OR gates. A register for storing intermediate values may be provided in an intermediate stage of these logic circuits. Here, if the number of logic elements between the registers is increased in order to suppress the number of registers, it is necessary to lower the operation clock, and the operation frequency is lowered. That is, in order to increase the operating frequency, it is necessary to reduce the number of logic elements between registers. However, this increases the number of registers and the circuit scale. On the other hand, when the number of registers is increased and the circuit scale is increased, noise generated by each element is increased and resistance to side channel attacks is improved. That is, generally, when the circuit scale is reduced, the resistance against the operating frequency and the side channel attack is reduced, and when the resistance against the operating frequency and the side channel attack is increased, the circuit scale is increased.

  Here, even if a target circuit scale is given, an appropriate circuit configuration is determined under certain conditions so that the operating frequency is not optimized depending on the position of the register to be added. There is a need to. The present invention provides such a design apparatus.

<First embodiment>
In the present embodiment, the design apparatus inputs a logical expression and the number of registers to be added determined in consideration of desired safety and circuit scale, and outputs a circuit configuration that increases the operating frequency as much as possible. In the following embodiments, the delay time in each logic element is the same.

  FIG. 9A is a schematic configuration diagram of the design apparatus 1 in the present embodiment. Hereinafter, the design process in this embodiment will be described.

Procedure 0: A logical expression and the number of registers to be added are input to the input unit 11 of the design apparatus 1. In the following description, as an example, an input logical expression is (X∧ (Y ⁻ ) ∨ (Z∧ (U∨W) ⁻ )), and the number of registers to be added is 3. The operator “ ⁻ ” means a NOT (NOT) operation.

Procedure 1: The conversion unit 12 of the design apparatus represents the input logical expression in a tree structure. Note that the leaf node of the tree structure is a register that stores the value of each variable, and the other nodes are logic elements. The output of the logical expression is stored in the register REG. The input logical expression (X∧ (Y ⁻ ) ∨ (Z∧ (U∨W) ⁻ )) in this example can be represented by the tree structure of FIG. In FIG. 1, X, Y, U, W, and Z are registers representing variables, and the root node is not the register REG in which the result of the logical expression is stored, but the OR operation executed last.

  Procedure 2: The dividing unit 13 of the design apparatus calculates the depth of each leaf node of the tree structure. The depth of the node indicates the distance from the root node of the node. Here, the depth of the root node is 0, and the depth of the other nodes is the sum of the depth of the parent node plus 1. To do. For example, the number below each leaf node in FIG. 1 indicates the depth of each leaf node.

  Procedure 3: The dividing unit 13 selects a leaf node having the maximum depth, and inserts a register at an intermediate point of a route from the root node to the selected leaf node to divide the tree structure into two. Here, the intermediate point is a position where a register is inserted and the path is divided into two parts, so that the number of logical elements in the two divided parts is the same or the difference is 1. If there are a plurality of leaf nodes having the maximum depth, an arbitrary one is selected. For example, in FIG. 1, the maximum value of the depth is 4, and the leaf node U or W is selected. Here, when the leaf node U is selected, a register is inserted at a position between the AND operation and the NOT operation and is divided into two, whereby the number of logical elements between the register U and the register to be inserted, and the register REG are inserted. Since the number of logic elements between the registers to be both is 2, the register is inserted at this position. FIG. 2 shows two tree structures after division. As shown in FIG. 2, the root node of the new tree structure generated by dividing is a NOT operation, and the result of the NOT operation is stored in the inserted register REG1.

  Procedure 4: The dividing unit 13 repeats the procedures 2 and 3 until the added number of registers becomes 3, which is the number of input registers. In this example, the leaf node depth calculated in the second procedure 2 is as shown in FIG. 2, and the leaf node Y having the maximum depth is selected in the second procedure 3. In this case, the tree structure is divided by inserting the register REG2 between the AND operation and the NOT operation. The state after the division is as shown in FIG.

  Furthermore, the depth of the leaf node calculated in the second procedure 2 is as shown in FIG. If the leaf node X having the maximum depth 2 is selected in the third procedure 3, for example, the register REG3 is inserted between the OR operation and the AND operation to divide the tree structure. The state after the division is as shown in FIG. Since the number of registers added at this time is equal to the number of input registers, the procedure 4 is terminated.

  Procedure 5: The output unit 14 of the design apparatus configures a logic circuit according to the tree structure determined in Procedure 4.

  In the present embodiment, adding a register to the midpoint of the path to the leaf node having the maximum depth and dividing the tree structure are repeated for the number of registers to be added. As a result, the number of logic elements between the registers is substantially averaged. Therefore, the number of logic elements between the registers is biased, and the maximum number of logic elements between the registers limits the operating frequency of the entire logic circuit. Can be prevented. In the above embodiment, the maximum difference in the number of logic elements between the registers is 1. However, the registers may be inserted so as to be equal to or less than a predetermined value.

<Second embodiment>
In the present embodiment, the design apparatus inputs a logical expression, the number of additional registers determined in consideration of safety, and the maximum number of logical elements between the registers determined in consideration of the operating frequency as inputs. It is determined whether or not a circuit configuration satisfying the maximum number of logic elements between the registers is possible, and if possible, the circuit configuration is output. FIG. 9B is a schematic configuration diagram of the design apparatus 2 in the present embodiment, and FIG. 8 is a flowchart of the processing of the present embodiment. Hereinafter, the design process in this embodiment will be described.

Procedure 0: A logical expression, the number of registers to be added, and the maximum number of logical elements (maximum number of elements) between the registers are input to the input unit 21 of the design apparatus 2. In the following description, the input logical expression is (X∧ (Y ⁻ ) ∨ (Z∧U)), the number of registers M to be added is 2, and the maximum number N of logic elements between the registers is 2. And

In S10 of FIG. 8, the conversion unit 22 of the design apparatus 2 represents the input logical expression in a tree structure as in the first embodiment. FIG. 5 shows the input (X∧ (Y ⁻ ) ∨ (Z∧U)) in a tree structure. Note that REG is a register that stores the output of an input logical expression as in the first embodiment. The dividing unit 23 of the design apparatus 2 initializes the counter i to 0 in S10.

  In S11, the dividing unit 23 calculates the depth of each leaf node of the tree structure as in the first embodiment. The numbers below each leaf node in FIG. 5 indicate the depth of each leaf node. Then, the dividing unit 23 determines whether or not the maximum depth is larger than the maximum number N of logic elements between the registers in S11. If it is larger, the process proceeds to S13, and if not, the process proceeds to S12. For example, in FIG. 5, the maximum depth is 3, which is larger than the maximum number N = 2, so that the process proceeds to S12.

  The dividing unit 23 selects a leaf node having the maximum depth in S12, inserts a register on the route from the root node to the selected leaf node, and divides the tree structure into two. Note that the position where the register is inserted is a position where the number of logical elements in either of the two divided parts becomes the maximum number N by inserting the register and dividing the path into two parts. If there are a plurality of leaf nodes having the maximum depth, an arbitrary one is selected. For example, in FIG. 5, a register is inserted between an AND operation and a NOT operation on the path leading to the leaf node Y having the maximum depth 3 and divided into two tree structures. Since the maximum number N of logic elements is N = 2, a register is inserted at this position. FIG. 6 shows two tree structures after division. In addition, since one register is added, the dividing unit 23 increases the counter i by one. Then, S11 is performed again.

  In this example, since the maximum depth of the tree structure is 2 in S11 for the second time and is equal to the maximum number N = 2, the process proceeds to S13.

The determination unit 24 of the design apparatus 2 determines whether i indicating the number of registers added in S13 is less than the number of added registers M = 2. If i is less than M, the process proceeds to S14; otherwise, the process proceeds to S15. In this example, the added register number i is 1, and the added register number M is less than 2, so the process proceeds to S14. In S <b> 14, the generation unit 25 of the design apparatus 2 adds (M−i) dummy logic circuits so that the number of registers to be added becomes the input register number M. If the number of logic elements between the registers is equal to or less than the maximum number N, the content of the arithmetic expression of the dummy logic circuit to be added is arbitrary. In this example, since (M−i) = 1, as shown in FIG. 7, REG 2 = (X X) regardless of the input logical expression (X∧ (Y ⁻ ) ∨ (Z∧U)). (Y) One logic circuit for calculating ⁻ is inserted. The output unit 26 of the design apparatus 2 configures a logic circuit according to a tree structure including a dummy and ends the process.

  If i is not less than M in S13, the determination unit 24 determines whether i and M are equal in S15. When i and M are equal, there is no need to add a dummy logic circuit, so the output unit 26 configures the logic circuit in a tree structure and ends the process. On the other hand, if i and M are not equal in S15, the number of registers to be added must be larger than M in order to make the maximum number of logical elements between registers N or less, the output unit 26 is configured to have S16. Then, an output indicating that the maximum number cannot be reduced to N or less with the number of registers M is performed, and the process is terminated.

  In the present embodiment, it is possible to determine whether or not there is a logic circuit configuration that satisfies the desired safety and operating frequency, and if so, the configuration.

  The design apparatuses 1 and 2 according to the present invention can be realized by a program that causes a computer to operate as the design apparatuses 1 and 2. These computer programs can be stored in a computer-readable storage medium or distributed via a network.

Claims (5)

An apparatus for designing a logic circuit corresponding to an input logic expression,
An input means for inputting the number of registers;
A determination means for determining a register insertion position of the number of registers for storing intermediate values separately from a register for storing an input value to the logic circuit and a register for storing an output value of the logic circuit;
With
The design apparatus is characterized in that the determination means determines a register insertion position so that a difference in the number of logical elements between registers is equal to or less than a predetermined value. The determining means includes
Whether the number of nodes of the two parts generated by dividing the path from the root node of the tree structure to the leaf node farthest from the root node is the same, associating the logical expression with the tree structure, Divide the tree structure so that the difference is 1,
When the number of registers to be added is 2 or more, for each tree structure generated by division, the farthest leaf from the root node of the tree structure having the leaf node farthest from the root node Dividing the tree structure at a position where the number of nodes in the two parts generated by dividing the route is the same or the difference between them is 1 on the route to the node. Repeated as many times as
2. The design apparatus according to claim 1, wherein a position where the tree structure is divided is determined as an insertion position of a register for storing the intermediate value. An apparatus for designing a logic circuit corresponding to an input logic expression,
Input means for inputting the number of registers and the maximum number of elements;
Separately from the register for storing the input value to the logic circuit and the register for storing the output value of the logic circuit, the register for storing the intermediate value of the logic circuit is inserted by the number of registers input to the input means. Determining means for determining whether the number of elements between the registers can be equal to or less than the maximum number of elements,
An output means for outputting a warning when the maximum number of elements cannot be reduced,
A design apparatus characterized by comprising: Determining means for determining a register insertion position so that the number of elements between the registers is equal to or less than the maximum number of elements;
If the number of registers for which the determining means has determined the insertion position is less than the number of registers input to the input means, a dummy logic is used so that the number of registers to be added is equal to the number of registers input to the input means. Generating means for generating a circuit;
The design apparatus according to claim 3, further comprising:   A program that causes a computer to function as the design apparatus according to claim 1.

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