JP2014063346A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase in a memory capacity for storing trace data of coverage measurement.SOLUTION: While executing a program including a plurality of branch instructions, an input part 107 inputs branch source data and corresponding branch destination data of each branch instruction each time the branch instruction is executed. A control part 110 stores the branch source data to be inputted about a branch instruction to be executed at the next position of the branch instruction in an address designation area of a memory 101 for coverage measurement based on the branch destination data of the branch instruction inputted by the input part.

Description

  The present invention relates to an information processing apparatus, and can be used, for example, in an information processing apparatus that detects how many instructions in a target program have been executed.

  An MCU (Micro Computer Unit), which is a kind of microcomputer, has been incorporated into various electrical devices such as home appliances, and a debugging process for finding and correcting bugs in software built in the MCU is important. In the debugging process, an emulator such as an ICE (In-Circuit Emulator) is connected to the MCU in order to check whether the program operates properly, and the state of each part in the MCU that is executing the program is monitored by the ICE.

  One of the items to be monitored is measurement of a so-called program coverage rate in which the ratio of instructions executed by branch instructions in the program to the program is detected from the trace data of the program. For example, in Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-21939), all branch source / branch destination addresses included in trace data output from an MCU during program execution are temporarily recorded in a memory in the ICE. Then, the branch information recorded after the program execution is completed is analyzed by software, and the branch rate is calculated from the analysis result.

JP 2004-21939 A

  Also, when recording trace data to measure the coverage rate, when the trace data cannot be transferred directly from the MCU to the large-capacity memory in the host computer (for example, when the transfer bandwidth cannot be secured) The normal trace data is transferred from the MCU to a memory provided in the emulator and recorded. However, since the memory that can be installed in the emulator is overwhelmingly small compared to the host computer, if the amount of trace data increases due to long-time program execution, etc., overwriting recording of trace data occurs in the emulator memory, There was a problem that the coverage rate could not be measured.

  Patent Document 1 discloses a method of selecting and outputting trace data and compressing and restoring branch information for increasing the trace speed and reducing the number of trace packets, but discloses a method for reducing the memory capacity for storing trace data. do not do.

  Therefore, it is desired to provide an information processing apparatus that suppresses an increase in memory capacity for storing trace data related to coverage measurement of a target program.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In one embodiment of the present invention, when an information processing apparatus executes a program including a plurality of branch instructions, an input for inputting branch source data of the branch instruction and corresponding branch destination data each time the branch instruction is executed And a memory for storing data relating to a plurality of branch instructions, and a control unit for controlling access to the memory. The control unit stores branch source data to be input for a branch instruction to be executed next to the branch instruction in the addressing area of the memory based on the branch destination data of the branch instruction input by the input unit.

  An information processing apparatus according to an embodiment of the present invention suppresses an increase in memory capacity necessary for storing trace data related to coverage measurement of a target program.

It is a schematic block diagram of the system which concerns on Embodiment 1 of this invention. It is a hardware block diagram of the host computer which concerns on Embodiment 1 of this invention. It is a figure which shows the hardware constitutions and packet structure of the emulator which concern on Embodiment 1 of this invention. It is a flowchart of the main process for the coverage measurement which concerns on Embodiment 1 of this invention. It is a flowchart of the data recording process to the memory for coverage measurement which concerns on Embodiment 1 of this invention. It is a flowchart of the analysis process which concerns on the coverage measurement which concerns on Embodiment 1 of this invention. It is a figure explaining the storage data of the memory for coverage measurement which concerns on Embodiment 1 of this invention. It is a figure which shows typically the object program which concerns on Embodiment 1 of this invention, and the storage data of the memory for coverage measurement. It is a figure which shows the specific example of the analysis process which concerns on embodiment of this invention. It is a figure which shows typically the object program which concerns on Embodiment 2 of this invention, and the storage data of the memory for coverage measurement. 6 is a timing chart showing an operation of the emulator according to the second embodiment of the present invention. It is a figure explaining the branch from the target program which concerns on Embodiment 3 of this invention to a non-target program. It is a schematic block diagram of the emulator which concerns on Embodiment 3 of this invention.

  Hereinafter, embodiments of the invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  In the present embodiment, an addressed and accessed (data read / write) area is referred to as an “address area”. Data used for addressing is referred to as “address”. The address used for addressing indicates a value according to hexadecimal (hexadecimal). In this embodiment, the “address value” indicates this hexadecimal value. The address expression is not limited to the expression according to hexadecimal.

  “Coverage” (or coverage rate) is a value indicating how much of all the command statements (program code) of the target program is executed when the target program is executed, and is called so-called C0 coverage.

[Embodiment 1]
<System configuration>
FIG. 1 is a schematic configuration diagram of a system according to Embodiment 1 of the present invention. Referring to FIG. 1, the system is connected to emulator 100 such as ICE corresponding to an information processing apparatus, MCU 200 connected to emulator 100 via bus 500 serving as a data transmission path, and to emulator 100 via cable 400. A host computer 300 is provided. The emulator 100 corresponds to an information processing apparatus such as ICE.

  The communication format of the cable 400 is, for example, USB (Universal Serial Bus), but is not limited to USB. Further, the emulator 100 and the host computer 300 are not limited to wired communication using the cable 400, and may be wireless communication.

  The MCU 200 includes a CPU (Central Processing Unit) 201, an I / O circuit 202, a storage unit 203 for storing data and programs, and an OCD circuit 204 on a substrate. The I / O circuit 202 is connected to the bus 500 and controls data input / output between the bus 500 and the MCU 200. These units are connected to each other via a communication bus.

  The storage unit 203 includes a volatile / nonvolatile memory, a ROM (Read Only Memory), a RAM (Random Access Memory), and the like.

  An OCD (On Chip Debugging Emulator) circuit 204 generates a packet to be described later and outputs it to the I / O circuit 202. The I / O circuit 202 receives data including a packet from the OCD circuit 204, converts the data according to the transfer format, and outputs the converted data to the bus 500.

<Branch source / branch destination data related to branch instruction>
In the present embodiment, a coverage rate measurement target program (hereinafter referred to as a target program) includes a plurality of branch instructions. When a branch instruction is executed when the target program is executed, branch source data indicating the branch source of the branch instruction and branch destination data indicating the branch destination are detected.

  Specifically, in the MCU 200, the program code of the target program is stored in a predetermined storage area of the storage unit 203. When the program is executed, an instruction in the target program in the storage unit 203 is read by address designation based on a count value of a program counter (not shown) in the CPU 201, and the read instruction is executed. When the instruction is executed, the count value of the program counter is incremented to indicate the address where the next instruction is stored. The CPU 201 reads the next instruction by addressing based on the incremented count value, and executes the read instruction. Thereby, the target program stored in the storage unit 203 is executed.

  When the CPU 201 executes a branch instruction during execution of the target program, the OCD circuit 204 monitors a bus (not shown) between the CPU 201 and the storage unit 203 to acquire branch source data and branch destination data. Here, the branch source data indicates an address where the branch instruction is stored, and the branch destination data indicates an address based on the count value of the program counter after being incremented when the branch instruction is executed. In other words, it indicates the branch destination data and the address at which the branch destination instruction (jump etc.) is stored.

  FIG. 2 is a hardware configuration diagram of the host computer 300 according to the first embodiment of the present invention. Referring to FIG. 2, host computer 300 corresponds to a general information processing apparatus. Specifically, a storage unit 302 including a CPU 301, volatile / nonvolatile memory, ROM, RAM, and hard disk, a communication unit 303 to which a cable 400 is connected, a display unit 304, a timer 305, and an input unit 306 are provided. Further, a recording medium such as a CD-ROM (Compact Disc Read Only Memory) 308 is detachably mounted, and an I / F (Interface) 307 for accessing the mounted recording medium is provided. Each unit communicates via a bus. The storage unit 302 includes an analysis memory 312 that is a predetermined storage area in which data to be analyzed by the CPU 301 (hereinafter referred to as analysis data) is stored. Further, the input unit 306 receives a user operation using a mouse, a keyboard, or the like, and inputs a command / data according to the received operation content.

  Data may be transferred between the host computer 300 and the emulator 100 via a recording medium such as the CD-ROM 308 instead of communication using the cable 400 or the like.

  The host computer 300 is not limited to the stationary type as shown in FIG. 1, and may be a portable information processing terminal.

<Emulator configuration and packet configuration>
FIG. 3 is a diagram showing a hardware configuration and a packet configuration of the emulator 100 according to the first embodiment of the present invention. 3A includes an input unit 107 to which a bus 500 is connected, a coverage measurement memory 101 including a nonvolatile RAM, and a memory control circuit 102 for controlling the coverage measurement memory 101. . In relation to these circuits, a memory address register 103, a branch source holding register 104, a magnitude comparator 105 for comparing the magnitudes of branch source address values, and a branch destination holding register 106 are further provided. The coverage measurement memory 101 is a memory for recording trace data output as a result of program execution in the MCU 200, and is a memory for storing information related to branch instructions (hereinafter referred to as branch information).

  The memory control circuit 102 addresses the coverage measurement memory 101 with the address 113 and reads / writes the data 114 for the designated address area.

  The input unit 107 includes a multiplexer (not shown) for outputting input data.

  FIG. 3B shows a field configuration of a packet transferred via the trace bus 500. When a branch instruction is executed when executing the target program, the OCD circuit 204 generates a packet for the branch instruction. When the CPU 201 determines the type of instruction code to be executed and determines that it is a branch instruction, the CPU 201 instructs the OCD circuit 204 to generate a packet and outputs branch source data and branch destination data related to the branch instruction.

  With reference to FIG. 3B, the packet includes a header field for storing information HE indicating the type of the packet, the destination / source of the packet, and the like, and a data field for storing data to be transferred. In the data field, branch source data 112 and branch destination data 111 output from the CPU 201 are stored as a set.

  The input unit 107 of the emulator 100 inputs a packet from the MCU 200 and analyzes the information HE of the input packet. When it is detected that the packet type is a packet storing branch information based on the analysis result, the multiplexer outputs the branch source data 112 of the packet to the magnitude comparator 105 and the branch destination data 111 is stored in the memory address register 103. Control to output to.

  Here, to simplify the description, it is assumed that a packet of a branch instruction is transmitted to the emulator 100 via the bus 500 every time a branch instruction is executed while the target program is being executed by the MCU 200.

<Recording algorithm to coverage measurement memory>
FIG. 4 is a flowchart of the main process for coverage measurement according to Embodiment 1 of the present invention. Referring to FIG. 4, the main processing includes data recording processing (step T1) in coverage measurement memory 101 and analysis processing (step T2) related to coverage measurement of recorded data in coverage measurement memory 101.

  FIG. 5 is a flowchart of data recording processing to the coverage measurement memory 101 according to the first embodiment of the present invention. Note that each memory address of the coverage measurement memory 101 is assigned one-to-one to the address of the program storage area of the storage unit 203 of the MCU 200. After the allocation, the coverage measurement memory 101 is initialized. In initialization, zero is stored in the entire address area. This is called zero clear.

  Thereafter, the MCU 200 starts executing the target program. The OCD circuit 204 of the MCU 200 notifies the emulator 100 of the execution start of the program. When the emulator 100 inputs the notification via the bus 500, the emulator 100 starts the process of FIG.

  Here, the program starts to be executed from the program code at the head address, and the program codes at the subsequent addresses are sequentially executed. Note that the execution start address is not fixed to the head address, but may be variably changed according to a user instruction.

  When the packet is input from the bus 500 (step S3), the input unit 107 of the emulator 100 stores the address value indicated by the branch destination data 111 of the data portion of the packet in the memory address register 103 (step S7).

  The memory control circuit 102 addresses the coverage measurement memory 101 based on the value (address value) stored in the memory address register 103 (step S9). Then, the data is read from the designated address area, and the read data is stored in the branch source holding register 104 (step S11). At the same time, the contents of the memory address register 103 are transferred to the branch destination holding register 106 (step S13).

  Thereafter, a packet of a branch instruction to be executed next is input by the input unit 107 (step S15).

  The magnitude comparator 105 compares the address value of the branch source data 112 of the input packet with the value of the branch source holding register 104 (the value indicates zero in the first comparison after the start of program execution) (step S17). If the memory control circuit 102 determines that the former is larger than the latter based on the comparison result (YES in step S19), the value of the branch destination holding register 106 (the branch indicated by the branch destination data 111 of the packet input last time). The value of the address designation area of the coverage measurement memory 101 based on the destination address) is rewritten to the branch source address value indicated by the branch source data 112 of the packet input this time (step S21).

  If it is determined from the comparison result that the address value indicated by the branch source data 112 to be input is equal to or less than the value of the branch source holding register 104 (NO in step S19), rewriting (step S21) is not performed. Control goes to step S23.

  When the MCU 200 finishes executing the target program, the MCU 200 notifies the emulator 100 of an execution end notification.

  When the input unit 107 of the emulator 100 inputs an execution end notification, the processing in FIG. 5 ends (YES in step S23), and the processing returns to the original processing in FIG. While the execution end notification is not input (NO in step S23), the process returns to step S7.

  Thereafter, each time a packet that is trace data is input, steps S7 to S21 are executed based on branch information in the packet.

  By the above recording process, the trace data is recorded in the address of the coverage measurement memory 101 (corresponding to the branch destination address of the branch instruction) in a format in which the value of the branch source address of the next branch instruction is stored.

  Further, the address measurement memory 101 stores the address value comparison process by the magnitude comparator 105 and the memory control circuit 102 and the branch destination address value rewrite process (step S21) of the coverage measurement memory 101 based on the comparison result. The branch source address value indicates the size of the address area in which the program code continuously executed from the preceding branch destination address is stored.

<Analysis of trace data>
FIG. 6 is a flowchart of analysis processing related to coverage measurement according to Embodiment 1 of the present invention. The analysis process (step T2 in FIG. 4) will be described with reference to FIG. It is assumed that an analysis memory 312 having the same size as the program code storage area of the target program in the MCU 200 is secured in advance in the storage unit 302 of the host computer 300 and is cleared to zero.

  The CPU 301 communicates with the emulator 100 to sequentially read data from the head address of the coverage measurement memory 101 (step S23). It is determined whether or not the read data is “zero” (step S25). If it is determined to be “zero” (NO in step S25), the process returns to step S23, data is read from the next address in the coverage measurement memory 101, and the subsequent processing is repeated.

  On the other hand, if it is determined that it is not “zero” (YES in step S25), the analysis memory 312 is marked (step S27). The marking indicates a process for indicating the executed program code in the target program. Specifically, from the branch destination address of the analysis memory 312 (the address read in step S23 immediately before the coverage measurement memory 101) to the next branch source address (in step S23 immediately before the coverage measurement memory 101). Mark data is stored in each address area up to (read address value). The mark data may be any data that can be distinguished from the program code that has not been executed. In the present embodiment, the value “1” is stored.

  Thereafter, the CPU 301 determines whether or not the data in the final address area in which the trace data of the coverage measurement memory 101 is stored has been read (step S29), and determines that the data in the final address area has not been read yet (step S29). If NO in step S29), the process returns to step S23, but if it is determined that the data has been read (YES in step S29), the process in FIG. 6 ends and the process returns to the original process in FIG.

  As a result of the above analysis processing, the result of coverage measurement in which the executed mark is stored only in the address area in which the program code executed by the MCU 200 is finally stored in the analysis memory 312 is generated. The generated coverage measurement result is output via an output device such as the display unit 304.

  Here, the coverage measurement in the case where the branch destination data of each branch instruction in the target program indicates a different branch destination address will be specifically described below.

<Specific examples of trace data>
FIG. 7 is a diagram for explaining an example of data stored in the coverage measurement memory 101 according to the first embodiment of the present invention. Referring to FIG. 7A, tracing is started when program execution is started in MCU 200. A packet is output for each branch instruction executed when the trace is started. Here, each of the traces (1) to (4) indicating packets to be output includes a set of branch destination data 111 and branch source data 112. In the figure, (1) to (4) use circles instead of parentheses.

  When the branch information of FIG. 7A corresponding to each branch instruction is output from the MCU 200, data as shown in FIG. 7B is stored in the coverage measurement memory 101 according to the flowchart of FIG. That is, for each branch instruction, the control unit 110 in FIG. 7B executes the branch executed next to the address area of the coverage measurement memory 101 corresponding to the branch destination address indicated by the corresponding branch destination data 111. Stores the branch source address indicated by the branch source data 112 of the instruction. The coverage measurement memory 101 has a memory area 101E corresponding to the program code size to be measured.

  Note that the control unit 110 indicates a portion excluding the input unit 107 of the emulator 100 in FIG.

  According to this configuration, the branch destination data 111 (that is, the branch destination address) can be replaced with the address of the coverage measurement memory 101. As a result, the data to be stored in the coverage measurement memory 101 can be only the branch destination data 111 (that is, the branch destination address), and the conventional method (a set of the branch destination data 111 and the branch source data 112 is stored). The memory capacity required for the coverage measurement memory 101 can be reduced as compared with the (method).

  FIG. 8 is a diagram schematically showing a target program according to Embodiment 1 of the present invention and data stored in the coverage measurement memory 101. 8A shows an example of data stored in the coverage measurement memory 101, and FIG. 8B schematically shows a target program stored in a predetermined area of the storage unit 203 of the MCU 200. .

  Referring to FIG. 8B, the predetermined area of storage unit 203 includes an address area designated by addresses H′0100 to H′0500. The target program stored in the predetermined area includes, for example, three branch instructions. When the execution of the target program is started, the first branch instruction is first executed.

  The packet that is output when the first branch instruction is executed stores the branch source address, that is, the address H′0000 where the first branch instruction is stored and the branch destination address H′0100. In the packet output when the second branch instruction is executed, a branch source address, that is, an address H′0200 and a branch destination address H′0300 in which the branch instruction is stored are detected. In the packet output when the third branch instruction is executed, a branch source address, that is, an address H′0400 and a branch destination address H′0000 in which the branch instruction is stored is detected. Note that program execution ends when the third branch instruction is executed. The OCD circuit 204 that detects the end of program execution generates an address H′0000 as a branch destination address.

  In FIG. 8B, the broken line schematically shows the execution flow of instructions executed by the CPU 201, and the address area indicated by the solid line includes an address area in which the program code of the target program is stored. In addition, address values (H′0100 to H′0500) are shown in association with the broken line. A rectangle superimposed on the solid line indicates a storage area for program code executed at the time of coverage measurement. Specifically, the length of the rectangle in the longitudinal direction indicates the size of the address area in which the executed program code is stored.

  The coverage measurement of FIG. 8 will be described according to the flowchart of FIG. In the emulator 100, the coverage measurement memory 101 is initialized (zero-cleared) in advance. When the execution of the target program is started by the MCU 200, coverage measurement is started.

  First, when the first branch instruction is executed, the emulator 100 inputs a packet storing the branch destination address H′0100 and the branch source address H′0000 (step S3), and the branch destination address H′0100 of the packet. Is stored in the memory address register 103 (step S7).

  The memory control circuit 102 reads the branch source address value (in this case, zero) from the coverage measurement memory 101 by address designation based on the address H′0100 stored in the memory address register 103, and reads the read data into the branch source Store in the holding register 104 (steps S9, S11). At the same time, the address value (H′0100) stored in the memory address register 103 is transferred to the branch destination holding register 106 (step S13).

  Thereafter, the packet of the second branch instruction is input (step S15). The magnitude comparator 105 compares the branch source address H′0200 of the packet with the value (in this case, zero) of the branch source holding register 104 (step S16). And based on a comparison result, it determines with the former being larger than the latter (it is YES at step S19). The memory control circuit 102 addresses the coverage measurement memory 101 based on the address value of the branch destination holding register 106 (the branch destination address H′0100 of the first branch instruction). Then, the value of the address designation area is rewritten to the branch source address H′0200 of the packet of the second branch instruction (step S21).

  Thus, in the coverage measurement memory 101, the branch source address value (H'0200) of the next (second) branch instruction is stored in the area specified by the branch destination address H'0100 of the first branch instruction. The

  Since it is not yet determined that the program has been executed (NO in step S23), the process returns to step S7.

  The branch destination address H′0300 of the packet of the second branch instruction is stored in the memory address register 103 (step S7). The memory control circuit 102 reads the branch source address value (in this case, zero) from the coverage measurement memory 101 by address designation based on the address H′0300 stored in the memory address register 103, and reads the read data into the branch source The data is stored in the holding register 104 (steps S9 and S11). At the same time, the address value (H′0300) stored in the memory address register 103 is transferred to the branch destination holding register 106 (step S13).

  Thereafter, the third branch instruction packet is input (step S15). The magnitude comparator 105 compares the branch source address H′0400 of the packet with the value of the branch source holding register 104 (in this case, zero) (step S16). Based on the comparison result, it is determined that the former is larger than the latter (YES in step S19). The memory control circuit 102 addresses the coverage measurement memory 101 based on the address value of the branch destination holding register 106 (the branch destination address H′0300 of the second branch instruction). Then, the value in the address designation area is rewritten to the branch source address H′0400 of the packet of the third branch instruction (step S21).

  Thus, in the coverage measurement memory 101, the branch source address value (H'0400) of the next (third) branch instruction is stored in the area specified by the branch destination address H'0300 of the second branch instruction. The

  Thereafter, since it is determined that the execution of the program has ended (YES in step S23), the processing returns to the original FIG. Thereby, the storage of the trace data in the coverage measurement memory 101 ends.

  When the target program shown in FIG. 8B is executed, the coverage measurement memory 101 has an address area designated by the branch destination address H′0100 of the first branch instruction, as shown in FIG. The branch source address H′0200 of the second branch instruction is stored. The branch source address H′0400 of the third branch instruction is stored in the address area specified by the branch destination address H′0300 of the second branch instruction. Thus, the trace data is recorded in the coverage measurement memory 101 so that the value of the branch source address of the branch instruction executed next is stored in the address (corresponding to the branch destination address of the branch instruction) area. Is done.

<Specific examples of analysis processing>
FIG. 9 is a diagram showing a specific example of analysis processing for data stored in the coverage measurement memory 101 according to the embodiment of the present invention.

  FIG. 9 shows the results (1) to (7) obtained by analyzing the data stored in the coverage measurement memory 101 according to FIG. 8 according to the procedure of FIG. 6 (the parentheses are replaced with circles in the figure). . Here, the analysis memory 312 has the same size as the program code area of the target program in the storage unit 203. The analysis memory 312 has an address area specified by addresses H′0000 to H′FFFF. The CPU 301 detects the size occupied by the address area in which the branch source address value is stored among all the address areas of the coverage measurement memory 101 assigned one-to-one to the address of the program code storage area in the storage unit 203. To do.

  First, the CPU 301 of the host computer 300 initializes (clears to zero) the analysis memory 312 (see result (1)).

  Thereafter, the CPU 301 starts the reading process from the area of the start address H′0000 of the coverage measurement memory 101. If it is determined that the read value is the initial value (zero), that is, if the branch source address value is not stored in the address area, the next address area is read. In this way, when the reading process of each address area from the start address H'0000 to the address H'00FF is repeated, the value read from each address area is determined to be zero, and thus the above-described marking is not executed ( (See result (2)).

  Thereafter, the CPU 301 reads the branch source address value (H′0200) from the area of the address H′0100. Therefore, the CPU 301 marks each address area of the addresses H′0100 to H′0200 in the analysis memory 312. Here, “1” is stored in each address area (see result (3)).

  Since the value read from each address area from the subsequent addresses H′0101 to H′02FF is zero, the above-described marking is not executed (see result (4)).

  Thereafter, the CPU 301 reads the address H′0400 from the address area of the address H′0300. Therefore, the CPU 301 stores “1” in each address area of the addresses H′0300 to H′0400 of the analysis memory 312 (see the result (5)).

  Since the value read from each address area from the subsequent addresses H′0301 to H′FFFF is zero, the above-described marking is not executed (see result (6)).

  Finally, the analysis memory 312 stores the values (1 or 0) of the above results (1) to (6) in each address area from the head address (H′0000) to the last address (H′FFFF). Is stored (see result (7)).

  As a result, the size occupied by the address area in which the branch source address value is stored in the entire address area of the coverage measurement memory 101 is detected.

  The CPU 301 displays an image or information based on the result (7) in FIG. Thereby, the user can confirm the coverage measurement result about the target program. For example, only the “1” portion of the result (7) is displayed with the color reversed.

  As information, the ratio of the number of executed codes to the total number of program codes of the target program may be calculated and displayed based on the result (7). That is, the ratio of the address area in which the branch source address value is stored among all the address areas of the coverage measurement memory 101 assigned one-to-one to the addresses of the target program code storage area of the storage unit 203, that is, coverage. (Coverage rate) may be calculated and displayed.

Note that the output is not limited to display but may be printing.
<Effect of Embodiment 1>
In the coverage measurement by the conventional trace data recording method compared with the first embodiment, the following problems remain.

  Problem (1): The time required for the analysis process of the trace data by the software after executing the target program increases as the amount of recorded trace data increases. For this reason, when a large amount of trace data is acquired by an emulator, analysis takes a long time.

  Problem (2): When using trace memory (corresponding to coverage measurement memory 101) installed in the emulator for recording trace data, in the case where trace data exceeding the capacity of the trace memory is output, Trace data exceeding this point is stored in the race memory by overwriting. Due to overwriting, part of the trace data is lost and coverage measurement fails. As a workaround, it is possible to apply a method of adding processing for suppressing overwriting of the trace memory. In other words, when the trace data is stored and the trace memory becomes full, the execution of the target program by the MCU is stopped, then the trace data in the trace memory is transferred to the host computer, and the execution that has been stopped after the transfer Overwriting is suppressed by resuming program execution. However, the real-time property of coverage measurement is impaired by the addition of processing.

In the first embodiment, it is possible to obtain the effect of solving the above problem.
Effect (1): When the usage method of the coverage measurement memory 101 and the branch information recording algorithm shown in FIGS. 7 to 9 are used, the branch information stored in the coverage measurement memory 101 is indicated by the branch source data 112. Only a branch address is required. Further, the capacity required for the coverage measurement memory 101 can be set to a fixed size according to the program size regardless of the length of time for executing the target program, and the above problem (1) is solved.

  Effect (2): The coverage measurement memory 101 only needs to have an address area of a corresponding size in the area storing the target program code in the storage unit 203. Even in this case, overwriting of the coverage measurement memory 101 does not occur regardless of the number of branch instructions in the target program, and the above problem (2) is solved.

  Effect (3): The analysis target by the host computer 300 can be limited to the range corresponding to the program code area size allocated to the coverage measurement memory 101 without being affected by the amount of branch information (number of packets) from the MCU 200. Analysis at a constant time is always possible. In addition, there is no failure due to overwriting of the trace memory.

  Effect (4): The above-described effect can be obtained without special processing of the target program.

[Embodiment 2]
In the second embodiment, a case where the target program includes a plurality of branch instructions that branch to the same address will be described. That is, in the first embodiment, the branch destination data of each branch instruction in the target program indicates a different branch destination address. However, in the second embodiment, a plurality of branch instructions in the target program are branched. Coverage measurement when the destination data 111 indicates the same address will be described.

  In the second embodiment, the configuration shown in FIGS. 1 to 3 and the flowcharts shown in FIGS. 4 to 6 are applied, and the description thereof will not be repeated.

  FIG. 10 is a diagram schematically showing the target program according to the second embodiment of the present invention and the data stored in the coverage measurement memory 101. 10A shows an example of data stored in the coverage measurement memory 101, and FIG. 10B schematically shows a target program stored in a predetermined area of the storage unit 203 of the MCU 200. .

  Referring to FIG. 10B, the predetermined area of storage unit 203 includes an address area designated by addresses H′0100 to H′0500. The target program stored in the predetermined area includes, for example, four branch instructions. When the execution of the target program is started, the first branch instruction is executed.

  The packet that is output when the first branch instruction is executed stores the branch source address H′0000 and the branch destination address H′0100. A packet that is output when the second branch instruction is executed stores a branch source address H′0200 and a branch destination address H′0300. The packet that is output when the third branch instruction is executed stores the branch source address H′0400 and the branch destination address H′0300. The packet that is output when the fourth branch instruction is executed stores the branch source address H′0500 and the branch destination address H′0000. Note that the program execution ends when the fourth branch instruction is executed. When detecting the end of program execution, the OCD circuit 204 detects an address H′0000 as a branch destination address.

  When the first, second, and third branch instructions are executed, in the coverage measurement memory 101 of FIG. 10A, the branch destination of the first branch instruction is the same as in the first embodiment. A branch source address value (H′0200) of the second branch instruction is stored in the address area specified by the address H′0100. Then, the branch source address value (H′0400) of the third branch instruction is stored in the address area specified by the branch destination address H′0300 of the second branch instruction.

  Since it is not yet determined that the program has been executed (NO in step S23), the process returns to step S7.

  The branch destination address H′0300 of the packet of the third branch instruction is stored in the memory address register 103 (step S7). The memory control circuit 102 reads the branch source address value (in this case, H′0400) from the coverage measurement memory 101 by address designation based on the address H′0300 stored in the memory address register 103, and reads the read data. Store in the branch source holding register 104 (steps S9 and S11). At the same time, the address value (H′0300) stored in the memory address register 103 is transferred to the branch destination holding register 106 (step S13).

  Thereafter, the packet of the fourth branch instruction is input (step S15). The magnitude comparator 105 compares the branch source address H′0500 of the packet with the value of the branch source holding register 104 (in this case, H′0400) (step S16). Based on the comparison result, the former is greater than the latter. It determines with it being large (it is YES at step S19). The memory control circuit 102 addresses the coverage measurement memory 101 based on the address value of the branch destination holding register 106 (the branch destination address H′0300 of the third branch instruction). Then, the value of the address designation area is rewritten to the branch source address value (H′0500) of the packet of the fourth branch instruction (step S21).

  Thus, in the coverage measurement memory 101, the branch source address value (H'0500) of the fourth branch instruction is stored in the area specified by the branch destination address H'0300 of the second branch instruction.

  Thereafter, since it is determined that the execution of the program has ended (YES in step S23), the processing returns to the original processing in FIG.

  In FIG. 10B, as in FIG. 8B, the broken line schematically shows the execution flow of instructions executed by the CPU 201 in the storage unit 203, and the address area indicated by the solid line stores the program code of the target program. Address area. Further, the length in the longitudinal direction of the rectangle shown in relation to the solid line indicates the size of the address area in which the executed program code is stored.

  As described above, the branch source address H′0500 is detected by the execution of the fourth branch instruction, and the branch source address value (H′0400) of the immediately preceding (third) branch instruction and the newly detected branch source address value. (H′0500) is compared, and the larger value (H′0500) is stored in the address (H′0300) area of the coverage measurement memory 101. That is, the original value (H′0400) stored in the address (H′0300) area is rewritten with a new branch source address value (H′0500). Thereby, at the end of execution of the target program, it can be shown from the recorded contents of the coverage measurement memory 101 that the program code from the address H′0300 to H′0500 of the target program has been executed.

<Timing chart>
FIG. 11 is a timing chart showing the operation of the emulator 100 according to the second embodiment of the present invention. The operation of the emulator 100 when a plurality of branch instructions having the same branch destination address in FIG. 10 are executed will be described with reference to FIG.

  FIG. 11A shows a packet signal from the MCU 200. A signal from the MCU 200 is a trace information unit (corresponding to a packet) synchronized with an internal control clock (see FIG. 11B) of the emulator 100 after being input to the emulator 100. For example, “ It is shaped into branch 1 "to" branch 4 ".

  When “branch 1” to “branch 4” corresponding to the first, second, third and fourth branch instructions are input (see FIGS. 11C and 11D), the memory address register The data 103 changes from address values H′0100 → H′0300 → H′0300 (see FIG. 11E). The address corresponds to the address 113. The memory control circuit 102 reads the data 114 from the address area of the coverage measurement memory 101 specified by the address 113 (see FIGS. 11F and 11G), and the read data 114 is read from the branch source holding register 104. (See FIG. 11H).

  The comparator 105 compares the input branch source address value (see FIG. 11C) with the address value of the branch source holding register 104, and determines from the comparison result that the former is larger than the latter. Addresses the coverage measurement memory 101 based on the address value of the branch destination holding register 106 (see FIG. 11D and FIG. 11K), and the write data register value (FIG. 11 (I )) Is stored (see FIG. 11J). The write data register is a register (not shown) in the memory control circuit 102 and temporarily stores data to be written to the coverage measurement memory 101.

<Effect of Embodiment 2>
When the emulator 100 continuously inputs a plurality of packets having the branch destination data 111 indicating the same branch destination address from the MCU 200, the emulator 100 switches the branch source between the previously input packet and the next input packet in the input order. An algorithm is used in which the branch source addresses indicated by the data 112 are compared and the larger one is stored in the branch destination address area of the coverage measurement memory 101 based on the comparison result.

  Thus, when a plurality of branch instructions indicating the same branch destination address are executed, the area indicated by the same branch destination address of the coverage measurement memory 101 regardless of the branch source address value (regardless of the branch pattern) Stores a branch source address indicating the maximum value of the plurality of branch instructions. Therefore, it is possible to record a range of program codes that are continuously executed when a plurality of branch instructions are executed from the same branch destination address value and the maximum branch source address value. Therefore, even when a program in which a branch instruction indicating the same branch destination address is executed is measured, an increase in the amount of trace data in the coverage measurement memory 101 and an increase in analysis time by the host computer 300 are prevented. it can.

[Embodiment 3]
In the third embodiment, a case will be described in which the target program branches to another program. In Embodiments 1 and 2 described above, the branch destination is in the target program. In Embodiment 3, coverage measurement in the case of branching to a non-target program during execution of the target program will be described. Here, it is assumed that a timer interrupt occurs during execution of the target program and branches to an interrupt program outside the target program.

  FIG. 12 is a diagram for explaining the target program and the branch to the interrupt program according to Embodiment 3 of the present invention. FIG. 13 is a schematic configuration diagram of an emulator 1000 according to the third embodiment of the present invention. A difference between the emulator 1000 in FIG. 13 and the emulator 100 in FIG. 3A is that the emulator 1000 includes a memory control circuit 1020 instead of the memory control circuit 102. Other portions are the same as those shown in FIG. 3A, and description thereof will not be repeated.

  FIG. 12A schematically shows a program stored in the storage unit 203. In FIG. 12B, a range of program codes to be executed when the program of FIG. 12A is executed is schematically shown by a thick arrow. FIG. 12C schematically shows branch information output when the target program is executed.

  In FIG. 12A, the program code of the target program is stored at addresses H′0100 to H′0280 of the storage unit 203, and the interrupt program is stored at addresses H′10000 to H′10020 that are not covered by the coverage. Yes. In FIG. 12A, each continue statement of the target program originally branches to address H′0250, but it is assumed that it branches to address H′0140 for convenience of explanation.

  In operation, when the execution of the target program is started from the program code at the head address, the program code for the length of each arrow is executed in the order of arrows (1) to (8) as shown in FIG. The The program code at the tip (end) of each arrow corresponds to a branch instruction. Therefore, the address corresponding to the tip corresponds to the branch source address, and the address corresponding to the start end of the next arrow corresponds to the branch destination address.

  Assume that a timer interrupt (timer_int) occurs when the program code at the address (H′0230) in FIG. 12A is executed (the tip of the arrow (5) in FIG. 12B). At this time, the CPU 201 saves the current value of the program counter in a register (not shown) (referred to as a save register). As a result, the address value (H′0230) for returning from the interrupt program to the target program can be stored in the save register.

  Thereafter, the value of the program counter is updated to H′10000, and the program branches to the interrupt program after the address H′10000 (the shaded area in FIG. 12B), and the interrupt program starts to be executed (FIG. 12). (B) arrow (6)).

  When the execution of the interrupt program ends, the CPU 201 rewrites the value of the program counter based on the value of the save register. For example, it is rewritten to indicate the address H′0240. As a result, execution of the target program is resumed from the program code at the time of occurrence of the timer interrupt (timer_int) (see arrow (7)).

  Thereafter, a branch instruction is executed at the tip address of the arrow (7), and the program code indicated by the arrow (8) is executed. Thereafter, the execution of the target program ends, and a program execution end notification is transmitted from the MCU 200 to the emulator 1000.

  During execution of the target program in FIG. 12A, branch information is output to the coverage measurement memory 101 by the same processing as in the first and second embodiments. The branch destination information (set of branch destination address and branch source address) output from the start to the end of the target program is schematically shown in FIG.

  Each of the branch information 600 and 700 in FIG. 12C includes branch destination information (branch destination address (H'10000) and branch source address) output when the branch instruction in the tip address area indicated by the arrow (5) is executed. (H′0230)) and branch destination information (branch destination address (H′0240) and branch source address (H′10020) output when the branch instruction in the tip address area indicated by the arrow (6) is executed. ) Set) Indicates each.

  The branch destination address (H′10000) of the branch information 600 exceeds the addressable range of the coverage measurement memory 101. If the branch source address (H′10020) of the branch information 700 is stored in the area of the branch destination address (H′0240) indicated by the arrow (5) in the coverage measurement memory 101, erroneous measurement occurs. That is, the subsequent analysis result by the host computer 300 indicates that the program code from the address H′0240 to H′10020 has been executed.

  Therefore, the memory control circuit 1020 of the emulator 1000 according to the third embodiment performs coverage measurement so that the above erroneous measurement does not occur even when the target program branches from the target program during execution of the target program. Branch information is stored in the memory 101.

  Specifically, when the memory control circuit 1020 detects branch information of the data 600 for the input packet, that is, compares the branch destination address value indicated by the data 113 with a threshold value, and determines the branch destination address from the comparison result. When it is determined that the value is larger than the threshold value, the data 113 is discarded. Then, the packet in which the value of the address designation area of the coverage measurement memory 101 based on the data 113 indicating the branch destination address (H′02040) of the branch information (that is, data 700) of the next input packet is input first. Is rewritten with the branch source address (H'0230) value of the branch information (ie, data 600). Note that the above threshold value indicates the final address value of the storage area of the target program in the storage unit 203 and is assumed to be stored in a register (not shown) in the memory control circuit 1020.

  As a result, the branch source address H′0230 can be stored in the area of the address H′0240 of the coverage measurement memory 101, and a branch instruction for branching from the target program to the non-target program is executed during execution of the target program. Even if it has been done, the trace data enabling coverage measurement without the above-mentioned erroneous measurement can be stored in the coverage measurement memory 101.

<Modification 1>
Although the above branch destination data 111 and branch source data 112 indicate a branch destination address and a branch source address, these data are not limited to addresses. For example, the branch destination data 111 and the branch source data 112 may indicate offset values based on the start address of the area in the storage unit 203 in which the target program is stored. In that case, the branch destination address and the branch source address are calculated from the reference and the offset value stored in the data portion of the input packet, for example, by the input unit 107 inside the emulator 100.

<Modification 2>
In the above embodiment, the target program is executed by the MCU 200, but may be executed by the host computer 300. In that case, the target program is stored in the storage unit 302 of the host computer 300, and the CPU 301 executes the target program. Branch information detected during execution (branch information detected each time a branch instruction is executed) is stored in a predetermined trace area (corresponding to the coverage measurement memory 101) of the storage unit 302 in accordance with the flowchart of FIG. Then, after the execution of the target program is completed, the program according to the flowchart of FIG. 6 is executed to analyze the trace data in the trace area of the storage unit 302, and for example, the analysis result shown in FIG. 9 is output.

[Embodiment 4]
In the first to third embodiments, the emulator 100 records the trace data and the host computer 300 analyzes the trace data. However, the trace data recording may be executed by the host computer 300 instead of the emulator 100. In that case, the data storage and analysis processing in the coverage measurement memory 101 shown in the first to third embodiments can be provided as a program according to the flowcharts of FIGS. Such a program can be recorded on a computer-readable recording medium such as a CD-ROM, ROM, RAM, and memory card attached to the computer and provided as a program product. Alternatively, the program can be provided by non-temporarily recording on a recording medium such as a hard disk built in the computer. A program can also be provided by downloading via a network.

  For example, in the configuration of FIG. 2, the program can be supplied to the host computer 300 including the CPU 301 using the CD-ROM 308. The CPU 301 reads and executes a program stored in the CD-ROM 308 via the I / F 307.

  The provided program product is installed in a program storage unit such as a hard disk in the storage unit 302, read by the CPU 301, and executed. The program product includes the program itself and a recording medium on which the program is recorded.

  In the above-described embodiment, an information processing system is shown. The information processing system includes a program execution unit for executing a program including a plurality of branch instructions, and an information processing apparatus connected to the program execution unit via a transmission path. The information processing apparatus includes an input unit for inputting branch source data of a branch instruction to be executed and corresponding branch destination data from a program execution unit, a memory for storing data relating to a plurality of branch instructions, A control unit for controlling access to the memory.

  The control unit described above stores the branch source data input by the input unit for the branch instruction executed next to the branch instruction in the address area of the memory specified based on the branch destination data of the branch instruction input by the input unit. Store.

  In the above-described embodiment, a program for causing a computer including a processor to execute an information processing method is shown. The program includes inputting a branch source data of a branch instruction to be executed and corresponding branch destination data from an external program execution unit for executing a program including a plurality of branch instructions to the processor; Controlling access to a memory for storing data relating to the branch instruction. In the step of controlling access, the branch input by the step of inputting the branch instruction executed next to the branch instruction in the address area of the memory specified based on the branch destination data of the branch instruction input by the input step Store the original data.

  In the above-described embodiment, a machine-readable recording medium in which the above program is recorded non-temporarily is shown.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  100 Emulator, 101 Coverage measurement memory, 102 Memory control circuit, 103 Memory address register, 104 Branch source holding register, 105 Size comparator, 106 Branch destination holding register, 111 Branch destination data, 112 Branch source data, 200 MCU, 300 Host computer, 312 Memory for analysis.

Claims (8)

When executing a program including a plurality of branch instructions, each time a branch instruction is executed, an input unit for inputting branch source data of the branch instruction and corresponding branch destination data;
A memory for storing data relating to the plurality of branch instructions;
A control unit for controlling access to the memory,
The controller is
The branch source data input by the input unit for the branch instruction executed next to the branch instruction is stored in the address area of the memory specified based on the branch destination data of the branch instruction input by the input unit. Information processing device. The controller is
A comparison unit for comparing the value indicated by the data stored in the designated address area with the value indicated by the branch source data input by the input unit for the branch instruction executed at the next level;
From the result of the comparison, when it is determined that the value indicated by the input branch source data is larger than the value indicated by the specified address area data, the address area data is rewritten to the branch source data. The information processing apparatus according to claim 1. The controller is
3. The information processing apparatus according to claim 2, wherein the rewriting is not performed when it is determined from the result of the comparison that a value indicated by the input branch source data is equal to or less than a value indicated by the data in the designated address area. . A storage area for storing the program;
The information processing apparatus according to claim 1, wherein the memory includes the address area assigned one-to-one to the address of the storage area.   The information processing apparatus according to claim 1, further comprising an analysis unit configured to detect an address area in which branch source data is stored from all address areas of the memory.   The information processing apparatus according to claim 5, wherein the analysis unit detects a ratio of address areas in which branch source data is stored among all address areas of the memory. The controller is
When the value indicated by the branch destination data of the branch instruction input by the input unit is greater than a threshold value, the branch source data corresponding to the branch destination data is set, and then the branch destination of the branch instruction input by the input unit The information processing apparatus according to claim 1, wherein the information processing apparatus is stored in an address area of the memory designated based on data. A step of inputting branch source data of the branch instruction and corresponding branch destination data each time the branch instruction is executed when executing a program including a plurality of branch instructions;
Controlling access of a memory for storing data relating to the plurality of branch instructions,
In the step of controlling the access,
The branch source data input by the step of inputting the branch instruction executed next to the branch instruction in the address area of the memory specified based on the branch destination data of the branch instruction input by the input step An information processing method for storing.

Images