JP2014045508A - Critical-path circuit for performance monitoring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin.SOLUTION: The monitor circuit comprises two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Description

  The present invention relates to digital integrated circuits, and in particular to timing error detection in digital circuits.

  Recently, circuit designers have explored various techniques for predicting errors in an integrated circuit (IC). One such technique is known as critical path performance monitoring. In conventional critical path performance monitoring, circuit designers are known as one or more signal paths ("critical paths" or "critical data paths") that are considered critical to the normal operation of an integrated circuit. ), Usually identify the path with the largest delay. For a given circuit element in the critical path, the designer further specifies a target timing margin, i.e., the time period over which the data signal transition reaches the circuit element before the clock signal transition. A timing monitoring circuit (or “aging sensor”) is provided on the integrated circuit to monitor the timing of each critical path signal. As the integrated circuit changes over time, the actual timing of each critical path signal tends to be worse. When the timing monitoring circuit determines that the actual timing margin of the critical path signal is less than the target timing margin, it can predict that a circuit error is likely to occur. Measures can be taken to self-correct by adjusting the clock frequency, voltage supply, or even the body bias voltage of the transistors in the integrated circuit. For example, Neil Savage, “Intel and ARM area Exploring Self-Corporation Schemes to Boost Processor Performance and Cut Power”, Spectrum on April 2, 2007, which is incorporated herein by reference in its entirety. // www. spectrum. iee. org / feb08 / 5975 and Midul Agarwal et al., “Circuit Failure Prediction and its applications to Transistor Aging”, 25th IEEE VLSI Test Symposium, May 6-10, May 6, 2007.

FIG. 1 is a block diagram of an integrated circuit 100 including a critical path 102 and a timing monitoring circuit 110 described by Agarwal et al. The critical path 102 includes circuit elements 104 and 106. The timing monitoring circuit 110 includes: (i) a D-type flip-flop 118 inserted after the circuit element 104 in the critical path 102 and before the circuit element 106; and (ii) a target at this position along the critical path 102. A delay element 114 having a delay value _TG equal to the timing margin and connected to the output of the first circuit element 104; and (iii) another D-type flip-flop 116 connected to the output of the delay element 114. And (iv) an exclusive OR (XOR) logic gate 122 connected to the outputs of flip-flops 118,116. Depending on the application, the delay value _TG is typically in the range from a few hundred picoseconds to a few nanoseconds. The timing monitoring circuit 110 delays the copy of the signal 112 appearing at the output of the circuit element 104 by a delay value _TG , latches the delayed signal in the flip flop 116, and from the flip flop 116 via the XOR logic gate 122. And the output signal 120 appearing at the output of the flip-flop 118. The output signal 126 from the XOR logic gate 122 is then latched into the timing error display register 124, which generates the output signal 128. The output signal 128 is then passed to the controller, which can adjust either the clock rate or the supply voltage of the integrated circuit based on the output signal 128.

As a first example, if signal 112 includes a data transition from logic 0 to logic 1 and the setup time of flip-flop 116 is just satisfied (ie, the timing margin is 0), A logical value of 1 is successfully latched in the flip-flop 116 with the clock CL. Since the transition from 0 to 1 reaches the input D of the flip-flop 118 at a slightly earlier time than the clock CL, the flip-flop 118 also latches normally with a logical value of 1. Since both flip-flops have the same output value, the XOR timing error indication register 126 has a logic value of zero. The logical value 0 indicates that the setup time of the flip-flop 118 in the critical path is satisfied at least until the target timing margin set to the delay value _TG .

As a second example, when the data transition of signal 112 from 0 to 1 occurs slightly later than in the previous example (eg, due to aging of circuit elements upstream of signal 112 in critical path 102) ), Flip-flop 118 can successfully latch with a logic value of 1 along with clock CL, while flip-flop 116 latches with a logic value of 0 for delay value _TG . Here, the XOR timing error indication register 126 has a logic value of 1, indicating that a setup failure has occurred in the flip-flop 116 and that the flip-flop 118 has a setup margin less than the delay value _TG. Show. Thus, timing errors tend to occur, for example, when the circuit continues to change over time.

  However, under certain circumstances, the timing monitoring circuit 110 may display an error that satisfies the timing of the critical path 102 even if a setup abnormality occurs. Specifically, when the transition from 0 to 1 occurs later than in the second example, both flip-flops 116 and 118 are set up abnormally, but can be erroneously latched with a logical value of 0. There is sex. In this case, since the XOR timing error display register 126 cannot detect the setup abnormality in both flip-flops, it erroneously indicates the logical value 0.

In addition to this susceptibility that causes detection omissions, the timing monitoring circuit 110 has several other drawbacks. First, since only one delay element 114 is used, the timing problem can be identified only with the resolution of the delay value _TG of that element.

  Secondly, in the critical path 102 to cause a data transition of the signal 112 sufficient to generate a timing error (or success) indication for the timing monitor circuit 110 to test the timing of the critical path 102. Some minimum amount of data activity needs to occur. When there is little data activity in the critical path 102, a delay in the critical path 102 (eg, due to aging) occurs but cannot be detected by the timing monitor circuit 110.

  Third, the timing monitoring circuit is typically added to the integrated circuit only after the integrated circuit physical design and static timing analysis (including critical path identification) is complete. However, when the flip-flop 118 in the timing monitoring circuit 110 is inserted into the critical path 102, both the timing and load of the critical path 102 are affected. Thus, after the timing monitor circuit 110 is deployed, the circuit load and timing analysis may need to be repeated, and the physical design may need to be changed to accommodate the timing monitor circuit 110. . Such changes can have a significant impact on the integrated circuit design schedule.

Neil Savage, “Intel and ARM are Exploring Self-Correcting Schemes to Boost Processor Performance and Cut Power”, Spectrum Online, February 2008, http: //www.Neil Savage. spectrum. iee. org / feb08 / 5975 Midul Agalwal et al., “Circuit Failure Prediction and its application to Transistor Aging”, 25th IEEE VLSI Test Symposium, May 6-10, 2007, pages 277-286.

  The problems in the prior art are solved according to the principles of the present invention by an improved timing monitoring circuit located in a region in the integrated circuit near the monitored critical path.

Accordingly, in one embodiment, the present invention is an integrated circuit that includes a monitoring circuit that monitors timing in a critical path therein. The critical path has a target timing margin. The monitoring circuit includes a first shift register having an input portion and an output portion and having a delay circuit that adds a delay value to the received signal. The monitoring circuit further includes a second shift register having an input and an output, wherein the inputs of the first and second shift registers form a signal input node that can receive the input signal. Are connected together.
The monitoring circuit also includes a logic circuit having an output and at least two inputs, each input being connected to a corresponding one of the outputs of the first and second shift registers. The output of the logic circuit indicates whether the target timing margin is satisfied or not satisfied.

  In another embodiment, the present invention is an apparatus for monitoring timing in a critical path in an integrated circuit. The critical path has a target timing margin. The apparatus comprises: (a) means for splitting an input signal into a first path including a first shift register and a second path including a second shift register; and (b) a first Means for delaying the input signal in the path by a first delay amount; (c) means for comparing the input signal in the second path with the delayed input signal in the first path; and (d) for the comparison. And generating an output indicating whether the target timing margin is satisfied or not satisfied.

In yet another embodiment, the present invention is a method for monitoring timing in a critical path in an integrated circuit. The critical path has a target timing margin.
The input signal is split into a first path that includes a first shift register and a second path that includes a second shift register. The input signal in the first path is delayed by a first delay amount.
The input signal in the second path is compared with the delayed input signal in the first path. Finally, based on the comparison, an output is generated that indicates whether the target timing margin is satisfied or not satisfied.

  Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings, in which like reference numerals refer to like or identical elements. Is identified.

1 is a schematic block diagram of a prior art timing monitoring circuit. FIG. 2 is a schematic block diagram of a timing monitoring circuit according to an embodiment of the present invention. FIG. FIG. 4 is a schematic block diagram of a timing monitoring circuit including a fine delay detector according to another embodiment of the present invention. FIG. 4 is a detailed block diagram of one embodiment of the fine delay detector of FIG. FIG. 5 is a timing diagram showing the operation of the timing monitoring circuit shown in FIG. 3 including the fine delay detector shown in FIG. 4. FIG. 5 is a timing diagram showing the operation of the timing monitoring circuit shown in FIG. 3 including the fine delay detector shown in FIG. 4. FIG. 5 is a timing diagram showing the operation of the timing monitoring circuit shown in FIG. 3 including the fine delay detector shown in FIG. 4.

  FIG. 2 illustrates an integrated circuit 200 that includes a timing monitoring circuit 210 according to one embodiment of the present invention. The timing monitoring circuit 210 is preferably located sufficiently close to the critical path 202 that includes the circuit elements 204 and 206, so the timing monitoring circuit 210 is the same process, voltage, temperature, and as the circuit elements in the critical path 202. Subject to aging effects. In contrast to the timing monitoring circuit 110 described above in FIG. 1 that is placed in and connected to the critical path 102, the timing monitoring circuit 210 is sufficiently independent of the critical path 202 (ie, It is preferable that there are no components in common with the critical path 202 and that the timing monitoring circuit 210 and the clock CL that can be shared by the critical path 202 do not depend on signals traversing the critical path 202).

Timing monitor circuit 210 includes (i) a first shift register 230 formed by D-type flip-flops 232 and 234 and (ii) a second shift register formed by D-type flip-flops 242 and 248. Register 240. The second shift register 240 further includes a delay element 244 that provides a delay value T _DELAY . The design value of the delay value T _DELAY is preferably equal to a predetermined time period that is a function of the target timing margin of the circuit element 206 in the critical path 202. For example, the predetermined time period may be approximately the difference between one clock period and the target timing margin. However, the actual delay value T _DELAY can increase over time, for example due to aging effects.

  The outputs of shift registers 230 and 240 are connected to the inputs of XOR logic gate 260, and the outputs of XOR logic gate 260 are connected to flip-flop 270, which is a timing error indicator. A timing error indication signal passed to 280 is generated. The timing monitoring circuit 210 can further include an enable / disable circuit 290 that passes the clock signal CL to other elements in the circuit only when receiving the enable signal EN. Enable / disable circuit 290 may be implemented as a NAND, NOR, OR, or XOR logic gate (with appropriate polarity enable signal EN) as an AND logic gate as shown in FIG. 2 or alternatively. it can.

Timing monitoring circuit 210 may further include a pulse generator 220 that generates signal 224, which is used as a “test data” signal that is input to shift registers 230 and 240. In the embodiment shown in FIG. 2, the pulse generator 220 is a flip-flop configured as a divide-by-2 circuit (ie, having its knot Q output connected to its D input) driven by a clock CL. Although flop 222, other suitable pulse generators can be used. In the embodiment shown in FIG. 2, the flip-flop 222 generates one output pulse at its knot Q output for each two clock periods. Next, the signal at the knot Q output of the flip flop 222 is divided and input to the D inputs of the flip flops 232 and 242.
Alternatively, the Q output, rather than the knot Q output of flip flop 222, can be used to drive the D inputs of flip flops 232 and 242.

For a given rising edge of clock CL, the data transition of signal 224 (eg, from 0 to 1) is latched in flip-flops 232 and 242. On the next rising edge of clock CL, the data transition is latched into flip-flop 234 in non-delayed shift register 230. When the actual delay value T _DELAY of the delay element 244 does not exceed the sum of the predetermined time period and the target timing margin (eg, the actual delay value T _DELAY does not exceed approximately one clock period), the flip-flop 248 The set-up time is not violated and the flip-flop 248 in the delay shift register 240 latches normally on the same data transition. Thus, the XOR logic gate 260 produces a logic zero at its output, indicating that the timing of the test data path that includes the flip-flop 242, the delay element 244, and the flip-flop 248 matches the design limit. . A test data path including flip-flop 242, delay element 244, and flip-flop 248 is sufficient for critical path 202 so that the elements in the two paths are subjected to the same process, voltage, temperature, and aging effects. Since it is arranged in the vicinity, a logical value 0 at the output of the XOR logic gate 260 is considered to indicate that the timing of the critical path 202 also matches the design limit.

On the other hand, due to process, voltage, temperature, and / or aging effects, the actual delay value T _DELAY exceeds the sum of the predetermined time period and the target timing margin (eg, the actual delay value T _DELAY is approximately one clock). The target timing margin is no longer satisfied. The flip-flop 234 in the non-delayed shift register 230 latches normally with a data transition value (eg, a logical value of 1), while the flip-flop 248 in the delay shift register 240 has an incorrect data transition value (eg, a logic value of 1). Latch at 0). In this case, the XOR logic gate 260 generates a logic value 1 at its output, indicating that the timing of the critical path 202 was not satisfied. Next, the flip-flop 270 generates a timing error indication signal that is passed to the timing error indicator 280.

  In practice, the delay element 244 is preferably selected during a design process from a predetermined set of standard delay circuits (eg, including macro circuits). Standard delay circuits can provide propagation delays corresponding to various sections of the clock period based on the particular target timing margins that can be set at the start of the project. The standard delay circuit preferably includes a standard battery having a high threshold voltage value, a standard threshold voltage value, and a low threshold voltage value mixed in close proximity to the critical path of the monitored integrated circuit. Further, the delay element 244 can be a variable delay element so that the timing monitoring circuit 210 can accommodate various clock frequencies during operation of the integrated circuit 200.

  Timing monitoring circuit 210 has many advantages over prior art timing monitoring circuit 110 of FIG. First, the timing monitoring circuit 210 can be incorporated into the physical design long before the final statistical timing analysis is performed. Without adding any additional load on the critical path, an additional load is added to the clock signal of the logic gate that is added only once per instance of the timing monitor circuit 210, and at various key locations on the integrated circuit, Parallel arrangement can be performed. As a result, the timing monitoring circuit 210 has minimal impact on static timing analysis or the final physical design of the integrated circuit.

  Secondly, the timing monitoring circuit 210 is not easily affected by the above-described detection omission problem in the timing monitoring circuit 110 because the flip-flop 234 always latches the correct data.

  Third, the timing monitoring circuit 210 does not rely on an integrated circuit that causes data transitions to test the monitored critical path. Rather, the pulse generator 220 introduces many data transitions through the timing monitoring circuit 210 to test the monitored critical path frequently, albeit indirectly.

  Fourth, the enable / disable circuit 290 receives the clock signal CL and distributes the clock signal CL to the remaining circuit elements in the timing monitor circuit 210, so that the timing monitor circuit 210 is simply added to the integrated circuit. Only one gate is added to the integrated circuit clock load.

  FIG. 3 shows a timing monitoring circuit 310 according to another embodiment of the present invention. The timing monitoring circuit 310 of FIG. 3 is similar to the timing monitoring circuit 210 of FIG. 2, and in the timing monitoring circuit 310, the fine delay detection circuit 346 connected to the total delay element 344 and the fine delay output register 350 is replaced by the fine delay detection circuit 346 of FIG. Similar elements are identified using a code having the same last two digits, except that they are substituted for the delay element 244.

The delay value of the total delay element 344 is selected to be approximately the same as the majority of the delay values provided by the delay element 244, but the delay value for the fine delay detector 346 is the delay value provided by the delay element 244. Selected to be the rest of. Therefore, the total path delay value between the flip-flops 242 and 248 in the timing monitoring circuit 210 of FIG. 2 and the total path delay value between the flip-flops 342 and 348 in the timing monitoring circuit 310 of FIG. The same. The fine delay detector 346 (ii) compares (ii) the actual delay of the total delay element 344 with a predetermined time period (which is a function of the target timing margin as described above) with a predetermined resolution. Based on the results, it is preferably configured to generate a detector output signal corresponding to the actual timing margin of the timing monitoring circuit 310. The detector output signal is then passed to the fine delay detection register 350.
In the preferred embodiment, fine delay detector 346 is configured to detect not only an increase in the actual delay amount for total delay element 344, but also a decrease in such delay amount. At that time, the fine delay detector 346 can also evaluate the increase and decrease of the actual timing margin in the timing monitoring circuit 310.

FIG. 4 illustrates an exemplary embodiment of the fine delay detection circuit 346 of FIG. As shown in FIG. 4, the fine delay detection circuit 346 includes nine delay line elements (DLE) 406 _{0 to} 406 ₈ , nine flip-flops 404 _{0 to} 404 ₈ and eight XOR logic gates connected in series. 402 _{0 to} 402 ₇ . Input of the flip-flop 404 ₀ and DLE406 ₀ is connected to the signal _{TR IN} taken from the output of the total delay element 344 of FIG. DLE406 ₀ ~406 ₇ the output of each connected to the input of the D input and DLE406 ₁ ~406 ₈ flip-flops ₄₀₄ 1 to 404 _8. DLE406 ₈ is provided as the output load of DLE406 ₇ is the same as the output load of DLE406 ₀ ~406 _6. Therefore, the output of DLE406 ₈ is not used.

In this configuration, the input signal _{TR IN} propagates down delay line formed by DLE406 ₀ ~406 _8. DLE 406 ₀ -406 ₈ and flip-flops 404 ₀ -404 ₈ form a “thermometer” register. When the thermometer register has a set of n output bits, the 0th to i-th output bits are all high, but the remaining output bits (ie (i + 1) th to (n-1) th) Output bits) are all low (or vice versa). The transition point of the value of the thermometer register output bit (eg, from logic 1 to logic 0) occurs when the clock signal CL reaches the flip-flops 404 ₀ -404 ₈ , the input signal TR _IN becomes DLE 406. a delay line formed by _{0-406 8} shows a distance propagated downward.

The successive pairs of Q outputs of flip-flops 404 ₀ -404 ₈ connect to corresponding inputs of XOR logic gates 402 ₀ -402 ₇ . Then, XOR logic gate ₄₀₂ 0-402 _7, respectively, to produce an output bit _B 0 .about.B _7, to measure the actual delay of the total delay element 344. Thus, DLE 406 ₀ -406 ₈ , flip-flops 404 ₀ -404 ₈ , and XOR logic gates 402 ₀ -402 ₇ form a “one hot” register, with only one output bit being high (ie, “1”). But the rest will be low (ie, “0”) (or vice versa). The position of the high output bit within the output bits B ₀ -B ₇ is the delay formed by the DLE 406 ₀ -406 ₈ when the input signal TR _IN is reached when the clock signal CL reaches the flip-flops 404 ₀ -404 _8. Shows the distance traveled down the line.

The output bits B ₀ -B ₇ are then stored in the fine delay detector output register 350 for use by, for example, an IC timing controller (not shown). In doing so, the IC timing controller can use the timing information provided by the output bits B ₀ -B ₇ , for example, adjusting the rate of the integrated circuit clock or the power supply voltage based on the timing information. For example, when dealing with the target timing margin with an extra margin, the clock rate can be increased without fear of generating a critical path 202 timing error. On the other hand, when the target timing margin is not met, the clock rate can be decreased to improve the timing of the critical path 202.

Output signal _{TR OUT} of the detection circuit 346, the any one of the output portion of DLE406 ₀ ~406 _8, can be connected to the D input of the flip-flop 348 of FIG. The particular DLE output used as a connection for the output signal TR _OUT allows the designer to detect success (ie earlier) or unsuccessful (ie later) timing, as further described below. Depending on the range desired, it can be selected during integrated circuit design. In the embodiment shown in FIG. 4, for example, the output signal _{TR OUT} is taken directly at the output of DLE406 _1.

Alternatively, the outputs of DLE 406 ₀ -406 ₈ can be connected to a 9 × 1 selection switch (not shown) and the output from the selection switch can be taken as an output signal TR _OUT . The selection switch can be an active gate multiplexer, a transmission gate (T-gate) multiplexer, a ternary buffer multiplexer, or other suitable selection switch or multiplexer. In this alternative embodiment, the selection switch may select any one of the outputs from DLE 406 ₀ -406 ₈ for use as output signal TR _OUT , eg, based on a control signal from a timing controller. it can.

  Further, the operation of the timing monitoring circuit 310 shown in FIG. 3 and the fine delay detection circuit 346 shown in FIG. 4 will be described with reference to the following three cases, respectively illustrated by the timing diagrams shown in FIGS. I can understand.

Case 1: Corresponding to Target Timing Margin with No Surplus Margin FIG. 5 shows the timing of Case 1 corresponding to the target timing margin with no surplus margin. In case 1, (i) delay from clock CL to output Q of flip-flop 342, (ii) delay by total delay element 344, and (iii) delay by fine delay detector 346 (eg, signal TR _IN there are design values for the sum of the time advance to signal TR _OUT), it is chosen to be approximately equal to one clock cycle (i.e., the target timing margin is a minimum as little or not at all there is room Is considered).

At the first rising edge of clock CL, indicated by time t ₁ in the timing diagram of FIG. 5, the data logic value 1 is latched in flip-flops 332 and 342 of FIG. Therefore, the Q outputs of flip-flops 332 and 342 transition from a logical value of 0 to a logical value of 1.

Intentionally, immediately before the second rising edge of the clock CL at time _{t 2} in FIG. 5, across two first DLE406 ₀ and 406 ₁ of the output portion of the total total delay element 344 and fine delay the detector 346 , A transition from 0 to 1 is observed. In the second rising edge of the clock CL (at time _{t 2),} the output of the first DLE two closest to the _{TR IN} input section (i.e., DLE406 ₀ and 406 _1), the logical value 1 is observed . The output of the remaining seven DLE406 ₂ ~406 _8, all show a logic zero. The second rising edge of clock CL also records a logic value 1 in flip-flops 334 and 348 of FIG. 3, so that timing error indicator 380 eventually records a logic value 0 and time Indicates that the physical constraint is satisfied.

The second rising edge of the clock CL is further a logical value 1 in the flip-flop ₄₀₄ 0-404 ₂ in FIG. 4, the logical value 0 is recorded in the flip-flop ₄₀₄ 3-404 _8. Accordingly, the bit values B [0: 7] output by the XOR logic gates 402 _{0 to} 402 ₇ each have a logic value {0010 0000}. A B ₂ bit value of logic 1 indicates that a transition from 0 to 1 occurs in the third DLE (DLE 406 ₂ ) at the time of the second rising edge of the clock CL. In other words, in the second rising edge of the clock CL (time _{t 2),} (the output from and DLE406 ₁₎ input to DLE406 ₂ is a logical value 1, the output from DLE406 _2, the logical value 0. In this example, these XOR output bit values (B [0: 7] = {0010 0000}) indicate that the target timing margin corresponds to the minimum detectable surplus margin.

Case 2: Corresponding to Target Timing Margin with Large Surplus Margin FIG. 6 shows the timing of Case 2 corresponding to the target timing margin with a large surplus margin. In case 2, as in case 1, (i) delay from clock CL to output Q of flip-flop 342, (ii) delay by total delay element 344, and (iii) delay by fine delay detector 346 Is selected to be approximately equal to one clock period (ie, the target timing margin is considered minimal so that there is little or no margin). However, in case 2, if the combination of reduced clock distribution speed and / or increased data path speed over time results in a transition from 0 to 1, lowering the delay line further than originally designed. It is regarded.

Initially, a logical value of 1 is clocked into flip-flops 332 and 342 at the first rising edge of clock CL, indicated by time t ₁ in the timing diagram of FIG. Therefore, the Q outputs of flip-flops 332 and 342 transition from a logical value of 0 to a logical value of 1. Just before the second rising edge of the clock CL at time _{t 2,} over a first DLE406 ₀ ~406 output of ₆ 7 total total delay element 344 and the delay line of the fine delay detection circuit 346, from 0 to 1 A transition to is observed. At time _{t 2} in FIG. 6, the second rising edge of the clock CL, the input unit _{TR IN} closest seven first DLE to (i.e., DLE406 ₀ ~406 ₆₎ to the output of logic value 1 is observed Is done. The output of the remaining DLE406 ₇ and 406 ₈ illustrates a logic value 0. The second rising edge of clock CL also records a logic value 1 in flip-flops 334 and 348 of FIG. 3, and timing error indicator 380 eventually records a logic value 0, which is a time constraint. Is satisfied.

The second rising edge of the clock CL is further a logical value 1 to the flip-flop ₄₀₄ 0-404 in ₇ of FIG. 4, the logical value 0 is recorded in the flip-flop 404 _8. Accordingly, each XOR output bit value B [0: 7] has the value {0000 0001}. Here, the eighth bit value B ₇ of the logical value 1 transitions from 0 to 1 within the eighth DLE (DLE406 ₇ ) at the time of the second rising edge of the clock CL (time t ₂ ). Indicates that happens. In other words, in the time of the second rising edge of the clock CL, the input to DLE406 ₇ (and DLE406 output from ₆₎ is a logical 1, the output from DLE406 ₇ has a logic value 0. These XOR output bit values indicate that the target timing margin corresponds to the maximum detectable surplus margin. In this case, the maximum detectable surplus margin is approximately 5 DLE delay.

Case 3: Timing is not satisfied due to setup error FIG. 7 shows Case 3 where the target timing margin is not satisfied and a setup error is detected. In case 3, similar to cases 1 and 2, (i) delay from clock CL to output Q of flip-flop 342, (ii) delay by total delay element 344, and (iii) fine delay detector 346. Is selected to be approximately equal to one clock period (ie, the target timing margin is considered minimal so that there is little or no margin). However, in case 3, the combination of increased clock distribution speed and / or decreased data path speed over time results in a transition from 0 to 1, further increasing the delay line beyond the target timing margin and causing a setup error Happens.

In FIG. 3, at time t ₁ in FIG. 7, a logical 1 is clocked into flip-flops 332 and 342 on the first rising edge of clock CL. Therefore, the Q outputs of flip-flops 332 and 342 transition from a logical value of 0 to a logical value of 1. Just before the second rising edge of the clock CL at time _{t 2,} over a first DLE406 output of ₀ total total delay element 344 and the delay line, the transition is observed from 0 to 1.
At time t ₂ , at the second rising edge of the clock CL, a logic value 1 is observed at the output of the first DLE closest to the input TR _IN (ie, DLE 406 ₀ ). The output units of the remaining eight DLEs 406 _{1 to} 406 ₈ all indicate a logical value of zero. The second rising edge of clock CL also records a logical value of 1 in flip-flop 334 in non-delayed shift register 330 of FIG. However, the second rising edge of clock CL records a logical value of 0 in flip-flop 348 of delay shift register 340 of FIG. As a result, the timing error indicator 380 eventually records a logical value 1, indicating that a timing error has occurred and the target timing margin has not been satisfied.

At time t ₂ , the second rising edge of clock CL further records a logic value 1 in flip-flops 404 ₀ -404 ₁ and a logic value ₀ in flip-flops 404 ₂ -404 ₈ in FIG. To do. Thus, each XOR output bit value B [0: 7] has the value {0100 0000}. Here, the output bit value _{B 1} of logic value 1 indicates the second rising edge of the clock CL (time _{t 2),} the second DLE406 _1, that the transition from 0 to 1 occurs . In other words, at the time of the second rising edge of clock CL, the input to DLE 406 ₁ (and the output from DLE 406 ₀ ) has a logical value of 1, and the output from DLE 406 ₁ has a logical value of 0. These output bit values B [0: 7] indicate that the target timing margin is not supported and that a setup abnormality of approximately 1 DLE delay amount has occurred.

Similar to the embodiment of FIG. 2, the embodiment of FIGS. 3 and 4 has many advantages over the prior art. As a first matter, the embodiments of FIGS. 3 and 4 share all of the advantages of FIG. 2 described above. In addition, the embodiments of FIGS. 3 and 4 make numerical measurements (both positive and negative) of actual timing margin as well as presence / absence of timing error indication.
Further, the timing margin measurement range can be adjusted by adjusting the total delay 344 and / or the number of delay line elements and their corresponding flip-flops and XOR logic gates. Further, the range of clock frequencies can be accommodated by adjusting the total path delay element 344 during operation of the timing monitoring circuit 310. Finally, the relative range of the timing margin measurement capability from plus to minus can be managed by changing the position of the output section TR _out in the DLE in the fine delay detection circuit 346.

  Although the present invention has been described with respect to circuitry including XOR logic gates 260, 360, the present invention can also be implemented using other types of logic gates, such as non-XOR (NXOR) gates.

In addition, fine delay detection circuit 346 shown in FIG. 4 includes nine DLE406 ₀ ~406 _8, 9 one flip-flop ₄₀₄ 0-404 ₈ and eight XOR logic gate ₄₀₂ 0-402 _7, the actual For example, the number of DLE, flip-flop, and XOR logic gates can be greater or less than the number shown in FIG. 4 depending on the amount of fine delay resolution desired in a particular application.

  Further, in the embodiment shown in FIGS. 2 and 3 above, the data signals 224, 324 are generated by the pulse generators 220, 320, although it is understood that the use of the pulse generator 220 is optional. I want. Thus, in one embodiment of the present invention, the data signal traversing critical data path 202 (eg, the output signal from circuit element 204) can be split and used as data signal 224, where data signal 224 is , Flip-flops 232 and 242 and / or 332 and 342.

  The present invention is based on a digital (or analog and digital hybrid) circuit base that can be implemented as a single integrated circuit (such as an ASIC or FPGA), a multi-chip module, a single card, or a multi-card circuit pack. Can be implemented as a process. As will be apparent to those skilled in the art, the various functions of the circuit elements can also be implemented as processing blocks in the software program. Such software can be used, for example, in a digital signal processor, microcontroller, or general purpose computer.

  Further, in this description, the terms “coupled”, “coupled”, “coupled”, “connect”, “connected”, “connected” are not required, Reference is made to any method known or later developed in the art that can transfer energy between two or more elements and contemplate the intervention of one or more additional elements. Conversely, the terms “directly coupled”, “directly connected”, and the like, suggest that there are no such additional elements.

  Here, signals and corresponding nodes or ports can be referred to by the same name and can be interchanged depending on the purpose.

  Unless expressly stated otherwise, each numerical value and range should be interpreted as being approximate as if the term “about” or “approximately” preceded the value or range.

  In addition, various modifications of the details, materials, and construction of the parts described and illustrated to illustrate the characteristics of the invention can be made by those skilled in the art without departing from the scope of the invention. It will be understood. Rather, the scope of the invention is set forth in the following claims.

  The present invention has been described with respect to the shift register 240 of FIG. 2 including the delay element 244 and the shift register 340 of FIG. 3 including the delay elements 344 and 346. In general, the shift register of the present invention can be implemented with any suitable circuit that adds an appropriate amount of delay to the signal propagating through the shift register.

  Use of the figure numbers and / or figure reference signs in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. And Such use is to be construed as not having to limit the scope of those claims to the embodiments shown in the corresponding figures.

  It should be understood that the steps of the exemplary methods described herein are not necessarily performed in the order described, and that the order of the steps of such methods should be understood as merely exemplary. . Similarly, in methods consistent with various embodiments of the invention, such methods can include additional steps, and some steps can be omitted or combined.

  Elements in the following method claims, if any, are listed with their corresponding symbols in a particular order, but the claims statement must separately suggest a particular order to implement some or all of those elements. For example, those elements are not necessarily intended to be limited to implementation in that particular order.

  In this specification, references to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described with respect to the embodiment can be included in at least one embodiment of the invention. means. When the phrase “in one embodiment” appears in various places in the specification, it is not necessary to refer to the same embodiment, and separate or alternative embodiments need not exclude each other from each other. . The same applies to the term “implementation”.

Claims (11)

An integrated circuit comprising monitoring circuits (210, 310) for monitoring timing in a critical path (202) in the integrated circuit, wherein the critical path has a target timing margin, and the monitoring circuit includes:
A first flip-flop (242, 342) having an input and an output;
A second flip-flop (232, 332) having an input and an output, the input of the first and second flip-flops receiving an input signal (224, 324); A second flip-flop connected together to form a possible signal input node;
A delay circuit (244, 344/346) configured to add a delay value to the signal output from the first flip-flop;
A logic circuit (260, 360) having an output unit and at least a first input unit and a second input unit, wherein the first input unit is connected to the delay circuit, and the second input unit is A logic circuit connected to the output of the second flip-flop,
The output of the logic circuit indicates whether the target timing margin is satisfied or not satisfied;
The delay circuit is
A total delay element configured to provide a total delay value; and a fine delay detection circuit configured to generate an output signal indicating a range in which the target timing margin is satisfied based on the total delay value. Including integrated circuits. When an input pulse is inserted into the signal input node,
(I) the first flip-flop generates a first pulse at its output;
(Ii) the second flip-flop generates a second pulse at its output; (iii) the logic circuit is configured such that the first pulse comprises the predetermined time period and the target timing margin. The integrated circuit of claim 1, generating an output indicating that the target timing margin has not been satisfied only when temporally separated from the second pulse by an amount of time that is greater than the sum of the two.   The integrated circuit of claim 1, wherein the total delay element has an adjustable delay value. The fine delay detection circuit includes:
A delay line having an input section and a plurality of delay line elements (406 _{0 to} 406 ₈ ) connected in series, each delay line element including a delay line having an input section and an output section. An integrated circuit as described. The fine delay detection circuit includes:
A plurality of flip-flops (404 ₀ -404 ₈ ), wherein one or more flip-flops have an input and an output, each said input being said input of a corresponding delay line element A plurality of flip-flops connected to the section;
The integrated circuit according to claim 4, wherein the output unit of the plurality of flip-flops indicates a range in which the target timing margin is satisfied. The fine delay detection circuit includes:
A plurality of logic gates (402 ₀ -402 ₇ ), each logic gate being connected in series with a corresponding pair of outputs of adjacent flip-flops in the plurality of flip-flops along the delay line, respectively. A plurality of logic gates having at least two inputs,
6. The integrated circuit of claim 5, wherein the output of at least one logic gate indicates a range in which the target timing margin is satisfied. A method for monitoring timing in a critical path in an integrated circuit, the critical path having a target timing margin,
(A) dividing the input signal into a first path including a first flip-flop (242, 342) and a second path including a second flip-flop (232, 332);
(B) delaying the input signal in the first path by a first delay amount;
(C) comparing the input signal in the second path with the delayed input signal in the first path;
(D) generating an output (280, 380) indicating whether the target timing margin is satisfied or not based on the comparison;
(E) detecting a range in which the target timing margin is satisfied or not satisfied, and the detecting includes:
Delaying the input signal in the first path by the first delay amount, and subsequently delaying the input signal by a plurality of delay elements in a delay line;
Generating for each delay element in the delay line an output signal corresponding to a signal state at the input of the delay element.   The method of claim 7, further comprising adjusting the first delay amount.   9. The method of claim 8, wherein adjusting the first amount of delay is performed based on one of a plurality of clock frequencies of the integrated circuit. Detecting a range where the target timing margin is satisfied or not satisfied,
For each successive pair of output signals corresponding to successive pairs of delay elements in the delay line, whether the input signal has reached the corresponding delay element in the delay line at a time determined by a clock signal Performing a logical operation to determine, based on the successive pairs of output signals,
8. The method of claim 7, further comprising outputting the result of the logical operation corresponding to at least one successive pair of output signals. An apparatus for monitoring timing in a critical path in an integrated circuit, the critical path having a target timing margin,
(A) means for splitting the input signal into a first path including a first flip-flop and a second path including a second flip-flop;
(B) means for delaying the input signal in the first path by a first delay amount;
(C) means for comparing the input signal in the second path with the delayed input signal in the first path;
(D) means for generating an output indicating whether the target timing margin is satisfied or not based on the comparison;
(E) means for detecting a range where the target timing margin is satisfied or not satisfied, and the detecting means includes:
Means for delaying the input signal in the first path by the first delay amount, and subsequently delaying the input signal by a plurality of delay elements in a delay line;
Means for generating, for each delay element in the delay line, an output signal corresponding to a signal state at the input of the delay element.

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