JP2014045406A - Image forming apparatus, control method of image forming apparatus, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To switch a frequency of a clock to be supplied to each of image processing units individually according to the amount of processing data required in each of the image processing units, so as to achieve power saving of the image processing units as a whole.SOLUTION: An image processing apparatus has a plurality of image processing units connected in series each performing image processing set on the basis of an input clock, to perform a series of image processing, and determines a ratio of the amount of processing data processed in subsequent image processing units with respect to the amount of processing data processed by an initial image processing unit as a reference (S503). The image processing apparatus inputs clocks having different frequencies individually determined from the processing speed programed in each of the image processing units and the calculated ratio of processing data, to each of the image processing units.

Description

  The present invention relates to an image forming apparatus that performs power saving control, a method for controlling the image forming apparatus, and a program.

  In general, an image processing apparatus has a plurality of image processing functions to cope with various processing contents. As an implementation form of each image processing function, there is a form executed by an image processing program using a processor, and a form executed by connecting each of the image processing functions in a logic circuit and connecting them in series. The latter is necessary in the field where high-speed processing is required. For example, Patent Document 1 discloses a configuration in which image data output from a reading device can be processed through a plurality of image processing units configured in series in an image processing device.

  Further, in the prior art, there is disclosed a technique for saving power by switching a clock supplied to an image processing unit to a lower frequency based on a format of image data in order to reduce power consumption of an image processing circuit in operation. (Patent Document 2).

JP 2009-225270 A Japanese Patent No. 3945328

  As described above, an image processing apparatus that performs a plurality of image processes at once by connecting a plurality of image processing units in series has the following problems.

The amount of data processed by each image processing unit depends on the content of the image processing. Depending on the content of processing, the amount of data processed by each image processing unit may be biased. Since the speed at which each image processing unit processes data is fixed, some image processing units may become rate-limiting (bottleneck). Since each processing unit performs pipeline processing, when a part of the processing units is rate-determined, the other image processing units are suppressed to a processing speed slower than the original processing speed.
The image processing units other than the rate limiting unit are reduced in speed, but the power consumption is not reduced at the same rate. This is because even if the number of data to be processed is reduced, the leakage power and the power for driving the clock tree are not reduced.

The present invention has been made to solve the above-described problems, and an object of the present invention is to perform processing required in each image processing section even when performing image processing by connecting a plurality of image processing sections in series. It is to provide a mechanism that can save power as the whole image processing unit by individually switching the frequency of the clock supplied to each image processing unit in accordance with the data amount.

The image processing apparatus of the present invention that achieves the above object has the following configuration.
An image processing apparatus that performs a series of image processing by connecting a plurality of image processing units that perform image processing set based on an input clock in series, and processing data amount processed by the first image processing unit Is calculated separately from the calculation means for obtaining the ratio of the processing data amount processed by the subsequent image processing unit, and the ratio of the processing speed scheduled by each image processing unit and the calculated processing data amount. Clock means for inputting the clocks having different frequencies to the image processing units.

  According to the present invention, even when a plurality of image processing units are connected in series to perform image processing, the frequency of the clock supplied to each image processing unit is adapted to the amount of processing data required by each image processing unit. Can be switched individually to save power as the entire image processing unit.

It is a block diagram explaining the structure of the image processing apparatus which shows this embodiment. The internal block diagram of the image processing part for edit shown in FIG. 1 is shown. FIG. 3 is a block diagram illustrating details of a clock generation unit illustrated in FIG. 2. 3 is a timing chart for explaining the operation of the image processing apparatus. It is a flowchart explaining the control method of an image processing apparatus. It is a figure which shows the relationship between the parameter of image processing, and setting frequency. It is a block diagram which shows the detailed signal connection state between image processing parts. It is a timing chart explaining the operation | movement shown in FIG. It is a block diagram explaining the detailed structure of the image processing part for edit.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
<Description of system configuration>
[First Embodiment]
FIG. 1 is a block diagram illustrating the configuration of the image processing apparatus according to the present embodiment.

  In FIG. 1, an image forming apparatus 130 reads a document optically to obtain an image data, a reading section 140, processes the obtained image data and controls the entire apparatus, and processes the processed data on a printer sheet. A printing unit 117 for printing is provided. The image forming apparatus 130 includes a LAN interface 120 that can be connected to the LAN 114 according to the Ethernet (registered trademark) standard and a FAX interface 110 that can be connected to the FAX line 115.

  In the controller unit 100, a CPU 101 executes a software program stored in the ROM 103 or the HDD 112 and controls the entire image forming apparatus 130. The ROM 103 mainly stores a program for starting an OS (operation system). The HDD 112 stores an OS and application programs such as printing and copying executed on the OS.

  An SDRAM 111 is used as a work area for storing temporary data when the CPU 101 controls the entire image forming apparatus 130. An OS and application program for the CPU 101 to control the entire apparatus are also loaded from the HDD 112 to the SDRAM 111 and executed on the SDRAM 111.

  Reference numeral 109 denotes a panel, which includes a touch panel that displays an apparatus state and receives an operator's command, an input key, and the like. A panel control unit 106 displays a display image formed in advance on the SDRAM 111 on the display unit of the panel 109. Further, the panel control unit 106 acquires the state of the input keys and the touch panel arranged on the panel 109 and transmits them to the CPU 101.

  A printer control unit 104 performs operation control and status acquisition of the printing unit 117 according to instructions from the CPU 101. A scanner control unit 116 performs operation control and status acquisition of the scanner 140 in accordance with instructions from the CPU 101.

  A printer image processing unit 108 converts image data prepared in advance by the CPU 101 into the SDRAM 111 or the HDD 112 into a color space for printing, performs image processing such as binarization, and sends the processed data to the printing unit 117.

  A scanner image processing unit 113 is an image processing unit that performs non-linear correction, color space correction, and the like on the read image data generated by the reading unit 140, converts the read image data into regular data, and transmits the data to the SDRAM 111 or the HDD 112.

  The editing image processing unit 119 is an image processing unit that performs page assignment processing during reduced printing, image processing during FAX transmission / reception, image processing during image transmission to the LAN 114, preview image generation processing before printing, and the like. The location of the original data and processed data is the SDRAM 111 or the HDD 112. Details of the image processing unit for editing will be described later.

  The LAN controller 107 controls the LAN interface 120 to receive data to be printed by this apparatus and store it in the SDRAM 111. Further, the image data stored in the SDRAM 111 or the HDD 112 is transmitted to the LAN 114.

  The FAX controller 104 controls the FAX interface 110 and transmits the image data stored in the SDRAM 111 to the FAX line. At the time of FAX reception, the image data received from the FAX line 115 is stored in the SDRAM 111.

  In the image processing apparatus described above, the printer image processing unit 108 and the scanner image processing unit 113 or the editing image processing unit 119 each have a plurality of image processing units therein and process input image data in a pipeline manner. To do. The present invention can be applied to an image processing block including a plurality of such image processing units. In the present embodiment, an example in which the present invention is implemented in the editing image processing unit 119 will be described.

FIG. 2 shows an internal configuration diagram of the editing image processing unit 119 shown in FIG. This example corresponds to an example of an image processing apparatus that performs a series of image processing by connecting a plurality of image processing units that perform image processing set based on an input clock in series. In the present embodiment, the CPU 101 performs a calculation process for obtaining a ratio with the processing data amount processed by the subsequent image processing units 212 and 213 with reference to the processing data amount processed by the first image processing unit 211. In addition, a clock generation unit 220 is provided that inputs each clock having a different frequency, which is individually determined from the processing speed planned by each image processing unit and the ratio of the processing data amount calculated by the CPU 101, to each image processing unit.
A process for specifying an image processing unit to which a clock with the highest frequency should be input from a processing speed scheduled for each image processing unit and a ratio of the calculated processing data amount, and an input to the specified image processing unit The CPU 101 includes a configuration in which a CPU 101 executes a determination process for determining a clock frequency to be input to each subsequent image processing unit with reference to a clock frequency to be performed according to a flowchart described later.
In FIG. 2, reference numeral 201 denotes a read DMAC, which autonomously issues sequential read access to the SDRAM 111 via the system bus 128 and supplies image data stored in the SDRAM 111 to a subsequent processing unit. The read address, transfer data amount, etc. on the SDRAM 111 are set in the DMAC 201 in advance by the CPU 101.
An image processing unit 211 performs resolution conversion processing according to setting information set in advance by the CPU 101. The setting information includes an input data type, an input image size, and a scaling factor.
An image processing unit 212 performs color conversion processing based on setting information set in advance by the CPU 101. The setting information includes an input data type, an output data type, and an input image size. An image processing unit 213 performs binarization processing using setting information set in advance by the CPU 101. The setting information includes an input data type and a binarization processing type.

  Reference numeral 205 denotes a write DMAC that autonomously issues sequential write access to the SDRAM 111 via the system bus 128 and stores image data after image processing in the SDRAM 111. The write address on the SDRAM 111, the amount of transfer data, etc. are preset in the DMAC 205 by the CPU 101.

  In the path from the read DMAC 201 to the write DMAC 205, the image processing units and the DMAC are connected by a buffer 240, a buffer 241, a buffer 242, and a buffer 243. These buffers are prepared for buffering local transfer speed changes and for transferring data between circuits having different operating frequencies without loss. Details will be described later.

  The clock control unit 210 receives, as input, information related to the processing data amount among setting information set in the image processing unit 211, the image processing unit 212, and the image processing unit 213, and a frequency of a clock supplied to each of the image processing units 211 to 213. And frequency information is output to the clock generator 220. The clock control unit 210 can be realized by a small CPU. The clock generation unit 220 supplies each image processing unit 211 to 213 with each clock having a different frequency that is individually determined from the processing speed planned by each image processing unit 211 to 213 and the ratio of the processing data amount calculated by the CPU 101. Performs input clock input processing.

The clock generation unit 220 receives the system clock and outputs predetermined clocks 331 to 333 to the corresponding image processing unit 211, image processing unit 212, and image processing unit 213 according to the frequency designation information given from the clock control unit 210. Although not shown in FIG. 1, the system clock is an operation clock for the entire controller unit 100, and is 100 MHz in this embodiment.
FIG. 3 is a block diagram showing details of the clock generation unit 220 shown in FIG.
In FIG. 3, in this embodiment, clocks other than the system clock are generated by thinning them out with an AND gate 311, an AND gate 312, and an AND gate 313.

  For example, assume that a 25 MHz clock is to be supplied to the image processing unit 212. In that case, the clock control unit 322 gives a signal designating 25 MHz to the mask generation circuit 302. When receiving a signal designating 25 MHz, the mask generation circuit 302 outputs a mask M322 shown in the timing chart shown in FIG. The mask M322 is a logic circuit that receives a system clock of 100 MHz and outputs one mask signal every four cycles. Since those skilled in the art can easily design, description is omitted.

  In the editing image processing unit 119 of FIG. 2, blocks other than the image processing unit 211, the image processing unit 212, and the image processing unit 213, for which clock input is not explicitly shown, are operated by inputting a system clock. . FIG. 5 shows a control flow of an image processing job when the present invention is applied to the editing image processing unit 119 configured as described above.

FIG. 4 is a timing chart for explaining the operation of the image processing apparatus according to the present embodiment. Here, FIG. 4A shows the timing for G3 FAX transmission, and FIG. 4B shows the timing for G4 FAX transmission.
FIG. 5 is a flowchart for explaining a control method of the image processing apparatus according to the present embodiment. Here, each step shown in FIG. 5A is realized by the CPU 101 executing a control program stored in the ROM 103. Further, each step shown in FIG. 5B is realized by the CPU in the clock control unit 210 executing a control program stored in the internal memory. In this example, the image processing job is image processing for G3 FAX transmission. That is, an image process is assumed in which 400 dpi, RGB color multivalued image data is converted into monochrome binary data in order to obtain an image for G3 FAX transmission.

First, if the original image data is stored in the HDD 112, the CPU 101 transfers the original image data from the HDD 112 to the SDRAM 111 (S511). Subsequently, the CPU 101 sets parameters for image processing in the respective registers of the image processing unit 211, the image processing unit 212, and the image processing unit 213 (S512). The setting parameters are shown in the first column of the table TAB1 shown in FIG. That is, as the image processing unit A, for example, in order to obtain a 200 dpi image, 50% scaling is performed in both the x and y directions, and the RGB multi-valued color is converted into a single-color multi-valued by the image processing unit B. In part C, parameters are set for performing binarization processing based on error diffusion.
Next, the CPU 101 sets a parameter set end flag (not shown) in the clock control unit 210 (S513).

  On the other hand, in step S501, the clock control unit 210 monitors a parameter set end flag set by the CPU 101 and waits for the flag to be set. If it is confirmed that the parameter set end flag is set, the process proceeds to S502, and the parameter set end flag is cleared for the next job.

In step S <b> 503, the clock control unit 210 detects the ratio of the processing data amounts of the image processing units 211 to 213 based on the increase / decrease of the data in the parameters of each image processing. That is, if the processing data amount of the image processing unit 211 is “1”, the image processing unit 211 performs ½ scaling in the vertical and horizontal directions, so the processing data amount of the image processing unit 211 is “1”. Then, the processing amount of the image processing unit 212 is ¼.
Since the image processing unit 212 outputs only one color from three colors (R, G, B), if the processing data amount of the image processing unit 211 is “1”, the processing data amount of the image processing unit 213 is 1/12 (see the second column of the table TAB1 in FIG. 6A).

Next, the clock control unit 210 detects at least one processing unit that determines the rate from the ratio of the processing data amount and the known processing speed of each image processing unit (S504).
First, the known processing speed is shown in the third column of the table TAB1 in FIG. The number of cycles for processing the unit data can be obtained by dividing the value of column 1 by the value of column 2. As a result, the image processing unit 211 has one cycle, the image processing unit 212 has a ¼ cycle, and the image processing unit 213 has an This is 1/6 cycle (the fourth column of the table TAB1 in FIG. 6A). Therefore, since the image processing unit 211 consumes the most cycle, it is determined to be a rate-limiting unit (the fifth column of the table TAB1 in FIG. 6A).

  Next, in step S505, the clock control unit 210 calculates the frequency of the clock supplied to the other image processing unit with the processing unit that is rate limiting as the highest frequency (in the sixth column of the table TAB1 in FIG. 6A). ). That is, the image processing unit 211 is set to 100 MHz equal to the system clock, and the frequencies of the image processing unit 212 and the image processing unit 213 are determined to be 5 MHz and 16.7 MHz in accordance with the ratio of the table TAB4 in FIG. .

  In step S <b> 506, the clock control unit 210 outputs a signal indicating the calculated clock frequency to the mask generation circuit 301, the mask generation circuit 302, and the mask generation circuit 303 in the clock generation unit 220. Mask generation circuits 301 to 303 generate a mask M321, a mask M322, and a mask M323 (see the timing chart of FIG. 4 and FIG. 1), which are mask signals corresponding to the input signal.

Thereby, as shown in FIG. 4A, since the mask M321 is always at the high level, the clock 331 remains at 100 MHz. On the other hand, the mask M322 masks the system clock with three cycles being low level in four cycles. Therefore, the pseudo 25 MHz clock 322 is output to the image processing unit 212. In addition, since the mask M323 masks the system clock with 5 cycles being at a low level in 6 cycles, the clock 333 of 16.7 MHz is output to the image processing unit 213.
Next, the clock control unit 210 sets a frequency setting completion flag (not shown) arranged in the clock control unit 210 (S507), returns to the top of the flow, and waits for the next job.

On the other hand, after setting the image processing parameter set end flag in the clock control unit 210 (S513), the CPU 101 sets parameters of the read DMAC 201 and the write DMAC 205 in S514 (S514). The CPU 101 polls the frequency setting completion flag (S515), confirms the setting of the flag, clears the flag for initialization (S516), and activates the read DMAC 201 and the write DMAC 205 (S517). . When the CPU 101 detects that the write DMAC 205 has ended (S518), the image processing job is ended.
Accordingly, the frequency of the clock supplied to each image processing unit can be individually switched in accordance with the amount of processing data required by each image processing unit, and power saving can be achieved as a whole image processing unit.
Here, in order to explain that the present invention can set the frequency corresponding to various image processing settings, the difference will be described by taking a job for generating an image for G4 FAX transmission as an example. In the flow of FIG. 6, the original image is assumed to be RGB color multivalued image data of 400 dpi.

  The settings (S512) in the image processing unit 211, the image processing unit 212, and the image processing unit 213 are shown in the first column of FIG. 6B. That is, since 400 dpi binary monochrome image is necessary for G4 FAX transmission, the image processing unit 211 is set to the same magnification, the image processing unit 212 is set to monochrome multi-value output of RGB multi-value input, and the image processing 213 is monochrome binary based on error diffusion. Set conversion parameters.

  The processing speed of each of the image processing units 211 to 213 is equal to that of the table TAB1 (third column in FIG. 6B). The number of cycles for processing unit data may be obtained by dividing the value in column 1 by the value in column 2 and the result is 1 cycle for image processing unit 211, 1 cycle for image processing unit 212, and 2/3 cycle for image processing unit 213. (The fourth column in FIG. 6B). Accordingly, since the image processing unit A211 and the image processing unit B212 consume the most cycle, it is determined as a rate-limiting unit (the fifth column in FIG. 6B).

  Next, the clock control unit 210 calculates the frequency of the clock supplied to the other image processing units with the processing unit that is rate limiting as the highest frequency (the sixth column in FIG. 6B). That is, the image processing unit 211 and the image processing unit 212 are set to 100 MHz equal to the system clock, and the frequency of the image processing unit is determined to be 66.7 MHz in accordance with the ratio of the column 4 in FIG.

  Next, the clock control unit 210 outputs a signal indicating the calculated clock frequency to the mask generation circuit 301, the mask generation circuit 302, and the mask generation circuit 303 in the clock generation unit 220. Mask generation circuits 301 to 303 generate masks M321, M322, and M323 (see the timing chart of FIG. 4B), which are mask signals corresponding to the input signals.

Since the mask M321 and the mask M322 are always at the high level, the clock 331 and the clock 332 remain at 100 MHz. On the other hand, the mask M323 outputs the clock 333 of 66.7 MHz because 1 cycle is masked at 3 cycles. .
Although the control flow of the image processing unit to which the present invention is applied has been described above, a method for transferring data between blocks having different frequencies via a buffer without loss will be described.

FIG. 7 is a block diagram showing a detailed signal connection state between the image processing unit 212 and the image processing unit 213 in the editing image processing unit 119 shown in FIG. In this example, data is transferred via a buffer 242 that operates on the system clock.
Therefore, it is only necessary to transfer data from a block operating at a frequency lower than 100 MHz to a block operating at 100 MHz, and from a block operating at 100 MHz to a block operating at a frequency lower than 100 MHz.

  Data handshaking is performed by a VALID signal and a READY signal. The data transmission side indicates the output of valid data by a VALID signal, and the reception side indicates that reception is possible by a READY signal. In both cases, if the VALID or READY output by itself and the READY or VALID signal input from the other party are both high at the rising edge of the clock input thereto, it is determined that the data is transferred.

It is necessary to prevent the VALID signal or the READY signal output from the low frequency side from being erroneously sampled a plurality of times on the high frequency side. Therefore, the VALID_B signal output from the image processing unit 212 is input to the buffer 242 as masked_VALID_B masked by the AND gate 702.
Similarly, the READY_C signal output from the image processing unit 213 is input to the buffer 242 as masked_READY_C masked by the AND gate 703.

FIG. 8 is a timing chart for explaining the operation shown in FIG.
8A shows a signal waveform between the image processing unit 212 operating at 25 MHz and the buffer 242 operating at 100 MHz. The image processing unit 212 on the transmission side starts outputting valid data from cycle 2, and the buffer 242 on the reception side returns READY_buffer 242 in cycle 8, so that the transfer condition is detected in cycle 9 and the data output is completed with the clock of cycle 10. .

  The receiving-side buffer 242 is ready to receive in cycle 8 and outputs READY_buffer 242 but does not receive immediately because VALID_B is masked and the condition is not satisfied. Since masked_VALID_B becomes valid in cycle 9, reception is completed with the system clock of cycle 10.

  The timing chart shown in FIG. 8B shows signal waveforms between the buffer 242 operating at 100 MHz and the image processing unit 213 operating at 16.7 MHz. The image processor C213 on the receiving side is ready to receive in cycle 2, and the buffer 242 on the transmitting side starts outputting valid data from cycle 3, but does not transmit immediately because READY_C is masked and the condition is not satisfied. In cycle 7, READY_buffer 242 becomes valid, and transmission is completed with the system clock of the cycle.

  The image processing unit 213 on the reception side is ready to receive in cycle 2 and starts outputting READY_C. Since VALID_buffer 242 becomes valid in cycle 3, reception is completed in cycle 8 of the next sampling point.

  In the above embodiment, an example in which power saving is performed by reducing the operating frequency supplied to the image processing unit has been described. In general, when a circuit operating at a certain frequency is operated at a lower frequency, the operating voltage can be lowered from the original voltage. Therefore, it is possible to obtain a further power saving effect by separating the power source for each image processing unit so that the power source voltage can be individually controlled.

FIG. 9 is a block diagram illustrating a detailed configuration of the editing image processing unit 119 shown in FIG. The difference between this example and the configuration shown in FIG. 2 is that the variable voltage generator 290 is the variable voltage generator 290, and the minimum voltage at which each image processor can operate is determined according to the signal indicating the operating frequency output from the clock controller 210. This is supplied to the processing unit.
In the present embodiment, a variable voltage generation unit 290 is provided as a power generation unit that individually supplies power of a potential corresponding to the determined clock frequency to each image processing unit.

  Each process of the present invention can also be realized by executing software (program) acquired via a network or various storage media by a processing device (CPU, processor) such as a personal computer (computer).

  The present invention is not limited to the above embodiment, and various modifications (including organic combinations of the embodiments) are possible based on the spirit of the present invention, and these are excluded from the scope of the present invention. is not.

101 CPU
102 ROM
119 Image processing unit for editing

Claims (6)

An image processing apparatus that performs a series of image processing by connecting a plurality of image processing units that perform image processing set based on an input clock in series,
A calculation means for obtaining a ratio of a processing data amount processed by a subsequent image processing unit with reference to a processing data amount processed by the first image processing unit;
A clock means for inputting each clock of different frequencies separately calculated from a processing speed scheduled in each image processing unit and a ratio of the calculated processing data amount to each image processing unit;
An image processing apparatus comprising: An image processing apparatus that performs a series of image processing by connecting a plurality of image processing units that perform image processing set based on an input clock in series,
A calculation means for obtaining a ratio of a processing data amount processed by a subsequent image processing unit with reference to a processing data amount processed by the first image processing unit;
A specifying means for specifying an image processing unit to which a clock with the highest frequency is to be input, based on a ratio between a processing speed scheduled for each image processing unit and the calculated processing data amount;
Determining means for determining the frequency of the clock to be input to each subsequent image processing unit, with reference to the frequency of the clock to be input to the specified image processing unit;
Clock means for generating a clock of the determined frequency and inputting it to each image processing unit;
An image processing apparatus comprising:   The image processing apparatus according to claim 1, further comprising a power generation unit that individually supplies power of a potential corresponding to the determined clock frequency to each image processing unit. A control method of an image processing apparatus that performs a series of image processing by connecting a plurality of image processing units that perform image processing set based on an input clock in series,
A calculation step for obtaining a ratio of the processing data amount processed in the subsequent image processing unit with reference to the processing data amount processed in the first image processing unit;
A clock input step of inputting from the clock means to each image processing unit each clock having a different frequency, which is individually determined from the processing speed planned in each image processing unit and the ratio of the calculated processing data amount;
An image processing apparatus control method comprising: A control method of an image processing apparatus that performs a series of image processing by connecting a plurality of image processing units that perform image processing set based on an input clock in series,
A calculation step for obtaining a ratio of the processing data amount processed in the subsequent image processing unit with reference to the processing data amount processed in the first image processing unit;
A specific step of specifying an image processing unit to which a clock with the highest frequency is to be input, based on a ratio between the processing speed planned for each image processing unit and the calculated processing data amount;
A determination step of determining a frequency of a clock to be input to each subsequent image processing unit with reference to a frequency of the clock to be input to the specified image processing unit;
A clock input step of generating a clock of the determined frequency and inputting it to each image processing unit from a clock means;
An image processing apparatus control method comprising:   A program for causing a computer to execute the control method of the image processing apparatus according to claim 4 or 5.

Images