JP2013255056A - Optical signal detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a precise adjustment of detection sensitivity to an optical signal.SOLUTION: A differential amplification circuit 11 differentially amplifies a differential signal Tout input via coupling capacitors C1, C2. A differential current addition circuit 12 adds a DC current depending on an offset adjustment voltage Vos to a normal phase signal and a reverse phase signal of a resultant amplified output signal Fout to regulate a DC offset voltage of the normal phase signal and the reverse phase signal. A comparator 13 compares voltage values of a normal phase signal and a reverse phase signal of a resultant current-added output signal Aout. A holding circuit 14 holds a resultant comparison output signal Cout as a DC holding voltage Vhd. A hysteresis comparator circuit 15 compares the holding voltage Vhd with two different determination threshold voltages Vth_SD, Vth_LOS determined by a sensitivity adjustment voltage Vsens, and outputs a comparison result as an optical signal detection signal SD/LOS.

Description

  The present invention relates to an optical receiver in optical communication, and more particularly to a circuit (SD: Signal Detect and LOS: Loss Of Signal detection circuit) for determining whether or not an effective optical reception intensity is obtained.

  In an optical receiver that receives an optical signal and obtains a reception output composed of an electrical signal, light that determines whether or not an optical signal is input is used to prevent unnecessary noise from being output from the optical receiver in the absence of the optical signal. A signal detection circuit (SD: Signal Detect) is used. This optical signal detection circuit generates an optical signal detection signal that indicates whether or not an optical signal with sufficient signal strength is received, thereby detecting communication abnormality and outputting noise from the limiting amplifier LA when there is no signal. A squelch circuit control is performed to block the signal.

  FIG. 9 is a block diagram showing a configuration of a conventional optical receiver (see, for example, Patent Document 1). In the optical receiver 200, the optical signal Pin received by the photodiode PD is photoelectrically converted into a photocurrent signal Iin and amplified by a transimpedance amplifier TIA that is a preamplifier. The differential signal Tout of the transimpedance amplifier TIA is input to a limiting amplifier LA that is a post amplifier, and is amplified so that optical signals Pin having different intensities become electric signals having a constant amplitude, and output as a reception output signal Rout. The A waveform shaping circuit such as CDR (Clock Data Recovery) or a timing adjustment circuit is usually connected to the subsequent stage of the limiting amplifier LA, and a clock signal is extracted from the data signal and shaped into a waveform that can be easily handled as a digital signal.

  Further, the positive phase signal Tout + and the negative phase signal Tout− of the differential signal Tout input from the transimpedance amplifier TIA are AC-coupled to the optical signal detection circuit 20 via the respective coupling capacitors C. In the optical signal detection circuit 20, only when the differential signal Tout is received, the comparator 21 outputs the comparison output signal Cout. The comparison output signal Cout is held by the SR latch 22, and the optical signal detection signal SD made up of a DC signal. Convert to / LOS. The holding release of the optical signal detection signal SD / LOS in the SR latch 22 is performed by the reset signal RESET. For example, in burst communication typified by a PON system, the PON control IC can output a reset signal RESET at the end of reception of a burst packet.

  Therefore, if this optical signal detection signal SD / LOS is used for squelch control, for example, the squelch is closed until the next burst signal is received after receiving a reset, and noise is output from the limiting amplifier LA. Can be prevented. Further, when the next burst signal is received, the squelch can be opened to set the normal reception state.

  FIG. 10 is a circuit diagram showing a configuration of a comparator used in the conventional optical signal detection circuit. The comparator 21 includes a bias circuit 21A, a first stage amplifier circuit 21B, a first stage emitter follower circuit 21C, and a next stage amplifier circuit 21D.

  The positive-phase signal Tout + and the negative-phase signal Tout− of the differential signal Tout input from the transimpedance amplifier TIA are AC-coupled to the first-stage bias circuit 21A via the respective coupling capacitors C. Since the coupling capacitor C is a differential circuit, the differential waveforms of the positive phase signal Tout + and the negative phase signal Tout− are input to the differential transistor pair Q21, Q22 of the first stage amplifier circuit 21B.

Here, if the values of the load resistors R25, R26 of the differential transistor pair Q21, Q22 are different from each other, the output of the first stage amplifier circuit 21B has an offset voltage at its DC level.
Therefore, if the positive phase signal Tout + and the negative phase signal Tout− having sufficient amplitude are not input, the output amplitude of the first stage amplifier circuit 21B is insufficient and a differential signal is not formed, that is, the non-inverted output from the transistor Q21 and the transistor Q22. Therefore, the comparison output signal Cout is not output from the next stage amplifier circuit 21D connected via the first stage emitter follower circuit 21C, and remains at the low level.

On the other hand, when the amplitudes of the input normal phase signal Tout + and the negative phase signal Tout− are sufficiently large, the non-inverted output from the transistor Q21 and the inverted output from the transistor Q22 intersect, so that the comparison output signal Cout is the intersection. The High level and the Low level corresponding to the portion appear alternately.
Since the comparison output signal Cout is held by the SR latch 22, for example, when the reception of the optical signal Pin is started, the High level is continuously output as the optical signal detection signal SD / LOS. Therefore, this circuit is characterized in that once the high level is output as the comparison output signal Cout, the level is held and output as the optical signal detection signal SD / LOS, so that high-speed optical signal detection that responds immediately to signal reception is possible. The circuit 20 can be realized.

JP 2009-044228 A

  In such a conventional optical signal detection circuit 20, in order to accurately output a significant pulse having an amplitude greater than or equal to the reference value as the comparison output signal Cout, the detection sensitivity for detecting whether or not the optical signal Pin is input is adjusted in the comparator 21. There is a need. If the detection sensitivity is too high, the mixed noise may be erroneously detected as a significant pulse in a section without a burst signal. On the other hand, if the detection sensitivity is too low, a detection delay may occur at the beginning of the burst signal. Further, since the characteristics of the photodiode PD and the transimpedance amplifier TIA vary depending on the temperature and the power supply potential, the amplitude of the differential signal Tout also varies, which affects the detection sensitivity of the comparator 21. Therefore, it is necessary to adjust the detection sensitivity of the optical signal according to the temperature and the power supply potential.

As a configuration for adjusting the detection sensitivity of the optical signal in the comparator 21, a configuration in which the load resistance value of the amplifier circuit provided in the comparator 21 is automatically adjusted from the outside according to the temperature and the power supply potential can be considered.
FIG. 11 shows an example of optical signal detection sensitivity adjustment in the comparator. Here, among the resistance elements R29 and R30 which are load resistances of the next stage amplifier circuit 21D in the comparator 21, the load resistance used for amplification of the positive phase signal Fout + of the amplified output signal Fout output from the first stage emitter follower circuit 21C. A variable resistor Radj for adjusting sensitivity is connected in parallel to R29. That is, one end of the variable resistor Radj is connected to the collector terminal of the transistor Q25 of the first-stage emitter follower circuit 21C, and the other end is connected to the power supply potential Vcc.

  When the resistance value of the variable resistor Radj is changed, the load resistance value of Q25 composed of the combined resistance of R29 and Radj is changed, and the amplitude of the comparison output signal Cout output from the collector terminal of Q25 is changed. As a result, for example, the presence / absence of latch with respect to the comparison output signal Cout is determined based on the comparison result between the threshold voltage at the input terminal S of the SR latch 22 and the pulse amplitude of the comparison output signal Cout. Sensitivity is adjusted.

  Here, when the comparison output signal Cout having a large amplitude is required, a differential amplifier circuit may be disposed at the subsequent stage of the next-stage amplifier circuit 21D. In such a case, the differential signal obtained from the collector terminals of the transistors Q25 and Q26 constituting the next-stage amplifier circuit 21D of FIG. 10 is input to the differential amplifier circuit arranged in the subsequent stage. .

  When the detection sensitivity adjustment example of FIG. 11 is applied to such a circuit configuration, only the amplitude of the output signal from Q25 corresponding to the positive phase signal Fout + is adjusted, and from Q26 corresponding to the negative phase signal Fout−. The amplitude of the output signal is not adjusted. For this reason, the positive and negative phase output signals having different amplitudes are differentially amplified by the differential amplifier circuit disposed in the subsequent stage to generate the comparison output signal Cout. As a result, the temperature, the power supply potential, and the detection sensitivity Therefore, there is a problem that it is difficult to accurately adjust the detection sensitivity of the optical signal.

  Further, since the load resistance value of Q25 is a combined resistance value of R29 and Radj, linearity between Radj and detection sensitivity cannot be obtained. As a result, there is a problem that it is difficult to accurately adjust the detection sensitivity of the optical signal because the linearity of the temperature, the power supply potential, and the detection sensitivity cannot be obtained.

  The present invention has been made to solve such problems, and an object thereof is to provide an optical signal detection technique capable of accurately adjusting the detection sensitivity of an optical signal.

  In order to achieve such an object, an optical signal detection circuit according to the present invention detects an optical signal input presence or absence based on a differential signal obtained by photoelectrically converting an optical signal. The differential signal input through a coupling capacitor is differentially amplified and output as an amplified output signal, and the positive phase signal and the negative phase signal of the amplified output signal, A differential current addition circuit that adjusts the DC offset voltage of the positive phase signal and the negative phase signal by adding a DC current corresponding to the input offset adjustment voltage, and outputs the current addition output signal, and the current addition Comparing the voltage values of the positive and negative phase signals of the output signal and outputting the comparison result as a comparison output signal; rectifying the comparison output signal and charging it with a holding capacitor; A holding circuit that discharges the DC holding voltage obtained by the discharge resistor, and the holding voltage is compared with two different determination threshold voltages determined by the input sensitivity adjustment voltage, and the comparison result is A hysteresis comparator circuit that outputs an optical signal detection signal indicating whether or not an optical signal is input.

  Also, in one configuration example of the optical signal detection circuit according to the present invention, the current adding circuit has a collector terminal connected to one end of a first load resistor used for amplification of the positive phase signal of the amplified output signal. A first transistor that receives a set voltage value from a set voltage source at a base terminal, and a differential pair with the first transistor, and a collector terminal that amplifies the negative-phase signal out of the amplified output signal. A constant current source connected to a connection point of a second transistor connected to one end of a second load resistor to be used and having the adjustment voltage value inputted to a base terminal thereof, and an emitter terminal of the first and second transistors Is included.

  Also, in one configuration example of the optical signal detection circuit according to the present invention, the hysteresis comparator circuit has a negative phase input terminal connected to the sensitivity adjustment voltage, and a positive phase input terminal connected to the holding voltage via an input resistor. It includes an operational amplifier that is connected and whose output terminal is connected to the positive phase input terminal via a feedback resistor.

  In addition, one configuration example of the optical signal detection circuit according to the present invention includes a plurality of offset adjustment voltages having a voltage value corresponding to a transmission speed according to a transmission speed selection signal indicating the transmission speed of the optical signal. And an offset adjustment voltage selector circuit that selects any one of the offset adjustment voltages and inputs the selected voltage to the differential current addition circuit.

  In addition, one configuration example of the optical signal detection circuit according to the present invention is selected from among a plurality of sensitivity adjustment voltages having a voltage value corresponding to a transmission speed in accordance with a transmission speed selection signal indicating the transmission speed of the optical signal. , Further comprising a sensitivity adjustment voltage selector circuit for selecting any one of the sensitivity adjustment voltages and inputting the selected voltage to the hysteresis comparator circuit.

  Further, one configuration example of the optical signal detection circuit according to the present invention further includes a voltage follower circuit that receives the holding voltage of the holding circuit as an input and converts the holding voltage by impedance conversion, and the hysteresis comparator circuit includes: Instead of the holding voltage from the holding circuit, the holding voltage after impedance conversion obtained by the voltage follower circuit is compared with the sensitivity adjustment voltage.

  According to the present invention, in the differential current adding circuit, it is possible to adjust the amplitude-voltage conversion characteristic when converting the amplitude of the input differential signal into the holding voltage by the offset adjustment voltage. In addition to the adjustment of the amplitude-voltage conversion characteristic, in the hysteresis comparator circuit, the detection sensitivity of the presence / absence of an optical signal can be adjusted by the sensitivity adjustment voltage. Therefore, the linearity of temperature, power supply potential, and detection sensitivity can be improved, and the detection sensitivity of the optical signal in the optical signal detection circuit can be adjusted with high accuracy.

It is a block diagram which shows the structure of the optical signal detection circuit concerning 1st Embodiment. 2 is a detailed circuit configuration example of the optical signal detection circuit according to the first embodiment; It is explanatory drawing which shows operation | movement of a current addition circuit. It is an example of the circuit simulation result concerning 1st Embodiment. It is explanatory drawing which shows adjustment of the amplitude-voltage conversion characteristic by an offset adjustment voltage. It is explanatory drawing which shows detection sensitivity adjustment by a sensitivity adjustment voltage. It is a block diagram which shows the structure of the optical signal detection circuit concerning 2nd Embodiment. It is a block diagram which shows the structure of the optical signal detection circuit concerning 3rd Embodiment. It is a block diagram which shows the structure of the optical signal detection circuit concerning 4th Embodiment. It is a block diagram which shows the structure of the conventional optical receiver. It is a circuit diagram which shows the structure of the comparator used with the optical signal detection circuit concerning a prior art. It is an example of detection sensitivity adjustment of the optical signal in a comparator.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, an optical signal detection circuit 10 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the optical signal detection circuit according to the first embodiment.

The optical receiver 100 is a communication device that converts an optical signal received via an optical fiber into an electrical signal and outputs it. For example, in the PON system adopted in the FTTH system, an OLT that accommodates a plurality of users on the station side. Used in
The optical receiver 100 includes a photodiode PD, a transimpedance amplifier TIA, a limiting amplifier LA, and an optical signal detection circuit 10 as main circuit configurations.

  In the optical receiver 100, the optical signal Pin that has reached through the optical fiber is received by the photodiode PD, converted into a photocurrent signal Iin, and amplified by a transimpedance amplifier TIA that is a preamplifier. The differential input signal Rin obtained by the transimpedance amplifier TIA is input to the limiting amplifier LA that is a post amplifier, is amplified, and is output as a reception output signal Rout.

The limiting amplifier LA is used in an optical receiver that converts an optical signal received via an optical fiber into an electrical signal and outputs it. The differential input is input so that optical signals of different intensities have the same amplitude. The signal Rin is amplified and output as a differential reception output signal Rout.
In LA, the input stage is provided with an emitter follower circuit EF that impedance-converts and outputs a differential input signal Rin. Further, a differential amplifier MA connected in multiple stages is provided after the EF, and the differential signal Tout obtained by the EF is amplified and output as a reception output signal Rout.

  In LA, in order to amplify the differential input signal Rin by the differential amplifier MA connected in multiple stages, the EF is generally provided in the first stage to adjust the level of the differential input signal Rin. In this embodiment, the case where the differential signal Tout whose level is adjusted by EF is used as an input signal of the optical signal detection circuit 10 is described, but the present invention is not limited to this. When the EF is not provided in the first stage of LA, an output signal from the first stage differential amplifier among the differential amplifiers MA connected in multiple stages may be used as an input signal of the optical signal detection circuit 10.

The optical signal detection circuit 10 detects the presence / absence of an optical signal based on the differential signal Tout from the limiting amplifier LA or the differential input signal Rin from the TIA, and displays the optical signal input presence / absence. It is a circuit unit that outputs a detection signal SD / LOS.
The optical signal detection circuit 10 includes a differential amplifier circuit 11, a differential current addition circuit 12, a comparator 13, a holding circuit 14, and a hysteresis comparator circuit 15 as main circuit portions.

The differential amplifier circuit 11 has a function of differentially amplifying the differential signal Tout from LA input through the coupling capacitors C1 and C2 and outputting the amplified signal as an amplified output signal Fout.
The differential current adding circuit 12 is a DC current corresponding to the input set voltage Vs and the offset adjustment voltage Vos with respect to the positive phase signal Fout + and the negative phase signal Fout− of the amplified output signal Fout from the differential amplifier circuit 11. Is added to adjust the DC offset voltage of the positive phase signal and the negative phase signal and output as a current addition output signal Aout.

The comparator 13 compares the voltage values of the positive phase signal Aout + and the negative phase signal Aout− of the current addition output signal Aout whose DC offset voltage has been adjusted by the differential current addition circuit 12, and the comparison result is used as a comparison output signal Cout. It has a function to output.
The holding circuit 14 has a function of charging the voltage of the comparison output signal Cout from the comparator 13 with the holding capacitor Ch and discharging the DC holding voltage Vhd obtained by the charging with the discharge resistor Rh.

  The hysteresis comparator circuit 15 compares the holding voltage Vhd of the holding circuit 14 with two different determination threshold voltages Vth_SD and Vth_LOS determined by the input sensitivity adjustment voltage Vsens, and the comparison result is the presence or absence of the input of the optical signal. It has a function of outputting an optical signal detection signal SD / LOS indicating.

FIG. 2 is a detailed circuit configuration example of the optical signal detection circuit according to the first embodiment. FIG. 3 is an explanatory diagram showing the operation of the current adding circuit.
The differential amplifier circuit 11 is provided with an initial stage bias circuit 11A, an initial stage amplifier circuit 11B, and an initial stage emitter follower circuit 11C. The differential current adder circuit 12 is provided with a next stage bias circuit 12A, a next stage amplifier circuit 12B, a current adder circuit 12C, and a next stage emitter follower circuit 12D. These circuit parts are each integrated on a semiconductor chip.

  The first stage bias circuit 11A is composed of a resistance voltage dividing circuit including a resistance element R1 pulled up to the power supply potential Vcc and a resistance element R2 pulled down to the ground potential GND, and is input via the coupling capacitors C1 and C2. The DC bias voltages corresponding to the resistance ratios of R1 and R2 are respectively applied to the differential signals Tout + and Tout− via the resistors R11 and R12. As a result, equal DC bias voltages are applied to the input differential signals Tout + and Tout−.

  The first stage amplifier circuit 11B includes transistors Q1 and Q2 forming a differential pair, a resistance element R5 connected between the collector terminal of Q1 and Vcc, and a resistance element connected between the collector terminal of Q2 and Vcc. A differential composed of R6, resistance elements R7 and R8 connected in series between the emitter terminals of Q1 and Q2, and a constant current source I1 connected between the connection point of the resistance elements R7 and R8 and GND. The amplifier circuit has a function of differentially amplifying differential signals Tout + and Tout− input to the base terminals of the transistors Q1 and Q2.

  Here, R5 and R6 correspond to the load resistance of the differential amplifier circuit, and different resistance values corresponding to the reference values are set in advance. For this reason, a voltage difference corresponding to the DC offset voltage is applied to the differential outputs respectively output from the emitter terminals of Q1 and Q2.

  The first-stage emitter follower circuit 11C includes transistors Q3 and Q4 and constant current sources I2 and I3 connected between the collector terminals of the transistors Q3 and Q4 and GND, respectively, and the bases of these Q3 and Q4. Each of the terminals has a function of outputting the amplified output signal Fout of the first stage amplifier circuit 11B input to each terminal with low impedance.

  The next stage bias circuit 12A is composed of a resistance voltage dividing circuit composed of a resistance element R3 pulled up to the power supply potential Vcc and a resistance element R4 pulled down to the ground potential GND, and is input via the coupling capacitors C1 and C2. Further, it has a function of applying a DC bias voltage corresponding to the resistance ratio of R3 and R4 via the resistors R13 and R14 to the amplified output signals Fout + and Fout− from the first-stage emitter follower circuit 11C. As a result, equal DC bias voltages are applied to the input amplified output signals Fout + and Fout−.

  The next stage amplifier circuit 12B includes transistors Q5 and Q6 forming a differential pair, a resistor element R9 (first load resistor) connected between the collector terminal of Q5 and Vcc, the collector terminal of Q6, and Vcc. From a differential amplifier circuit composed of a resistance element R10 (second load resistance) connected between and a constant current source I4 connected between the connection point of the emitter terminals of Q5 and Q6 and GND. Thus, the amplified output signal Fout of the first-stage emitter follower circuit 11C input to the base terminals of the transistors Q5 and Q6 is differentially amplified and output as the next-stage amplified signal Nout.

  In this case, since the DC offset voltage is applied by the first stage amplifier circuit 11B to the positive phase signal Fout + and the negative phase signal Fout− of the amplified output signal Fout input to the base terminals of Q5 and Q6, these positive phase signals When the amplitudes of the pulses included in the signal Fout + and the negative-phase signal Fout− are smaller than the DC offset voltage, these signals do not cross each other, and as a result, the next-stage amplified signal Nout output from the emitter terminals of Q5 and Q6 does not change. . For this reason, among pulses included in the differential signals Tout + and Tout− input to the differential amplifier circuit 11, a pulse having an amplitude that does not satisfy the reference value corresponding to the DC offset voltage determined by R5 and R6 is removed. Thus, only a pulse having an amplitude greater than or equal to the reference value is output as the next stage amplified signal Nout.

  The current adder circuit 12C has a transistor Q7 (first transistor) whose collector terminal is connected to the collector terminal (positive phase signal Nout +) of the transistor Q5 and a differential pair with the transistor Q7, and the collector terminal of the transistor Q6 The transistor Q8 (second transistor) connected to the collector terminal (reverse phase signal Nout−), and the constant current source I5 (constant current source) connected between the connection point of the emitter terminals of Q7 and Q8 and GND. And a setting voltage Vs connected between the base terminal of Q7 and GND, and an offset adjustment voltage Vos connected externally between the base terminal of Q8 and GND, A DC load current corresponding to the voltage ratio between the voltage Vs and the offset adjustment voltage Vos is applied to the load resistors R9 and R10 of the next stage amplifier circuit 12B. It has a function to be added.

  As shown in FIG. 3, when the DC load current flowing through the load resistors R9 and R10 of the next stage amplifier circuit 12B is increased by the current adding circuit 12C, the positive phase signal Nout + and the negative phase signal Nout− of the next stage amplified signal Nout The DC bias voltage decreases. Since the emitter terminals of Q7 and Q8 are commonly connected to the constant current source I5 and the magnitude of the total current drawn into Q7 and Q8 is constant, the current drawn into each of Q7 and Q8 is the set voltage Vs. Distribution is performed according to a voltage ratio with the offset adjustment voltage Vos. Here, the set voltage Vs is fixed, but instead of the set voltage Vs, an offset adjustment voltage composed of a variable voltage may be input from the outside of the current addition circuit 12C.

  The next-stage emitter follower circuit 12D includes transistors Q9 and Q10 whose emitter terminals are connected to Vcc, and constant current sources I5 and I6 connected between the collector terminals of these Q9 and Q10 and GND, respectively. The positive phase signal Nout + and the negative phase signal Nout− from the next stage amplifier circuit 12B input to the base terminals of Q9 and Q10, respectively, are used as a current addition output signal Aout composed of the positive phase signal Aout + and the negative phase signal Aout−. Each has a function of outputting with low impedance.

  The comparator 13 has MOSFETs M1 and M2 forming a differential pair each having a drain terminal connected to Vcc and the gate terminals connected to each other, a positive phase signal Aout + input to the gate terminal, and a source terminal having a drain terminal M1 And a MOSFET M3 connected to the gate terminals of M1 and M2, a reverse phase signal Aout− input to the gate terminal, a MOSFET M4 whose drain terminal is connected to the source terminal of M2, and a connection point between the source terminals of M3 and M4 A voltage comparison circuit composed of a constant current source I8 connected to GND, and a positive phase signal Aout + and a negative phase signal Aout− output from the next-stage emitter follower circuit 12D of the differential amplifier circuit 11 The voltage values are compared, and a single-phase comparison output signal Cout indicating the comparison result is output from the drain terminal of M4. It has a function.

  Here, the case where the so-called BiCMOS circuit technology in which the differential amplifier circuit 11 and the differential current adder circuit 12 are configured by bipolar transistors and the comparator 13 is configured by CMOSFET has been described as an example, but the present invention is not limited thereto. It is not a thing. For example, some or all of the bipolar transistors included in the differential amplifier circuit 11 and the differential current adding circuit 12 may be configured by MOSFETs, and some or all of the CMOSFETs included in the comparator 13 are configured by bipolar transistors. May be.

The holding circuit 14 includes a diode Dh that rectifies each pulse included in the comparison output signal Cout output from the comparator 13, a holding capacitor Ch that charges these pulses rectified by the diode Dh, and a direct current obtained by charging. And a discharge resistor Rd for discharging the holding voltage Vhd.
Specifically, in the diode Dh, the anode terminal is connected to the output terminal of the comparator 13 and the cathode terminal is connected to one end of the holding capacitor Ch. The other end of the holding capacitor Ch is connected to the ground potential GND. The diode Dh may be a diode-connected NPN transistor.

  As a result, among the pulses included in the comparison output signal Cout output from the comparator 13, only the pulse higher than the holding voltage Vhd of the holding capacitor Ch by the diode junction voltage is extracted by the diode Dh and charged to the holding capacitor Ch. Is done.

  Further, a discharge resistor Rd is connected in parallel to the holding capacitor Ch, and the holding voltage Vhd charged in the holding capacitor Ch is naturally discharged via the discharge resistor Rd. As a result, when the optical signal Pin is in a signal disconnection state, Vhd is discharged, so that the optical signal detection signal SD / LOS indicating the signal disconnection of the optical signal Pin is autonomously output. Regarding the time constant determined by the holding capacitor Ch and the discharge resistor Rd, the response speed for detecting the head of the burst signal input as the differential signals Tout + and Tout− and the same sign continuous section included in the burst signal are expressed as follows. It is determined in consideration of the signal interruption and the same sign continuity tolerance that is not erroneously determined.

The hysteresis comparator circuit 15 is composed of, for example, a positive feedback circuit of an operational amplifier OP, and an input resistor Rs that inputs the comparison output signal Cout to the positive phase input terminal of OP, and a feedback that connects the positive phase input terminal and output terminal of OP. And a resistor Rf. In addition, a sensitivity adjustment voltage Vsens for determining two determination threshold voltages Vth_SD and Vth_LOS used for determining whether or not an optical signal is input is connected to the negative phase input terminal of OP.
The OP output terminal is connected to the gate terminal of the MOSFET Mout. The source terminal of Mout is connected to the ground potential GND, and the drain terminal is connected to the power supply potential Vcc via the resistance element RL, and SD / LOS is output from this drain terminal.

[Operation of First Embodiment]
Next, the operation of the optical signal detection circuit 10 according to the present exemplary embodiment will be described with reference to FIGS.

  The differential signal Tout output from the previous stage circuit such as LT or the transimpedance amplifier TIA is input to the differential amplifier circuit 11, and the difference between the first stage amplifier circuit 11B via the coupling capacitors C1 and C2 of the first stage bias circuit 11A. Dynamically amplified.

  At this time, it is desirable that the differential signal Tout passes through C1 and C2, and then the DC level is preferably matched between the positive phase and the negative phase. Then, there is a risk of including a new DC offset voltage due to variations in the resistance value of the bleeder resistance. Therefore, in this example, in the first stage bias circuit 11A, a DC bias voltage is applied by one bleeder resistor R1-R2. R11 and R12 are desirably sufficiently larger than R1 and R2 in consideration of signal attenuation of the differential signal Tout.

The amplified output signal Fout obtained by the first stage amplifier circuit 11B is input to the differential current adder circuit 12 via the first stage emitter follower circuit 11C, and then connected to the next stage via the coupling capacitors C3 and C4 of the next stage bias circuit 12A. Differential amplification is performed by the amplifier circuit 12B.
Similarly to the first-stage bias circuit 11A, the next-stage bias circuit 12A is preferably connected by AC coupling while applying a DC bias voltage by one bleeder resistor R3-R4. As a result, the DC offset voltage generated in the amplified output signal Fout is removed from the variation of the transistors and the resistance elements in the amplification process of the differential amplifier circuit 11.

  The DC bias voltage of each of the positive phase signal Nout + and the negative phase signal Nout− of the next stage amplified signal Nout obtained by the next stage amplifier circuit 12B is adjusted by the current adding circuit 12C. The DC offset voltages of the positive phase signal Nout + and the negative phase signal Nout− are closely related to the amplitude-voltage conversion characteristics between the amplitude of the differential signal Tout and the holding voltage Vhd shown in FIG. 5A described later.

  In the current addition circuit 12C, a DC bias voltage is applied to either the positive phase signal or the negative phase signal of the next stage amplification signal Nout. In this example, the positive phase side is fixed at the set voltage Vs (Q7), and the offset adjustment voltage Vos lower than Vs is given to the negative phase side by an external power source. Thereby, the direct current level of the negative phase signal Nout− becomes lower than the direct current level of the positive phase signal Nout +, and the overlapping state of these two signals changes. This difference is adjusted by the magnitude of the difference between Vs and the offset adjustment voltage Vos. This difference is not variable and may be fixed. Further, Vs and Vos may be given by dividing the power supply potential Vcc by bleeder resistors having different voltage dividing ratios.

In the current addition circuit 12C, the next-stage amplified signal Nout to which the DC offset voltage is applied is input to the next-stage emitter follower circuit 12D and input to the comparator 13 as the current addition output signal Aout.
The comparator 13 detects a crossing period of the current addition output signal Aout, and outputs a comparison output signal Cout having a pulse corresponding to the crossing period from the comparator 13 to the holding circuit 14.

Here, when the amplitudes of the positive-phase signal Aout + and the negative-phase signal Aout− are sufficiently large, the signals cross each other, and the comparator 13 detects the crossing period. Does not cross, and the comparator 13 does not detect the crossing period. Therefore, the holding voltage Vhd of the holding circuit 14 changes according to the amplitude of the differential signal Tout.
On the other hand, when the offset adjustment voltage Vos is adjusted to adjust the DC bias of the positive phase signal Aout + and the negative phase signal Aout−, the overlapping state of both signals changes, and the crossing period of both signals changes. Therefore, the amplitude-voltage conversion characteristic when converting the amplitude of the differential signal Tout to the holding voltage Vhd can be adjusted by the offset adjustment voltage Vos.

The holding voltage Vhd held by the holding circuit 14 is compared with determination threshold voltages Vth_SD and Vth_LOS determined by the sensitivity adjustment voltage Vsens by the hysteresis comparator circuit 15. Here, when Vhd> Vth_SD, that is,
Vsens <Rf · Vhd / (Rf + Rs)
At this time, the optical signal detection signal SD / LOS from the hysteresis comparator circuit 15 becomes the Low level and displays the signal reception (SD).
When Vhd <Vth_LOS, that is,
Vsens> Rs · (Vcc−Vhd) / (Rf + Rs) + Vhd
When it becomes, SD / LOS becomes High level and displays a signal loss (LOS).

Here, the determination threshold voltages Vth_SD and Vth_LOS are determined by Vsens, Rf, Rs, and Vcc. Therefore, if Rf, Rs, and Vcc are fixed values, Vth_SD and Vth_LOS are determined by Vsens.
Therefore, if the sensitivity adjustment voltage Vsens changes, the DC voltage levels of the determination threshold voltages Vth_SD and Vth_LOS change and the SD / LOS determination changes. Therefore, the detection sensitivity of the presence / absence of an optical signal is adjusted by the sensitivity adjustment voltage Vsens. can do.

FIG. 4 is an example of a circuit simulation result according to the first embodiment.
In this circuit simulation, Vs−Vos = 0.5V was set, and Vsens was 1.2V. The bit rate of the differential signal Tout input to the optical signal detection circuit 10 is 10 Gbps, the amplitude (single phase) is changed in the range of 3 mV to 40 mV, and signals of main nodes are observed. Note that Vcc = 3.3 V, and a 4.7 kΩ pull-up resistor was connected to the output terminal of the optical signal detection signal SD / LOS.

In this example, LOS is displayed when the input amplitude of the differential signal Tout is about 4 mV or less, and SD is displayed at 12 mV. Here, when the transimpedance Zt of TIA is 2 kΩ, the conversion efficiency η of the avalanche photodiode (APD) is 0.85 A / W, the gain coefficient M is 7, and the extinction ratio ER of the input optical signal is 6. Input signal amplitudes of 4 mV and 12 mV correspond to optical outputs of approximately -35.5 dBm and -30.5 dBm, respectively.
Since the minimum light sensitivity (minimum light output that must be received) defined in the 10G-EPON standard is -28 dBm, the area is sufficiently darker than the minimum light sensitivity, and sufficient hysteresis (generally about It can be seen that LOS and SD are displayed.

  As described above, according to this embodiment, it is possible to detect reception and disappearance of extremely weak signals without chattering even in high-speed communication of 10 Gbps. Note that the holding voltage Vhd of the holding circuit 14 tends to saturate when the input amplitude of the differential signal Tout increases, but the determination threshold for SD display should be set to −28 dBm or less. Don't be. In this calculation example, when the bit rate is 10 Gbps, it corresponds to −28 dBm with an amplitude of about 20 mV.

[Effect of the first embodiment]
Thus, in the present embodiment, the differential amplifier circuit 11 differentially amplifies the differential signal Tout input via the coupling capacitors C1 and C2, and the positive phase signal of the obtained amplified output signal Fout and The differential current adding circuit 12 adjusts the DC offset voltage of the positive phase signal and the negative phase signal by adding the DC current corresponding to the input offset adjustment voltage Vos to the negative phase signal. The comparator 13 compares the voltage values of the positive phase signal and the negative phase signal of the current addition output signal Aout, and the holding circuit 14 holds the obtained comparison output signal Cout as the DC holding voltage Vhd. The hysteresis comparator circuit 15 However, the holding voltage Vhd is determined by the input sensitivity adjustment voltage Vsens, and two different determination threshold voltages Vth_SD and Vth_LO. Compared with, in which to output the comparison result as an optical signal detection signal SD / LOS showing input the presence or absence of an optical signal.

FIG. 5A is an explanatory diagram showing adjustment of amplitude-voltage conversion characteristics by an offset adjustment voltage, and FIG. 5B is an explanatory diagram showing detection sensitivity adjustment by a sensitivity adjustment voltage.
The amplitude of the differential signal Tout input to the optical signal detection circuit 10 changes due to a change in temperature, a change in power supply potential, or the like. Also in the differential amplifier circuit 11, the amplification factor changes due to the influence of temperature change, power supply potential change, etc., so the amplitudes of the amplified output signals Fout and Nout also change. Since such an amplitude change results in a change in the holding voltage Vhd, in the present embodiment, the differential current adding circuit 12 changes the amplitude-voltage conversion characteristics between the amplitude of the differential signal Tout and the holding voltage Vhd. It is adjusting.

  In the adjustment by the offset adjustment voltage Vos in the differential current addition circuit 12, as shown in FIG. 5A, the slope is changed in the amplitude-voltage conversion characteristic. In this case, the crossing position with Vth_SD or Vth_LOS changes according to the change in the slope of the amplitude-voltage conversion characteristic, which contributes to the adjustment of the detection sensitivity of the optical signal. However, since the slope of the amplitude-voltage conversion characteristic changes, the voltage width of the input amplitude with respect to Vth_SD and Vth_LOS changes.

For example, in the characteristic 51, the voltage width of the input amplitude with respect to Vth_SD and Vth_LOS is ΔV1 from V_LOS1 to V_SD1, but in the characteristic 52, the slope is smaller than that of the characteristic 51. Become.
Therefore, even if the characteristic 51 and the characteristic 52 have the same amplitude change width ΔV of the differential signal Tout, the results of the SD / LOS determination are different. For this reason, it is difficult to adjust the amplitude-voltage conversion characteristics and the optical signal detection sensitivity to good values at the same time only by adjustment using the offset adjustment voltage Vos.

  On the other hand, in the adjustment by the sensitivity adjustment voltage Vsens in the hysteresis comparator circuit 15, as shown in FIG. 5B, the gradient of the amplitude-voltage conversion characteristic does not change, and only the voltage values of Vth_SD and Vth_LOS are changed. In this case, since the voltage values of Vth_SD and Vth_LOS are determined by Vsens, Rf, Rs, and Vcc as described above, these voltage differences ΔVth are substantially constant although they are affected by fluctuations in Vcc.

  Thus, if the amplitude-voltage conversion characteristic is specified as a certain characteristic 53 by adjustment by the offset adjustment voltage Vos in the differential current addition circuit 12, the sensitivity adjustment voltage Vsens is changed, and the voltage values of Vth_SD and Vth_LOS are changed. Even if the adjustment is performed, the input amplitude from V_LOS3 to V_SD3 with respect to Vth_SD and Vth_LOS is constant at the voltage width ΔV3. For this reason, when the amplitude change width of the differential signal Tout is the same, the same determination result is obtained in the SD / LOS determination.

  Therefore, according to the present embodiment, in the differential current adding circuit 12, the amplitude-voltage conversion characteristic when the amplitude of the differential signal Tout is converted into the holding voltage Vhd can be adjusted by the offset adjustment voltage Vos. . In addition to the adjustment of the amplitude-voltage conversion characteristic, the hysteresis comparator circuit 15 can adjust the detection sensitivity of the presence or absence of an optical signal by the sensitivity adjustment voltage Vsens. Therefore, the linearity of temperature, power supply potential, and detection sensitivity can be increased, and the detection sensitivity of the optical signal in the optical signal detection circuit 10 can be adjusted with high accuracy.

  Further, in the present embodiment, the collector terminal of the differential current adding circuit 12 is connected to one end of the first load resistor R9 used for amplifying the positive phase signal Aout + of the current added output signal Aout and offset to the base terminal. A first transistor Q7 to which the adjustment voltage Vos is input, and a second load resistor that forms a differential pair with the first transistor and whose collector terminal is used to amplify the negative-phase signal Aout− of the current addition output signal Aout. The second transistor Q8 connected to one end of R10 and having the base terminal supplied with the offset adjustment voltage Vos, and the constant current source I5 connected to the connection point of the emitter terminals of the first and second transistors Q7 and Q8. Are provided.

  Thereby, the DC bias voltages of the positive phase signal Aout + and the negative phase signal Aout− can be changed linearly with respect to the offset adjustment voltage Vos. Further, only the DC bias voltage can be adjusted by this offset adjustment voltage Vos without changing the amplitudes of the positive phase signal Aout + and the negative phase signal Aout−. For this reason, when automatically adjusting from the outside according to the temperature and the power supply potential, it is possible to accurately adjust the DC bias of the positive phase signal Aout + and the negative phase signal Aout−.

  In this embodiment, the hysteresis comparator circuit 15 has a negative phase input terminal connected to the sensitivity adjustment voltage Vsens, a positive phase input terminal connected to the holding voltage Vhd via the input resistor Rs, and an output terminal fed back. Since the operational amplifier OP is connected to the positive-phase input terminal via the resistor Rf, Vth_SD and Vth_LOS, which are determined by the sensitivity adjustment voltage Vsens and have a substantially constant voltage difference ΔVth with a very simple circuit configuration, The holding voltage Vhd can be compared and determined.

[Second Embodiment]
Next, an optical signal detection circuit 10 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram illustrating a configuration of an optical signal detection circuit according to the second embodiment.

  In the PON system, a system that receives a burst of data signals having different bit rates (transmission speeds) has been studied. For example, when receiving data of 1 Gbps and 10 Gbps, the transimpedance Zt of the TIA is switched according to the reception bit rate from the relationship between the band and the noise, and 1 Gbps is larger than 10 Gbps. This indicates that even when signals having the same optical output are received, the electric signal amplitude input to LA is larger at 1 Gbps. Therefore, it is desirable to switch the detection sensitivity of the optical signal detection circuit 10 in accordance with the switching of the reception bit rate.

  The optical signal detection circuit 10 according to this embodiment shown in FIG. 6 is an example in which a sensitivity switching function is mounted in addition to the configuration of FIG. That is, in the optical signal detection circuit 10 according to the present embodiment, the selector circuit SEL is connected to the differential current addition circuit 12. Two offset adjustment voltages of Vos_10G and Vos_1G having different voltage values are input to this SEL. Of these, Vos_10G is an offset adjustment voltage used when the reception bit rate is 10 Gbps as in 10G-EPON, and Vos_1G is an offset adjustment voltage used when the reception bit rate is 1 Gbps as in GE-PON. .

  Therefore, one of Vos_10G and Vos_1G is selected by the transmission speed selection signal RS (Rate Select) corresponding to the reception bit rate, and is input to the differential current addition circuit 12. For this reason, if Vos_10G and Vos_1G are set in advance, even if the reception bit rate is switched, the same reception sensitivity can be realized with respect to the received light intensity. In the PON system, the transmission speed selection signal RS is generated and output by the PON control LSI. This is because, in the PON system, it is possible to grasp which subscriber transmits data to be received next.

  For example, when 1G Zt is four times larger than 10G Zt, the TIA output signal amplitude is four times larger even with the same optical power input. On the other hand, since the determination threshold value in operation corresponds to the optical power, it is necessary to determine LOS / SD with the same optical power for both 1G and 10G. Since the present invention makes a determination based on the amplitude after being converted into an electric signal, in this example, the sensitivity needs to be ¼ at 1G. In the present embodiment, such adjustment is realized by switching the offset adjustment voltage Vos in accordance with the transmission speed. In the third embodiment to be described later, such adjustment is realized by switching the sensitivity adjustment voltage Vsens according to the transmission speed.

[Third Embodiment]
Next, an optical signal detection circuit 10 according to a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram illustrating a configuration of an optical signal detection circuit according to the third embodiment.

  The optical signal detection circuit 10 according to the present exemplary embodiment shown in FIG. 7 uses the hysteresis comparator circuit 15 instead of DC offset adjustment switching as the sensitivity adjustment switching means corresponding to the reception bit rate in the configuration of FIG. This is an example applied to switching of the sensitivity adjustment voltage Vsens. The selector circuit SEL that is switched by the transmission speed selection signal RS is connected to the hysteresis comparator circuit 15, and the sensitivity adjustment voltage Vsens in FIG. 1 can be switched to Vsens_10G or Vsens_1G according to the reception bit rate.

  The object and effect according to the present embodiment are the same as those of the second embodiment. Therefore, by combining the second embodiment and the third embodiment, both the offset adjustment voltage Vos and the sensitivity adjustment voltage Vsens may be switched by the transmission speed selection signal RS, and the amplitude-voltage conversion characteristics. Even when the dynamic range is narrow, the linearity of the temperature, the power supply potential, and the detection sensitivity can be increased, and the detection sensitivity of the optical signal in the optical signal detection circuit 10 can be accurately adjusted.

[Fourth Embodiment]
Next, with reference to FIG. 8, an optical signal detection circuit 10 according to a fourth embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of an optical signal detection circuit according to the fourth embodiment.

  This embodiment is an example in which the output of the holding circuit 14 and the hysteresis comparator circuit 15 are connected via the voltage follower circuit 16 to the first to third embodiments. Specifically, the holding voltage Vhd of the holding circuit 14 is input to the positive-phase input terminal of the operational amplifier, and the impedance-converted holding voltage Vhd is output from the output terminal that is the negative-phase input terminal of the operational amplifier. 15 is input.

When the voltage follower circuit 16 is not passed, current flows through Rs and Rf constituting the hysteresis comparator circuit 15, and if Rs and Rf are small, the discharge characteristics of the holding circuit 14 are affected. It needs to be bigger.
According to the present embodiment, by connecting the holding circuit 14 and the hysteresis comparator circuit 15 via the voltage follower circuit 16, it is possible to convert the impedance and accurately transmit the holding circuit output value to the hysteresis comparator circuit 15. It becomes possible. However, since an operational amplifier is used, a delay due to the slew rate is added, so that the response speed becomes slow.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.
In each of the above embodiments, a circuit using a BiCMOS process has been described as an example. However, the present invention is not limited to this, and a CMOS circuit may be used.

  DESCRIPTION OF SYMBOLS 100 ... Optical receiver, PD ... Photodiode, TIA ... Transimpedance amplifier, LA ... Limiting amplifier, EF ... Emitter follower circuit, MA ... Differential amplifier, 10 ... Optical signal detection circuit, 11 ... Differential amplification circuit, 11A 1st stage bias circuit, 11B ... 1st stage amplifier circuit, 11C ... 1st stage emitter follower circuit, 12 ... Differential current addition circuit, 12A ... Next stage bias circuit, 12B ... Next stage amplification circuit, 12C ... Current addition circuit, 12D ... Next stage Emitter-follower circuit, 13 ... comparator, 14 ... holding circuit, 15 ... hysteresis comparator circuit, 16 ... voltage follower circuit, Q1-Q10, Qout ... transistor, R1-R14, RL ... resistance element, C1, C2, C3, C4 ... Coupling capacitors, M1 to M4 ... MOSFETs, Dh ... diodes, Ch ... Holding capacitor, Rd ... discharge resistor, Rs ... input resistor, Rf ... feedback resistor, I1-I8 ... constant current source, Pin ... optical signal, Iin ... photocurrent signal, Tout ... differential signal, Fout ... amplified output signal, Nout ... Next stage amplified signal, Aout ... Current addition output signal, Cout ... Comparison output signal, SD / LOS ... Optical signal detection signal, Rout ... Reception output signal, Vcc ... Power supply potential, GND ... Ground potential, Vs ... Setting voltage, Vos ... offset adjustment voltage, Vhd ... holding voltage, Vsens ... sensitivity adjustment voltage.

Claims (6)

An optical signal detection circuit that detects the presence or absence of an input of the optical signal based on a differential signal obtained by photoelectric conversion of the optical signal,
A differential amplifier that differentially amplifies the differential signal input via a coupling capacitor and outputs the amplified signal as an amplified output signal;
By adding a direct current corresponding to the input offset adjustment voltage to the positive phase signal and the negative phase signal of the amplified output signal, the direct current offset voltage of the positive phase signal and the negative phase signal is adjusted, and the current A differential current addition circuit that outputs as an addition output signal;
A comparator that compares the voltage value of the positive phase signal and the negative phase signal of the current addition output signal, and outputs the comparison result as a comparison output signal;
A holding circuit that rectifies the comparison output signal and charges it with a holding capacitor, and discharges a DC holding voltage obtained by charging with a discharge resistor;
A hysteresis comparator circuit that compares the holding voltage with two different determination threshold voltages determined by the input sensitivity adjustment voltage and outputs the comparison result as an optical signal detection signal indicating whether or not the optical signal is input; An optical signal detection circuit comprising: The optical signal detection circuit according to claim 1.
In the current adding circuit, a collector terminal is connected to one end of a first load resistor used for amplification of the positive phase signal of the amplified output signal, and a set voltage value from a set voltage source is input to a base terminal. 1 transistor and a differential pair with the first transistor, the collector terminal is connected to one end of a second load resistor used for amplification of the negative phase signal of the amplified output signal, and the adjustment is made at the base terminal An optical signal detection circuit comprising: a second transistor to which a voltage value is input; and a constant current source connected to a connection point between the emitter terminals of the first and second transistors. The optical signal detection circuit according to claim 1 or 2,
The hysteresis comparator circuit has a negative phase input terminal connected to the sensitivity adjustment voltage, a positive phase input terminal connected to the holding voltage via an input resistor, and an output terminal connected to the positive phase input terminal via a feedback resistor. An optical signal detection circuit comprising a connected operational amplifier. In the optical signal detection circuit according to any one of claims 1 to 3,
In response to a transmission rate selection signal indicating the transmission rate of the optical signal, one of the offset adjustment voltages having a voltage value corresponding to the transmission rate is selected and the differential current is added. An optical signal detection circuit further comprising an offset adjustment voltage selector circuit to be input to the circuit. In the optical signal detection circuit according to any one of claims 1 to 4,
In response to a transmission speed selection signal indicating the transmission speed of the optical signal, one of the sensitivity adjustment voltages having a voltage value corresponding to the transmission speed is selected and sent to the hysteresis comparator circuit. An optical signal detection circuit further comprising a sensitivity adjustment voltage selector circuit for input. In the optical signal detection circuit according to any one of claims 1 to 5,
A voltage follower circuit that takes the holding voltage of the holding circuit as an input, converts the holding voltage into impedance, and outputs the converted voltage;
The hysteresis comparator circuit compares the holding voltage after impedance conversion obtained by the voltage follower circuit with the sensitivity adjustment voltage instead of the holding voltage from the holding circuit. .

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