JP2013250593A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power consumption while maintaining the performance of a semiconductor for performing dynamic branch prediction using a branch history table.SOLUTION: An instruction processing part for processing the fetch and execution of an instruction including a condition branch instruction executes a fixing instruction to instruct the fixing of a branch prediction direction showing either "branched" or "not branched". With respect to a condition branch instruction after the fixing instruction is executed, the instruction processing part executes branch prediction in the branch prediction direction instructed by the fixing instruction without referring to a branch history table BHT (S120 to S122).

Description

  The present invention relates to a semiconductor device, for example, a processor that performs branch prediction.

  In a pipeline processor, in order to maintain the effect of pipeline processing as much as possible and to improve performance, prediction of whether or not a conditional branch instruction branches in the flow of program execution (Take or Not-Take), So-called “branch prediction” is performed (Patent Documents 1 to 5).

  There are various branch prediction methods. For example, as disclosed in paragraph [0005] of Patent Document 2, a technique using a branch history table (BHT) is known as one of dynamic branch prediction methods.

  In the technique, when executing a conditional branch instruction, branch prediction is performed by referring to the history stored in the branch history table, and learning is performed by updating the branch history table based on the execution result of the conditional branch instruction. .

  In addition, among existing processors, there are some which can disable the function by a control register while the function is mounted. This processor performs dynamic branch prediction using a branch history table when the function is enabled, and for all conditional branch instructions when the function is disabled, Predicted that it will not branch).

JP 2010-079841 A JP 2009-048633 A JP 2007-058875 A JP 2001-142705 A Japanese Patent Laid-Open No. 08-249181

  In recent years, a semiconductor device provided with a processor has followed a diagram of high functionality and multi-functionality, which inevitably increases power consumption. Against this background, semiconductor device developers are struggling to reduce power consumption while maintaining functionality.

  Since a processor that performs dynamic branch prediction using a branch history table refers to the branch history table every time a conditional branch instruction is executed, a read to the branch history table always occurs. In addition, when the branch history table is updated based on the execution result of the conditional branch instruction, writing to the branch history table also occurs. For example, in the case of 1-bit learning, a write to the branch history table occurs only when the branch prediction is unsuccessful, and in the case of 2-bit learning, the branch is performed both when the branch prediction is successful and when it is failed. A write to the history table occurs.

  The branch history table is configured by a memory. Access to the memory that is the branch history table for each conditional branch instruction is one factor in increasing the power consumption of the processor.

  On the other hand, if the function of dynamic branch prediction using the branch history table is disabled, not-taken branch prediction is always performed, so access to the branch history table can be eliminated, but the processor performance is reduced. descend.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment performs processing including fetch and execution of an instruction, performs an instruction processing unit that performs branch prediction when executing a conditional branch instruction, and history of whether or not a branch has occurred as a result of execution of the conditional branch instruction And a branch history table updated by the instruction processing unit.

  The instruction processing unit can execute a fixed instruction instructing fixing in a branch prediction direction indicating either “branch” or “not branch”.

  The instruction execution unit performs a dynamic branch for performing branch prediction with respect to the conditional branch instruction with reference to the history stored in the branch history table. After executing the fixed instruction, the instruction processing unit performs a fixed prediction for performing a branch prediction in a branch prediction direction indicated by the fixed instruction without referring to the branch history table for the conditional branch instruction.

  Desirably, the instruction processing unit may not update the branch history table based on the execution result of the conditional branch instruction when performing fixed prediction on the conditional branch instruction.

  More preferably, the instruction processing unit may be able to execute a fixed release instruction for releasing the fixation for releasing the fixation of the branch prediction direction indicated by the fixed instruction. After executing the fixed release instruction, the instruction processing unit performs dynamic prediction to perform branch prediction with reference to the history stored in the branch history table for the conditional branch instruction and displays the execution result of the conditional branch instruction. Based on this, the branch history table is updated.

  According to another embodiment, the instruction processing unit is a fixed instruction that is a conditional branch instruction including a fixed instruction indicating that the instruction is fixed in a branch prediction direction indicating either “branch” or “not branch” It is possible to execute an attached branch instruction.

  The instruction processing unit performs fixed prediction on the branch instruction with a fixed instruction without performing a branch prediction in the branch prediction direction indicated by the fixed instruction without referring to the branch history table.

  The instruction processing unit performs dynamic prediction for performing branch prediction with reference to the history stored in the branch history table for a conditional branch instruction that does not include a fixed instruction, and the execution result of the conditional branch instruction. The branch history table is updated based on

  In addition, a representation in which the devices in the above-described or following embodiments are replaced with methods and systems, a program that causes a computer to execute these devices or a part of the devices, and the like are also effective as the embodiments.

  According to the above-described embodiment, it is possible to suppress power consumption while maintaining the performance of a semiconductor device that performs dynamic branch prediction using a branch history table.

It is a figure which shows the semiconductor device for demonstrating the 1st-3rd technique. FIG. 2 is a diagram illustrating an example of a fixed instruction to which an instruction processing unit in the semiconductor device illustrated in FIG. 1 corresponds when the first technique is applied. It is a figure which shows the example of the fixed release command which the command processing part in the semiconductor device shown in FIG. 1 respond | corresponds when the 1st technique is applied. It is a figure which shows the comparative example of the program at the time of applying a 1st technique, and the conventional program. FIG. 3 is a diagram illustrating an example of a flowchart illustrating processing performed by an instruction processing unit in the semiconductor device illustrated in FIG. 1 when the first technique is applied. FIG. 10 is a diagram illustrating an example of a branch instruction with a fixed instruction to which the instruction processing unit in the semiconductor device illustrated in FIG. 1 corresponds when the second technique is applied. It is a figure which shows the example of a program at the time of applying a 1st technique. It is a figure which shows the example of the flowchart which shows the process which the command process part in the semiconductor device shown in FIG. 1 performs when the 2nd technique is applied. It is a figure which shows the example of the flowchart which shows the process which the command process part in the semiconductor device shown in FIG. 1 performs when the 3rd technique is applied. It is a figure which shows the semiconductor device for demonstrating the 4th technique. It is a figure which shows the example of the flowchart which shows the process which the command process part in the semiconductor device shown in FIG. 10 performs. 1 is a diagram illustrating a semiconductor device according to a first embodiment. FIG. 13 is a diagram showing a CPU (Central Processing Unit) in the semiconductor device shown in FIG. 12. It is a figure which shows CPU in the semiconductor device of 3rd Embodiment. It is a figure which shows CPU in the semiconductor device of 4th Embodiment. FIG. 16 is a diagram illustrating a correspondence relationship between an area setting register and a program execution area in the CPU illustrated in FIG. 15.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof, and is not limited to any one. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  Further, the above-described program can be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROM (Read Only Memory) CD-R, CD -R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

Prior to specific embodiments, four techniques applied to the embodiments will be described.
First, the first to third techniques will be described with reference to the semiconductor device 10 shown in FIG.

  The semiconductor device 10 has a microcomputer constituted by a single semiconductor chip. For example, the semiconductor device 10 has an external terminal electrically connected to the semiconductor chip, and takes the form of a semiconductor package in which the semiconductor chip is sealed with resin and the external terminal is exposed. The microcomputer includes an instruction processing unit 12 and a branch history table 14, and executes an instruction sequence constituting a program by pipeline processing.

  The instruction processing unit 12 performs processing including instruction fetch and execution, and performs branch prediction when executing a conditional branch instruction.

  The branch history table 14 is used to store a history of whether or not a branch has occurred as a result of execution of a conditional branch instruction, and is updated by the instruction processing unit 12.

<First technology>
In the first technique, the instruction processing unit 12 is configured to be able to execute a fixed instruction and a fixed release instruction.
The fixed instruction is an instruction that instructs the branch prediction direction to be fixed to one of “branch” (Taken) and “not branch” (Not-Taken).

  The instruction processing unit 12 performs a dynamic branch for performing a branch prediction with reference to the history stored in the branch history table for a conditional branch instruction. Dynamic prediction means that branch prediction is performed with reference to the history stored in the branch history table 14.

  The instruction processing unit 12 performs fixed prediction on the conditional branch instruction after executing the fixed instruction. “Fixed prediction” refers to branch prediction in a branch prediction direction designated by a fixed instruction without referring to the branch history table 14 for a conditional branch instruction. Further, the instruction processing unit 12 does not update the branch history table 14 after the execution of the conditional branch instruction that is the target of fixed prediction.

  After executing the fixed release instruction, the instruction processing unit 12 performs dynamic prediction on the conditional branch instruction and updates the branch history table 14 based on the execution result of the conditional branch instruction.

  Regarding the update of the branch history table 14 after execution of the conditional branch instruction for which dynamic prediction has been performed, the instruction processing unit 12 has, for example, 1 bit as in a conventional processor that performs dynamic branch prediction using a branch history table. In the case of learning, the branch history table 14 is updated only when the branch prediction is a mistake, and in the case of 2-bit learning, the branch history table is obtained both when the branch prediction is correct and when it is a mistake. 14 is updated.

  FIG. 2 shows an example of the format of a fixed instruction. In this example, the instruction length is 16 bits. As shown in the figure, there are two types of fixed instructions: a fixed instruction bptf shown at the top and a fixed instruction bpnf shown at the bottom.

  In the fixed instruction bptf, “10101111111100” in the upper 14 bits indicates that the instruction is a fixed instruction or a fixed release instruction, and “00” in the lower 2 bits indicates that the instruction “branches” the branch prediction direction ( Taken) indicates that the instruction is fixed.

  In the fixed instruction bpnf, “10101111111100” in the upper 14 bits indicates that the instruction is a fixed instruction or a fixed release instruction, and “01” in the lower 2 bits indicates that the instruction does not branch the branch prediction direction. "(Not-Taken)" indicates that the instruction is a fixed instruction for fixing.

  FIG. 3 shows an example of a fixed release instruction corresponding to the fixed instruction shown in FIG. As shown in the figure, in the fixed release instruction bpr, the upper 14 bits “10101111111100” indicates that the instruction is a fixed instruction or fixed release instruction, and the lower 2 bits “10” indicates that the instruction is immediately before Indicates that it is a fixed release command corresponding to the fixed command that was present.

  After executing the fixed instruction, the instruction processing unit 12 always performs fixed prediction on the conditional branch instruction until the fixed release instruction is executed. By executing the fixed release instruction, the instruction processing unit 12 releases the conditional branch based on the fixed prediction, and performs dynamic prediction on the conditional branch instruction executed after the fixed release instruction.

  FIG. 4 shows an example of a conventional program that executes a loop process (FIG. 4 left) and a program that executes the loop process with a program including a fixed instruction and a fixed release instruction (right side of FIG. 4). The loop processing in this example is processing for initializing an area starting from 0C000000 for 4 × 1000 bytes. “mov” indicates a transfer command, and the first three mov commands perform initialization of loop processing. The first mov instruction indicates the number of bytes to be initialized (1000), the second mov instruction indicates the initial value (11223344), the third mov instruction indicates the start address (0C000000) of the area to be initialized, and the register r0. , R1 and r2. In the loop, “mov” is a transfer instruction for transferring the value of the register r1 to the address address specified by the value of the register r2. “add” is an addition instruction for adding 4 to the value of the register r2. “dt” is an instruction that sets a specific flag to 1 when the value of the register R0 is decremented to zero, and sets to 0 otherwise. “bf” is a branch instruction that branches to a Loop when the specific flag indicates 0, and becomes a NOP (No operation) without branching when the flag is 1.

  When a processor having a branch prediction function using a branch history table executes the conventional program shown in the left part of FIG. 4, the loop is repeated or the loop is exited (normal end) at the end of each loop. Do branch prediction. For this reason, access (read) to the branch history table occurs by the sum (1000 times) of the number of times the loop is repeated and the last branch of the loop execution (normal end of the loop). In the case of 2-bit learning, whether the branch prediction is correct or incorrect, access (write) to the branch history table occurs after the branch prediction, and in the case of 1-bit learning, the branch prediction is incorrect. In addition, access (write) to the branch history table occurs after branch prediction.

  By the way, in the case of a program that performs loop processing, the program creator knows that the loop is repeated except for the last branch of the loop execution. Therefore, as shown in the right part of FIG. 4, by inserting a fixed instruction bptf prior to loop processing, the subsequent branch prediction direction is fixed to “branch prediction”, and after the normal termination of the loop, the fixation is released. By inserting the instruction bpr, a program can be created so as to release the fixed branch prediction direction by the fixed instruction bptf.

  FIG. 5 shows an example of a flowchart of program execution by the instruction processing unit 12. As shown in the figure, when there is no fixed instruction (S100: Yes), or when there is a fixed instruction but there is a fixed release instruction (S100: Yes, S114: Yes), the instruction processing unit 12 Dynamic prediction is performed for conditional branch instructions. Specifically, for the conditional branch instruction, branch prediction is performed with reference to the branch history table 14, and after execution of the conditional branch instruction, the branch history table 14 is updated based on the execution result (S102: Yes). , S106, S108, S110, S112).

  In the case of the conventional program shown in the left part of FIG. 4, the processing of step S102 to step S112 is performed.

  On the other hand, after the fixed instruction and before the fixed release instruction (S100: Yes, S114: No), the instruction processing unit 12 performs fixed prediction on the conditional branch instruction. Specifically, for a conditional branch instruction, branch prediction is performed in the branch prediction direction (Taken or Not-Take) indicated by the fixed instruction without referring to the branch history table 14, and after execution of the conditional branch instruction Does not update the branch history table 14 regardless of the execution result (S116: Yes, S120, S122).

  In the case of the program shown in the right part of FIG. 4, the instruction processing unit 12 performs branch prediction on a branch (Taken) for repeating the loop until the loop ends normally. Therefore, the prediction is incorrect at the last branch (1000th) of the loop execution, but all other (999) branch predictions are correct.

  Note that branch instructions are not predicted for instructions other than conditional branch instructions, and the instruction processing unit 12 fetches and executes these instructions in the same manner as a normal processor (S102: No, S104) (S116: No, S118).

  In the first technique, when the instruction processing unit 12 corresponds to a fixed instruction and a fixed release instruction and performs branch prediction on a conditional branch instruction positioned between the fixed instruction and the fixed release instruction, the branch history table 14 The branch history table 14 is not updated based on the execution result of the conditional branch instruction, while the branch prediction is always performed in the branch prediction direction indicated by the fixed instruction without referring to. Therefore, in the case of a program such as a loop that is known in advance as to whether or not to branch, the instruction creator 12 can be caused to make a fixed prediction by inserting a fixed instruction by the program creator. In the case of fixed prediction, since access to the branch history table 14 does not occur, the power consumption of the semiconductor device 10 can be suppressed.

  Further, by using the fixed release instruction in pair with the fixed instruction, it is possible to avoid that the instruction processing unit 12 always performs the fixed prediction after the fixed instruction. Therefore, in the case of a conditional branch instruction that does not know whether or not to branch, normal dynamic branch prediction that accompanies access to the branch history table can be performed, thereby preventing performance degradation of the semiconductor device. Can do.

<Second technology>
In the second technique, the instruction processing unit 12 is configured to be able to process a branch instruction with a fixed instruction.
The branch instruction with a fixed instruction is a conditional branch instruction including a fixed instruction indicating that the instruction is fixed in a branch prediction direction indicating either “branch” or “not branch”.

  The instruction processing unit 12 performs fixed prediction on a branch instruction with a fixed instruction. Here, fixed prediction refers to the branch prediction direction indicated by the fixed instruction included in the branch instruction with fixed instructions without referring to the branch history table 14 for the conditional branch instruction (branch instruction with fixed instructions). This means branch prediction. Further, the instruction processing unit 12 does not update the branch history table 14 after executing the conditional branch instruction included in the branch instruction with a fixed instruction.

  For a normal conditional branch instruction that does not include a fixed instruction, the instruction processing unit 12 performs dynamic prediction that performs branch prediction with reference to the history stored in the branch history table 14. Along with the dynamic prediction, the instruction processing unit 12 updates the branch history table 14 based on the execution result after execution of the conditional branch instruction.

  FIG. 5 shows an example of the format of a branch instruction with a fixed instruction. In this example, the instruction length is 16 bits. As shown in the figure, there are four types of branch instructions with fixed instructions, from top to bottom: a branch instruction with fixed instructions bpt, a branch instruction with fixed instructions bpft, a branch instruction with fixed instructions bptf, and a branch instruction with fixed instructions bpff. is there.

  In any of these four types of branch instructions with fixed instructions, “1010111111110” in the upper 13 bits indicates that the instruction is a branch instruction with fixed instructions. The upper 1 bit among the lower 3 bits indicates a branch condition (True or False), and the other 2 bits are fixed instructions indicating a branch prediction direction (Taken or Not-Taken).

  The branch instruction with fixed instruction bptt indicates that the branch condition is “True” (branch when true), and the fixed instruction indicates “branch” (Taken).

  The branch instruction bpft with a fixed instruction indicates that the branch condition is “False” (branch when it is False), and the fixed instruction indicates “branch” (Taken).

  The branch instruction bptf with a fixed instruction indicates that the branch condition is “True” and the fixed instruction indicates “not branch” (Not-Taken).

  The branch instruction bpff with a fixed instruction indicates that the branch condition is “False” and the fixed instruction indicates “not branch” (Not-Taken).

  FIG. 7 shows an example in which the loop processing by the conventional program shown in the left part of FIG. 4 is executed by a program including a branch instruction with a fixed instruction.

  As shown in FIG. 7, in this case, the branch instruction with fixed instruction “bpft Loop” is used instead of the branch instruction with fixed instruction “bf Loop” at the bottom of the loop processing in the conventional program shown in the left part of FIG. It is done.

  As described above, in the branch instruction bpft with a fixed instruction, the branch condition is “False” and the fixed instruction indicates “branch” (Taken). Therefore, “bf Loop” in the program of FIG. 7 is a conditional branch instruction that “repeats the loop when r0 is not 0 (false)” and a fixed instruction that “fixes the branch prediction direction to Taken (repeats the loop)”. Will be shown.

  FIG. 8 shows an example of a flowchart of program execution by the instruction processing unit 12. As illustrated, the instruction processing unit 12 performs dynamic prediction for a conditional branch instruction (S130: Yes, S134: No) that does not include a fixed instruction. Specifically, branch prediction is performed with reference to the branch history table 14, and after execution of the conditional branch instruction, the branch history table 14 is updated based on the execution result (S136, S138, S140, S142).

  In the case of a conditional branch instruction that does not include a fixed instruction as in the conventional program shown in the left part of FIG. 4, the processes in steps S136 to S142 are performed.

  On the other hand, for the branch instruction with a fixed instruction (S130: Yes, S134: Yes), the instruction processing unit 12 performs fixed prediction. Specifically, branch prediction is performed in the branch prediction direction indicated by the fixed instruction included in the instruction without referring to the branch history table 14, and after execution of the conditional branch instruction, the branch history is determined regardless of the execution result. The table 14 is not updated (S144, S146).

  In the case of the program shown in FIG. 7, the instruction processing unit 12 performs branch prediction on a branch (Taken) for repeating the loop until the loop ends normally. Therefore, the prediction is incorrect at the last branch (1000th) of the loop execution, but all other (999) branch predictions are correct.

  Note that branch instructions are not predicted for instructions other than conditional branch instructions, and the instruction processing unit 12 fetches and executes these instructions in the same manner as a normal processor (S130: No, S132).

The second technique can obtain the same effects as the first technique.
Further, in the second technique, a fixed instruction is attached to a conditional branch instruction, and the instruction processing unit 12 performs fixed prediction only for a branch instruction with a fixed instruction. Therefore, it is not necessary to use the fixed release instruction in the first technique, the number of instructions can be reduced, and consequently the performance of the semiconductor device 10 can be improved.

<Third technology>
The first and second techniques described above are fixed depending on whether the conditional branch instruction is positioned between the fixed instruction and the fixed release instruction or whether the conditional branch instruction is a branch instruction with a fixed instruction. Switch between prediction and dynamic prediction. On the other hand, in the third technique, the instruction processing unit 12 performs switching between fixed prediction and dynamic prediction according to the operation mode. Note that “fixed prediction” or “dynamic prediction” can be set for each operation mode. The setting of fixed prediction includes a branch prediction direction.

  Here, “fixed prediction” means that branch prediction is performed in the branch prediction direction included in the setting of fixed prediction without referring to the branch history table 14. In this case, the branch history table 14 is not updated after execution of the conditional branch instruction subject to fixed prediction regardless of the execution result.

  “Dynamic prediction” means that branch prediction is performed with reference to the branch history table 14. In this case, the branch history table 14 is updated based on the execution result after execution of the conditional branch instruction to be subjected to dynamic prediction.

  The CPU of the processor has at least two operation modes. The two operation modes are a kernel mode (also referred to as a privileged mode or a supervisor mode) that allows a completely unlimited CPU operation, and a user mode (also referred to as a slave mode) that permits only a limited CPU operation.

  In the third technique, the instruction processing unit 12 has a plurality of operation modes including at least a kernel mode and a user mode, and setting dynamic prediction or “branch” for each operation mode. It is possible to set fixed prediction including a branch prediction direction indicating one of “do not branch”.

  The instruction processing unit 12 performs branch prediction with reference to the history stored in the branch history table 14 for the conditional branch instruction in the operation mode in which dynamic prediction is set, and the conditional branch The branch history table 14 is updated based on the instruction execution result.

  In the operation mode in which the fixed prediction is set, the instruction processing unit 12 does not refer to the branch history table 14 for the conditional branch instruction, and includes the branch prediction direction included in the fixed prediction setting. While branch prediction is performed, the branch history table 14 is not updated.

  FIG. 9 shows an example of a flowchart of program execution by the instruction processing unit 12. In this example, the instruction processing unit 12 has two modes, a kernel mode and a user mode, and dynamic prediction is set for one mode (first mode) and the other mode (first mode). Suppose that fixed prediction (including the branch prediction direction) is set for (mode 2).

  As illustrated in FIG. 9, the instruction processing unit 12 performs dynamic prediction on the conditional branch instruction (S150: Yes, S152, Yes) when operating in the first mode. Specifically, branch prediction is performed by referring to the history stored in the branch history table 14, and after execution of the conditional branch instruction, the branch history table 14 is updated based on the execution result (S156, S158, S160). , S162).

  Unless the switching from the first mode to the second mode occurs (S164: No), the instruction processing unit 12 performs dynamic prediction in steps S156 to S162 for the conditional branch instruction.

  The instruction processing unit 12 performs fixed prediction on the conditional branch instruction when operating in the second mode (S150: No, S166, Yes). Specifically, branch prediction is performed in the branch prediction direction set in advance for the second mode without referring to the branch history table 14, and after execution of the conditional branch instruction, regardless of the execution result. The branch history table 14 is not updated (S170, S172).

  As long as the switching from the second mode to the first mode does not occur (S174: No), the instruction processing unit 12 performs the fixed prediction of Step S170 to Step S172 for the conditional branch instruction.

  When switching from the first mode to the second mode occurs (S164: Yes), the instruction processing unit 12 thereafter performs fixed prediction on the conditional branch instruction (S170, S172).

  When switching from the second mode to the first mode occurs (S174: Yes), the instruction processing unit 12 thereafter performs dynamic prediction on the conditional branch instruction (S156 to S162).

  Note that branch prediction is not performed for instructions other than conditional branch instructions, and the instruction processing unit 12 fetches and executes these instructions in the same manner as a normal processor (S152: No, S154) (S166: No, S168).

  In the processor, the CPU executes different types of programs depending on the operation mode. For example, normally, an OS (Operating System) program is executed in a kernel mode, and a user program is executed in a user mode. Further, the relevance between instructions of different types of programs such as the OS program and the user program is lower than the relevance between the instructions of the same type of program.

  For this reason, if the same branch history table is referenced and learned for branch prediction for all programs, the history of execution results of conditional branch instructions in a plurality of less relevant programs will be mixed, and branch There may be a problem that the probability that a prediction is missed increases.

  The third technique makes it possible to set a branch prediction method (dynamic prediction or fixed prediction) for each operation mode, and the branch prediction set for the operation mode according to the operation mode. Branch prediction by the method. Therefore, if different branch prediction methods are set according to the operation mode, the program executed in the operation mode set to fixed prediction is executed in the operation mode set to dynamic prediction from the viewpoint of branch prediction. Can be lost, and the above problem can be avoided.

  For example, by setting fixed prediction for the kernel mode and setting dynamic prediction for the user mode, a user program environment that is not affected by the execution result of the conditional branch instruction in the OS program is constructed. be able to.

  In addition, when the user of the semiconductor device 10 wants to prioritize the suppression of power consumption, he / she sets fixed prediction for more operation modes, and when he / she wants to prioritize performance, he / she enters more operation modes. On the other hand, operation such as setting dynamic prediction is possible, and the adjustment of the balance between the suppression of power consumption and the maintenance of performance is flexible.

  Normally, a context switch occurs when a transition between operation modes is required in a processor. Therefore, switching between operation modes can be detected by the occurrence of a context switch. In the third technology, for example, the instruction processing unit 12 detects the switching of the operation mode by a context switch that occurs in association with the switching between the operation modes, and switches between dynamic prediction and fixed prediction according to the context switch. Can do.

<Fourth technology>
The first technique described above performs switching between fixed prediction and dynamic prediction depending on whether or not the conditional branch instruction is located between the fixed instruction and the fixed release instruction. In the second technique, switching between fixed prediction and dynamic prediction is performed depending on whether or not the conditional branch instruction is a branch instruction with a fixed instruction. In the third technique, switching between fixed prediction and dynamic prediction is performed according to the operation mode.

  On the other hand, the fourth technique performs switching between fixed prediction and dynamic prediction according to the execution area of the program. The fourth technique will be described with reference to the semiconductor device 20 shown in FIG.

  The semiconductor device 20 is, for example, a microcomputer that executes pipeline processing, and includes an instruction processing unit 22, a branch history table 24, and a memory 26.

  The instruction processing unit 22 performs processing including instruction fetch and execution, and performs branch prediction when executing a conditional branch instruction.

  The branch history table 24 is used to store a history of whether or not a branch is made as a result of execution of a conditional branch instruction, and is updated by the instruction processing unit 22.

  The memory 26 forms a program execution area and includes a plurality of areas (26A, 26B, 26C,...). In the plurality of areas, either fixed prediction setting or dynamic prediction setting is set. Note that the fixed prediction setting includes a branch prediction direction that is one of “branch” and “not branch”.

  In FIG. 10, as an example, an area 26 </ b> A is a fixed prediction area in which fixed prediction of “branch” (Taken) is set. The region 26B is a fixed prediction region in which a fixed prediction of “Do not branch” (Not-Taken) is set. The region 26C is a dynamic prediction region in which dynamic prediction is set.

  FIG. 11 shows an example of a flowchart of program execution by the instruction processing unit 22. As illustrated, the instruction processing unit 22 performs dynamic prediction on a conditional branch instruction of a program whose execution region is an area where dynamic prediction is set (S180: Yes, S184: No). Specifically, branch prediction is performed with reference to the history stored in the branch history table 24, and the branch history table 24 is updated based on the execution result of the conditional branch instruction (S186, S188, S190, S192). .

  For example, the instruction processing unit 22 performs dynamic prediction on a conditional branch instruction in a program that uses the dynamic prediction area 26C of the memory 26 as an execution area.

  On the other hand, the instruction processing unit 22 performs fixed prediction on a conditional branch instruction of a program whose execution region is an area where fixed prediction is set (S180: Yes, S184: Yes). Specifically, the branch prediction is performed in the branch prediction direction set for the area without referring to the branch history table 24 (S194). In this case, the instruction processing unit 22 does not update the branch history table 24 after execution of the conditional branch instruction (S196) regardless of the execution result.

  For example, for a conditional branch instruction of a program that uses the fixed prediction area 26 A of the memory 26 as an execution area, the instruction processing unit 22 always performs a branch prediction of “Taken” and does not update the branch history table 24.

  In addition, the instruction processing unit 22 always performs “Not-Take” branch prediction for a conditional branch instruction of a program that uses the fixed prediction area 26 B of the memory 26 as an execution area, and does not update the branch history table 24.

  Note that branch instructions are not predicted for instructions other than conditional branch instructions, and the instruction processing unit 22 fetches and executes these instructions in the same manner as a normal processor (S180: No, S182).

  The fourth technique provides a memory 26 having a plurality of areas in which different branch prediction methods are set as program execution areas, and switches the branch prediction method according to the area to be the program execution area. . Therefore, the user can program depending on the number of conditional branch instructions included in the program, the number of cases where the conditional branch instruction branches and does not branch, whether you want to prioritize power consumption or performance, etc. By setting an area in which is executed, an optimal branch prediction method can be selected.

Of course, in order to avoid the problem described in the third technique, the history of execution results of conditional branch instructions in a plurality of less relevant programs is mixed, and the probability that a branch prediction is missed increases. However, the fourth technique is effective. In this case, for example, an execution region is designated as an area having the same setting (dynamic prediction or fixed prediction) for a highly relevant program, and an execution region is designated for a plurality of less relevant programs. It is only necessary to designate areas with different settings.
Of course, the setting of each area of the memory 26 may be changed by the user.

The embodiment will be described based on the above technologies.
<First Embodiment>
FIG. 12 shows the semiconductor device 110 according to the first embodiment. The semiconductor device 110 has a microcomputer constituted by a single semiconductor chip. For example, the semiconductor device 110 has an external terminal electrically connected to the semiconductor chip, and takes the form of a semiconductor package in which the semiconductor chip is sealed with a resin and the external terminal is exposed. An external device 120 is connected to the semiconductor device 110. Various storage devices are illustrated as the external device 120. The semiconductor device 110 and the external device 120 constitute a digital information terminal including a mobile phone or an electronic device 100 such as a digital home appliance. Hereinafter, the semiconductor device 110 is also referred to as a “microcomputer 110”.

  The external device 120 includes a nonvolatile memory and a volatile memory. 12 exemplifies a DDR type DRAM (Double Data Rate Type Dynamic Random Access Memory, hereinafter referred to as “DDR memory”) 121 and an SRAM (Static Random Access Memory) 122 as a volatile memory, and flashes as a non-volatile memory. The memory 123 is illustrated.

  The flash memory 123 stores a boot program, an OS program, and a user program. When the electronic device 100 is activated or reset, a boot program is loaded from the flash memory 123 into the SRAM 122 and executed by the CPU 111 of the microcomputer 110. Thereafter, along with the execution of the boot program, a part of the OS program is also loaded into the SRAM 122 and executed by the CPU 111. The user program is also loaded into the SRAM 122 when executed.

  That is, the SRAM 122 constitutes a program execution area. Each program stored in the flash memory 123 is loaded into the SRAM 122 upon execution.

  The DDR memory 121 is a memory that can be accessed at a higher speed than the SRAM, and is used as an execution area for the OS and the user program in the same manner as the SRAM.

  The semiconductor device (microcomputer) 110 may have a part or all of the external device 120. For example, one or both of the SRAM 122 and the flash memory 123 may be provided on the same semiconductor substrate as the microcomputer, or may be provided on a semiconductor substrate different from the microcomputer in the same semiconductor package.

  Similarly, the DDR memory 121 may be provided on the same semiconductor substrate as the microcomputer, or may be provided on a semiconductor substrate different from the microcomputer in the same semiconductor package.

  The microcomputer 110 is connected to a CPU 111 as a central processing unit, a DMA controller 112 that performs DMA (Direct Memory Access) transfer, a bus 119, a time unit 114 that measures time, and a serial communication device (not shown). Serial communication interface 115, time unit 114, peripheral bus controller 113 that controls data transfer with bus 119 of serial communication interface 115, DDR controller 116 that controls access to DDR memory 121, access to SRAM 122 and flash memory 123 A local bus controller 117 for controlling the clock and a clock generator (CPG) 118 for supplying a clock.

  The CPU 111, DMA controller 112, peripheral bus controller 113, DDR controller 116, and local bus controller 117 are connected to the bus 119.

  In the microcomputer 110, the DMA controller 112, the peripheral bus controller 113, the time unit 114, the serial communication interface 115, the DDR controller 116, the local bus controller 117, and the clock generator 118 are provided in this type of semiconductor device. This is the same, and detailed description is omitted here.

  FIG. 13 is a diagram showing the CPU 111 in detail. The CPU 111 executes an instruction by pipeline processing, and an instruction fetch control unit 140, a prediction result determination unit 142, a branch history table 144, a speculative instruction execution control unit 146, an instruction cache 148, a predecoder 150, an instruction queue 152, an instruction decoder 154, an instruction execution unit 156, and a general-purpose register 158.

  In the CPU 111, other functional blocks excluding the branch history table 144 constitute an instruction processing unit, perform processing including instruction fetch and execution, and perform branch prediction when executing a conditional branch instruction.

  The branch history table 144 is used to store a history of whether or not a branch has occurred as a result of execution of a conditional branch instruction. The branch history table 144 can be referred to by the instruction fetch control unit 140 and the speculative instruction execution control unit 146, and is updated by the instruction fetch control unit 140.

  The instruction fetch control unit 140 is connected to the local bus controller 117 and the DDR controller 116 via the bus 119, fetches an instruction from the SRAM 122, the DDR memory 121, or the instruction cache 148, and sends an instruction code to the predecoder 150. , Transfer to instruction queue 152 and instruction decoder 154.

  The predecoder 150 decodes (predecodes) the conditional branch instruction and transfers the result to the instruction queue 152 and the instruction fetch control unit 140.

  The instruction decoder 154 decodes instructions from the instruction queue 152 and the instruction cache 148 and outputs them to the instruction execution unit 156.

  The instruction execution unit 156 executes the instruction from the instruction decoder 154. As the instruction is executed, reading from or writing to the general-purpose register 158 is performed as necessary.

  The instruction fetch control unit 140 fetches the next instruction based on the result of predecoding by the predecoder 150 as described below.

  For an unconditional branch instruction, the instruction fetch control unit 140 acquires a branch destination from the result of predecoding by the predecoder 150 and fetches the branch destination instruction.

  For a conditional branch instruction, the instruction fetch control unit 140 first performs branch prediction. When the result of branch prediction is “branch” (Taken), the instruction fetch control unit 140 acquires a branch destination from the result of predecoding by the predecoder 150 and fetches the instruction at the branch destination.

  On the other hand, when the result of the branch prediction is “do not branch” (Not-Taken), the instruction fetch control unit 140 fetches an instruction from the address next to the address of the conditional branch instruction.

  The speculative instruction execution control unit 146 performs control speculation in cooperation with branch prediction by the instruction fetch control unit 140. Specifically, for the conditional branch instruction, the instruction fetched by the instruction fetch control unit 140 based on the result of the branch prediction is input to the pipeline to start execution. If the branch prediction is correct, the execution is continued as it is. On the other hand, if the branch prediction is incorrect, the instruction input to the pipeline is invalidated based on the branch prediction result. In this case, the instruction fetch control unit 140 fetches an instruction in a direction opposite to the branch predicted direction.

  The prediction result determination unit 142 determines whether the branch prediction result is correct. The instruction fetch control unit 140 determines whether to fetch an instruction in the direction opposite to the branch predicted direction according to the determination result by the prediction result determination unit 142.

  Since the processing flow by the CPU 111 described above is the same as the processing by a normal processor that performs branch prediction, except for the branch prediction method by the instruction fetch control unit 140, further detailed description is omitted.

Here, a method of branch prediction by the instruction fetch control unit 140 will be described.
The instruction fetch control unit 140 performs branch prediction using the first technique described above. That is, the instruction fetch control unit 140 corresponds to the above-described fixed instruction and fixed release instruction.

  For a conditional branch instruction between a fixed instruction and a fixed release instruction, the instruction fetch control unit 140 does not refer to the branch history table 144 as a fixed prediction, but in the branch prediction direction indicated by the fixed instruction. Perform branch prediction. In this case, the instruction fetch control unit 140 does not update the branch history table 144 regardless of whether or not the branch prediction is correct.

  For other conditional branch instructions, the instruction fetch control unit 140 performs branch prediction by referring to the branch history table 144 as dynamic branch prediction, and for speculative execution of the conditional branch instruction. The branch history table 144 is updated based on the result determined by the prediction result determination unit 142.

  Such branch prediction by the instruction fetch control unit 140 is based on the first technique. Therefore, the semiconductor device 110 according to the first embodiment can obtain all the effects described for the first technique.

<Second Embodiment>
The second embodiment is also a semiconductor device. The semiconductor device is the same as the semiconductor device 110 except for the difference in the branch prediction method from the semiconductor device 110 of the first embodiment. Therefore, in the second embodiment, only the branch prediction method is used. explain. Further, for the sake of brevity, the semiconductor device of the second embodiment is not illustrated and will be described using functional blocks of the semiconductor device 110.

  In the semiconductor device of the second embodiment, the instruction fetch control unit 140 performs branch prediction using the second technique described above. That is, the instruction fetch control unit 140 corresponds to a conditional branch instruction (a branch instruction with a fixed instruction) including the above-described fixed instruction.

  Then, for a branch instruction with a fixed instruction, the instruction fetch control unit 140 does not refer to the branch history table 144 as fixed prediction, but in the branch prediction direction indicated by the fixed instruction included in the branch instruction with the fixed instruction. Perform branch prediction. In this case, the instruction fetch control unit 140 does not update the branch history table 144 regardless of whether or not the branch prediction is correct.

  For a conditional branch instruction that does not include a fixed instruction, the instruction fetch control unit 140 performs branch prediction with reference to the branch history table 144 as dynamic branch prediction and speculative execution of the conditional branch instruction. The branch history table 144 is updated based on the result determined by the prediction result determination unit 142.

  Such branch prediction is based on the second technique. Therefore, the semiconductor device according to the second embodiment can obtain all the effects described for the second technique.

<Third Embodiment>
The third embodiment is also a semiconductor device. The semiconductor device is the same as the semiconductor device 110 shown in FIG. 12 except that a CPU 200 shown in FIG. 14 is provided instead of the CPU 111. Here, only the CPU 200 will be described. Also, the CPU 200 will be described only with respect to differences from the CPU 111.

  As shown in FIG. 14, the CPU 200 is the same as the CPU 111 in the semiconductor device 110 except that an instruction fetch control unit 240 is provided instead of the instruction fetch control unit 140 and a status register 210 is provided.

  The status register 210 has a plurality of bits and stores information indicating an operation mode of the CPU 200, a register bank to be used, and the like.

  In the present embodiment, the CPU 200 has two operation modes, a kernel mode and a user mode. The current operation mode of the CPU 200 is indicated by one bit of the status register 210 (hereinafter referred to as “operation mode bit”). In addition, when the operation mode is switched, the value of the operation mode bit is changed with the occurrence of the context switch.

  In the CPU 200, the instruction fetch control unit 240 is different from the CPU 111 in the semiconductor devices of the first and second embodiments with respect to the branch prediction method.

  The above-described third technique is applied to the CPU 200. Specifically, of the two operation modes of the CPU 200, fixed prediction is set for the kernel mode, and dynamic prediction is set for the user mode. These settings are stored in, for example, the status register 210 or another register (not shown), and are written by executing the boot program at the time of startup. In addition, the setting of the fixed prediction includes a branch prediction direction of “branch” or “not branch”. As an example, it is assumed that the branch prediction direction included in the fixed prediction set for the kernel mode is “no branch”.

  The instruction fetch control unit 240 performs branch prediction on the conditional branch instruction according to the prediction method set for the current operation mode of the CPU 200. Specifically, when the current operation mode of the CPU 200 is a kernel mode in which fixed prediction (branch prediction direction: no branch) is set, the instruction fetch control unit 240 performs branch history for a conditional branch instruction. Without referring to the table 144, the prediction that “does not branch” is always performed. In this case, the instruction fetch control unit 140 does not update the branch history table 144 regardless of whether or not the branch prediction is correct.

  On the other hand, when the current operation mode of the CPU 200 is the user mode in which dynamic prediction is set, the instruction fetch control unit 240 performs branch prediction with respect to the conditional branch instruction by referring to the branch history table 144. The branch history table 144 is updated based on the result of the prediction result determination unit 142 determining the speculative execution of the conditional branch instruction.

  Such branch prediction is based on the third technique. Therefore, the semiconductor device according to the third embodiment can obtain all the effects described for the third technique.

<Fourth embodiment>
The fourth embodiment is also a semiconductor device. The semiconductor device is the same as the semiconductor device 110 shown in FIG. 12 except that a CPU 300 shown in FIG. 15 is provided instead of the CPU 111. Here, only the CPU 300 will be described. Also, only the CPU 300 will be described, which is different from the CPU 111.

  As shown in FIG. 15, the CPU 300 is the same as the CPU 111 in the semiconductor device 110 except that an instruction fetch control unit 340 is provided instead of the instruction fetch control unit 140 and an area setting register 310 is provided.

  The area setting register 310 stores a plurality of sets (two sets in the illustrated example). Each set of settings consists of three pieces of information: an upper limit address, a lower limit address, and a branch prediction direction in the program execution area. These settings are written by executing the boot program at startup.

  For example, the setting of the group (1) includes three pieces of information on the branch prediction directions of the upper limit address “20000000”, the lower limit address “40000000”, and “Taken” in the program execution area. In addition, the setting of the set (2) includes three pieces of information on the branch prediction directions of the upper limit address “80000000”, the lower limit address “A0000000”, and “Not-Taken” in the program execution area.

  In the CPU 300, the instruction fetch control unit 340 is different from the CPU in the semiconductor device of the first to third embodiments with respect to the branch prediction method.

  As for CPU300, the 4th technique mentioned above is applied. Specifically, the instruction fetch control unit 340 of the CPU 300 determines the area of the SRAM 122 from the upper limit address to the lower limit address included in the setting of the group based on the setting of each group of the area setting register 310 as a “fixed prediction area”. An area that is not set in the area setting register 310 is regarded as a “dynamic prediction area”.

  FIG. 16 shows a correspondence relationship between the setting example stored in the area setting register 310 and the area of the SRAM 122.

  For example, since “20000000”, “40000000”, and “Taken” are set as the upper limit address, the lower limit address, and the branch prediction direction in the group (1), the areas “20000000” to “40000000” in the SRAM 122 are The fixed prediction area of “Taken” is regarded as the fixed prediction area.

  Further, since “80000000”, “A0000000”, and “Not-Taken” are set as the upper limit address, the lower limit address, and the branch prediction direction in the group (2), “80000000” to “A0000000” in the program execution area. This area is regarded as a fixed prediction area in which a fixed prediction of “Not-Taken” is set.

  Since other areas of the SRAM 122 are not set in the area setting register 310, they are regarded as dynamic prediction areas in which dynamic prediction is set.

  When performing branch prediction on a conditional branch instruction, the instruction fetch control unit 340 performs branch prediction based on an execution area of a program including the conditional branch instruction.

  Specifically, the instruction fetch control unit 340 performs dynamic prediction on a conditional branch instruction of a program whose execution area is an area regarded as a dynamic prediction area. That is, branch prediction is performed with reference to the branch history table 144, and the branch history table 144 is updated based on a result determined by the prediction result determination unit 142 for speculative execution of the conditional branch instruction.

  For example, in the case of the example shown in FIG. 16, with respect to a conditional branch instruction of a program having each area of “00000000” to “20000000”, “40000000” to “80000000”, and “A0000000” to “FFFFFFFF” as an execution area, Perform dynamic prediction.

  On the other hand, the instruction fetch control unit 340 performs fixed prediction on a conditional branch instruction of a program whose execution area is an area regarded as fixed prediction. That is, branch prediction is performed in the branch prediction direction set for the area without referring to the branch history table 144. Further, the branch history table 144 is not updated regardless of the result of the prediction result determination unit 142 determining the speculative execution of the conditional branch instruction.

  For example, in the case of the example shown in FIG. 16, “Taken” is fixedly predicted for a conditional branch instruction of a program having an area “20000000” to “40000000” as an execution region, and “80000000” to “A0000000” For a conditional branch instruction of a program whose area is an execution area, a fixed prediction of “Not-Taken” is performed.

  Such branch prediction is based on the fourth technique. Therefore, the semiconductor device according to the fourth embodiment can obtain all the effects described for the fourth technique.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Instruction processing part 14 Branch history table 20 Semiconductor device 22 Instruction processing part 24 Branch history table 26 Memory 26A Fixed prediction area 26B Fixed prediction area 26C Dynamic prediction area 100 Electronic device 110 Semiconductor device (microcomputer)
111 CPU
112 DMA controller 113 Peripheral bus controller 114 Time unit 115 Serial communication interface 116 DDR controller 117 Local bus controller 118 Clock generator 119 Bus 120 External device 121 DDR memory 122 SRAM
123 Flash memory 140 Instruction fetch control unit 142 Prediction result determination unit 144 Branch history table 146 Speculative instruction execution control unit 148 Instruction cache 150 Predecoder 152 Instruction queue 154 Instruction decoder 156 Instruction execution unit 158 General-purpose register 200 CPU
210 Status register 240 Instruction fetch control unit 300 CPU
310 Area setting register 340 Instruction fetch control unit

Claims (9)

An instruction processing unit that performs processing including instruction fetch and execution, and performs branch prediction when executing a conditional branch instruction;
As a result of execution of a conditional branch instruction, for storing a history of whether or not a branch, comprising a branch history table updated by the instruction processing unit,
The instruction processing unit
A fixed instruction instructing to fix in a branch prediction direction indicating either “branch” or “not branch” and the fixed instruction are paired with the fixed instruction instructed by the fixed instruction. It is possible to execute a fixed release command to release
For a conditional branch instruction, perform a dynamic branch that performs branch prediction with reference to the history stored in the branch history table,
After executing the fixed instruction, with respect to the conditional branch instruction, without performing a reference to the branch history table, performing a fixed prediction that performs branch prediction in the branch prediction direction indicated by the fixed instruction.
Semiconductor device. The instruction execution processing unit
2. The branch history table is not updated based on an execution result of the conditional branch instruction when the fixed prediction is performed on the conditional branch instruction after the fixed instruction is executed. Semiconductor device. The instruction processing unit
It is possible to execute a fixing release instruction to release fixing to release the fixing of the branch prediction direction indicated by the fixing instruction,
After executing the fixed release instruction, the conditional branch instruction is subjected to dynamic prediction to perform branch prediction with reference to the history stored in the branch history table, and based on the execution result of the conditional branch instruction. The semiconductor device according to claim 1, wherein the branch history table is updated. An instruction processing unit that performs processing including instruction fetch and execution, and performs branch prediction when executing a conditional branch instruction;
As a result of execution of a conditional branch instruction, for storing a history of whether or not a branch, comprising a branch history table updated by the instruction processing unit,
The instruction processing unit
It is possible to execute a branch instruction with a fixed instruction that is a conditional branch instruction including a fixed instruction indicating that the instruction is fixed in a branch prediction direction indicating either “branch” or “not branch”.
For the branch instruction with a fixed instruction, without referring to the branch history table, performing a fixed prediction to perform branch prediction in the branch prediction direction indicated by the fixed instruction,
For a conditional branch instruction that does not include the fixed instruction, dynamic prediction is performed to perform branch prediction with reference to the history stored in the branch history table, and based on the execution result of the conditional branch instruction Update the branch history table,
Semiconductor device. The instruction execution processing unit
The semiconductor device according to claim 4, wherein after executing the fixed instruction, the branch history table is not updated when the fixed prediction is performed on the conditional branch instruction. An instruction processing unit that performs processing including instruction fetch and execution, and performs branch prediction when executing a conditional branch instruction;
As a result of execution of a conditional branch instruction, for storing a history of whether or not a branch, comprising a branch history table updated by the instruction processing unit,
The instruction processing unit
A plurality of operation modes including at least a kernel mode and a user mode;
For each of the operation modes, dynamic prediction can be set, or fixed prediction including a branch prediction direction indicating “branch” or “not branch” can be set.
In the operation mode in which the dynamic prediction is set, for the conditional branch instruction, the branch prediction is performed with reference to the history stored in the branch history table, and the execution result of the conditional branch instruction Updating the branch history table based on
While in the operation mode in which the fixed prediction is set, the branch prediction is performed in the branch prediction direction included in the fixed prediction setting without referring to the branch history table for the conditional branch instruction. , Do not update the branch history table,
Semiconductor device. The fixed prediction is set for the kernel mode,
The dynamic prediction is set for the user mode,
The semiconductor device according to claim 6. The instruction processing unit
Switching between the dynamic prediction and the fixed prediction according to a context switch that occurs in association with switching between the plurality of operation modes,
The semiconductor device according to claim 6. It has multiple areas where either fixed prediction that fixes in one of the branch prediction directions of “branch” or “not branch” and dynamic prediction are set, and the program execution area Memory
An instruction processing unit that performs processing including instruction fetch and execution, and performs branch prediction when executing a conditional branch instruction;
As a result of execution of a conditional branch instruction, for storing a history of whether or not a branch, comprising a branch history table updated by the instruction processing unit,
The instruction processing unit
For a conditional branch instruction of a program whose execution area is an area where the dynamic prediction is set, branch prediction is performed with reference to the history stored in the branch history table, and the conditional branch instruction Update the branch history table based on the execution result,
For a conditional branch instruction of a program whose execution region is an area where the fixed prediction is set, branch prediction is performed in the branch prediction direction set for the area without referring to the branch history table. On the other hand, the branch history table is not updated.
Semiconductor device.

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