JP2013250573A - Memory control device and control method of memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology capable of avoiding memory address passing and suppressing, as soon as possible, image degradation in which motion becomes unnatural.SOLUTION: A memory control device comprises: a memory comprising a plurality of regions; a memory control section for sequentially writing image data in each region of the memory by synchronizing with a first synchronous signal, and reading the image data from the memory by synchronizing with a second synchronous signal created without synchronizing with the first synchronous signal; a timing determination section for determining reference timing with reference to the first synchronous signal; a region determination section for determining a region read by the memory control section on the basis of order of the reference timing and the second synchronous signal; and an exchange period detection section for detecting an exchange period which is a period where occurrence of order exchange between the reference timing and the second synchronous signal is predicted. The timing determination section changes the reference timing in the exchange period in a direction in which the order exchange easily occurs.

Description

  The present invention relates to a memory control device.

  In Patent Document 1, the read address value at the start of a write frame is added to the read address amount that proceeds during one write frame, and the added value is compared with the address amount of one write frame. It is described that the presence or absence is determined. Japanese Patent Application Laid-Open No. 2004-228561 describes that an address overtaking determination of a storage device is performed from a difference between a read address and a write address and a predetermined allowable value, and writing of the storage device is executed or stopped.

  In Patent Document 2, a time difference between a reset time of a write address and a reset time of a read address is detected, and whether or not a memory overtaking occurs in the next write frame is determined based on the detected time difference. Is disclosed. Japanese Patent Application Laid-Open No. H10-228561 describes that any of the following processes is performed when overtaking of a memory occurs. (1) Stop writing to the frame memory in the next writing frame. (2) Data for one frame is read from the same memory area as that read immediately before in the next read frame. (3) In the next read frame, data is read from the memory area that is one order ahead of the memory area in the order in which data is to be read.

Here, when the input video signal is an interlaced video signal, the vertical synchronization period for one field may be different between the odd field and the even field. In general, in an interlaced video signal, the phases of the vertical synchronizing signal and the horizontal synchronizing signal are shifted by 0.5 lines between the odd field and the even field in order to make it possible to determine whether the field is an odd field or an even field. For example, the total number of scanning lines included in the vertical synchronization period in a video signal having 1080 effective scanning lines is 1125, and the vertical synchronization period for one field in the interlace format of such a video signal is 562.5. Become a book. That is, when the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal is aligned in one field, the other field is shifted by 0.5 lines. As a result, it is possible to determine whether the input video signal is an odd-field video signal or an even-field video signal from the phase relationship with the horizontal synchronization signal at the change point of the vertical synchronization signal.

  After the field determination, for example, processing is performed in which the change points of the vertical synchronization signal and the horizontal synchronization signal are aligned and output to the subsequent processing circuit. In this case, one field has 562 vertical synchronization periods and the other field has 563 vertical synchronization periods. That is, a difference of one line occurs between the vertical synchronization period of the odd field and the vertical synchronization period of the even field. In such a case, when the overtaking avoidance process shown in Patent Document 1 or Patent Document 2 is performed, the determination of the presence or absence of overtaking is not stable, and the image is displayed repeatedly and temporarily. Image quality degradation may occur.

  Patent Document 3 discloses that an unstable state (chattering) of a read memory selection bit occurs due to jitter (temporal fluctuation) that occurs when an input video signal and a display-side vertical synchronization signal are close to each other. Yes. In order to avoid chattering, the first pulse starting from the memory switching point and the second pulse starting from the end point of the first pulse are generated, and the switching point of the read memory is any pulse. It is disclosed that the read memory is determined depending on whether it is detected.

JP 2001-13934 A JP 2001-83928 A JP 2004-177738 A

  In the display device, the vertical synchronization signal on the display side may be generated asynchronously with the vertical synchronization signal of the input video signal. In such a case, even if the period of the vertical synchronization signal on the display side (reading side) is to be matched with the period on the input side (writing side), it is difficult to make the periods coincide completely. This is because, since the period of the vertical synchronization signal is a stack of clocks in units of one pixel, a difference occurs in the period of the vertical synchronization signal on the input side and the display side due to the accumulation of pixel clock errors. Therefore, if the vertical synchronization signal on the input side and the display side are asynchronous, either the output side is faster (shorter cycle) or slower (longer cycle) than the input side. Occur. Such a difference in the period of the vertical synchronization signal is referred to as a “speed difference”.

  The overtaking avoidance technique disclosed in Patent Document 3 is inappropriate when there is a speed difference between the vertical synchronization signal on the input side and the display side, and the period of the vertical synchronization signal on the input side varies for each field. There is a possibility that the read memory is selected. For this reason, it is not possible to sufficiently avoid image quality deterioration in which the motion is unnatural, such as temporarily displaying images repeatedly.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique capable of avoiding overtaking of the memory and suppressing image quality deterioration that causes unnatural movement as much as possible. It is in. A further object of the present invention is to avoid overtaking of the memory even when the synchronization signal on the reading side is generated asynchronously with the synchronization signal on the writing side, and to minimize image quality degradation that causes unnatural movement. It is to provide a technology that can be suppressed. A further object of the present invention is to avoid overtaking of the memory even when the period of the synchronization signal on the writing side fluctuates for each image data (field or frame), and as much as possible to deteriorate the image quality that causes unnatural movement. It is to provide technology that can be suppressed.

  In order to achieve the above object, the present invention adopts the following configuration.

A first aspect of the present invention is a memory having a plurality of areas;
Image data is sequentially written in each area of the memory in synchronization with a first synchronization signal, and image data is read from the memory in synchronization with a second synchronization signal generated asynchronously with the first synchronization signal. A memory controller;
A timing determination unit that determines a reference timing based on the first synchronization signal;
An area determination unit that determines an area to be read by the memory control unit based on the reference timing and the order of the second synchronization signals;
A replacement period detection unit that detects a replacement period that is a period in which the switching of the order of the reference timing and the second synchronization signal is predicted to occur;
With
The timing determination unit is a memory control device that changes the reference timing in the replacement period in a direction in which the change of order is likely to occur.

A second aspect of the present invention is a method of controlling a memory having a plurality of areas,
A writing step of sequentially writing image data in each area of the memory in synchronization with a first synchronization signal;
A reading step of reading image data from the memory in synchronization with a second synchronization signal generated asynchronously with the first synchronization signal;
In the reading step, an area to be read is determined based on the order of the reference timing determined based on the first synchronization signal and the second synchronization signal,
The control method further includes:
Detecting a replacement period, which is a period during which a change in the order of the reference timing and the second synchronization signal is expected to occur;
And changing the reference timing within the replacement period in a direction in which the change of order is likely to occur.

  According to the present invention, overtaking of a memory can be avoided and image quality deterioration that causes unnatural movement can be suppressed as much as possible.

FIG. 1 is a block diagram illustrating a configuration example of a memory control device according to an embodiment of the present invention. 2A is a diagram showing the relationship between the vertical synchronization signal of the input video signal and the effective line number, and FIG. 2B is a diagram showing the relationship between the vertical synchronization signal of the output video signal and the effective line number. FIG. 3 is a diagram illustrating how overtaking occurs. FIG. 4 is a timing chart showing the switching period of the memory unit to be read. FIG. 5 is a timing chart showing how the timing signal is generated by the detection timing signal generator. FIG. 6 is a timing chart showing how the speed difference detection unit detects the speed difference between the IVS signal and the OVS signal. FIG. 7 is a timing chart showing how the switching period of the memory unit read by the overtaking avoidance detection unit is detected. FIG. 8 is a timing chart showing how the memory unit read by the output memory selection unit is switched. FIG. 9 is a timing chart showing how the memory unit to be read is determined by the output memory selection signal generation unit. FIG. 10 is a timing chart showing how the memory unit to be read is determined in the memory control device of the comparative example. FIG. 11 is a timing chart showing how a memory unit to be read is determined in the memory control device according to the embodiment of the present invention. FIG. 12 is a timing chart showing how the memory unit to be read is determined in the memory control device of the comparative example. FIG. 13 is a timing chart showing how the memory unit to be read is determined in the memory control device according to the embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A memory control device according to an embodiment of the present invention is a device for controlling writing and reading of a frame memory that stores image data. This memory control device is applied to control of a frame memory in a drive circuit of a display device such as a television device or a video processing circuit (computer, video recorder, etc.) that supplies a video signal to the display device. can do.

  The memory control device of the present embodiment includes a memory (1 in FIG. 1) having a plurality of areas (for example, BA0 to BA3 in FIG. 1). Each area is an area for temporarily storing image data for one screen (one field or one frame).

  The memory control device includes a memory control unit (2 in FIG. 1) that controls memory writing and reading. The memory control unit sequentially writes the image data in each area of the memory in synchronization with the first synchronization signal (IVS signal in FIG. 1). On the other hand, the memory control unit reads the image data from the memory in synchronization with the second synchronization signal (OVS signal in FIG. 1).

  Here, the second synchronization signal is a signal generated asynchronously with the first synchronization signal. Therefore, as described above, the periods of the first synchronization signal and the second synchronization signal do not completely match, and there is a speed difference. At this time, both a case where the first synchronization signal is faster and a case where the second synchronization signal is faster may occur, and it may not be possible to determine in advance which is faster. Further, as in the case of handling an interlaced video signal, the period of the first synchronization signal may vary for each image data (each field).

The memory control device employs the following configuration in order to prevent the read position of the memory from overtaking the write position. First, the timing determination unit (6 and 7 in FIG. 1) determines the reference timing (lat_IBA_sel signal) based on the first synchronization signal (IVS signal).
The reference timing is set within a range (memory switching period in FIG. 4) in which overtaking does not occur when reading is started from the reference timing with respect to the area where writing is started in synchronization with the first synchronization signal. The Then, the area determination unit (4, 5 in FIG. 1) determines an area (OBA signal) to be read by the memory control unit based on the order of the reference timing (lat_IBA_sel signal) and the second synchronization signal (OVS signal). . Specifically, when the second synchronization signal (OVS signal) is after the reference timing (lat_IBA_sel signal), overtaking does not occur.
Reading is performed from the area being written (see t3 to t6 in FIG. 11 and t10 to t11 in FIG. 13). On the other hand, when the second synchronization signal is ahead of the reference timing, overtaking may occur, so reading is performed from the area immediately before the area being written (t1 to t2 in FIG. 11). 13 t12-t16). This avoids overtaking.

  In such an overtaking avoidance method, when the reference timing and the order of the second synchronization signal are switched, image data for one screen is skipped (see t2 → t3 in FIG. 11), or the same image data is 2 It is read once (see t11 → t12 in FIG. 13). Although this may cause unnatural motion of the moving image, it must be allowed to avoid overtaking.

  However, when the first synchronization signal and the second synchronization signal are in an asynchronous relationship or when the cycle of the first synchronization signal fluctuates, the phenomenon shown in FIGS. 10 and 12 may occur. is there. That is, immediately after the order of the reference timing and the second synchronization signal is changed (t2 → t3 in FIG. 10), the order is restored (t3 → t4), and the order is changed (t4 → t5). Replacements occur frequently. When such a phenomenon occurs, image data is skipped and repeated unnecessarily, resulting in degradation of image quality.

Therefore, the memory control device adopts the following configuration in order to suppress the above phenomenon. First, the replacement period detection unit (9 in FIG. 1) detects a replacement period that is a period in which the switching of the order of the reference timing and the second synchronization signal is expected (the near signal in FIG. 11 is “1”). Is a replacement period). Then, the timing determination unit (6 and 7 in FIG. 1) changes the reference timing (lat_IBA_sel signal) in the replacement period in a direction in which the order is likely to change. For example, as shown in FIG. 11, when the planned change in the replacement period is “first: second synchronization signal, rear: reference timing → first: reference timing, rear: second synchronization signal” Advance the reference timing (change from lat_IBA (2) to lat_IBA (1)). On the contrary, as shown in FIG. 13, when the change of the order planned in the replacement period is “first: reference timing, after: second synchronization signal → destination: second synchronization signal, after: reference timing”. , Delay the reference timing (change from lat_IBA (2) to lat_IBA (3)).

  By adjusting the reference timing in the replacement period in this way, the switching of the reference timing in the replacement period and the order of the second synchronization signal is promoted, while the order once switched is suppressed from being restored. Therefore, the phenomenon that the order is frequently changed is preferably suppressed, and the deterioration of the image quality can be suppressed as much as possible.

  Here, when the first synchronization signal and the second synchronization signal are in an asynchronous relationship, both the case in which the reference timing overtakes the second synchronization signal and the case in which the second synchronization signal overtakes the reference timing are available. Can occur. Therefore, the speed difference detection unit (8 in FIG. 1) detects which of the cycle of the second synchronization signal and the cycle of the first synchronization signal is faster. When the cycle of the first synchronization signal is faster (ov_direction = 1), the timing determination unit sets the reference timing within the replacement period to the first timing (lat_IBA (1) signal) (see FIG. 11). The first timing is earlier than the second timing (lat_IBA (2) signal) which is the reference timing outside the replacement period. Further, when the cycle of the second synchronization signal is faster (ov_direction = 0), the timing determination unit sets the reference timing within the replacement period to a third timing (lat_IBA (3) signal) that is later than the second timing. Set (see FIG. 13). With such a configuration, it is possible to favorably suppress deterioration in image quality regardless of which of the first synchronization signal and the second synchronization signal is fast.

  The speed difference detection unit (8 in FIG. 1) can determine which synchronization signal cycle is faster, for example, by examining the order of the second synchronization signal and the second timing before the replacement period. . When the second synchronization signal is preceded, it may be considered that the period of the first synchronization signal is faster. The fact that the second synchronization signal precedes the replacement period means that the second synchronization signal is gradually delayed from the first synchronization signal, and the second synchronization signal and the second synchronization signal during the replacement period. This is because it means that the order of the timings of 2 is switched. On the contrary, when the second timing is preceded, it can be considered that the period of the second synchronization signal is faster.

More specifically, the following configuration is preferable. The window setting unit (6 in FIG. 1) sets the first window (near_off (1) = 1) before the second timing (lat_IBA (2) signal),
A second window (near_off (2) = 1) is set after the second timing (see FIG. 5). When the speed difference detection unit detects the second synchronization signal (OVS signal) within the first window (near_off (1) = 1), the cycle of the first synchronization signal is faster (ov_direction = 1 ) (See FIG. 6). Further, when the second synchronization signal (OVS signal) is detected within the second window (near_off (2) = 1), it is determined that the cycle of the second synchronization signal is faster (ov_direction = 0). This makes it possible to determine which cycle of the first synchronization signal and the second synchronization signal is fast with a simple configuration and processing.

<Detailed configuration of memory control device>
Now, a detailed configuration of the memory control device according to the embodiment of the present invention will be described.

FIG. 1 is a block diagram showing the configuration of the memory control device. Reference numeral 1 denotes a frame memory having a plurality of memory units capable of storing image information for forming one input screen. In this example, each memory unit is called a bank area (hereinafter referred to as BA), and has four memory units from BA0 to BA3. Here, the number of memory units is not limited to four, and if there are two or more memory units, overtaking avoidance control by switching the memory units is possible. Reference numeral 2 denotes a memory control unit that controls writing or reading of the frame memory 1. Reference numeral 3 denotes an input memory selection signal generation unit that selects a memory unit to which input video data is written. Reference numeral 4 denotes an input memory selection signal holding unit for holding the input memory selection signal generated by the input memory selection signal generation unit 3 at a timing at which no overtaking occurs in the video data reading from the frame memory 1. . Reference numeral 5 denotes an output memory selection signal generation unit that selects a memory unit from which video data to be output is read. Reference numeral 6 denotes a detection timing signal generation unit that generates a signal for detecting overtaking. Reference numeral 7 denotes an output memory selection unit that generates and outputs a timing signal for holding the input memory selection signal generated by the input memory selection signal generation unit 3 to the input memory selection signal holding unit 4. A speed difference detection unit 8 detects a speed difference between the input vertical synchronization signal (first synchronization signal) and the output vertical synchronization signal (second synchronization signal). Reference numeral 9 denotes an overtaking avoidance detecting unit that detects avoidance of overtaking in reading video data from the frame memory 1. Reference numeral 10 denotes an output timing signal generation unit that generates timing for outputting video data read from the frame memory 1.

  In the configuration of FIG. 1, the detection timing signal generation unit 6 and the output memory selection unit 7 correspond to the “timing determination unit” described above. The input memory selection signal holding unit 4 and the output memory selection signal generation unit 5 correspond to the above-described “region determination unit”. Further, the overtaking avoidance detection unit 9 corresponds to the “replacement period detection unit” described above. The detection timing signal generator 6 corresponds to the “window setting unit” described above.

<Control signal>
Control signals handled by the memory control device will be described.

“IFLD” is a field signal indicating whether the input video data is odd field video data or even field video data. “IVS” is the vertical sync signal (first
Synchronization signal). “IHS” is a horizontal synchronization signal of input video data. "IACT"
This is a valid data signal for input video data.

  “OVS” is a vertical synchronization signal (second synchronization signal) of output video data. “OHS” is a horizontal synchronization signal of output video data. “OACT” is an effective data signal of output video data.

  “IBA” is an input memory selection signal for designating a BA to which video data is written. “OBA” is an output memory selection signal for designating a BA from which video data is read.

“Lat_IBA (1)”, “lat_IBA (2)”, and “lat_IBA (3)” are timing signals generated based on the IVS signal. The lat_IBA (2) signal is the default timing (second timing). The lat_IBA (1) signal has an earlier timing (first timing) than the lat_IBA (2) signal, and the lat_IBA (3) signal has a later timing (third timing) than the lat_IBA (2) signal. “Lat_IBA_sel” is a signal selected from lat_IBA (1) to lat_IBA (3), and is used to specify the timing of referring to the IBA signal and latching the value. The lat_IBA_sel signal corresponds to the “reference timing” described above. “IBA_lat” is a signal indicating the value of the IBA signal latched at the timing of the lat_IBA_sel signal. That is, the IBA_lat signal is a signal whose value changes in the same manner as the IBA signal. However, the timing at which the value of the IBA_lat signal changes is delayed by the amount specified by the lat_IBA_sel signal compared to the IBA signal, and the amount of delay is lat_IBA (1)
It changes by ~ lat_IBA (3).

“Near_on” is a window used to detect whether the OVS signal is near the lat_IBA (2) signal. “Near_off (1)” is a first window used to detect whether the OVS signal is near the lat_IBA (1) signal. "Near_off (2)"
A second window used to detect whether the OVS signal is near the lat_IBA (3) signal.

“Near” is a signal indicating whether or not the OVS signal is close to the lat_IBA (2) signal. When the OVS signal is detected within the near_on signal window, the near signal becomes 1, and when the OVS signal is detected within the near_off (1) signal or near_off (2) signal window, the near signal becomes 0. The period in which the near signal is 1 corresponds to the “alternating period” described above.

  “Ov_direction” is a signal indicating which one of the cycle of the IVS signal and the cycle of the OVS signal is fast (short). When the OVS signal is detected within the near_off (1) signal window, the ov_direction signal becomes 1, and when the OVS signal is detected within the near_off (2) signal window, the ov_direction signal becomes 0.

<Operation of memory control device>
Next, the operation of the memory control device described above will be described in detail.

  Based on the IVS signal, IHS signal, IACT signal, and IBA signal, the memory control unit 2 generates a control signal for sequentially writing the input video data to the memory unit designated by the IBA signal of the frame memory 1 to generate a frame. Output to memory 1. The memory control unit 2 generates a control signal for sequentially reading video data from the frame memory 1 based on the OVS signal, the OHS signal, the OACT signal, and the OBA signal, and outputs the control signal to the frame memory 1.

  In this embodiment, the input video data is assumed to be an interlaced video signal. The memory control unit 2 refers to the IFLD signal, and interpolates interlaced line pixel information with respect to the interlaced video signal stored in the frame memory 1 to convert it into a progressive video signal. Section (hereinafter referred to as an IP conversion processing section). The IP conversion processing unit can use generally known IP conversion processing. As a known IP conversion process, the inter-frame difference information of the pixel value is obtained for each pixel, and further, the movement for each pixel is determined from the inter-frame difference information. Then, there is a motion adaptation method that performs interpolation processing between frames. In the motion adaptive IP conversion processing, a frame delay occurs when performing the interpolation processing. Therefore, a method of simply performing the interpolation processing within the frame may be used here.

  The frame memory 1 stores the input video data while circulating in the memory units from BA0 to BA3 in units of fields according to the control signal output from the memory control unit 2. The frame memory 1 reads out and outputs the video data stored in the memory unit according to the control signal. Progressive video data is output from the frame memory 1.

  The input memory selection signal generation unit 3 updates the IBA signal in synchronization with the change of the input IVS signal. The input memory selection signal generation unit 3 is composed of a simple counter that updates a 2-bit counter value that designates a memory unit from BA0 to BA3 each time an IVS signal is issued, for example. Output as.

  The detection timing signal generation unit 6 generates and outputs a timing signal for performing overtaking avoidance control. FIG. 5 is a timing chart showing an example of the timing signal generated by the detection timing signal generation unit 6. The detection timing signal generator 6 has a counter that sets an initial value when the IVS signal changes and counts down when the IHS signal changes. The timing signal is generated according to the count value of the counter.

In the example of FIG. 5, the lat_signal signal is output at the IHS signal change point when the initial value is “10” in hexadecimal and the count value is “10”. The lat_IBA (1) signal is output at the IHS signal change point when the count value is “E”. The lat_IBA (2) signal is output at the IHS signal change point when the count value is “A”. The lat_IBA (3) signal is output at the IHS signal change point when the count value is “6”.

When the count values are “A” and “9”, a near_on signal is output, and when the count values are “E” and “D”, a near_off (1) signal is output, and the count values are “6” and “5”. When "", the near_off (2) signal is output. The near_on signal and the near_off signal are generated within a period in which no overtaking of the memory occurs.

The timing for generating the near_on signal and the near_off signal will be described with reference to FIGS. 2A, 2B, 3, and 4. FIG. 2A is a diagram illustrating a vertical synchronization signal in an input video signal, and FIG. 2B is a diagram illustrating a display-side vertical synchronization signal generated by the output timing signal generation unit 10.

  In FIG. 2A, the horizontal axis indicates one vertical synchronization period in the input video signal, and there are blanking periods IVB1 and IVB2 before and after, and valid data is transferred in a period excluding the blanking period. The vertical axis indicates the line number of the input valid data. In this example, 1080 valid data is input, and 1080 valid data is sequentially input during a period excluding the blanking period (a straight line indicated by a solid line). In this example, since the input video data is assumed to be an interlaced video signal, there are an odd field composed only of odd line video data and an even field composed only of even line video data. Repeated alternately. It is assumed that the video data of the skipped line is generated by the memory control unit 2 and written to the frame memory 1.

  As shown in FIG. 2B, in one vertical synchronization period on the display side, there are blanking periods OVB1 and OVB2 before and after, and valid data is read out during the period excluding the blanking period (a straight line indicated by a broken line). .

  Here, since the display-side synchronization signal is generated without being synchronized with the input-side synchronization signal, the input vertical synchronization period shown in FIG. 2A and the output vertical synchronization period shown in FIG. 2B are not the same. As for the blanking period, the blanking period on the display side is arbitrarily determined by the characteristics of the display device, so the blanking period on the input side (IVB1, IVB2) and the blanking period on the display side (OVB1, OVB2). Will not be the same. For this reason, overtaking may occur in reading video data from the frame memory 1.

  FIG. 3 shows the input vertical synchronization period shown in FIG. 2A and the output vertical synchronization period shown in FIG. 2B in an overlapping manner. Overtaking occurs when the timing of writing input video data indicated by a solid line into the frame memory 1 and the timing of reading video data from the frame memory 1 indicated by a broken line intersect (tOVER).

Whether overtaking occurs can be determined from the generation timing of the input vertical synchronization signal (IVS) and the output vertical synchronization signal (OVS). As shown in FIG. 4, when the OVS signal is generated before and after the generation of the IVS signal (period shown by hatching), an intersection (tOVER) as shown in FIG. 3 appears and overtaking occurs. Conversely, if the OVS signal is generated outside the hatching period of FIG. 4, no overtaking occurs. Therefore, when the timings of the IVS signal and the OVS signal gradually shift, the memory unit to be read is switched before the OVS signal enters the hatching period (that is, while the OVS signal is within the memory switching period). , Can avoid overtaking. The near_on signal and the near_off signal shown in FIG. 5 are arranged within the memory switching period of FIG. In the present embodiment, the memory unit to be read and detected while a period in which overtaking does not occur is switched. However, even if the memory unit to be read and detected in a period in which overtaking occurs is switched, an equivalent process is performed.

  Next, FIG. 6 is a timing chart showing a state of processing in the speed difference detection unit 8. The speed difference detector 8 determines the speed difference of the OVS signal with respect to the IVS signal from the near_off signal and the OVS signal. When the cycle of the OVS signal is faster than the cycle of the IVS signal, the ov_direction signal is output as “0”, and when the cycle of the OVS signal is slower than the cycle of the IVS signal, the ov_direction signal is output as “1”. To do. As illustrated in FIG. 6, the speed difference detection unit 8 sets the ov_direction signal to “1” when a rising change of the OVS signal is detected during a period in which the near_off (1) signal is “1”. If the rising change of the OVS signal is detected during the period when the near_off (2) signal is “1”, the ov_direction signal is set to “0”.

  When the period of the OVS signal is slower than the period of the IVS signal, the OVS signal moves away from the IVS signal, and passes the assert period of the near_off (2) signal after passing the assert period of the near_off (1) signal. . In the meantime, the ov_direction signal is output as “1”. When the OVS signal cycle is faster than the IVS signal cycle, the OVS signal moves closer to the IVS signal, and after passing the near_off (2) signal assertion period, the near_off (1) signal assertion period is increased. pass. During this period, the ov_direction signal is output as “0”.

As described above, the speed difference between the IVS signal and the OVS signal can be easily determined by using the near_on signal, the near_off signal, and the OVS signal.

FIG. 7 is a timing chart showing a state of processing in the overtaking avoidance detecting unit 9. The overtaking avoidance detection unit 9 detects the OVS from the near_on signal, the near_off signal, and the OVS signal.
It is determined whether or not the signal is in the vicinity of the switching timing of the memory unit to be read. As shown in FIG. 7, the overtaking avoidance detection unit 9 performs O during the period when the near_on signal is output as “1”.
When the rising change of the VS signal is detected, the near signal is set to “1”. The overtaking avoidance detection unit 9 outputs the near signal as “0” when the rising change of the OVS signal is detected during the period when the near_off (1) signal or the near_off (2) signal is output as “1”. To do.

FIG. 8 is a timing chart showing the state of processing in the output memory selection unit 7. The output memory selection unit 7 selects one of the lat_IBA (1) signal, the lat_IBA (2) signal, and the lat_IBA (3) signal based on the ov_direction signal and the near signal, and outputs the selected signal as a lat_IBA_sel signal. As shown in FIG. 8, the output memory selection unit 7 first generates an ov_direction_lat signal holding the state of the ov_direction signal and a near_lat signal holding the state of the near signal at the timing of the lat_signal signal. Next, when the near_lat signal is “0”, the lat_IBA (2) signal is selected and output as the lat_IBA_sel signal. When the near_lat signal is “1”, either the lat_IBA (1) signal or the lat_IBA (3) signal is selected according to the state of the ov_direction_lat signal and output as the lat_IBA_sel signal. When the ov_direction_lat signal is “1”, the lat_IBA (1) signal is selected as shown in FIG. 8A, and when the ov_direction_lat signal is “0”, as shown in FIG. 8B, lat_IBA (3) A signal is selected and output.

The input memory selection signal holding unit 4 holds the state of the IBA signal at the timing when the lat_IBA_sel signal changes and outputs it as an IBA_lat signal. The output memory selection signal generator 5 is OV
The state of the IBA_lat signal is held at the timing when the S signal changes, and is output as an OBA signal.

  The output timing signal generator 10 generates and outputs a vertical synchronization signal (OVS), a horizontal synchronization signal (OHS), and an effective data signal (OACT) as timing signals for outputting video data stored in the frame memory 1. To do.

The operation of the memory control device described above is shown in the timing chart of FIG. FIG. 9A shows a state in which the OVS signal is generated at a position away from the assert period of the near_on signal. (B) shows a state in which the OVS signal is generated in the assert period of the near_on signal in the state where the ov_direction signal is “1”. (C) shows a state in which the OVS signal is generated in the assert period of the near_on signal in the state where the ov_direction signal is “0”. Since the OVS signal is generated asynchronously with the IVS signal, any of the states (a) to (c) can occur.

  The IBA signal repeats the count-up operation with a value from “0” to “3” in synchronization with the rising change of the IVS signal.

In FIG. 9A, since the near signal is “0”, the output memory selection unit 7 outputs the lat_IBA_sel signal at the timing of the lat_IBA (2) signal. The input memory selection signal holding unit 4 outputs the state of the IBA signal at that time as an IBA_lat signal. The output memory selection signal generation unit 5 outputs the state of the IBA_lat signal as an OBA signal at the rising change timing of the OVS signal.

In FIG. 9B, since the near signal is “1” and the ov_direction signal is “1”, the output memory selection unit 7 outputs the lat_IBA_sel signal at the timing of the lat_IBA (1) signal. The input memory selection signal holding unit 4 outputs the state of the IBA signal at that time as an IBA_lat signal. The output memory selection signal generation unit 5 outputs the state of the IBA_lat signal as an OBA signal at the rising change timing of the OVS signal.

In FIG. 9C, since the near signal is “1” and the ov_direction signal is “0”, the output memory selection unit 7 outputs the lat_IBA_sel signal at the timing of the lat_IBA (3) signal. The input memory selection signal holding unit 4 outputs the state of the IBA signal at that time as an IBA_lat signal. The output memory selection signal generation unit 5 outputs the state of the IBA_lat signal as an OBA signal at the rising change timing of the OVS signal.

<Example of overtaking avoidance>
FIG. 10 to FIG. 13 show how a stable overtaking avoidance process is performed even in a video signal in which a vertical synchronization signal in an input video is output at a different period for each field by the operation of the memory control device described above. We will explain in.

10 and 11 show a case where the cycle of the OVS signal is slower than the cycle of the IVS signal. FIG. 10 shows a comparative example (an example in which the change timing of the IBA_lat signal is fixed), and FIG.
The operation | movement of the memory control apparatus of this embodiment is shown.

Here, the input video signal is an interlaced video signal and has a different period for each field. That is, the cycle of the IVS signal in the even field is tIVS1, the cycle of the IVS signal in the odd field is tIVS2, and tIVS1 and tIVS2 have the relationship of Equation 1.

tIVS1 <tIVS2 ... Formula 1

The OVS signal is generated at a constant period (tOVS1), and the IVS signal and the OVS signal are in the relationship of Expressions 2 to 4.

(TIVS1 + tIVS2) <tOVS1 × 2 Equation 2
tIVS1 <tOVS1 Equation 3
tIVS2> tOVS1 Equation 4

As shown in FIG. 10, the IBA signal repeats the count-up operation with a value from “0” to “3” in synchronization with the rising change of the IVS signal. The state of the IBA signal is further maintained at a constant timing (here, the timing of the lat_IBA (2) signal) from the rising change of the IVS signal, and the IBA_lat signal is generated. Here, since the IVS signal is output at a different period for each field, the timing of the lat_IBA (2) signal also changes in synchronization with the IVS signal. IBA_lat
The state of the signal is held at the rising change timing of the OVS signal and is output as an OBA signal.

In FIG. 10, at the rising change timing of the OVS signal indicated by t1 and t2, the state of the IBA_lat signal at that time is output to the OBA signal, and the OBA signal changes to “0” and “1”.
If the OBA signal is changed to “2” or “3” as it is, overtaking occurs in the video data read from the frame memory 1. However, since the value of “3” generated at the timing of the lat_IBA (2) signal is output as the OBA signal at the timing of t3, overtaking occurs by skipping the video data stored in the memory unit of BA2. Is avoided.

  However, since the IVS signal and the OVS signal are in the relationship of Equations 2 to 4, the value “3” is output again as the OBA signal at the timing t4. Therefore, the video data stored in the memory unit BA3 is continuously read from the frame memory 1. Furthermore, since the value of “1” is output as the OBA signal at the timing of t5, the video data stored in the memory unit of BA0 is skipped. As a result, an image that changes at 60 Hz is displayed for a certain period as an image that changes at 30 Hz, resulting in an unnatural display.

FIG. 11 is a timing chart showing the operation of the memory control device of this embodiment. At the timing t1, since the rising change of the OVS signal occurs during the period when the near_off (1) signal is output as “1”, the ov_direction signal changes to “1”. At the timing of t2, since the rising change of the OVS signal occurs during the period when the near_on signal is output as “1”, the near signal changes to “1”. Since the near signal has changed to “1”, the ov_direction signal is “1” from the period of the next IVS signal, so the lat_IBA (1) signal is selected and output as the lat_IBA_sel signal.

After that, at the timing of t5, it is OV during the period when the near_off (2) signal is output as “1”
Since the rising change of the S signal occurs, the ov_direction signal and the near signal change to “0”. From the period of the next IVS signal, the lat_IBA (2) signal is again selected and output as the lat_IBA_sel signal. The IBA_lat signal is output while holding the state of the IBA signal at the timing when the lat_IBA_sel signal is output. Further, the state of the IBA_lat signal is held at the rise change timing of the OVS signal and is output as an OBA signal.

  As shown in FIG. 11, by performing the processing described in this configuration, the occurrence of overtaking can be avoided by skipping the video data stored in the memory unit of BA2 at the timing t3. After that, the video data stored in the memory units BA0 to BA3 are sequentially read again, and the deterioration of the quality of the moving image as shown in FIG. 10 can be avoided.

12 and 13 show a case where the cycle of the OVS signal is faster than the cycle of the IVS signal. FIG. 12 shows a comparative example (an example in which the change timing of the IBA_lat signal is fixed), and FIG.
The operation | movement of the memory control apparatus of this embodiment is shown.

  Here, the input video signal is an interlaced video signal similar to that shown in FIG. 10, and has a different period for each field.

The OVS signal is generated at a constant cycle (tOVS2), and is generated at a cycle faster than the cycle (tOVS1) shown in FIG. That is, the relationship between tOVS1 and tOVS2 is assumed to be the relationship of Equation 5.

tOVS1> tOVS2 ... Formula 5

Further, it is assumed that the IVS signal and the OVS signal shown in FIG.

(TIVS1 + tIVS2)> tOVS2 × 2 Equation 6
tIVS1 <tOVS2 ... Formula 7
tIVS2> tOVS2 ... Formula 8

  As shown in FIG. 12, the IBA signal repeats the count-up operation with a value from “0” to “3” in synchronization with the rising change of the IVS signal. The state of the IBA signal is further maintained at a constant timing (here, the timing of the lat_IBA (2) signal) from the rising change of the IVS signal, and the IBA_lat signal is generated. The state of the IBA_lat signal is held at the rise change timing of the OVS signal, and is output as the OBA signal.

In FIG. 12, at the timing of the rising change of the OVS signal indicated by t10 and t11, the state of the IBA_lat signal at that time is output to the OBA signal, and the OBA signal changes to “0” and “1”. If the OBA signal is changed to “2” or “3” as it is, overtaking occurs in the video data read from the frame memory 1. However, at the timing of t12, the value “1” generated at the timing of the lat_IBA (2) signal is output as the OBA signal.
The occurrence of overtaking can be avoided by reading the video data stored in the memory unit twice.

However, since the IVS signal and the OVS signal have a relationship of Expressions 6 to 8, a value of “3” is output as the OBA signal at the timing of t13. As a result, the video data stored in the memory unit of BA2 is skipped from the frame memory 1. Furthermore, since the value of “3” is output as an OBA signal at the timing of t14, the video data stored in the memory unit of BA3 is read again. As a result, an image that changes at 60 Hz is displayed for a certain period as an image that changes at 30 Hz, resulting in an unnatural display.

FIG. 13 is a timing chart showing the operation of the memory control device of this embodiment. t11
At this timing, since the rising change of the OVS signal occurs during the period when the near_off (2) signal is output as “1”, the ov_direction signal changes to “0”. At the timing t12, since the rising change of the OVS signal occurs during the period when the near_on signal is output as “1”, the near signal changes to “1”. Since the near signal has changed to “1”, the ov_direction signal is “0” from the period of the next IVS signal, so the lat_IBA (3) signal is selected and output as the lat_IBA_sel signal.

Thereafter, at the timing of t14, the rise of the OVS signal occurs during the period in which the near_off (1) signal is output as “1”, so that the ov_direction signal and the near signal change to “0”. From the period of the next IVS signal, lat_IBA (2) is again selected and output as the lat_IBA_sel signal. The IBA_lat signal is output while holding the state of the IBA signal at the timing when the lat_IBA_sel signal is output. Further, the state of the IBA_lat signal is held at the rise change timing of the OVS signal and is output as an OBA signal.

As shown in FIG. 13, by performing the processing described in this configuration, the occurrence of overtaking can be avoided by reading the video data stored in the memory unit of BA1 twice at the timing t12. After that, the video data stored in the memory units BA0 to BA3 are sequentially read again, and it is possible to avoid the deterioration of the quality of the moving image as shown in FIG.

  According to the configuration described above, the input video signal and the vertical sync signal on the display side are in an asynchronous relationship, and the video signal in which the vertical sync signal in the input video is output with a different period for each field is stable. The overtaking avoidance process is performed. In addition, it is possible to avoid image quality deterioration that causes unnatural movement such as temporarily displaying images repeatedly.

  Furthermore, according to this configuration, it is possible to suppress the occurrence of chattering due to jitter that occurs when the input video signal and the vertical synchronization signal on the display side are close as shown in Patent Document 3.

In addition, since the speed difference between the IVS signal and the OVS signal is detected and the change timing of the IBA_lat signal is adjusted according to the detection result, it is automatic in both cases where the OVS signal is faster and the OVS signal is slower. Can be handled.

DESCRIPTION OF SYMBOLS 1 Frame memory 2 Memory control part 3 Input memory selection signal generation part 4 Input memory selection signal holding part 5 Output memory selection signal generation part 6 Detection timing signal generation part 7 Output memory selection part 8 Speed difference detection part 9 Overtaking avoidance detection part 10 Output timing signal generator

Claims (5)

A memory having a plurality of areas;
Image data is sequentially written in each area of the memory in synchronization with a first synchronization signal, and image data is read from the memory in synchronization with a second synchronization signal generated asynchronously with the first synchronization signal. A memory controller;
A timing determination unit that determines a reference timing based on the first synchronization signal;
An area determination unit that determines an area to be read by the memory control unit based on the reference timing and the order of the second synchronization signals;
A replacement period detection unit that detects a replacement period that is a period in which the switching of the order of the reference timing and the second synchronization signal is predicted to occur;
With
The memory controller according to claim 1, wherein the timing determination unit changes the reference timing in the replacement period in a direction in which the order change is likely to occur. A speed difference detector for detecting which one of the period of the second synchronization signal and the period of the first synchronization signal is faster;
When the period of the first synchronization signal is faster, the timing determination unit sets the reference timing within the replacement period to a first timing that is earlier than a second timing that is a reference timing outside the replacement period. And
The timing determination unit sets the reference timing within the replacement period to a third timing that is later than the second timing when the cycle of the second synchronization signal is faster. 2. The memory control device according to 1. The speed difference detector is
Check the order of the second synchronization signal and the second timing before the replacement period,
When the second synchronization signal is preceded, it is determined that the cycle of the first synchronization signal is faster,
3. The memory control device according to claim 2, wherein when the second timing is preceded, it is determined that the cycle of the second synchronization signal is faster. A window setting unit that sets a first window before the second timing and sets a second window after the second timing;
The speed difference detection unit determines that the period of the first synchronization signal is faster when the second synchronization signal is detected in the first window, and the second synchronization signal is detected in the second window. 4. The memory control device according to claim 3, wherein when the signal is detected, it is determined that the cycle of the second synchronization signal is faster. A method of controlling a memory having a plurality of areas,
A writing step of sequentially writing image data in each area of the memory in synchronization with a first synchronization signal;
A reading step of reading image data from the memory in synchronization with a second synchronization signal generated asynchronously with the first synchronization signal;
In the reading step, an area to be read is determined based on the order of the reference timing determined based on the first synchronization signal and the second synchronization signal,
The control method further includes:
Detecting a replacement period, which is a period during which a change in the order of the reference timing and the second synchronization signal is expected to occur;
A step of changing the reference timing within the replacement period in a direction in which the change of the order is likely to occur.

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