JP2013161362A - Information processing device and program execution method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device which can reduce a processing load of a CPU compared to the case of obtaining a processing result by execution of an instruction, in the situation in which the same processing result is obtained.SOLUTION: An information processing device 100 comprises: program storage means 24 which stores a program 14; input value acquisition means 12 and 25 which acquire an input value of the program; arithmetic means 23 which generates an output value from the input value by executing the program; value storage means 16 which stores a past input value and the output value in association with each other; comparison means 13 which compares the input value acquired by the input value acquisition means with the input value stored in the value storage means; and execution control means 11 which adopts the output value in the value storage means as the output value of the program without causing the arithmetic means to execute the program when the input value acquired by the input value acquisition means matches the input value stored in the value storage means.

Description

  The present invention relates to an information processing apparatus that executes a program, and more particularly to an information processing apparatus that generates an output value using an input value.

  In-vehicle devices such as engines and motors are being electronically controlled, but there is a tendency that the number of electronic control units (ECUs) mounted on one vehicle increases. For this reason, so-called function integration in which a plurality of functions are mounted on one electronic control device is being promoted. However, if a plurality of functions are to be provided by a single electronic control device, the processing capability may be insufficient.

  As one of the measures for dealing with the shortage of processing capacity, it is conceivable to reinforce the processing capacity of the electronic control unit. For example, the processing capability can be reinforced by increasing the operation clock of the CPU mounted on the electronic control unit. However, since the power consumption of the CPU increases in proportion to the operation clock, there is an inconvenience of an increase in power consumption and an accompanying increase in heat generation. Further, for example, the processing capability can be reinforced by mounting a multi-core CPU in the electronic control unit. However, since the multi-core CPU is expensive, there is an inconvenience that the cost of the electronic control device is increased.

  Therefore, it is conceivable to reduce the processing load on the CPU (for example, see Patent Document 1). Patent Document 1 discloses a program control device that repeatedly executes the same instruction for the number of times set in a repeat register. According to this program control device, once an instruction is read, it is possible to reduce the overhead of reading the instruction and setting the number of repetitions while executing the same instruction.

JP 08-286912 A

  However, the program control device disclosed in Patent Document 1 has a problem that the processing load on the CPU cannot be greatly reduced because the same instruction is repeatedly executed. That is, when the same instruction is executed using the same input data, the processing result is the same. However, in Patent Document 1, since the instruction is executed without considering the identity of the input data, the processing load can be reduced. The processing load cannot be reduced.

  In view of the above problems, an object of the present invention is to provide an information processing apparatus that can reduce the processing load of a CPU in a situation where the same processing result is obtained, compared to a case where a processing result is obtained by executing an instruction.

  The present invention includes a program storage unit that stores a program, an input value acquisition unit that acquires an input value of the program, and an arithmetic unit that generates an output value by executing the program that performs processing using the input value. A value storage means for storing the past input value and the output value in association with each other; a comparison means for comparing the input value acquired by the input value acquisition means with the input value stored by the value storage means; When the input value acquired by the input value acquisition means matches the input value stored by the value storage means, the output value of the value storage means is not executed by the calculation means. An information processing apparatus having execution control means employed as the output value of the program is provided.

  In a situation where the same processing result is obtained, it is possible to provide an information processing apparatus that can reduce the processing load of the CPU as compared with the case where the processing result is obtained by executing an instruction.

It is an example of the figure explaining the schematic characteristic of the microcomputer of this embodiment. It is an example of the hardware block diagram of ECU. It is an example of the functional block diagram of a microcomputer. It is an example of the figure which shows the execution procedure of the function I, and the execution procedure of the function II. It is an example of the figure which illustrates an example of a last time value table typically. It is an example of the figure which illustrates dependency relationship data typically. It is an example of the flowchart figure which shows the operation | movement procedure in which a microcomputer performs the function I. It is an example of the functional block diagram of a microcomputer. It is an example of a steady state determination result table. It is an example of the flowchart figure explaining the process of a steady state determination part.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is an example of a diagram illustrating schematic features of the microcomputer 100 of the present embodiment. The microcomputer 100 is equipped with a plurality of functions I and II by function integration. Function I and function II are functional blocks that process input values and output output values. Examples of the function block include a program, a function in the program, a task, or a thread.

  The microcomputer 100 of this embodiment stores the previous input value and the previous output value of each of the functions I and II. When the current input value is given and the function I is executed, the microcomputer 100 compares the current input value with the previous input value, and when they match, outputs the stored previous output value without executing the function I. To do.

  For example, if the input value of function I is the input value a, the microcomputer compares the current input value a with the previous input value a. If they match, the microcomputer uses the stored previous output value z as the output value of function I. To do. If the input value this time matches the previous input value, the microcomputer 100 does not need to execute the corresponding function I or function II, so the processing load on the CPU can be reduced.

  By the way, when the vehicle is in a stable state as seen from each of the functions I and II, the input values of the functions I and II tend to be constant. As the state where the vehicle is stable, for example, a state where the vehicle stops, a state where the vehicle travels on a straight line at a constant vehicle speed, a state where the vehicle accelerates at a constant acceleration, etc. are assumed. Is different for each function.

  In the present embodiment, a state in which the vehicle is stable as viewed from each of the functions I and II is referred to as a “steady state”. Therefore, the steady state can be defined as a state in which the previous input value and the current input value match. A state that is not in a steady state is referred to as a high load state.

  Here, since the function I and the function II are mounted on one microcomputer 100 by function integration, the functions are highly independent. For this reason, even if the function I is in the steady state, the function II is not necessarily in the steady state, and the microcomputer 100 can be expected to be in a state where the functions in the steady state and the functions in the high load state are mixed.

  Since the microcomputer 100 of this embodiment can reduce the processing load in the steady state, the processing load at the peak of the microcomputer 100 can be suppressed in a situation where independent functions are mixed. Therefore, the specification of the microcomputer 100 can be reduced, power can be saved, and heat generation can be suppressed.

  In this embodiment, the description will be made on the assumption that the microcomputer 100 has a plurality of functions I and II integrated by function integration. However, there is even one function that uses an input value regardless of the presence or absence of function integration. For example, it can be applied to each microcomputer. However, the processing load reduction method of the present embodiment can be more suitably applied to the function-integrated microcomputer 100 in which a plurality of functions can be expected to be in a steady state independently.

[Configuration example]
FIG. 2 shows an example of a hardware configuration diagram of the ECU 200. The ECU 200 includes an input I / F 11, a power supply circuit 14, a microcomputer 100, and an output I / F 13. In addition, although it has a communication device for communicating with other electronic control devices such as a CAN controller, the illustration is omitted.

  There are various types of ECU 200 mounted on the vehicle. For example, HV-ECU (Electronic Control Unit), engine ECU, brake ECU, body ECU, power steering ECU, navigation ECU (AV / information processing ECU), gateway ECU, and the like are known. The ECU of this embodiment may have these multiple functions by function integration. Moreover, it is possible to reduce the processing load regardless of what functions are installed.

  The power supply circuit 14 detects ON / OFF of the IG-SW 15. When the ON state of the IG-SW 15 is detected, the power supply circuit 14 steps down the power supplied from the battery 16 as necessary and supplies it to the input I / F 11, the microcomputer 100, and the output I / F 13. In addition, when the IG-SW 15 is detected to be OFF, the power supply circuit 14 stops supplying power to each circuit. For example, the power may be supplied only to the RAM 25 to hold the parameters. By such power saving control at the time of IG-OFF, the ECU 200 can use the parameter calculated (learned) at the time of IG-ON after the next IG-ON, thereby improving the operability and the like.

  Various sensors are connected to the input I / F 11. The input I / F 11 functions as a multiplexer, reads the detection signal of each sensor based on time division or priority, and transmits it to the A / D 21 or I / O 22 of the microcomputer 100 together with the sensor identification information. Further, the input I / F 11 may acquire a detection signal from the sensor in response to an instruction from the CPU 23, or may acquire a detection signal from the sensor even if there is no instruction.

  The microcomputer 100 includes an A / D 21, an I / O 22, a flash ROM 24, a RAM 25, an I / O 26, and a WDT 27 that are connected to the CPU 23 via a bus. The I / O 22 notifies the CPU 23 of the detection signal input from the input I / F 11 together with the type of the detection signal using a mechanism such as an interrupt. The A / D 21 is a circuit that converts an analog detection signal into a digital detection signal, and notifies the CPU 23 of the converted detection signal together with the type of the detection signal using a mechanism such as an interrupt.

  The WDT 27 is a circuit that counts up the passage of time by dividing the operation clock by a division ratio set in a control register or the like. When the measured time reaches a predetermined reset time (overflow), fail-safe processing such as resetting the microcomputer 100 is performed. The CPU 23 clears the time that is regularly measured before the WDT 27 overflows. Therefore, while the WDT 27 does not reset the microcomputer 100, it can be estimated that the CPU 23 is executing each function within the expected time. Note that the WDT 27 may be arranged not on the microcomputer but on an electronic control device outside the microcomputer.

  The CPU 23 executes a program stored in the flash ROM 24 to read a detection signal, calculate, map, write to the RAM 25, or output to the I / O 26. This program includes a plurality of functions I and II. These specific processing contents vary depending on the type and function of the ECU 200.

  The subsequent I / O 26 outputs the calculation result to the output I / F 13 together with the identification information of the control target and the assertion of the chip selection line in response to an instruction from the CPU 23. The output I / F 13 is connected to various actuators. The output I / F 13 controls the actuator by outputting, for example, a D / A converted voltage value to the actuator. The output I / F 13 is, for example, a switch element, and energizes the solenoid to control opening and closing of the relay. The output I / F 13 is, for example, a driver circuit, which converts a DC voltage into an AC voltage and controls the rotation speed of the motor.

  FIG. 3 shows an example of a functional block diagram of the microcomputer 100. The microcomputer 100 has a function I and a function II. Function I and function II are functions mounted in separate ECUs. The CPU 23 of the microcomputer 100 executes the function I and the function II independently.

  4A shows the execution procedure of function I, and FIG. 4B shows the execution procedure of function II. When the CPU 23 is a single core, the microcomputer 100 executes the functions I and II by time-sharing resources including the CPU 23. For example, the CPU 23 may mechanically repeat the execution of the function I and the function II by reading the program in the order of addresses, or the function I and the function II may set a timer at the end of the execution and start execution by a timer interrupt. Good. Further, for example, a scheduler of an OS (Operating System) may be repeatedly executed by assigning the functions I and II to resources such as the CPU 23. In this case, instead of executing the entire functions I and II, the contexts may be switched at predetermined slice times.

  Returning to FIG. 3, the function I includes an overall control unit 11, a latch processing unit 12, a steady state determination unit 13, and a sub-function 14 (hereinafter referred to as sub-functions A to F when distinguished). The function II also has an overall control unit 11, a latch processing unit 12, a steady state determination unit 13, and sub-functions G and H. However, since the contents of the function I and the function II in the characteristic part of this embodiment are the same, the function II Description is omitted. Three or more functions may be integrated.

[Input value Output value]
The overall control unit 11 is, for example, a Main function, and executes each functional block according to the order in which each functional block is described or the determination result of conditions such as timing and flag.

  Among the functional blocks, the sub-functions A to F are functions included in the function I before function integration. The sub functions A to F are, for example, one or more functions or subroutines. In the case of a function, when an argument is given from the caller, processing specific to the function is performed and a return value is returned to the caller. The caller is, for example, the overall control unit 11 or another function. The subroutine is similar, but there may be no return value. In some cases, the function or subroutine directly controls the actuator or the like. In this case, the control result is returned to the caller. Therefore, in the subfunctions A to F, the input value is, for example, an argument, and the output value is, for example, a return value or a calculation result of a function or subroutine.

  The input value includes a static variable, a register value, or a function itself, but what is the input value is determined in advance for each of the sub machines A to F. The output value includes a variable, a register value, a true / false variable, and the output value is predetermined for each of the sub functions A to F. Sub-functions A to F read the output value corresponding to the input value by referring to the map based on the input value, perform the four arithmetic operations and shift operation on the input value to generate the output value, and compare the input value and the threshold value Then, a process of using the determination result as an output value is performed.

[Dependency determination of steady state]
The overall control unit 11 first calls the latch processing unit 12 to latch the input values of the sub functions A to F. The latched input value is the current input value. Latch means collection or acquisition. In the latch processing unit 12, all input values of the sub functions A to F are listed in advance. The latch processing unit 12 reads and latches the input values of the sub functions A to F from the RAM or from the register. These are data detected by a sensor (not shown), data received by CAN communication, data received by a DCM (Data Communication Module), etc. via a mobile phone network.

  For example, the subfunctions A to F may use the processing result (output value) of another subfunction as an input value. In this case, the input value is acquired at the timing when the subfunctions A to F have processed. In the present embodiment, to simplify the description, it is assumed that the sub functions A to F do not use the processing result of another sub function as an input value, for example.

  The latch processing unit 12 latches all the current input values listed up and returns them to the overall control unit 11. The overall control unit 11 calls the steady state determination unit 13 and passes all current input values to the steady state determination unit 13 as arguments.

  The steady state determination unit 13 determines whether or not the function I is in a steady state by comparing the previous input value registered in the previous value table 16 with the current input value. When determining whether or not it is in a steady state, the steady state determination unit 13 refers to the dependency relationship data 15 to determine whether or not each sub function group having a dependency relationship is in a steady state.

  FIG. 5 is an example of a diagram for schematically explaining an example of the previous value table 16. In the previous value table 16, the previous input value and the previous output value are recorded for each sub-function. The steady state determination unit 13 determines whether or not the current input value matches the previous input value for each sub-function. For example, since the input values of the sub-function A are two values a1 and a2, the steady state determination unit 13 determines that the input values match if both the current input values a1 and a2 match the previous input values a1 and a2.

  Input values do not have to match in all significant digits. For example, if the developer knows that the value of the smallest digit among the input values of three digits does not greatly affect the output value, only the upper two digits of the input value need be compared. If it is known that digits after the decimal point do not significantly affect the output value, only integer digits need to be compared. In this way, by relaxing the criteria for determining whether or not they match, it is easier to determine the steady state and the processing load on the microcomputer 100 can be reduced.

  FIG. 6 is an example of a diagram for schematically explaining the dependency relationship data 15. In FIG. 6, each sub-function is connected in a tree shape. In the dependency relationship data 15, the dependency relationship between the sub-functions is registered. Dependencies include processing dependencies with restrictions on processing order and data dependencies that require data of other subfunctions. Since the dependency relationship is fixed, a developer or the like can extract the dependency relationship in advance and register it in the dependency relationship data 15. According to FIG. 6, sub function C is dependent on sub function B, sub function B is dependent on sub function A, and sub function D is dependent on sub function A.

  If there is such a dependency, even if the previous input value of the subfunction C and the current input value match, the previous input value of the subfunction A or the subfunction B does not match the current input value. The processing result of function C may be affected. If the previous input value of the subfunction A and the current input value match, but the previous input value of the subfunction B or C does not match the current input value, the return value to the subfunction A is set. Impact may occur. Therefore, in this embodiment, when the previous input value and the current input value of all subfunctions having a dependency relationship match, it is determined that the subfunction group is in a steady state. That is, it is determined whether or not each sub-function group is in a steady state.

  In the example of FIG. 6, one sub-function group is sub-functions A to D, and the other sub-function group is sub-functions E and F. There is only one sub-function with no dependency relationship, which is one sub-function group. Therefore, the steady state determination unit 13 determines whether or not the previous input values of the sub-functions A to D and the current input value all match, and the previous input values of the sub-functions E and F and the current input value all match. It is determined whether or not.

  Even when the function tree as shown in FIG. 6 is extracted, for example, it may be determined that the upper subfunction A is not affected by the processing results of the subfunctions B to D. Such knowledge is known to developers. Therefore, when a developer or the like identifies some upper subfunctions in the function tree, the steady state determination unit 13 separates from the lower subfunctions so that the previous input value matches the current input value. It can be determined whether or not (steady state). In this case, some upper sub-functions become sub-function groups.

  The steady state determination unit 13 registers the current input value used for comparison with the previous input value in the previous value table 16 as a new previous input value. As a result, the previous input value in the previous value table 16 is updated to the latest input value.

  The steady state determination unit 13 notifies the overall control unit 11 of the determination result as to whether or not the steady state exists for each sub-function group (or for each sub-function). The overall control unit 11 does not execute a steady state sub-function among the sub-functions A to F. Thereby, the processing load of CPU23 of the microcomputer 100 can be reduced.

  Then, the overall control unit 11 reads the previous output value of the sub function determined to be in the steady state from the previous value table 16. In addition, the overall control unit 11 passes and executes the current input value to the sub-function that has not been determined to be in the steady state, and acquires the current output value of each sub-function from each sub-function. Then, the previous output value in the previous value table 16 is updated with the current output value output by the sub-function. By doing so, the latest output value of the previous value table 16 can also be maintained as the latest output value.

[Operation procedure]
FIG. 7 is an example of a flowchart illustrating an operation procedure in which the microcomputer 100 executes the function I. The procedure of FIG. 7 is repeatedly executed, for example, periodically. In the function I, the overall control unit 11 is first executed. The overall control unit 11 calls the latch processing unit 12. Accordingly, the latch processing unit 12 latches all input values necessary for the function I (S10). The latch processing unit 12 returns all latched current input values to the overall control unit 11.

  The overall control unit 11 calls the steady state determination unit 13 using the current input value as an argument. Thus, the steady state determination unit 13 refers to the dependency relationship data 15 and determines whether or not the steady state is in units of sub-function groups (S20). Here, for example, it is assumed that the sub function groups of the sub functions E and F are in the steady state, and the sub function groups of the sub functions A to D are not in the steady state.

  Then, the overall control unit 11 sequentially executes the sub functions A to D of the sub function group determined not to be in the steady state. That is, the sub-function A is called with the current input value of the sub-function A as an argument, and the sub-function A is executed (S30). The sub function A returns the current output value to the overall control unit 11.

  Next, the sub function B is called with the current input value of the sub function B as an argument, and the sub function B is executed (S40). The subfunction B returns the current output value to the overall control unit 11.

  Next, the sub function C is called with the current input value of the sub function C as an argument, and the sub function C is executed (S50). The sub function C returns the current output value to the overall control unit 11.

  Next, the sub function D is called by using the current input value of the sub function D as an argument, and the sub function D is executed (S60). The sub function D returns the current output value to the overall control unit 11.

  Then, the overall control unit 11 omits the execution of the sub functions E and F even at the timing when the sub functions E and F are originally executed (S70, S80). The overall control unit 11 reads out the previous output values of the sub functions E and F from the previous value table 16 based on the determination result of the steady state determination unit 13 and adopts them as the output values of the sub functions E and F. Specifically, if there is an actuator or the like controlled by the output values of the sub-functions E and F, control is performed. If the sub-functions E and F directly control the actuator or the like by the output values, the sub-functions E and F are controlled. The output value is passed (in this case, the sub-functions E and F do not execute the operation). Further, the previous output values of the sub-functions E and F may be passed to another sub-function. Thereby, the load on the CPU 23 of the microcomputer 100 can be reduced.

  As described above, the microcomputer 100 according to the present embodiment can reduce the processing load on the CPU 23 that executes the steady-state function, so that the specifications of the microcomputer 100 and the CPU 23 can be reduced. In addition, since the power consumption of the CPU 23 is also reduced, fuel efficiency is improved and heat generation is suppressed, and the heat dissipation performance specifications of the ECU 200 can be reduced.

  In the first embodiment, the processing load is reduced by not executing the sub-function in the steady state, but a process for determining whether or not the steady state is present is necessary. For this reason, the processing amount of the sub-function determined not to be in the steady state is larger than that in the conventional case by the amount of determination processing for determining whether or not it is in the steady state. Therefore, in the present embodiment, a description will be given of the microcomputer 100 that learns the steady-state frequency of the sub-function and excludes from the determination target whether the sub-function that is less likely to be in the steady-state is a steady-state.

  FIG. 8 shows an example of a functional block diagram of the microcomputer 100 of the present embodiment. 8, the same parts as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted. The function I of the present embodiment has a new steady state determination result table 17. The steady state determination result table 17 is a table in which the number of times determined to be a steady state in the past is registered.

  FIG. 9A shows an example of the steady state determination result table 17. In the steady state determination result table 17, a determination opportunity, a steady determination count, and a non-steady determination count are registered for each sub-function. The determination opportunity is the number of opportunities for determining whether or not the sub-functions A to F are in a steady state. In the figure, the judgment opportunities are equally 100 times.

In the first embodiment, as shown in the flowchart of FIG. 7, when the function I is executed, all the sub functions A to F are executed. Therefore, it is determined whether or not all the sub functions A to F are in a steady state. It was. In the present embodiment, it is determined whether or not a steady state is reached in the following cases.
(I) Until a sufficiently large number of determination opportunities, it is determined whether or not the sub-function group is in a steady state only when the processing load of the microcomputer 100 is equal to or less than a predetermined value. (Ii) A sufficiently large number of determination opportunities After that, it is determined whether only the sub-function group whose omission execution probability is equal to or higher than the threshold is in a steady state. A sub-function group whose omission execution probability is less than the threshold is excluded from the determination target whether or not it is in a steady state.
(Iii) Only when the processing load of the microcomputer 100 is equal to or less than a predetermined value after the determination opportunity becomes a sufficiently large number, it is determined whether or not the sub-function group whose omission execution probability is less than the threshold is in a steady state. The processing load of 100 is provided from the OS of the microcomputer 100, for example, as a CPU load factor. The CPU load factor is obtained, for example, by dividing the value obtained by subtracting the idle task execution time from the unit time by the unit time.

  The number of times of steady determination is the number of times determined to be in a steady state, and the number of times of unsteady determination is the number of times determined to be not in a steady state. Therefore, there is a relationship of determination opportunity = number of steady determinations + unsteady determinations. In addition, since it is determined for each sub function group whether or not it is in a steady state, the number of times of steady determination is the same for the sub functions in the same sub function group.

  Each time the steady state determination unit 13 determines whether or not it is in the steady state, the determination opportunity is increased by one. If it is determined that the state is in the steady state, the steady determination number is increased by one. Increase the number by one.

In addition, when the number of determination opportunities becomes sufficiently large, the steady state determination unit 13 calculates an omitted execution probability when the processing load on the microcomputer 100 is not large.
Omission execution probability = 100 × number of regular determinations / determination opportunity In the example in the figure, the omission execution probability of the sub functions A to D is 70%, and the omission execution probability of the sub functions E and F is 30%. Then, the steady state determination unit 13 compares the omission execution probability with a threshold and holds a steady state determination omission flag corresponding to the comparison result. FIG. 9B is an example of a diagram showing a steady state determination omission flag. The steady state determination omission flag “1” indicates that the determination of the steady state is omitted, and the steady state determination omission flag “0” indicates that the determination of the steady state is performed.

  For example, a sub-function with an omission execution probability of less than 50% is executed once every two times, and therefore determination of whether or not it is in a steady state may increase the processing load. Developers, etc., determine the threshold value by taking into account how much load the steady state determination will be and reducing the load when execution is omitted.

  When the omission execution probability is less than the threshold value, the steady state determination unit 13 sets the steady state determination omission flag of the sub-function to “1” and holds it. For the sub-functions whose steady state determination omission flag is “1”, the determination of the steady state is omitted. As a result, the overall control unit 11 always executes the sub function whose steady state determination omission flag is “1”.

  As described in (iii) above, even after the steady state determination omission flag becomes “1”, the steady state determination unit 13 determines whether the microcomputer 100 is in a steady state when the processing load on the microcomputer 100 is low. Thus, the steady determination times and the unsteady determination times are updated. As a result, the steady state determination omission flag of the sub-function for which the number of steady determinations has increased is set to “0”, and can be the target of steady determination.

  FIG. 10 is an example of a flowchart for explaining the process of the steady state determination unit 13 of the present embodiment. The overall operation procedure is the same as in FIG. 7, and FIG. 10 shows the processing procedure of step S20 in FIG. The process of FIG. 10 starts when the overall control unit 11 calls the steady state determination unit 13 with the current input value as an argument.

First, the steady state determination unit 13 determines whether the determination opportunity is sufficiently large (S201). If the determination opportunity is sufficiently large (Yes in S201), the process proceeds to step S206.
When the determination opportunity is not sufficiently large (No in S201), the steady state determination unit 13 determines whether the processing load on the microcomputer is low (S202). If the processing load of the microcomputer is not low (No in S202), the processing load will be further increased if it is determined whether or not it is in the steady state, so the steady state determination unit 13 determines that all the sub-functions are not in the steady state ( S203). The determination result is returned to the overall control unit 11. In this case, the overall control unit 11 executes all the sub functions.

  When the processing load of the microcomputer is low (Yes in S202), the steady state determination unit 13 determines whether each sub-function is in a steady state (S204). Thereby, the determination opportunity can be increased.

  The steady state determination unit 13 updates the steady state determination result table 17 and returns the determination result to the overall control unit (S205). In this case, the overall control unit 11 executes only the sub-function that is determined not to be in the steady state.

  When the determination opportunity is sufficiently large (Yes in S201), the steady state determination unit 13 reads the steady state determination omission flag (S206).

  Then, it is determined whether or not the sub-function group has a sub-function whose steady state determination omission flag is “1” (S207). The reason for determining for each sub-function group is that it is determined for each sub-function group whether or not it is in a steady state. That is, if it is not determined whether or not one subfunction is in a steady state, the subfunction group is not determined to be in a steady state. Note that it is considered that the steady state determination omission flags of the sub functions of the same sub function group are in the same state.

  When the sub-function group has a sub-function whose steady state determination omission flag is “1” (Yes in S207), the steady-state determination unit 13 includes a sub function group including a sub-function whose steady state determination omission flag is “1”. It is not determined whether or not it is in a steady state (S208). Thereby, for example, the stationary determination of the sub-functions E and F can be omitted. Further, the overall control unit 11 always executes the sub functions E and F.

  If the sub-function group does not have a sub-function whose steady state determination omission flag is “1” (No in S207), the steady-state determining unit 13 determines whether each sub-function of the sub-function group is in a steady state (S209). . Thereby, the overall control unit 11 can omit the execution of the sub-function based on the determination result of whether or not the steady state. Before step S208, it may be determined whether or not the processing load of the microcomputer is low, and it may be determined whether or not it is in a steady state only when the processing load is low.

  Next, the steady state determination unit 13 determines whether or not the processing load of the microcomputer 100 is lower than a threshold value (S210).

  Then, only when the processing load of the microcomputer 100 is low (Yes in S210), the steady state determination unit 13 determines whether or not the sub-function that has not been determined whether or not the steady state is in the steady state (S211). By doing so, the sub function determination opportunities can be increased without increasing the processing load of the microcomputer 100.

  When the processing load of the microcomputer 100 is not low (No in S210), the steady state determination unit 13 updates the steady state determination result table (S212). That is, the determination opportunity, steady determination count, and non-steady determination count in the steady state determination result table 17 are updated, the omitted execution probability is calculated, and the steady state determination skip flag is updated by comparing with the threshold. In this way, when the steady state determination unit 13 is called next time, it can be determined whether or not to perform the steady determination based on the latest steady state determination omission flag.

  As described above, the microcomputer 100 according to the present embodiment can reduce the processing load of the CPU that executes the steady-state function in addition to the same effects as the first embodiment. In addition, since it is not necessary to determine whether or not a function is in a steady state, the processing load can be further reduced.

DESCRIPTION OF SYMBOLS 11 Overall control part 12 Latch process part 13 Steady-state determination part 14 Subfunction 15 Dependency relationship data 16 Previous value table 100 Microcomputer 200 ECU

Claims (5)

Program storage means for storing a program;
Input value acquisition means for acquiring an input value of the program;
An arithmetic means for generating an output value by executing the program for performing processing using the input value;
Value storage means for storing the past input value and the output value in association with each other;
Comparison means for comparing the input value acquired by the input value acquisition means with the input value stored by the value storage means;
When the input value acquired by the input value acquisition unit and the input value stored by the value storage unit match, the program stores the output value of the value storage unit without causing the calculation unit to execute the program. Execution control means employed as the output value of
An information processing apparatus. An execution omission frequency table in which the frequency at which the program is not executed by the computing unit is registered;
When the frequency registered in the execution omission frequency table is less than a threshold value, the comparison unit compares the input value acquired by the input value acquisition unit with the input value stored in the value storage unit. Omitted,
The information processing apparatus according to claim 1. A dependency table in which processing dependency relationships or data dependency relationships among the plurality of programs stored in the program storage unit are registered;
The comparison unit compares the input value acquired by the input value acquisition unit with the input value stored by the value storage unit for every program registered as having a dependency in the dependency relationship table. And
When the input value acquired by the input value acquisition unit for all the programs registered as having a dependency relationship in the dependency table matches the input value stored in the value storage unit,
The execution control means adopts the output value of the value storage means as the output value of the program without causing the calculation means to execute the program.
The information processing apparatus according to claim 1 or 2. When the program is a function written in a functional language,
The information processing apparatus according to claim 1, wherein the input value is a function argument, and the output value is a return value of the function. Program storage means for storing a program;
Input value acquisition means for acquiring an input value of the program;
A program execution method for an information processing apparatus, comprising: an arithmetic unit that executes the program and generates an output value from the input value,
A comparison means comparing the input value acquired by the input value acquisition means with the input value stored in the value storage means for storing the input value in the past and the output value in association with each other;
When the input value acquired by the input value acquisition means matches the input value stored by the value storage means, the execution control means does not cause the calculation means to execute the program, and the calculation means does not execute the program. Adopting an output value as the output value of the program;
A program execution method comprising:

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