JP2013132009A - Distortion compensator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of distortion compensation of a power amplifier.SOLUTION: An LMS algorithm using a feedback signal that is an output signal of a power amplifier 1 input via an attenuator 17 and pseudorandom data calculates a delay of an input signal to the power amplifier 1 and a delay of the feedback signal. Specifically, the delays of the input signal and feedback signal are calculated such that the delay of the input signal is only an integer delay. An input signal to the power amplifier 1 is adjusted on the basis of the calculated delay, and a delay of a feedback signal is adjusted by an SRC 42. Since the delay of the input signal is only an integer delay, a more accurate adjustment of the delay of the input signal times the input signal to the feedback signal with higher accuracy to improve DPD mode distortion compensation accuracy.

Description

  The present invention relates to a distortion compensator, a DPD system, and a control method for a DPD system.

Conventionally, various methods have been proposed as a method for compensating for distortion of a power amplifier. For example, a DPD system for compensating for distortion of a power amplifier using a DPD (Digital Pre-distortion) method has been proposed.
FIG. 12 is a configuration diagram illustrating an example of the DPD system 200. The operation principle of DPD distortion compensation will be described with reference to FIG. The DPD system 200 is a DPD system that performs distortion compensation of a power amplifier PA included in an RF-IC (Radio Frequency-Integrated Circuit).

  In FIG. 12, 101 is an input terminal for inputting an input signal, 102 is an output terminal for a signal after distortion compensation, 103 is a multiplier, 104 is a DA converter (DAC), 105 is a low-pass filter (LPF), and the like. 106 is a modulation unit (MOD), 107 is a power amplifier (PA) to be compensated for distortion, 108 is a carrier signal generator, 109 is an attenuator (ATT), and 110 is a look-up table (LUT). Table), 111 is a predistortion calculation unit, 112 is an AD converter (ADC), 113 is an anti-aliasing filter composed of a low pass filter (LPF), 114 is a demodulation unit (DEMOD), 115 is a delay adjustment unit, It is.

In the predistortion compensation calculation unit 111, a distortion characteristic opposite to the non-linear distortion generated in the power amplifier 107 is calculated, and the calculated reverse distortion characteristic data is stored in a lookup table 110 as a reverse distortion characteristic storage unit. To do.
In the DPD method, an LUT data (inverse distortion characteristic data) stored in a lookup table 110 and an input signal u (n) input to an input terminal 101 are multiplied by a multiplier 103 to have an inverse distortion characteristic. This is a method of canceling the distortion of the power amplifier 107 by generating the signal u (n) ′.

Note that the DPD method shown in FIG. 12 is a technique for obtaining the reverse distortion characteristics of the power amplifier 107 using a ramping signal that continuously increases as the input signal u (n).
Here, each waveform in FIG. 12 represents a waveform of an output signal in each part.
In such a DPD system 200, it is important to obtain a highly accurate reverse distortion characteristic of the power amplifier 107 in order to perform a good distortion correction of the power amplifier 107.

  For this purpose, it is necessary to match the timings of the input signal u (n) and the feedback signal. Here, the feedback signal is attenuated by the attenuator 109 so that the output of the power amplifier 107 becomes equal to the signal level before being amplified, down-converted to the baseband by the demodulator 114, and then the anti-aliasing filter 113. , And the signal after AD conversion by the AD converter 112 is meant.

  2. Description of the Related Art Conventionally, mobile phone base stations and the like calculate a feedback signal delay amount and inverse distortion compensation data by performing complex arithmetic processing such as matrix calculation using a DSP (Digital Signal Processor) (for example, (Refer nonpatent literature 1).

Dennis R. Morgan, Zhengxiang Ma, Jaehyeong Kim, Mishael G. Zierdt, and John Pastalan, "A Generalized Memory Polynomial Model for Digital Predistortion of RF Power Amplifiers", IEEE TRANSACTIONS ON SIGNAL PROSESSING, VOL.54, NO.10, OCTOBER 2006

Incidentally, in the mobile communication field such as portable terminals, low power consumption and area saving are required.
For this reason, when performing distortion compensation of a transmission signal of a portable terminal, it is difficult to incorporate a large-scale arithmetic circuit such as a DSP in an RF-IC (Radio Frequency-Integrated Circuit).
In addition, in a method in which a delay amount of a feedback signal depending on a system including a power amplifier to be compensated for distortion is estimated in advance and a delay stage corresponding to this delay amount is provided, a sufficient effect by the DPD method cannot be obtained. difficult.

  Therefore, the present invention has been made in view of the above points, and provides a distortion compensator capable of matching the timing of an input signal and a feedback signal with higher accuracy and further improving distortion compensation accuracy. The purpose is to do.

  A distortion compensator according to claim 1 of the present invention is a distortion compensator for compensating nonlinear distortion of a power amplifier, a delay circuit for adjusting a delay amount of an input signal, and feedback including nonlinear distortion from the power amplifier. The delay amount of the input signal and the delay amount of the feedback signal so that the timing of the SRC (Sample Rate Converter) that adjusts the delay amount of the signal matches the timing of the input signal and the feedback signal adjusted by the SRC. A delay amount setting unit that sets the delay amount of the input signal and the delay amount of the feedback signal based on pseudo-random data and the feedback signal. ) Set using an algorithm.

A distortion compensator according to a second aspect of the present invention is the distortion compensator according to the first aspect, further comprising a pseudo random data generator that generates the pseudo random data.
A distortion compensator according to a third aspect is the distortion compensator according to the first or second aspect, wherein the delay amount setting unit is configured such that the delay amount of the input signal is only an integer delay. And a delay amount of the feedback signal are set.

  The distortion compensator according to claim 4 is the distortion compensator according to any one of claims 1 to 3, wherein the delay amount setting unit generates an LMS output signal representing a delay amount of the input signal. A portion of the circuit constituting the delay amount setting unit excluding the signal generation unit is also used as a circuit constituting another system using the LMS algorithm, The circuit operates as a circuit constituting the other system except when setting the delay amount of the signal and the delay amount of the feedback signal.

  The distortion compensator according to claim 5 is the distortion compensator according to any one of claims 1 to 4, wherein the input signal delayed by the delay circuit and the feedback signal delayed by the SRC. A predistortion compensation calculation unit that calculates a distortion characteristic opposite to the non-linear distortion of the power amplifier based on the above, a storage unit that stores data for specifying the reverse distortion characteristic calculated by the predistortion calculation unit, and an input signal And an arithmetic unit that generates an input signal having the inverse distortion characteristic from the data stored in the storage unit, and outputs the generated signal to the power amplifier as the input signal after distortion compensation. It is a feature.

A DPD system according to a sixth aspect of the present invention includes the distortion compensator according to any one of the first to fifth aspects and the power amplifier.
Furthermore, a control method for a DPD system according to a seventh aspect of the present invention is a control method for a DPD (Digital Pre-distortion) system for compensating for distortion of the power amplifier, by the LMS algorithm using pseudo-random data. The delay amount of the input signal is set so as to match the timing of the input signal to the feedback signal from the power amplifier and the feedback signal so that the delay amount of the input signal is only an integer delay. And the input signal is corrected based on the input signal whose delay amount is adjusted according to the set delay amount and the feedback signal whose delay amount is adjusted using SRC (Sample Rate Converter). It is characterized by compensating for distortion of the power amplifier.

  According to the present invention, the delay amount of the input signal to the power amplifier is calculated using the LMS algorithm based on the pseudo-random data and the feedback signal that is the output signal of the power amplifier, and the delay of the input signal is calculated accordingly. In addition to adjusting the amount, the delay amount of the feedback signal is adjusted using an SRC (Sample Rate Converter) so that the delay amount of the input signal becomes an integer delay. There is no need to make any adjustments. Therefore, the delay amount with respect to the input signal can be adjusted more accurately. Since the delay amount of the input signal is an integer delay, for example, a circuit for adjusting the delay amount of the input signal can be configured by a delay element such as a flip-flop. Therefore, it is possible to easily add an integer delay, and delay adjustment of the input signal and the feedback signal can be performed with higher accuracy, and as a result, distortion compensation accuracy can be improved.

It is a block diagram which shows the basic composition of the DPD system in one Embodiment of this invention. It is a block diagram which shows an example of a pseudo random data generator. It is explanatory drawing which shows the concept of a LMS algorithm. It is a block diagram which shows an example of a delay adjustment part. It is explanatory drawing with which it uses for operation | movement description of the DPD system of FIG. (A) is an example of a filter coefficient value. (B) is an example of a correspondence between a PN signal and a filter coefficient value. It is explanatory drawing with which it uses for operation | movement description in a delay adjustment part. It is a block diagram which shows the DPD system in one Embodiment of this invention. It is a block diagram which shows an example of SRC (Sample Rate Converter). It is explanatory drawing with which it uses for operation | movement description of SRC of FIG. It is explanatory drawing with which it uses for operation | movement description of the DPD system of FIG. It is a block diagram which shows an example of the conventional DPD system.

Embodiments of the present invention will be described below with reference to the drawings.
First, a basic configuration of a DPD (Digital Pre-distortion) system 100 according to an embodiment of the present invention will be described with reference to FIG.
The DPD system 100 is a system that performs distortion compensation for a power amplifier (PA) 1 included in, for example, an RF-IC (Radio Frequency-Integrated Circuit).

  The DPD system 100 includes a pseudo random data generator (PN Gen) 11, a multiplier 12, a DA converter (DAC) 13, an image removal filter (LPF) 14 including a low pass filter, and a modulation unit ( MOD) 15, a carrier signal generator 16, an attenuator (ATT) 17, a look-up table (LUT) 18, a predistortion compensation calculation unit 19, an AD converter (ADC) 20, and a low-pass filter. The anti-aliasing filter (LPF) 21, the demodulator (DEMOD) 22, and the delay adjuster (LMS) 23 are provided.

  In the DPD system 100, the distortion compensator 10 includes a pseudo random data generator (PN Gen) 11, a multiplier 12, a look-up table 18, a predistortion compensation calculation unit 19, and a delay adjustment unit (LMS) 23. Is configured. The DA converter 13, the image removal filter 14, the modulation unit 15, and the carrier signal generator 16 constitute a part of the RF-IC transmitter. The attenuator 17, the AD converter 20, the anti-aliasing filter 21, and the demodulator 22 constitute a signal converter for converting the output of the power amplifier (PA) 1 into a feedback signal in a data format that can be processed by the distortion compensator 10. doing. That is, the digital signal before being input to the DA converter 13 is restored from the output signal of the power amplifier 1 by the signal conversion unit.

The distortion compensator 10 receives the output signal of the AD converter 20 and performs distortion compensation of the input signal u (n) using the output signal, and inputs the signal after distortion compensation to the DA converter 13.
The pseudo random data generator 11 is selectively connected to an input terminal 28 for inputting a signal to be amplified by the power amplifier 1 by a switch circuit or the like. Reference numeral 29 denotes an output end of an amplified signal from the power amplifier 1.

  The distortion compensator 10 performs delay adjustment on the input signal u (n) to be amplified by the power amplifier 1 using an LMS algorithm using pseudo-random data, so that the input signal u (n) and the fractional delay are adjusted. By matching the timing with the feedback signal including the output signal (output signal of the AD converter 20), the distortion compensation accuracy of the DPD method is improved. The fractional delay is a fractional delay that is a remainder that cannot be corrected by an integral multiple delay.

FIG. 2 is a configuration diagram showing an example of the pseudo random data generator 11.
Here, the pseudo-random data generator 11 is selectively connected to the input terminal 28 of the DPD system 100 as described above. Specifically, when adjusting the delay adjustment unit (LMS) 23, the pseudo random data generator 11 is connected to the input terminal 28, and the pseudo random data generated by the pseudo random data generator 11 is used. The delay adjustment unit (LMS) 23 is adjusted.
The pseudo-random data can be generated using a PN (Pseud random Noise) generating polynomial that can be realized by a small circuit. A circuit that generates, for example, a PN9 stage signal in the PN series is composed of a shift register composed of nine delay elements and one XOR operator as shown in FIG.

Specifically, the output of the delay element at the first stage and the output of the delay element at the sixth stage are input to the XOR operator, and the result of these XOR operations is output to the delay element at the second stage. Output as random data. The generator polynomial PN9 (X) of the pseudo random data generator 11 is expressed as PN9 (X) = X ⁹ + X ⁵ +1.
The signal generated by the pseudo-random data generator 11 is a signal repeated for every 9th power of “2”, but can be handled as pseudo-random data.

FIG. 3 is a diagram showing the concept of an LMS (Least Mean Square) algorithm. The delay adjustment unit (LMS) 23 performs delay adjustment using this LMS algorithm.
As shown in FIG. 3, the LMS algorithm is a system (Estimation System) composed of an output (d (n): desired signal) of an unknown system 23a and a FIR (Finite Impulse Response) filter. ) The error component (e (n): error signal) from the output of 23b (y (n): filter output signal) is calculated by the adder 23c, and the error component e (n) calculated by the adder 23c is Feedback is made to the filter coefficient of the FIR filter. As a result, the error component e (n) converges to “0”, so that the unknown system 23a can be identified.

Here, the equation of the LMS algorithm can be expressed by the following equation (1).
w (n) = w (n−1) + μe (n) u ^H (n)
e (n) = d (n) -y (n)
y (n) = w (n-1) u (n) (1)
In equation (1), w (n): filter coefficient, e (n): error signal, d (n): desired signal, y (n): filter output signal, u (n): input signal, μ : Step size, H: Complex conjugate.

FIG. 4 is a configuration diagram illustrating an example of the delay adjustment unit (LMS) 23, and is a configuration diagram in the case where the LMS algorithm is configured by a digital circuit. FIG. 4 shows a case where the circuit is configured with a circuit having three filter coefficients in order to simplify the description, but the same applies to a case where the circuit is configured with a circuit having an arbitrary number of filter coefficients.
As shown in FIG. 4, the delay adjustment unit (LMS) 23 includes an FIR filter 30a and a filter coefficient setting circuit 30b that sets filter coefficients h0 to h2 of the FIR filter 30a.

  The FIR filter 30 a includes two delay elements 31 for delaying an input signal (u (n): Input Signal), three multipliers 32, and an adder (3 to 1 adder) 33. The multiplier 32 has an input signal u (n), a filter coefficient h 0, an input signal u (n) delayed once by the delay element 31, a filter coefficient h 1, and an input signal u (n) delayed by the two delay elements 31. ) And the filter coefficient h2.

The adder 33 adds the multiplication results from these multipliers 32. The addition result of the adder 33 is the FIR filter output (y (n): LMS Output), that is, the LMS output of the delay adjustment unit (LMS) 23.
The filter coefficient setting circuit 30b includes a subtractor 34, a step size adjusting amplifier 35, three multipliers 36, three adders (2 to 1 adder) 37, three delay units 38, and three complex conjugates. And an arithmetic unit 39.

The subtractor 34 calculates an error component (e (n): Error Signal) between the FIR filter output (y (n): LMS Output) and the desired signal (d (n): Ref Signal). The step size adjusting amplifier 35 amplifies the error component e (n) calculated by the subtracter 34 with a certain step size (μ: Step Size).
Each of the complex conjugate calculators 39 includes an input signal u (n), an input signal u (n) after the delay process performed by the FIR filter 30a, and an input signal u (n) after the delay process twice. Of the complex conjugate of the error component e (n) amplified by the step size adjusting amplifier 35 and the input signal u (n) calculated by the complex conjugate calculator 39, respectively. Is multiplied by the signal.

Each adder 37 adds the output signal of the multiplier 36 and a signal obtained by delaying the output signal by the delay unit 38, and outputs the addition result to the delay unit 38. The outputs of the delay devices 38 become the filter coefficients h0 to h2, respectively.
With this configuration, the delay adjustment unit (LMS) 23 feeds back the error component e (n) to the filter coefficients h0 to h2, so that the error component e (n) becomes “0”. Operate.

The attenuator 17 receives the output signal of the power amplifier 1 and attenuates the output signal so as to be equal to the signal level before being amplified by the power amplifier 1. And the output signal of the multiplier 12 is DA After being converted into a digital signal by the converter 13 and an image component being removed by the image removal filter 14, the modulation unit 15 uses the carrier signal generated by the carrier signal generator 16 to be up-converted to a high frequency band signal, Input to the power amplifier 1. The output of the power amplifier 1 is attenuated by the attenuator 17 so as to be equal to the signal level before being amplified by the power amplifier 1. Thereafter, the demodulator 22 performs down-conversion using the carrier signal generated by the carrier signal generator 16, performs filter processing by the anti-aliasing filter 21, and then converts the analog signal by the AD converter 20.

In the DPD system 100 of FIG. 1, the power amplifier 1, the multiplier 12, the lookup table 18, and the predistortion compensation calculation unit 19 have the same functions as the corresponding units of the conventional DPD system 200 shown in FIG. It has a configuration.
Here, the digital circuit constituting the delay adjustment unit (LMS) 23 of FIG. 4 does not require a large-scale arithmetic circuit such as a DSP. Therefore, for example, even when the DPD system 100 is applied to a mobile terminal, the circuit area can be sufficiently realized.

  Further, when the DPD system 100 is applied to a mobile phone, when a digital filter generally used in a channel filter or the like of a transmission unit is an FIR type, the FIR filter 30a constituting the delay adjustment unit (LMS) 23 The channel filter of the mobile phone can also be used as an FIR filter circuit. Therefore, it is effective for area saving.

Next, a delay adjustment method using the LMS algorithm using pseudo-random data by the DPD system 100 will be described.
When delay adjustment is performed, first, a delay amount is set. Specifically, as shown in FIG. 5, the pseudo random data generator 11 is connected to the input terminal 28.
The pseudo random data generated by the pseudo random data generator 11 is input to the DA converter 13 without going through the multiplier 12, and the image component is removed by the image removal filter 14. Thereafter, in the modulation unit 15, the carrier signal generated by the carrier signal generator 16 is used to up-convert the signal into a high frequency band signal, which is input to the power amplifier 1. For example, by providing a switch circuit (not shown) or the like, a signal that is input to the input terminal 28 is supplied to the DA converter 13 via the multiplier 12, and is directly supplied to the DA converter 13 not via the multiplier 12. A path for supplying pseudo-random data directly to the DA converter 13 is formed by operating this switch circuit (not shown).

  At this time, the lookup table 18 and the predistortion operation unit 19 are not operated. For example, a switch circuit (not shown) or the like is provided on the signal input side to the lookup table 18 and the predistortion operation unit 19, and the lookup circuit 18 and the predistortion are operated by operating the switch circuit. What is necessary is just to make it switch whether the compensation calculating part 19 is operated.

The switch circuit for switching the path and the switch circuit for switching whether or not to operate the lookup table 18 and the predistortion operation unit 19 may be controlled by a control device (not shown), for example.
With this configuration, as shown in FIG. 5, the pseudo random data from the pseudo random data generator 11 is input to the power amplifier 1 via the DA converter 13, the image removal filter 14, and the modulation unit 15. The output of the power amplifier 1 is input as a feedback signal to the delay adjusting unit (LMS) 23 via the attenuator 17, the demodulating unit 22, the anti-aliasing filter 21, and the AD converter 20, and pseudo-random data is input to the delay adjusting unit ( LMS) 23 is formed.

In a state in which such a circuit is formed, in the delay adjustment unit (LMS) 23 shown in FIG. 4, the pseudo random data is input signal u (n), and the feedback signal (that is, the output signal of AD converter 20) is the reference signal d. Delay adjustment is performed using the LMS algorithm as (n).
6 shows the filter coefficients of the delay adjustment unit (LMS) 23 as h0 to h7. The feedback delay, that is, the input signal IN inputted to the delay adjustment unit (LMS) 23 in FIG. 5 and the output signal of the AD converter 20 are shown. FIG. 6A shows a filter coefficient when the deviation from a certain reference signal REF is “3.6 cycles” (FIG. 6A) and a diagram showing the relationship between the input signal and the filter coefficient value (FIG. 6B). )).

For example, when the feedback delay is “3.6 cycles”, pseudo random data (PN signal) is input to the delay adjustment unit (LMS) 23 as the input signal IN (u (n)) as shown in FIG. When input, the filter coefficient value of the delay adjustment unit (LMS) 23 changes with time.
Then, a delay of “3.6 cycles” is added to the input signal IN and output from the delay adjustment unit (LMS) 23 as an LMS output.
That is, a delay of “3.6 cycles” corresponding to a feedback delay is added to the input signal IN and becomes an LMS output, so that the timings of the LMS output and the feedback signal as the reference signal match.

  FIG. 6A shows, for example, a delay of “3.6 cycles” when the filter coefficient value of the filter coefficient “h3” is “0.4” and “h4” is “0.6”. Yes. At this time, the filter coefficient values of the other filter coefficients other than the filter coefficients “h3” and “h4” are all “0”. By using pseudo-random data having all frequency band components up to the Nyquist frequency, the filter coefficient of the delay adjustment unit (LMS) 23 is not diffused, and the feedback delay is expressed by the filter coefficient as shown in FIG. Is done.

  In this way, when the filter coefficient “h3” is “0.4” and “h4” is “0.6”, for example, “0 → 10 → 20 →...” As shown in FIG. When the ramping signal that changes is used as the input signal u (n), the output of the delay adjustment unit (LMS) 23 changes as “0 → 0 → 0 → 0 → 4 → 14 → 24 →. The feedback delay of “3.6 cycles” can be adjusted including the fractional delay of “0.6”.

In FIG. 7A, a characteristic line L1 represents a ramping signal input to the delay adjustment unit (LMS) 23, and a characteristic line L2 represents a delay-adjusted signal output from the delay adjustment unit (LMS) 23. Represents a signal. The minimum unit 1LSB of the delay adjustment unit (LMS) 23 is 1 code, and the step of the ramping signal is 10 code.
As described above, in order to obtain the reverse distortion characteristic of the power amplifier 1 in the DPD system 100, first, as described above, the delay adjustment unit (LMS) 23 calculates the feedback delay using the pseudo random data, and the feedback delay is calculated. The filter coefficient value of the delay adjustment unit (LMS) 23 to be expressed is fixed. Then, the ramping signal as described above is input.

  The filter coefficient is fixed, for example, by providing a switch circuit (not shown) on the signal input side of the adder 37 in the delay adjustment unit (LMS) 23 shown in FIG. 37 may be performed by inputting data of a determined value including “0” instead of the data from the multiplier 36, or the data from a storage unit (not shown) storing the filter coefficient value. It may be performed by inputting.

  1, the connection between the pseudo random data generator 11 and the multiplier 12 is released by a switch or the like (not shown), and the input signal u (n) is input to the DA converter 13 via the multiplier 12. Switch the route to be. Further, the input terminal 28 is connected to the lookup table 18, and the lookup table 18 and the predistortion compensation calculation unit 19 are operated. In this state, by inputting a ramping signal to be amplified by the power amplifier 1 to the input terminal 28, a delay adjustment unit (LMS) 23 adds a delay to the ramping signal. The timing of the ramping signal to which this delay is added coincides with the feedback signal that is the output signal of the AD converter 20 corresponding to the output signal of the power amplifier 1. Then, a distortion characteristic opposite to the non-linear distortion generated in the power amplifier 1 based on the feedback signal is calculated by the pre-distortion compensation calculation unit 19, and the data of the inverse distortion characteristic is stored in the lookup table (LUT) 18. .

  The LUT data stored in the look-up table (LUT) 18 and the input signal u (n), that is, the ramping signal to be amplified by the power amplifier 1 are multiplied by the multiplier 12 and then supplied to the DA converter 13. . As a result, a signal having a distortion characteristic opposite to the distortion characteristic of the power amplifier 1 is generated from the ramping signal to be amplified before being input to the power amplifier 1, and this is used as an input signal to the power amplifier 1. The distortion of the power amplifier 1 can be canceled out.

By the way, in the DPD system 100 shown in FIG. 1, when the step of the ramping signal as the input signal u (n) is the same as the minimum unit 1LSB in the delay adjustment unit (LMS) 23, the DPD system 100 shown in FIG. As described above, truncation occurs in the output of the delay adjustment unit (LMS) 23, and the fractional delay cannot be expressed.
In FIG. 7B, the characteristic line L3 is a ramping signal input to the delay adjustment unit (LMS) 23, and the characteristic line L4 is a signal after delay adjustment output from the delay adjustment unit (LMS) 23. The step of the ramping signal is 1 code, and the minimum unit 1LSB of the delay adjustment unit (LMS) 23 is 1 code.

In the case of the DPD system 100 of FIG. 1, as described above, there is a case where the fractional delay cannot be expressed. Therefore, in the present embodiment, as shown in FIG. 8, a DPD system 150 further including a fractional delay adjusting unit 40 in the basic configuration of the DPD system 100 shown in FIG. 1 is used.
In this DPD system 150, a pseudo random data generator (PN Gen) 11, a multiplier 12, a lookup table 18, a predistortion compensation calculation unit 19, a delay adjustment unit (LMS) 23, and a fractional delay adjustment The unit 40 constitutes the distortion compensator 10a. The SRC 42 and the channel filter 43 are used as part of the receiver during normal operation.

In this DPD system 150, the delay amount of the feedback signal including the fractional delay is calculated by the delay adjusting unit (LMS) 23 as described above by the LMS algorithm using pseudo-random data, and then fed back by the fractional delay adjusting unit 40. Adds a fractional delay to the signal and converts the delay of the feedback signal into an integer delay. As a result, the feedback signal delay itself becomes an integer delay with respect to an input signal that changes in increments of 1 LSB, which cannot represent the fractional delay, so that the input signal u (n) It is possible to easily add an integer delay by the delay element. As a result, the input signal u (n) and the feedback signal can be delay-adjusted with high accuracy. Thereby, the distortion compensation accuracy of the DPD method can be further improved.
In other words, in the present embodiment, the distortion compensator 10a having the LMS algorithm using pseudo-random data and the fractional delay correction by the fractional delay adjustment unit 40 causes a highly accurate delay between the input signal u (n) and the feedback signal. Realize the adjustment.

Hereinafter, the DPD system 150 shown in FIG. 8 will be described in detail.
The same parts as those in the DPD system 100 in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted.
As shown in FIG. 8, the fractional delay adjusting unit 40 is interposed between the delay adjusting unit (LMS) 23 and the AD converter 20. Then, the fractional delay adjustment unit 40 performs a predetermined process on the output signal of the AD converter 20 and outputs this to the predistortion compensation calculation unit 19 and the delay adjustment unit (LMS) 23 as a feedback signal.
The predistortion compensation calculation unit 19 calculates a distortion characteristic opposite to the non-linear distortion of the power amplifier 1 based on the output of the delay adjustment unit (LMS) 23 and the output signal of the fractional delay adjustment unit 40. Specifically, in the predistortion calculation unit 19, the input signal delayed by the delay adjustment unit (LMS) 23 and the output signal of the AD converter 20 are delayed by an SRC 42 of the fractional delay adjustment unit 40 described later. The distortion characteristic opposite to the nonlinear distortion of the power amplifier 1 is calculated on the basis of the above signal.

  The fractional delay adjustment unit 40 includes a fractional delay control unit 41 that sets a fractional delay value, an SRC (Sample Rate Converter) 42 that adjusts a sampling period in accordance with the fractional delay value set by the fractional delay control unit 41, and a digital filter The channel filter (DIGFIL) 43 which consists of these. The channel filter 43 is not necessarily provided in the distortion compensator 10a that performs distortion compensation. However, when the distortion compensator 10a is applied to the power amplifier 1 that constitutes the RF-IC transmission unit as in the DPD system 150, the RF-IC reception unit needs to perform channel selection during normal operation. When calculating the reverse distortion of the power amplifier 1, it is preferable to widen the band of the channel filter 43 so that the distortion component of the power amplifier 1 is not suppressed by the channel filter 43. The adjustment of the band of the channel filter 43 may be performed by, for example, performing processing such as switching the coefficients of the digital filter constituting the channel filter 43 so as to be a wide band.

FIG. 9 is a configuration diagram showing the configuration of the SRC 42.
The SRC 42 forms a multistage filter, and includes a plurality of FIR filters 51, a multiplier 52, and an adder 53. The multiplier 52 and the adder 53 are “1” more than the number of FIR filters 51. Prepare a small number. In the case of FIG. 9, four FIR filters 51, three multipliers 52, and three adders 53 are provided. 9, 54 is an input signal terminal for inputting a signal to the FIR filter 51, 55 is a fractional delay setting terminal for setting a fractional delay, and 56 is a signal output from the FIR filter 51. This is an output signal terminal.

The FIR filter 51 inputs an input signal to the input signal terminal 54, and the output of the FIR filter 51 is input to the multiplier 52.
The FIR filter 51 includes two delay units 51a, three filter coefficient multipliers 51b, and a 3to1 adder 51c.
In the FIR filter 51, the value obtained by multiplying the input signal by the filter coefficient by the first-stage filter coefficient multiplier 51b and the input signal delayed by the first-stage delay element 51a are multiplied by the second-stage filter coefficient. A value obtained by multiplying the filter coefficient by the multiplier 51b and a value obtained by multiplying the input signal after being delayed twice by the first-stage and second-stage delay elements 51a by the third-stage filter coefficient multiplier 51c. Is added by the 3to1 adder 51c. The addition result of the 3to1 adder 51 c becomes the output of the FIR filter 51. The filter coefficient value of the filter coefficient multiplier 51b is set based on the sampling ratio before and after the SRC 42 and the Nyquist frequency.

  The first-stage multiplier 52 receives the output of the first-stage FIR filter 51, multiplies this by the fractional delay value set in the fractional delay setting terminal 55, and outputs the multiplication result to the adder 53. The adder 53 outputs the sum of the output of the multiplier 52 and the output of the next-stage FIR filter 51 to the next-stage multiplier 53. Thereafter, calculation is similarly performed in each stage, and the output of the adder 53 in the final stage is output to the output signal terminal 56, which becomes the output of the SRC 42.

  That is, in the case of FIG. 9, the output of the first stage FIR filter 51 and the multiplication result of the fractional delay value and the output of the FIR filter 51 of the second stage are added, and the addition result and the multiplication result of the fractional delay value 3 The output of the FIR filter 51 at the stage is added, the addition result and the multiplication result of the fractional delay value and the output of the FIR filter 51 at the fourth stage are added, and this addition result becomes the output of the SRC 42.

  With the above configuration, the SRC 42 can calculate the fractional delay value from the sampling point data of the input signal input to the input signal terminal 54, that is, the data whose timing of “◯” shown in FIG. That is, sampling point data in consideration of the above, that is, data whose timing of “■” shown in FIG. 10A is a sampling point is generated. That is, the data whose timing is the sampling point is the data point calculated by the FIR filter 51.

The input signal to the input signal terminal 54 can be changed to an arbitrary sampling rate by changing the fractional delay value for each sampling.
That is, in the case of FIG. 10A, the sampling rate “0... Is changed by changing the fractional delay value to“ 0.25 → 0.27 → 0.29 → 0.31... (Cycles) ”. 98 (cycles) ".

Here, as described above, when the fractional delay value is changed for each sampling, the SRC 42 operates as a sampling rate converter.
On the other hand, when the fractional delay value is fixed, as shown in FIGS. 10B and 10C, sampling points corresponding to a fixed fractional delay value (0.25 (cycles in the case of FIG. 10B)) are obtained. Therefore, the SRC 42 can be operated as a fractional delay adjuster.

  Therefore, if the fractional delay value is changed for each sampling and operated as a sample rate converter, and a constant arbitrary fractional delay is always added to the fractional delay value, the fractional delay adjustment function is added to the sample rate converter. Can be added. In FIG. 10C, the broken line is an input signal input to the input signal terminal 54, and the solid line is an output signal of the SRC 42 when the fractional delay value is 0.25 (cycles).

In the DPD system 150, the SRC 42 to which the fractional delay adjustment function is added is used, thereby performing the fractional delay correction of the feedback signal.
A method for correcting the fractional delay of the feedback signal will be described below.
When correcting the fractional delay, first, the pseudo random data generator 11 is connected to the input terminal 28 as shown in FIG. Further, a path for inputting the pseudo random data generated by the pseudo random data generator 11 to the DA converter 13 without using the multiplier 12 is formed.

  For example, by providing a switch circuit (not shown) or the like, a signal that is input to the input terminal 28 is supplied to the DA converter 13 via the multiplier 12, and is directly supplied to the DA converter 13 not via the multiplier 12. A path for supplying pseudo-random data directly to the DA converter 13 is formed by operating this switch circuit (not shown). At this time, similarly to the DPD system 100 of FIG. 1, the lookup table 18 and the predistortion operation unit 19 are not operated.

  As a result, as shown in FIG. 11, the pseudo-random data from the pseudo-random data generator 11 is input to the power amplifier 1 via the DA converter 13, the image removal filter 14, and the modulation unit 15, and the output of the power amplifier 1. Is input to the delay adjustment unit (LMS) 23 as a feedback signal via the attenuator 17, the demodulation unit 22, the anti-aliasing filter 21, the AD converter 20, the channel filter 43, and the SRC 42. In addition, a circuit is formed in which pseudorandom data is input to the delay adjustment unit (LMS) 23.

Note that the delay amount of the fractional delay adjustment unit 40 is set to zero in the initial state.
In a state where such a circuit is formed, in the delay adjustment unit (LMS) 23, the pseudo random data is input signal u (n) and the feedback signal (that is, the output signal of SRC 42) is the reference signal d (n). Is used to adjust the delay in the same manner as the DPD system 100.

  For example, when the feedback delay is “3.6 cycles”, pseudo random data (PN signal) is input to the delay adjustment unit (LMS) 23 as the input signal u (n) as shown in FIG. Then, with time, the filter coefficient value of the delay adjustment unit (LMS) 23 changes to represent a feedback delay, and the filter coefficient value of the filter coefficient “h3” is “0.4” as shown in FIG. , The delay of “3.6 cycles” is represented by the filter coefficient value of “h4” being “0.6”.

  Next, in a state in which the delay adjustment unit (LMS) 23 is operated, the filter coefficients “h0 to h7” of the FIR filter 30a of the delay adjustment unit (LMS) 23 are monitored by the fractional delay control unit 41. The fractional delay control unit 41 supplies the fractional delay setting terminal 55 to “1.0” so that “h4” of “h3” and “h4” changed to “0.4” and “0.6” becomes “1.0”. Adjust the fractional delay value. For example, the fractional delay value is increased with a resolution corresponding to the number of bits of the fractional delay setting terminal (for example, 6 bits is a unit of 1/64) until “h4” becomes “1.0”.

As a result, the SRC 42 adds the fractional delay value set at the fractional delay setting terminal 55 of the SRC 42 to the feedback signal, that is, the output signal of the AD converter 20.
When a fractional delay is added, the delay amount of the feedback signal only increases, and therefore, a filter coefficient indicating a larger delay amount, in this case, “h4” approaches “1.0”. As a result, the filter coefficient value “h4” converges to “1.0”, “h3” converges to “0”, and finally “h4” becomes “1.0”. “0”. This means that the delay of the feedback signal is converted from the fractional delay to the integer delay.

  Here, when the delay of the feedback signal is converted into an integer delay, as a method of adding the integer delay to the input signal u (n), an integer can be added to the input signal with a delay element such as a flip-flop easily and with high accuracy. A method of adding a delay can be employed. Therefore, the delay of the feedback signal can be matched with high accuracy.

  The SRC 42 increases the fractional delay with higher accuracy by increasing the filter coefficient bit length of the FIR filter 51 and the data bit length depending on the circuit area allowed by the system to which the DPD system 150 is applied. It is possible to adjust. In addition, since the delay adjustment is performed by the digital circuit in the SRC 42, it is not necessary to consider the characteristic deterioration due to the circuit mismatch or the temperature change as in the case of the analog circuit.

  In the DPD system 150 of FIG. 8, in order to obtain the reverse distortion characteristics of the power amplifier 1 by the DPD method, after the filter coefficient of the digital filter constituting the channel filter 43 is switched and adjusted so that the band of the channel filter 43 is widened. As described above, the delay adjustment unit (LMS) 23 calculates the delay amount of the feedback signal using the pseudo-random data, sets the fractional delay value based on the filter coefficient value of the delay adjustment unit (LMS) 23, and performs feedback. Convert signal delay from fractional delay to integer delay. Then, the fractional delay value is fixed, and the filter coefficient value of the delay adjustment unit (LMS) 23 is fixed. Thereby, the setting of the delay amount is completed.

Next, the pseudo random data generator 11 is disconnected from the input terminal 28, and the ramping signal as described above is input as the input signal u (n).
For example, the connection between the input terminal 28 and the pseudo random data generator 11 is canceled by a switch or the like (not shown), and the input signal u (n) is converted into a multiplier 12, a DA converter 13, an image removal filter, as shown in FIG. 14. The path is switched so as to be input to the power amplifier 1 via the modulation unit 15. Further, by connecting the input terminal 28 to the lookup table (LUT) 18, the lookup table (LUT) 18 and the predistortion compensation calculation unit 19 are operated.

  When a ramping signal is input as the input signal u (n) in this state, a delay amount is added to the ramping signal input to the delay adjustment unit (LMS) 23 by the FIR filter 30a of the delay adjustment unit (LMS). . As a result, the ramping signal to which the delay amount is added is attenuated by the attenuator 17 so as to be equal to the signal level before being amplified by the power amplifier 1, and the feedback in which the fractional delay is added by the fractional delay adjustment unit 40. The signal and timing match.

  Then, a distortion characteristic opposite to the non-linear distortion generated in the power amplifier 1 is calculated by the predistortion calculation unit 19 and the LUT of the lookup table (LUT) 18 storing the data of the inverse distortion characteristic is stored. Data and an input signal (ramping signal) u (n) are multiplied by a multiplier 12 to generate a signal having reverse distortion characteristics before being input to the power amplifier 1, thereby canceling the distortion of the power amplifier 1. be able to.

Thus, since the input signal u (n) and the feedback signal can be matched with high accuracy, a highly accurate reverse distortion characteristic having a distortion characteristic opposite to the distortion characteristic generated in the power amplifier 1 is obtained. The distortion compensation accuracy can be further improved by performing the distortion compensation according to the highly accurate reverse distortion characteristic.
Further, as described above, since the fractional delay is added to the output signal of the power amplifier 1 by the fractional delay adjusting unit 40, the delay amount to be adjusted with respect to the output signal of the SRC 42 is an integer delay.

  Therefore, in order to match the timings of the feedback signal and the input signal u (n), the delay adjustment is performed without adding a delay to the input signal u (n) using the delay adjustment unit (LMS) 23 as described above. The input signal u (n) can be delayed using a delay element (not shown) such as a flip-flop other than the unit (LMS) 23. For this reason, the delay adjustment unit (LMS) 23 performs fractional delay correction by the fractional delay adjustment unit 40, converts the delay amount of the feedback signal into an integer delay, and then uses the delay element such as a flip-flop as the integer delay. Thus, the delay adjustment can be performed without the need for the delay adjustment unit (LMS) 23 thereafter. Therefore, after converting the delay of the feedback signal into the integer delay, the delay adjusting unit (LMS) 23 can be used for purposes other than the delay adjustment of the feedback signal.

  For example, a modulated wave signal is input from the input terminal 28, the output of the power amplifier 1 is fed back, and the inverse distortion characteristic of the power amplifier 1 is directly calculated using the LMS algorithm of the delay adjustment unit (LMS) 23. There is a possibility that it can be used for an adaptive DPD system in which reverse distortion correction is applied. In the delay adjustment method, the LMS algorithm is used with the feedback signal (that is, the output signal of the AD converter 20) as the reference signal d (n). However, in order to obtain the inverse distortion characteristic of the power amplifier 1, the feedback signal is used as the input signal. The LMS algorithm is used with u (n) and the modulated wave signal from the input terminal 28 as the reference signal d (n). By doing so, the filter coefficient of LMS shows the reverse distortion characteristic of the power amplifier 1. The inverse distortion characteristic data is stored in a look-up table (LUT) 18, and the multiplier 12 multiplies the look-up table (LUT) 18 and the input signal from the input terminal 28 to implement adaptive DPD. To do. In an adaptive DPD system, there is a possibility that a memory effect caused by a temperature change of the power amplifier 1 can be dealt with.

  In addition, in the distortion compensator 10a having a circuit that performs fractional delay correction by the LMS algorithm and the SRC 42, the SRC 42 requires a plurality of FIR filters 51, and thus the circuit scale becomes large. However, if the sampling rate of the AD converter differs from the sampling rate of the interface between the DBB (digital baseband) signal (not shown) and the RF-IC, for example, in the receiving unit of the RF-IC, In operation, since SRC is necessary, it is not necessary to newly provide the SRC 42 as the DPD system 150, and it is sufficient to use the already-provided SRC.

  Therefore, in order to perform the fractional correction in the distortion compensator 10a, it is not necessary to add or change the SRC itself, only the fractional delay control unit 41 is required, and the distortion compensator 10a is applied to the RF-IC. Therefore, the increase in the circuit area of the RF-IC due to the configuration of the DPD system 150 may be such that the entire circuit area is hardly affected.

As described above, according to the present invention, input processing can be performed by an LMS algorithm using pseudo-random data and fractional delay correction by the SRC 42, which can be realized even in applications such as portable terminals that require low power consumption and area saving. A highly accurate delay adjustment of the signal and the feedback signal can be realized.
Also, by using this delay adjustment method, the delay amount of the feedback signal can be adjusted including not only the integer delay but also the fractional delay.

Furthermore, since the delay adjustment method is adjusted by a digital circuit, there is no need to consider analog circuit mismatch or characteristic deterioration due to temperature change, and the filter of the FIR filter 51 constituting the SRC 42 depends on the allowable circuit area. By increasing the coefficient bit length and the data bit length, delay adjustment with higher accuracy can be performed.
In addition, the feedback signal itself becomes an integer delay with respect to the input signal that changes in increments of 1 LSB, which cannot represent the fractional delay, so that the input signal u (n) has a flip-flop or the like. An integer delay can be easily added by the delay element, and the input signal u (n) and the feedback signal can be delay-adjusted with high accuracy. Since the integer delay can be simply expressed by a delay element such as a flip-flop without using a delay adjustment unit (LMS), the delay of the input signal u (n) is calculated after performing the fractional delay correction by the LMS algorithm and the SRC 42. The LMS circuit which is adjusted by a delay element such as a flip-flop other than the delay adjustment unit (LMS) and used for the delay adjustment can be used as a circuit with another system using the LMS algorithm.

In the above embodiment, the pseudo random data generator 11 is selectively connected to the input terminal 28 by a switch circuit or the like. However, the present invention is not limited to this.
As described above, the pseudo random data generator 11 is used for adjusting the filter coefficient of the FIR filter 30a of the delay adjusting unit (LMS) 23 and adjusting the delay amount of the SRC 42. The filter coefficient and the delay amount of the SRC 42 are as follows. Since it is fixed after the adjustment, the pseudo random data generator 11 is not necessary except when setting the filter coefficient and the delay amount of the SRC 42.

Therefore, it is not always necessary to provide the pseudo-random data generator 11 as the distortion compensator 10a. For example, when adjusting the filter coefficient of the FIR filter 30a and the delay amount of the SRC 42, the pseudo-random data generator 11 is input to the input terminal. 28 may be connected.
Further, since the delay adjustment unit (LMS) 23 fixes the filter coefficient after adjusting the filter coefficient, in the normal state where the ramping signal is used as the input signal u (n), only the FIR filter 30a is provided. The filter coefficient setting circuit 30b is not necessarily provided.

Therefore, the filter coefficient setting circuit 30b constituting the delay adjustment unit (LMS) 23 is not necessarily provided as the distortion compensator 10a, and the filter coefficient setting circuit 30b is used when adjusting the filter coefficient of the FIR filter 30a. It is good also as a structure which connects.
In the above-described embodiment, the case of performing distortion compensation of the power amplifier 1 that constitutes the RF-IC transmission unit has been described. However, the present invention is not limited to this, and is applicable to a power amplifier that constitutes an arbitrary circuit. Can do.

  In this case, a circuit necessary for restoring the digital signal before being converted into the analog signal by the DA converter from the output signal of the power amplifier is provided between the output side of the power amplifier and the fractional delay adjusting unit 40. What is necessary is just to provide. That is, in the case of the above-described embodiment, after the analog signal is converted by the DA converter 13, the analog signal is converted from the low frequency signal to the high frequency signal by the image removal filter 14 and the modulation unit 15, and then input to the power amplifier 1. Because of this configuration, the attenuator 17, the demodulator 22, the anti-aliasing filter 21, and the AD converter 20 are provided to restore the digital signal before being input to the DA converter 13 from the output signal of the power amplifier 1. . Therefore, when applied to an arbitrary circuit, a circuit necessary for restoring a digital signal before being converted into an analog signal may be provided according to the applied circuit.

In the above embodiment, the case where distortion compensation is performed on the signal input to the DC converter 13 has been described. However, the present invention is not limited to this, and is a digital signal on the input side of the power amplifier 1 and Distortion compensation may be performed at any stage after the transmission channel filter (not shown).
In the above embodiment, the multiplier 12, the lookup table 18, and the predistortion compensation calculation unit 19 correspond to a delay circuit, the delay adjustment unit (LMS) 23 corresponds to a delay amount setting unit, and the FIR filter 30a Corresponding to the signal generation unit, a lookup table (LUT) 18 corresponds to the storage unit, and the multiplier 12 corresponds to the calculation unit.

1 Power amplifier 10, 10a Distortion compensator 11 Pseudo random data generator (PN Gen)
12 Multiplier 17 Attenuator 18 Look-up table (LUT)
19 Predistortion Compensation Operation Unit 23 Delay Adjustment Unit (LMS)
30a FIR filter 30b Filter coefficient setting circuit 40 Fractional delay adjustment unit 41 Fractional delay control unit 42 SRC (Sample Rate Converter)
43 Channel filter 51 FIR filter 52 Multiplier 53 Adder 54 Input signal terminal 55 Fractional delay setting terminal 56 Output signal terminal 100, 150 DPD system

Claims (7)

In a distortion compensator that compensates for nonlinear distortion of a power amplifier,
A delay circuit for adjusting the delay amount of the input signal;
SRC (Sample Rate Converter) for adjusting the delay amount of the feedback signal including nonlinear distortion from the power amplifier,
A delay amount setting unit that sets a delay amount of the input signal and a delay amount of the feedback signal so that timings of the input signal and the feedback signal adjusted by the SRC coincide with each other;
The delay amount setting unit sets the delay amount of the input signal and the delay amount of the feedback signal using an LMS (Least Mean Square) algorithm based on the pseudo-random data and the feedback signal. Distortion compensator.   The distortion compensator according to claim 1, further comprising a pseudo random data generator that generates the pseudo random data.   3. The delay amount setting unit sets the delay amount of the input signal and the delay amount of the feedback signal so that the delay amount of the input signal is only an integer delay. The distortion compensator described in 1. The delay amount setting unit includes a signal generation unit that generates an LMS output signal representing a delay amount of the input signal,
Of the circuit constituting the delay amount setting unit, the part excluding the signal generation unit is also used as a circuit constituting another system using the LMS algorithm, and the delay amount of the input signal and the feedback signal 4. The distortion compensator according to claim 1, wherein the distortion compensator operates as a circuit constituting the other system except when the delay amount is set. 5. A predistortion compensation calculation unit that calculates a distortion characteristic opposite to the nonlinear distortion of the power amplifier based on the input signal delayed by the delay circuit and the feedback signal delayed by the SRC;
A storage unit for storing data for specifying the reverse distortion characteristic calculated by the predistortion calculation unit;
An input unit having the inverse distortion characteristic is generated from the input signal and data stored in the storage unit, and the generated signal is output to the power amplifier as the input signal after distortion compensation;
The distortion compensator according to any one of claims 1 to 4, further comprising: The distortion compensator according to any one of claims 1 to 5,
The power amplifier;
A DPD (Digital Pre-distortion) system comprising: In a control method of a DPD (Digital Pre-distortion) system that compensates for distortion of a power amplifier,
The delay amount of the input signal is set and the delay amount of the input signal is set so that the timing of the input signal to the power amplifier and the feedback signal from the power amplifier are matched by an LMS algorithm using pseudo-random data. The delay amount of the feedback signal is set so that the amount is only an integer delay, and the delay amount is adjusted using the input signal and the SRC (Sample Rate Converter) in which the delay amount is adjusted according to the set delay amount. A control method of a DPD system, wherein distortion of the power amplifier is compensated by correcting an input signal based on a feedback signal.

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