JP2013114538A - Information processing apparatus, information processing method and control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time to access a memory, thereby enhancing the execution performance.SOLUTION: An information processing apparatus includes plural processors enabling parallel processing, and a memory shared between the plural processors. Allocation means allocates a work group in which an access range of the memory can be described in advance and which is constituted by plural threads, to be executed by any of the plural processors, by referring to each of the described access ranges.

Description

  Embodiments described herein relate generally to an information processing apparatus, an information processing method, and a control program.

Conventionally, a multi-thread processor that executes instructions of a plurality of threads in parallel is known (see, for example, Patent Document 1).
As such a multi-thread processor, GPU (Graphics Processing Units) is known, but in recent years, GPGPU (General Purpose computing on Graphics Processing Units) using parallel processing capability of this GPU for general-purpose computation has been proposed.

For example, technologies such as CUDA (Compute Unified Device Architecture) and OpenCL (Open Computing Language) are known as execution platforms for GPGPU.
In these GPGPU execution platforms, it is possible to execute a large-scale operation at high speed by operating a large number of operation processors mounted on the GPU in parallel.

JP 2010-277371 A

  By the way, in the programming on the execution platform of the GPGPU as described above, the factor that greatly affects the execution performance is not the calculation time on the calculation processor but the access time for each calculation processor to access the memory and read / write data. It was the main thing.

  The present invention has been made in view of the above, and it is an object of the present invention to provide an information processing apparatus, an information processing method, and a control program capable of reducing an access time to a memory and thus improving execution performance. .

The information processing apparatus according to the embodiment includes a plurality of processors capable of parallel processing and a memory shared by the plurality of processors.
The allocating unit is configured to allow a memory access range to be described in advance and to cause one of a plurality of processors to execute a work group composed of a plurality of threads with reference to each described access range. assign.

FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing apparatus according to the embodiment. FIG. 2 is an explanatory diagram of a schematic configuration of the GPU. FIG. 3 is an explanatory diagram of the detailed configuration of the arithmetic unit. FIG. 4 is a conceptual explanatory diagram of an execution model of an application program in the GPU. FIG. 5 is an explanatory diagram of the usage status of VRAM in each work group. FIG. 6 is an explanatory diagram of an example of API specifications. FIG. 7 is a processing flowchart of the embodiment.

Next, embodiments will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a schematic configuration of an information processing apparatus according to the embodiment.
The information processing apparatus 10 can be broadly divided into an MPU 11 that is a general-purpose processor, a GPU 12 that is a graphic processor, a north bridge 13 that performs an interface operation for a circuit that performs communication via a relatively high-speed bus (Bus), and a north bridge. 13 is connected via a memory bus 14 and functions as a recording medium. The ROM 15 stores various control programs and the like. The north bridge 13 is connected via a memory bus 14 and stores various data as a work area. The HDD 16 and the south bridge 17 connected to the south bridge 17 and the south bridge 17 that perform an interface operation for a circuit that is connected to the RAM 16 and the north bridge 13 and performs communication via a relatively low-speed bus, and function as an external storage device. Connect via PCI bus 19 It is provided with a communication interface (IF) unit 20 which performs a communication interface operation.
A VRAM 22 is connected to the GPU 12 via a cache 21.
In the above configuration, the MPU 11 is configured as a so-called microcomputer, and includes a CPU, a ROM, a RAM, and the like (not shown).
The GPU 12 includes a plurality of arithmetic units for performing repetition of formulated simple operations such as matrix operations at high speed.

Here, the GPU 12 will be described in detail with reference to FIG.
FIG. 2 is an explanatory diagram of a schematic configuration of the GPU.
The GPU 12 includes a plurality of arithmetic units 31 and a controller 32 that performs thread execution control on the plurality of arithmetic units 31. Each arithmetic unit 31 is connected to the cache 21 via, for example, a high-speed graphic bus 33 conforming to the PCI Express 2.0 standard. Further, a VRAM 22 shared by a plurality of arithmetic units 31 is connected via the cache 21.
The VRAM 22 includes a general-purpose memory area 34 and a constant memory area 35 for storing various constants.

FIG. 3 is an explanatory diagram of the detailed configuration of the arithmetic unit.
Each arithmetic unit 31 constituting the GPU 12 is associated with each of the arithmetic elements 41, a plurality of arithmetic elements 41, a local memory 42 constituting a memory area shared by all the arithmetic elements 41, and the corresponding arithmetic elements 41. A private memory 43 that constitutes a memory area occupied by the element 41 and a bus 44 that interconnects each arithmetic element 41 and the local memory 42 are provided. Here, the bus 44 and the high-speed graphic bus 33 are connected to each other.

Next, the configuration of the information processing apparatus will be described again.
The north bridge 13 performs a high-speed bus communication interface operation with a relatively wide bandwidth.
The ROM 15 stores data that needs to be stored in a nonvolatile manner such as a control program.
The RAM 16 constitutes a so-called main memory and temporarily stores various data.
The south bridge 17 performs a communication interface operation with a device connected to a relatively narrow-band, low-speed bus such as an HDD having a mechanical drive unit or an optical disk drive.
The HDD 18 stores a large amount of data although it operates at a low speed.
The communication interface (IF) unit 20 performs a communication interface operation when performing data communication with another information processing apparatus or the like via a communication network conforming to the Ethernet (registered trademark) standard (not shown).

Here, prior to describing the operation of the embodiment, data to be processed will be described.
In this embodiment, the arithmetic unit 31 that executes a thread is configured to execute a thread group (≈task) having a close memory access area (memory access range) at a close time if possible.
In the GPU 12, an execution model called SPMD (Single Program Multiple Data) in which one application program is executed for a plurality of data is often applied.

  By the way, one application program is composed of a small program called a thread (work item) executed in parallel. When executing threads, a plurality of threads are grouped as one work group and executed in units of work groups. Therefore, a plurality of work groups are executed in parallel by executing one application program.

Each arithmetic unit 31 is assigned in units of work groups. A plurality of threads constituting a work group assigned to the arithmetic unit 31 can share the local memory 42 corresponding to the assigned arithmetic unit 31. That is, a plurality of work groups assigned to the same arithmetic unit 31 share the local memory 42.
Furthermore, each thread constituting the work group is assigned to each computation element 41, and the thread assigned to each computation element 41 can use the private memory 43 that can be referred to only by the thread assigned to the computation element 41. It is in a state.

FIG. 4 is a conceptual explanatory diagram of an execution model of an application program in the GPU.
As shown in FIG. 4, the application program APL is conceptually configured by a plurality of work groups WG that are identified by a two-dimensional index = (Wx, Wy) and can be executed in parallel. Each work group WG is similarly composed of a plurality of threads TH that can be executed in parallel.

FIG. 5 is an explanatory diagram of the usage status of VRAM in each work group.
FIG. 5 is an explanatory diagram when three work groups are referring to a memory.
As shown in FIG. 5, the reference area of the general-purpose memory area 34 of the VRAM 22 of the work group WG1 to which the group ID = 100 is assigned and the general-purpose memory area 34 of the VRAM 22 of the work group WG3 to which the group ID = 300 is assigned. There is an area that partially overlaps the reference area.

On the other hand, the reference area of the work group WG2 to which the group ID = 200 is assigned is different from the area referred to by any of the work groups WG1 and WG3, and is a different area.
As described above, the reference area of the general-purpose memory area 34 of the VRAM 22 of the work group WG1 to which the group ID = 100 is assigned, and the reference area of the general-purpose memory area 34 of the VRAM 22 of the work group WG3 to which the group ID = 300 is assigned. And there is some overlap. Therefore, even if the work group WG1 and the work group WG3 are simultaneously executed in parallel, even if the work group WG1 and the work group WG3 are respectively assigned to different arithmetic units 31 capable of operating in parallel, It is not possible to access the same memory address. In other words, since the same data cannot be fetched simultaneously by different arithmetic units 31 due to the exclusive control, the substantial execution efficiency is lowered.

  Therefore, in such a case, by assigning the work group WG1 and the work group WG3 to the same arithmetic unit 31, it is possible to perform the optimum assignment in the memory access space (access optimization in the space direction).

On the other hand, a reference area of the general-purpose memory area 34 of the VRAM 22 of the work group WG1 to which the group ID = 100 is assigned, a reference area of the general-purpose memory area 34 of the VRAM 22 of the work group WG2 to which the group ID = 200 is assigned, There is no overlap.
For this reason, even if the work group WG1 and the work group WG2 are assigned to the same arithmetic unit 31, the work group WG2 is assigned to the same arithmetic unit 31 next to the work group WG1 and executed. That is, the arithmetic unit 31 needs to re-read data after the processing of the work group WG1 is completed and before the processing of the work group WG2 is performed, and the use efficiency of the cache 21 is reduced.

Therefore, in such a case, by assigning the work group WG1 and the work group WG2 to different arithmetic units 31 capable of processing in parallel, optimal assignment in the time axis direction (optimal access in the time direction) Can be performed.
For this reason, in this embodiment, in order to optimize the access in the spatial direction and the time direction for the work group, a configuration is adopted in which the runtime module is notified of the reference area (memory access range) of each work group.

In this case, as a mode in which the reference areas are allocated to the work groups WG1 to WG3, a raster-type allocation mode in which a memory area having consecutive addresses is allocated as a reference area, and addresses are discontinuous, but conceptually Tile-type allocation mode in which a tile-shaped (rectangular) memory area is allocated as a reference area on a two-dimensional memory space (in a continuous memory space, a plurality of memory spaces of the same capacity are arranged at predetermined addresses. Is present).
Therefore, in the present embodiment, as the API specification, a specification that can handle both the case where the reference area is assigned in the raster format and the case where the reference area is assigned in the tile format is adopted.

FIG. 6 is an explanatory diagram of an example of API specifications.
The description mode of FIG. 6 is a description mode of the reference area notification function in the case of complying with the OpenCL standard.
As a parameter of the reference area notification function FN when the reference area is notified in a raster format, a kernel name parameter for managing a system resource and specifying a kernel for managing the exchange of hardware and software components Reference area allocation format parameter corresponding to raster format = “TYPE_RASTER”, reference area start address parameter (start_position), reference area size parameter (size), and parameters not used to make the format of the reference area notification function FN constant , There is a NULL parameter indicating that there is no corresponding parameter.

  In addition, as parameters of the reference area notification function FN when the reference area is notified in the tile format, the kernel name parameter for specifying the kernel, the reference area allocation format parameter corresponding to the tile format = “TYPE_TILE”, the reference area When the start address parameter (start_position), the reference area horizontal size parameter (h_size) indicating the number of consecutive addresses corresponding to the horizontal width when the reference area is expressed as a two-dimensional memory space, and the reference area are expressed as a two-dimensional memory space There is a reference area vertical size parameter (v_size) corresponding to the vertical width of.

  In this case, the reference area start address parameter is determined by the work group WG and the number of threads TH (number of items) included in the work group WG, and includes a work group ID corresponding to an index for identifying the work group WG. It is calculated based on a thread number (number of items) built-in variable g_num indicating the number of threads TH included in the work group specified by the variable g_idx and the work group ID parameter g_idx. The work group ID built-in variable g_idx and the thread number built-in variable g_num are two-dimensional data in the x direction and the y direction for specifying the threads constituting the work group, and are parameters ([0]) representing dimensions. Or [1]) indicates the x direction (= [0]) and the y direction (= [1]).

In the example of FIG.
start_position = g_num [0] * g_idx [0] + g_num [1] * g_idx [1]
It has become.
The reference area size parameter (size) is a constant.

Next, the operation of the embodiment will be described.
FIG. 7 is a processing flowchart of the embodiment.
First, the controller 32 acquires the memory access area of the task group at the head of the queue (step S10).

Next, the controller 32 determines whether or not the queue is full (step S11).
If it is determined in step S11 that the queue is full (step S11; Yes), the process proceeds to step S10 again to enter a standby state.
If it is determined in step S11 that the queue is not full, that is, if there is room in the queue (step S11; No), there is a group of tasks waiting for a schedule, and other task groups are stacked in the queue. It is determined whether or not it is possible (step S12).

If it is determined in step S12 that there is no group of tasks waiting for a schedule (step S12; No), the process proceeds to step S10 again to enter a standby state.
If there is a group of tasks waiting for the schedule in the determination in step S12 and it is possible to queue other task groups (step S12; Yes), the task waiting for the schedule The memory access area of the group is calculated by calculation (step S13).

Next, the controller 32 determines whether or not the calculated memory access area overlaps the memory access area of the group at the head of the queue (step S14).
If it is determined in step S14 that the memory access area of the calculated task group overlaps with the memory access area of the group at the head of the queue (step S14; Yes), the memory access area overlaps the group of the task. It adds to the list | wrist of a group (step S15), and transfers a process to step S17.

On the other hand, if it is determined in step S14 that the calculated memory access area of the group of tasks does not overlap with the memory access area of the group at the head of the queue (step S14; No), the task group is assigned to the memory access area. Are added to the list of groups that do not overlap (step S16).
Subsequently, the controller 32 determines whether or not the number of task groups included in the list of groups in which the memory access areas overlap and the list of groups in which the memory access areas do not overlap accumulates the group of tasks in the queue. It is determined whether or not the threshold is exceeded (step S17).

If it is determined in step S17 that the number of groups of all tasks included in both lists does not exceed the predetermined threshold (step S17; No), the controller 32 has a group of tasks waiting for a schedule. Then, it is determined again whether another task group can be loaded in the queue (step S18).
If it is determined in step S18 that there is a group of tasks waiting for a schedule (step S18; Yes), the process proceeds to step S13 again, and the same process is performed thereafter.

  In the determination in step S18, if there is no task group waiting for the schedule (step S18; No), the controller 32 has the most overlapping area among the task groups included in the list of groups with overlapping memory access areas. A group of tasks having a large number is accumulated in the queue in the time direction (step S19). That is, after processing of the work group at the head of the queue, the same arithmetic unit 3 (or arithmetic element 41) is loaded in the queue so that the processing is performed.

  In addition, the controller 32 queues the task group having the closest address among the task groups included in the list of groups with which the memory access areas do not overlap (step S20). That is, the task group at the head of the queue is stacked in the queue so that processing is performed in another arithmetic unit 31 (or arithmetic element 41).

  As described above, according to the present embodiment, the memory access areas (memory reference areas) overlap, and work groups or threads that cannot access the memory at the same time are stacked in the queue in the time direction. Assigned. Therefore, the hit rate in the cache can be improved and the processing efficiency can be improved.

  In addition, work groups or threads that do not overlap memory access areas (memory reference areas) and can access the memory at the same time are stacked in a queue in the spatial direction, that is, another arithmetic unit 31 or another Are assigned to the calculation element 41. Accordingly, work groups or threads that can simultaneously access the memory can be processed in parallel at the same time, and the processing efficiency can be improved.

  The control program executed by the information processing apparatus of the present embodiment is an installable or executable file, and is a computer such as a CD-ROM, flexible disk (FD), CD-R, DVD (Digital Versatile Disk). Recorded on a readable recording medium.

  The control program executed by the information processing apparatus according to the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. The control program executed by the information processing apparatus according to the present embodiment may be provided or distributed via a network such as the Internet.

In addition, the control program for the information processing apparatus according to the present embodiment may be provided by being incorporated in advance in a storage medium such as a ROM.
The control program executed by the information processing apparatus of the present embodiment has a module configuration including the above-described units (reference means, assignment means), and the CPU (processor) is a storage medium such as a ROM as actual hardware. Alternatively, by reading the control program from the recording medium and executing it, the means are loaded onto the main storage device, and the reference means and the assigning means are generated on the main storage device.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Information processing apparatus, 11 ... MPU, 12 ... GPU, 15 ... ROM (recording medium), 21 ... Cache, 22 ... VRAM, 31 ... Arithmetic unit (processor), 32 ... Controller (reference means, allocation means), 33 ... High-speed graphic bus, 34 ... General-purpose memory area (memory), 41 ... Calculation element (processor), 42 ... Local memory (memory), 43 ... Private memory, 44 ... Bus, APL ... Application program, FN ... Reference area notification function TH, Thread, WG, WG1 to WG3, Work group, WGG, Work group group.

The information processing apparatus according to the embodiment includes a plurality of processors capable of parallel processing and a memory shared by the plurality of processors.
Then, assigning unit memory access range of workgroup composed of a plurality of threads are in advance can be described in the reference area notification function, refer to get a reference area information function describe the access range, acquires Based on the access range, the work group is assigned to be executed by one of a plurality of processors.

Claims (9)

Multiple processors capable of parallel processing;
A memory shared by the plurality of processors;
Allocation means for allocating a work group composed of a plurality of threads so that the access range of the memory can be described in advance and executed by any of the plurality of processors with reference to the described access range When,
An information processing apparatus comprising: The processor is connected to the memory via a cache;
The assigning means continuously assigns a plurality of work groups having at least a part of the access range to the same processor,
The information processing apparatus according to claim 1. The assigning means preferentially assigns a work group having the largest overlap range to the same processor among a plurality of work groups having at least a part of the access range overlapping.
The information processing apparatus according to claim 2. The assigning means assigns a plurality of work groups that do not have overlapping access ranges to different processors in order to perform parallel processing,
The information processing apparatus according to any one of claims 1 to 3. The assigning means preferentially assigns a work group having the closest address to a processor among a plurality of work groups whose access ranges do not overlap.
The information processing apparatus according to claim 4. The processor is configured as an arithmetic unit constituting a GPU,
The memory is configured as a VRAM shared by the arithmetic units.
The information processing apparatus according to any one of claims 1 to 5. The processor is configured as an arithmetic element constituting each of a plurality of arithmetic units included in the GPU,
The memory is configured as a local memory assigned to each arithmetic unit.
The information processing apparatus according to any one of claims 1 to 5. An information processing method executed in an information processing apparatus comprising a plurality of processors capable of parallel processing and a memory shared by the plurality of processors,
A reference process for referring to the described access range for a work group configured with a plurality of threads in which the access range of the memory can be described in advance.
An allocation process for assigning each of the workgroups to be executed by any of the plurality of processors based on the referenced access range;
An information processing method comprising: A control program for controlling an information processing apparatus including a plurality of processors capable of parallel processing and a memory shared by the plurality of processors by a computer,
Reference means for referring to the described access range for the work group configured with a plurality of threads and the access range of the memory can be described in advance.
Allocating means for allocating each work group to be executed by any of the plurality of processors based on the referenced access range;
Control program to function.

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