JP2013113607A - Semiconductor device and testing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that when performing a DC test of a semiconductor device provided with an output circuit including an AC coupling part in a data signal line, amplitude cannot be maintained, and thereby, a semiconductor device provided with an output circuit including an AC coupling part in a data signal line and capable of achieving a DC test is desired.SOLUTION: A semiconductor device includes: a main driver for outputting a data signal to the external; an AC coupling part including a capacitor connected to a wire for transmitting the data signal, a termination resistor whose one-end is connected to the capacitor and the other end is connected to a bias voltage source and a first switch connected between the bias voltage source and the termination resistor; and a control circuit for cutting off connection between the bias voltage source of the AC coupling part and the termination resistor by a first switch in a test mode.

Description

  The present invention relates to a semiconductor device and a test method thereof. In particular, the present invention relates to a semiconductor device including an output circuit and a test method thereof.

  In the manufacturing process of a semiconductor device, a test process for confirming the performance of the manufactured semiconductor device is indispensable. The test process of a semiconductor device is roughly divided into a DC (direct current) test and an AC (alternating current) test. The DC test is a test for confirming the static characteristics of the semiconductor device. More specifically, a DC test is performed to guarantee the voltage / current characteristics of the input / output buffer. The AC test is a test for confirming the dynamic characteristics of the semiconductor device. More specifically, it is performed to confirm the function (signal output) of the semiconductor device.

  Here, Patent Document 1 discloses a DC test circuit that reduces the cost of testing by performing a DC test of a multi-terminal semiconductor device using an LSI tester with a small number of terminals.

JP 2000-258505 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  In consideration of noise immunity, communication data and the like are often transmitted and received in a differential configuration. For this reason, an output-side semiconductor device often includes an AC coupling unit between a pre-driver that receives a signal generated by its internal circuit and a main driver that includes a differential pair. The AC coupling unit extracts the AC component and supplies it to the main driver.

  Further, the AC coupling unit may be operated as a level shifter to enable connection between semiconductor devices operating with different power supply voltages. This is because the level shifter using the AC coupling unit can reduce the power consumption accompanying the conversion of the power supply voltage.

  However, there is a problem in performing a DC test of a semiconductor device including an AC coupling unit. The semiconductor device receives a signal generated by an internal circuit by a pre-driver, extracts an AC component by an AC coupling unit, and outputs data from an output terminal via a main driver. At this time, since the AC coupling unit includes a capacitor, the DC path disappears. If the DC path does not exist, the amplitude cannot be maintained at the output terminal of the semiconductor device, and a normal DC test cannot be performed.

  In view of this, the inventors have studied a countermeasure for securing a DC path by providing a switch in a capacitor included in the AC coupling unit and turning on the switch during a DC test. However, such a measure increases parasitic capacitance at a node that transmits a signal, degrades the quality of a signal having a high frequency, and hinders execution of an AC test. The reason why the amplitude cannot be maintained at the output terminal of the semiconductor device when there is no DC path, and the reason why the AC test is hindered by the measures for securing the DC path by adding a capacitor will be described later. To do.

  Therefore, a semiconductor device including an output circuit in which an AC coupling unit is included in a data signal line, which enables a DC test and a test method thereof are desired.

  According to the first aspect of the present invention, a main driver for outputting a data signal to the outside, a capacitor connected to a wiring for transmitting the data signal, one end connected to the capacitor, and the other end biased An AC coupling unit including a termination resistor connected to a voltage source and a first switch connected between the bias voltage source and the termination resistor; and the bias of the AC coupling unit in a test mode There is provided a semiconductor device comprising: a control circuit that cuts off a connection between a voltage source and the termination resistor by the first switch.

  According to the second aspect of the present invention, a main driver for outputting a data signal to the outside, a capacitor connected to a wiring for transmitting the data signal, one end connected to the capacitor, and the other end biased A test method for a semiconductor device comprising: an AC coupling unit including a termination resistor connected to a voltage source, wherein when performing a DC test, the data rate of the data signal is determined by the capacitor and the termination. A step of setting a time constant longer than a time constant determined from a resistor, and when the data signal transitions to a logic level to be measured by a DC test, connection between the bias voltage source and the termination resistor is established. A method of testing the semiconductor device, including the step of blocking.

  According to each aspect of the present invention, a semiconductor device including an output circuit in which an AC coupling unit is included in a data signal line, and a semiconductor device that enables a DC test and a test method thereof are provided.

It is a figure for demonstrating the outline | summary of one Embodiment of this invention. 1 is a diagram illustrating an example of a test system including a semiconductor device 1. 2 is a diagram illustrating an example of an internal configuration of a semiconductor device 1. FIG. 6 is a diagram illustrating an example of a waveform when a DC test is performed on a semiconductor device 1; FIG. 1 is a diagram illustrating an example of a test system including a semiconductor device 4. 2 is a diagram illustrating an example of an internal configuration of a semiconductor device 4. FIG. It is a figure which shows an example of the test system comprised including the semiconductor device 5 which concerns on the 1st Embodiment of this invention. 2 is a diagram illustrating an example of an internal configuration of a semiconductor device 5. FIG. 6 is a diagram illustrating an example of an operation in a normal operation mode of the semiconductor device 5. FIG. 6 is a diagram illustrating an example of an operation in a DC test mode of the semiconductor device 5. FIG. FIG. 4 is a diagram illustrating a relationship between a supply voltage to the main driver 30 and an output voltage. It is a figure which shows an example of the test system comprised including the semiconductor device 6 which concerns on the 2nd Embodiment of this invention. 2 is a diagram illustrating an example of an internal configuration of a semiconductor device 6. FIG. 3 is a diagram illustrating an example of an internal configuration of an AC coupling termination unit 231. FIG. 5 is a diagram illustrating an example of the operation of a control circuit 60. FIG. 6 is a diagram illustrating an example of an operation in a test mode of the semiconductor device 6. FIG. It is a figure which shows an example of the internal structure of AC coupling | bond termination part 231a contained in the semiconductor device 7 which concerns on the 3rd Embodiment of this invention.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, there is a problem in performing a DC test of a semiconductor device including an output circuit in which an AC coupling unit is included in a data signal line. Therefore, a semiconductor device that includes an output circuit in which an AC coupling unit is included in the data signal line and that enables a DC test is desired.

  Therefore, as an example, the semiconductor device 100 illustrated in FIG. 1 is provided. A semiconductor device 100 shown in FIG. 1 includes a main driver 101 that outputs a data signal to the outside, a capacitor C that is connected to a wiring that transmits the data signal, one end connected to the capacitor C, and the other end connected to a bias voltage. AC coupling unit 102 including a termination resistor RT connected to the source, and a first switch SW connected between the bias voltage source and the termination resistor RT, and a bias of the AC coupling unit 102 in the test mode And a control circuit 103 that disconnects the connection between the voltage source and the termination resistor RT by the first switch SW.

  When performing the DC test, the control circuit 103 uses the first switch SW to cut off the connection between the bias voltage source and the termination resistor RT. As a result, the time constant of the AC coupling unit 102 determined from the capacitance value of the capacitor C and the resistance value of the termination resistor RT increases. As the time constant increases, the time from when the data signal changes until the voltage converges becomes longer. Therefore, DC measurement is performed (DC test is performed) before the amplitude of the data signal output from the main driver 101 converges to a constant voltage. As described above, the DC test can be performed even in the semiconductor device 100 in which the AC coupling unit 102 is included in the data signal line.

  In the present invention, the following modes are possible.

  [Mode 1] As in the semiconductor device according to the first aspect.

  [Mode 2] The control circuit turns off the first switch when the DC test of the semiconductor device is performed, and turns the first switch off during the normal operation mode of the semiconductor device and the AC test of the semiconductor device. It is preferable to turn it on.

  [Mode 3] The AC coupling unit has one end connected to a connection node between the bias voltage source and the termination resistor, and one end connected to the connection node and the first resistor. And a second switch disposed between the first voltage source and the first resistor, and a third switch connected across the second resistor. The control circuit turns on the second switch when performing a DC test, and turns on / off the third switch according to the logic level of the data signal output from the main driver. It is preferable to determine.

  [Mode 4] The AC coupling unit has one end connected in series between a third resistor connected to a connection node between the bias voltage source and the termination resistor, and a first power source and the third resistor. A fourth resistor arranged; a fourth switch connected to both ends of the fourth resistor; and a first MOS transistor connected to the other end of the third resistor. And a reference current generation unit including a second MOS transistor that forms a current mirror circuit with the first MOS transistor, and the control circuit outputs data output from the main driver when performing a DC test. It is preferable to determine whether the fourth switch is turned on or off according to the logic level of the signal.

  [Mode 5] The test method of the semiconductor device according to the second aspect.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

  First, the semiconductor device 1 including the AC coupling portion will be described.

  FIG. 2 is a diagram illustrating an example of a test system including the semiconductor device 1. The test system shown in FIG. 2 includes a semiconductor device 1, a tester 2, and a test board 3.

  The semiconductor device 1 is connected to the tester 2 via the test board 3. More specifically, signals output from the output terminals TXP and TXN of the semiconductor device 1 are received by testers CH51 and 52 and PMUs (Power Management Units) 53 and 54 included in the tester 2, and a DC test is performed.

  The semiconductor device 1 includes a pre-driver 10, an AC coupling unit 20, a main driver 30, and a bias circuit 40.

  The pre-driver 10 is disposed in the voltage VDDD region, and the main driver 30 is disposed in the voltage VDDIO1 region. AC coupling unit 20 is arranged at the boundary between voltage VDDD region and voltage VDDIO1 region. The pre-driver 10 receives a main signal and a post signal for generating a differential signal output from the output terminals TXP and TXN. The post signal is a signal obtained by shifting (delaying) the main signal by 1 bit. The main signal and the post signal are used to realize an emphasis function in which the amplitude is emphasized and output when the logic of the output data changes, and the output is attenuated and output when the logic of the output data does not transition.

  The bias circuit 40 supplies the voltage VTT1 to the AC coupling unit 20 (supplying a bias voltage).

  FIG. 3 is a diagram illustrating an example of the internal configuration of the semiconductor device 1.

  The pre-driver 10 includes buffers B01 to B04. The buffers B01 to B04 receive signals (main signal and post signal) from the nodes S01 to S04 connected to the internal circuit of the semiconductor device 1, and output the signals to the nodes S11 to S14. The buffers B01 to B04 are CMOS buffers and are preferably configured by SOX (single oxide structure) transistors.

  The AC coupling unit 20 includes capacitors C01 to C04 and termination resistors RT01 to RT04. Capacitors C01 to C04 are AC coupling capacitors. The AC coupling unit 20 extracts the AC component from the signals of the nodes S11 to S14, performs level shift by the termination resistors RT01 to RT04, and outputs them to the main driver 30.

  The main driver 30 includes N-channel MOS transistors N01 to N04 and constant current sources CI01 and CI02. N-channel MOS transistors N01 and N02 form a main signal differential pair, and N-channel MOS transistors N03 and N04 form a post-signal differential pair. As the N-channel MOS transistors N01 to N04, MOX (multi-oxide structure) transistors are preferably used. By using the main signal and the post signal, the main driver 30 can output four types of levels. The main driver 30 receives a signal output from the AC coupling unit 20 and outputs a non-inverted signal from the output terminal TXP and an inverted signal from the output terminal TXN.

  The tester 2 includes PMUs 53 and 54, and is connected to load resistors RL01 and RL02, respectively.

  Here, when the DC test of the semiconductor device 1 shown in FIG. 3 is performed, the DC test may not be performed because there is no DC path in the data signal line.

  FIG. 4 is a diagram illustrating an example of a waveform when a DC test is performed on the semiconductor device 1. FIG. 4A is a diagram illustrating an expected value of values output from the output terminals TXP and TXN when the DC test is performed. In FIG. 4A, the pattern running of the DC test is stopped at the timing 1.

  FIG. 4B is a diagram illustrating waveforms of the output terminals TXP and TXN that can be observed by the tester 2. At time T1, the DC test pattern running is stopped.

  The tester 2 stands by without measuring the output terminals TXP and TXN between T1 and T2. Thereafter, DC measurement of the output terminals TXP and TXN is performed between T2 and T3. Here, if the AC coupling unit 20 is not present, a DC path is present on the data signal line, so that the output terminals TXP and TXN can maintain the amplitude (middle stage in FIG. 4B). . That is, it is possible to perform a DC test with the tester 2.

なお、ＶＴＴ２はＰＭＵ５３及び５４に供給する電圧値、ｒｌは負荷抵抗ＲＬ０１及びＲＬ０２の抵抗値、ｉｐは定電流源ＣＩ０１が供給する電流値、ｉｍは定電流源ＣＩ０２が供給する電流値、である。このように、半導体装置１をテスタ２によって、ＤＣテストすることは不可能である。 On the other hand, when the AC coupling unit 20 is present, there is no DC path on the data signal line, and the output terminals TXP and TXN cannot maintain the amplitude (lower stage in FIG. 4B). That is, the voltages at the output terminals TXP and TXN converge to the voltage Vc expressed by the following equation (1).

VTT2 is a voltage value supplied to the PMUs 53 and 54, rl is a resistance value of the load resistors RL01 and RL02, ip is a current value supplied by the constant current source CI01, and im is a current value supplied by the constant current source CI02. . Thus, it is impossible to DC test the semiconductor device 1 using the tester 2.

  Therefore, the inventors have studied the semiconductor device 4 capable of performing the DC test even if the AC coupling portion is provided on the data signal line as follows.

  FIG. 5 is a diagram illustrating an example of a test system including the semiconductor device 4. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. The difference between FIG. 2 and FIG. 5 is that the control signal SEL is output from the tester CH driver 55 included in the tester 2 a, and the AC coupling unit 21 receives the control signal SEL via the input buffer 50.

  The test system shown in FIG. 5 can switch the operation of the AC coupling unit 21 between the normal operation mode and the test mode by using the control signal SEL.

  FIG. 6 is a diagram illustrating an example of the internal configuration of the semiconductor device 4. 6, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted. The difference between the semiconductor device 1 and the semiconductor device 4 is that in the AC coupling unit 21, switches SW01 to SW04 are added. In the AC coupling unit 21 of the semiconductor device 4, switches SW01 to SW04 are connected to both ends of the capacitors C01 to C04, and each switch is turned on to provide a DC path. That is, during the DC test of the semiconductor device 4, the switches SW01 to SW04 are turned on based on the control signal SEL. As a result, a DC path is formed on the data signal line, and a DC test can be performed by the tester 2a.

  However, with the measure of adding a switch, a problem occurs when the AC test is performed. That is, at the time of the AC test in the semiconductor devices 1 and 4, a high speed (high cycle) signal is supplied from the internal circuit to the nodes S01 to S04. Therefore, the voltage changes of the nodes S01 to S04 and the nodes S11 to S14 are also required to be fast.

  Here, since switches SW01 to SW04 are added to the semiconductor device 4, the parasitic capacitance for each node increases. The increase in parasitic capacitance can be a factor that degrades the signal transmitted through each node.

  Further, when the pre-driver 10 that receives the supply of the voltage VDDD and the AC coupling unit 21 that receives the supply of the voltage VTT1 are included in different power supply regions (when the voltage VDDD and the voltage VTT1 are different), the switches SW01 to SW04 It is also assumed that the potentials of the nodes S01 to S04 exceed the absolute maximum rating of the semiconductor element (for example, a transistor) that receives the supply of the voltage VDDD. In this case, there is a possibility of circuit deterioration and destruction.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 7 is a diagram illustrating an example of a test system including the semiconductor device 5 according to the present embodiment. In FIG. 7, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted. The difference between the semiconductor devices 4 and 5 is that an AC coupling unit 22 is provided instead of the AC coupling unit 21.

  FIG. 8 is a diagram illustrating an example of an internal configuration of the semiconductor device 5 according to the present embodiment. In FIG. 8, the same components as those in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted. The AC coupling unit 22 includes P-channel MOS transistors P01 to P04, and can block the DC bias supplied from the bias circuit 40. The P channel type MOS transistors P01 to P04 are preferably MOX transistors. A control signal SEL is connected to the gates of the P-channel MOS transistors P01 to P04.

  Next, the operation of the semiconductor device 5 according to this embodiment will be described.

  FIG. 9 is a diagram illustrating an example of the operation of the semiconductor device 5 in the normal operation mode. In the following description, “0” means an L level output, and “1” means an H level output. Further, among the output voltages of the output terminals TXP and TXN, an output in which the L level is emphasized is referred to as LE, and an output in which the H level is emphasized is referred to as HE.

  In the normal operation mode, the control signal SEL is set to L level. Since control signal SEL is set to the L level, P-channel MOS transistors P01 to P04 are turned on (conducted), and the DC operating points of nodes S21 to S24 are maintained at voltage VTT1. Therefore, the nodes S21 to S24 have a potential obtained by adding the signal (AC component) input through the capacitors C01 to C04 to the voltage VTT1 that is the DC operating point. Furthermore, if the output impedance of the buffers B01 to B04 is sufficiently lower than the resistance values of the termination resistors RT01 to RT04, the amplitude of the AC component becomes the voltage VDDD.

  Here, if the test pattern is continuously changed in a time longer than the time constant determined from the capacitance values of the capacitors C01 to C04 and the resistance values of the termination resistors RT01 to RT04, the nodes S21 to S24 can stabilize the operation of the center voltage VTT1 and the amplitude VDDD. And do it. That is, since the time constant determined by the capacitors C01 to C04 and the termination resistors RT01 to RT04 is much larger than the pulse width of the test pattern, the waveforms appearing at the nodes S21 to S24 are rectangular waves. The following description will be made assuming that the time constant determined by the capacitors C01 to C04 and the terminating resistors RT01 to RT04 is the time constant TRC.

  FIG. 10 is a diagram illustrating an example of the operation of the semiconductor device 5 in the DC test mode. FIG. 10 shows a waveform when a DC test is performed when the HE level is output from the output terminal TXP. Since the operation when measuring output levels of other output levels (H level, LE level, L level) is the same, the description thereof is omitted.

  Here, since the purpose of performing the DC test on the semiconductor device is to confirm the static characteristics (output voltage and output current) of the output buffer and the like, the change of the data rate (test pattern cycle) and the DC It has nothing to do with the results of the test.

  Therefore, during the DC test of the semiconductor device 5, it is possible to set the data rate of the test pattern supplied to the semiconductor device 5 to be longer than the time constant TRC. When the data rate is set longer than the time constant TRC, the potentials of the nodes S21 to S24 converge to the center voltage (convergence voltage) VTT1 within the time of one data rate. That is, the waveforms at the nodes S21 to S24 are differential waveforms. Therefore, the potentials of the nodes S21 to S24 become the voltage VTT1 + voltage VDDD or the voltage VTT1−voltage VDDD when the next test pattern is supplied (when data changes).

  On the other hand, the control signal SEL is changed from the L level to the H level at the timing when the data to be subjected to DC measurement is supplied as the test pattern (time T4). By setting the control signal SEL to the H level, all the P-channel MOS transistors P01 to P04 are turned off (non-conducting; high impedance). When the P-channel MOS transistors P01 to P04 are turned off, the time constant of the AC coupling unit 21 is increased, and the potential changes at the nodes S21 to S24 are extremely gradual.

  Here, the nodes S21 to S24 are connected to a differential pair included in the main driver 30. FIG. 11 is a diagram showing the relationship between the supply voltage to the main driver 30 and the output voltage. As shown in FIG. 11, if an amplitude greater than a certain value is input to the differential pair included in the main driver 30, the N-channel MOS transistors N01 to N04 constituting the differential pair operate in the saturation region, The output level is stable. However, the input common mode of the main driver 30 needs to be constant. Therefore, if an amplitude of ΔV or more shown in FIG. 10 is supplied to the differential pair, the level output from the main driver 30 matches the level in the normal operation mode.

  As described above, when the data changes, as in the normal operation mode, the electrons of the nodes S21 to S24 have the amplitude of the voltage VDDD with the voltage VTT1 as the center, so the outputs of the differential pair (output terminals TXP and TXN) are It matches the output in normal operation mode. Further, since the time constant TRC is extremely large, the nodes S21 to S24 can maintain the amplitude at which the differential pair included in the main driver 30 operates completely. As a result, the DC measurement of the output terminals TXP and TXN can be normally performed in the tester 2a.

Ｌレベル：

なお、ｒｔ１は終端抵抗ＲＴ０１の抵抗値、ｚｐｓｗはＰチャンネル型ＭＯＳトランジスタＰ０１のインピーダンスであって、式（２）及び（３）は、ノードＳ２１の電位を求める計算式である。 Here, the potentials of the nodes S21 to S24 after stopping the test pattern can be obtained from the following equations (2) and (3).

H level:

L level:

Note that rt1 is the resistance value of the termination resistor RT01, zpsw is the impedance of the P-channel MOS transistor P01, and equations (2) and (3) are calculation equations for obtaining the potential of the node S21.

  As described above, the potential changes of the nodes S21 to S24 can be obtained by the equations (2) and (3), so that the N-channel MOS transistors N01 to N04 included in the main driver 30 operate in the saturation region. The impedance of the P-channel MOS transistors P01 to P04 can be determined in consideration of the standby time from when the necessary input amplitude and pattern supply are stopped until DC measurement is performed.

  In the semiconductor device 5 according to the present embodiment, the data rate of the test pattern is set longer than the time constant TRC, and the control signal SEL is set to the H level at the timing when the data to be subjected to DC measurement is supplied. As a result, the amplitude of the output terminals TXP and TXN can be maintained during the DC measurement period (time period T5 to T6 in FIG. 10) in the tester 2a, and the DC test can be performed. In other words, the DC test can be performed even if an AC coupling portion is included on the data signal line of the semiconductor device 5. Note that when the semiconductor device 5 is normally operated or when an AC test of the semiconductor device 5 is performed, the P-channel MOS transistors P01 to P04 are kept on.

  Further, unlike the semiconductor device 4, since no switch is added on the data signal line, high-speed operation in the normal operation mode is not hindered. At the same time, no DC path is provided across different power supply regions, the absolute maximum ratings of the transistors included in each power supply region are not exceeded, and there is no fear of circuit deterioration or destruction.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings.

  The semiconductor device 6 according to the present embodiment realizes a DC test by supplying a voltage directly to the nodes S21 to S24 without operating the predriver 10 (not via the predriver 10) in the test mode. .

  FIG. 12 is a diagram illustrating an example of a test system including the semiconductor device 6 according to the present embodiment. In FIG. 12, the same components as those in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted. The difference between the semiconductor devices 5 and 6 is that the control circuit 60 is provided and the internal configuration of the AC coupling unit 23 is different. The signal supplied from the tester 2b is also different from the input buffer 50a receiving it.

  The tester CH driver 55 a included in the tester 2 b supplies a 3-bit test signal TEST [2: 0] to the semiconductor device 6. The control circuit 60 included in the semiconductor device 6 receives the test signals TEST [2: 0] via the input buffer 50a. The control circuit 60 supplies a 2-bit control signal SEL [1: 0] and a 4-bit control signal RSEL [3: 0] to the AC coupling unit 23.

  FIG. 13 is a diagram illustrating an example of an internal configuration of the semiconductor device 6 according to the present embodiment. In FIG. 13, the description of the tester 2b is omitted. In FIG. 13, the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted. The difference between FIG. 13 and FIG. 8 is the internal configuration of the AC coupling unit 23.

  The AC coupling unit 23 includes AC coupling termination units 231 to 234. AC coupling termination units 231 to 234 all have the same internal configuration, but receive different control signals. Specifically, the control signal SEL [1: 0] is supplied to all the AC coupling termination units 231 to 234. However, the control signals RSEL [3: 0] are supplied to individual AC coupling terminators, such as the control signal RSEL1 to the AC coupling terminator 231, the RSEL2 to the AC coupling terminator 232, and so on. Further, the AC coupling termination units 231 to 234 receive power supply of the voltage VTT1 and the voltage VDDIO1, are connected to the corresponding nodes S21 to S24, and are grounded to the ground voltage VSS.

  FIG. 14 is a diagram illustrating an example of the internal configuration of the AC coupling termination unit 231. In addition, since the internal structure of AC coupling | bond termination part 231-234 is the same as mentioned above, description regarding AC coupling | bond termination part 232-234 is abbreviate | omitted.

  The AC coupling termination unit 231 includes N-channel MOS transistors N05 and N06, P-channel MOS transistors P05 and P06, resistors R01 to R03, and a termination resistor RT01.

  The source of the P-channel MOS transistor P05 is connected to the voltage VTT1, the gate receives the control signal SEL0, and the drain is connected to the termination resistor RT01. The source of the P-channel MOS transistor P06 is connected to the voltage VDDIO1, the gate receives the control signal SEL1, and the drain is connected to the resistor R01. The other end of the termination resistor RT01 is connected to the node S21. The source of the N-channel MOS transistor N05 is grounded, the gate receives the control signal SEL0, and the drain is connected to the resistor R03. The source or drain of the N channel type MOS transistor N06 is connected to one end of the resistor R02, and the other end of the source or drain of the N channel type MOS transistor N06 is connected to the other end of the resistor R02. A control signal RSEL1 is received at the gate of the N-channel MOS transistor N06. N-channel MOS transistors N05 and N06 are connected via a resistor R03. As the MOS transistors N05, N06, P05 and P06, it is desirable to use MOX transistors.

  The AC coupling terminator 231 operates a switch constituted by each MOS transistor in accordance with a combination of the logic levels of the control signal SEL [1: 0] and the control signal RSEL1, and sets the node S21 in the normal operation mode and the test mode. Determine the potential. The control circuit 60 (see FIG. 12) sets the logic levels of the control signal SEL [1: 0] and the control signal RSEL [3: 0] based on the test signal TEST [2: 0] supplied from the outside. decide.

  FIG. 15 is a diagram illustrating an example of the operation of the control circuit 60. As is apparent from FIG. 15, the control circuit 60 switches the operation of the semiconductor device 6 to either the normal operation mode or the test mode according to the logic level of the test signal TEST2.

  If the test signal TEST2 is at the H level, the control circuit 60 causes the semiconductor device 6 to operate in the normal operation mode. More specifically, only the control signal SEL1 is set to H level. Then, the P-channel MOS transistor P05 included in the AC coupling termination units 231 to 234 is turned on, and the other transistors are turned off. As a result, the potential of the node S31 (a connection node between the drain of the P-channel MOS transistor P05 and the termination resistor RT01; see FIG. 14) becomes the voltage VTT1. By outputting a data signal from the pre-driver 10 in this state, the nodes S21 to S24 change the potential of the center voltage VTT1 and the amplitude VDDD.

  On the other hand, if the test signal TEST2 is at the H level, the control circuit 60 determines that the operation mode of the semiconductor device 6 is the test mode. Further, the voltage output from the output terminals TXP and TXN in the test mode is determined according to the test signals TEST [1: 0]. More specifically, when the HE level is output from the output terminal TXP and the LE level is output from the output terminal TXN, the test 1 is selected (operates according to the test signals TEST [1: 0] = 00).

  When the test mode is selected, the control circuit 60 sets the control signal SEL [1: 0] = 01, turns off the P-channel MOS transistor P05, turns on the P-channel MOS transistor P06, and turns on the N-channel type. The MOS transistor N05 is turned on. Further, the logic level of the control signal RSEL [3: 0] is determined based on the test signal TEST [1: 0]. When the logic level of the control signal RSEL [3: 0] is determined, ON / OFF of the N-channel MOS transistor N06 is determined.

  The logic level of the control signal RSEL [3: 0] determines the voltages of the nodes S31 to S34. Specifically, if RSELn (n is an integer of 0 to 3, the same applies hereinafter) = 0, the voltages of the nodes S31 to S34 correspond to the voltages when the H level is output from the output terminals TXP and TXN. Voltage. On the other hand, if RSELn = 1, the potentials of the nodes S31 to S34 are voltages corresponding to voltages at the time of outputting the L level. That is, if the control signal RSEL [3: 0] is at the L level, the N-channel MOS transistor N06 is turned off, and the presence of the resistor R02 is valid. If the control signal RSEL [3: 0] is at the H level, the N-channel MOS transistor N06 is turned on and the presence of the resistor R02 is invalidated.

By switching the resistor R02 between valid and invalid, the voltage supplied to the nodes S31 to S34 is switched (the voltage division ratio with respect to the voltage VDDIO1 is changed). That is, if no data signal is output from the pre-driver 10, the voltages at the nodes S21 to S24 can be voltages obtained by dividing the voltage between the voltage VDDIO1 and the ground voltage VSS by the resistors R01 to R03. Therefore, in the semiconductor device 6, when the transition is made in the test mode, the output of the data signal from the pre-driver 10 to the nodes S01 to S04 is stopped.

  FIG. 16 is a diagram illustrating an example of the operation of the semiconductor device 6 in the test mode. FIG. 16 shows a waveform when the operation of test 1 shown in FIG. 15 is performed. Since this is an operation of test 1, it is possible to measure voltages corresponding to the HE level from the output terminal TXP and the LE level from the output terminal TXN. Since the other test operations (tests 2 to 4) are similar operations, the description thereof is omitted.

  In this manner, by applying a voltage corresponding to the L level or the H level in the normal operation mode to the nodes S21 to S24, a desired voltage is output from the output terminals TXP and TXN. However, at this time, it is necessary to determine the resistance values of the resistors R01 to R03 in consideration of the voltage VDDD, the voltage VTT1, the voltage VDDIO1, and the logic levels of the nodes S21 to S24. This is because the validity / invalidity of the resistor R02 is determined according to the logic level of the control signal RSELn as described above.

Ｌレベル：

なお、ｒ０１〜ｒ０３は抵抗Ｒ０１〜Ｒ０３の抵抗値である。例えば、ＶＤＤＤ＝１Ｖ、ＶＴＴ１＝１．６Ｖ、ＶＤＤＩＯ１＝３．３Ｖの場合には、ｒ０１＝８ｋΩ、ｒ０２＝１０ｋΩ、ｒ０３＝４ｋΩと定めることができる。 Specifically, the resistance values of the resistors R01 to R03 may be determined so as to satisfy the following expressions (4) and (5).

H level:

L level:

R01 to r03 are resistance values of the resistors R01 to R03. For example, when VDDD = 1V, VTT1 = 1.6V, and VDDIO1 = 3.3V, r01 = 8 kΩ, r02 = 10 kΩ, and r03 = 4 kΩ can be determined.

  The tester 2b measures the voltage output from the output terminals TXP and TXN (performs a DC test). Note that the test signals TEST [2: 0] may be supplied as a test pattern or set by applying a voltage from an external terminal. Furthermore, in this embodiment, the switch to which the control signals RSELn [3: 0] are supplied is realized by an N-channel MOS transistor, but a P-channel MOS transistor may be used depending on the bias condition. In such a case, the logic level of RSELn may be inverted.

  As described above, in the semiconductor device 6 according to the present embodiment, the AC coupling termination units 231 to 234 generate the voltages of the nodes S21 to S24 in a pseudo manner, thereby enabling DC measurement by the tester 2b.

[Third Embodiment]
Next, a third embodiment will be described in detail with reference to the drawings.

  The semiconductor device 7 according to the present embodiment has a configuration in which the circuit configuration of the AC coupling termination unit in the semiconductor device 6 is changed. Therefore, description of the semiconductor device 7 corresponding to FIGS. 12 and 13 is omitted.

  FIG. 17 is a diagram illustrating an example of an internal configuration of the AC coupling termination unit 231a included in the semiconductor device 7 according to the present embodiment. In FIG. 17, the same components as those in FIG. 14 are denoted by the same reference numerals, and the description thereof is omitted. The AC coupling termination units 231a to 234a included in the semiconductor device 7 are connected to the reference current generation unit 235 in common.

  The AC coupling termination unit 231a includes N channel type MOS transistors N07 to N10. Further, the reference current generator 235 includes an N-channel MOS transistor N11 and a constant current source CI03. The control for the AC coupling terminators 231a to 234a is the same as the control in the semiconductor device 6, and thus the description thereof is omitted.

  In the test mode, when the N-channel MOS transistor N09 is turned off and the N-channel MOS transistor N10 is turned on, a current mirror circuit is formed by the N-channel MOS transistors N08 and N11, and the resistor R04 (or R05) is formed. A current supplied from the constant current source CI03 flows. From the current supplied from the constant current source CI03 and the resistance values of the resistors R04 and R05, the voltages of the nodes S21 to S24 can be determined.

Ｌレベル：

なお、ｒ０４及びｒ０５は抵抗Ｒ０４及びＲ０５の抵抗値であり、Ｉａは定電流源ＣＩ０３から供給される電流の電流値である。 Specifically, it is defined by the following formulas (6) and (7).

H level:

L level:

R04 and r05 are resistance values of the resistors R04 and R05, and Ia is a current value of the current supplied from the constant current source CI03.

  As described above, by using the reference current generation unit 235, the voltages of the nodes S21 to S24 are generated in a pseudo manner, and DC measurement by the tester 2b is enabled.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. It is. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1, 4-7, 100 Semiconductor device 2, 2a, 2b Tester 3 Test board 10 Pre-driver 20, 21, 22, 23, 102 AC coupling part 30, 101 Main driver 40 Bias circuit 50, 50a Input buffer 51, 52 Tester CH
53, 54 PMU
55, 55a Tester CH driver 60, 103 Control circuits 231 to 234, 231a to 234a AC coupling terminator 235 Reference current generator B01 to B04 Buffer C, C01 to C04 Capacitors CI01, CI02, CI03 Constant current source N01 to N11 N channel Type MOS transistors P01 to P06 P channel type MOS transistors R01 to R05 Resistors RT, RT01 to RT04 Termination resistors RL01, RL02 Load resistors SW, SW01 to SW04 switches

Claims (5)

A main driver for outputting data signals to the outside;
A capacitor connected to the wiring for transmitting the data signal, a termination resistor having one end connected to the capacitor and the other end connected to a bias voltage source, and between the bias voltage source and the termination resistor An AC coupling unit including a first switch connected to
A control circuit that cuts off the connection between the bias voltage source of the AC coupling unit and the termination resistor in the test mode by the first switch;
A semiconductor device comprising:   The control circuit turns off the first switch when a DC test of the semiconductor device is performed, and turns on the first switch during a normal operation mode of the semiconductor device and an AC test of the semiconductor device. 1. A semiconductor device. The AC coupling unit includes:
A first resistor having one end connected to a connection node of the bias voltage source and the termination resistor;
A second resistor having one end connected to the connection node and the first resistor;
A second switch disposed between a first voltage source and the first resistor;
A third switch connected to both ends of the second resistor,
The control circuit turns on the second switch when performing a DC test, and determines on / off of the third switch according to a logic level of a data signal output from the main driver. 1 or 2 semiconductor devices; The AC coupling unit includes:
A third resistor having one end connected to a connection node of the bias voltage source and the termination resistor;
A fourth resistor arranged in series between a first power source and the third resistor;
A fourth switch connected to both ends of the fourth resistor;
A first MOS transistor connected to the other end of the third resistor,
And a reference current generator including a second MOS transistor that forms a current mirror circuit with the first MOS transistor,
3. The semiconductor device according to claim 1, wherein the control circuit determines on / off of the fourth switch in accordance with a logic level of a data signal output from the main driver when performing a DC test. 4. A main driver for outputting data signals to the outside;
A capacitor connected to a wiring for transmitting the data signal;
An AC coupling unit including a termination resistor having one end connected to the capacitor and the other end connected to a bias voltage source;
A method for testing a semiconductor device comprising:
A step of setting a data rate of the data signal longer than a time constant determined from the capacitor and the termination resistor when performing a DC test;
Cutting off the connection between the bias voltage source and the termination resistor when the data signal transitions to a logic level that is the subject of a DC test measurement;
A method for testing a semiconductor device, comprising:

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