JP2013062566A - Information processing apparatus, operation method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing apparatus, an operation method and a program that execute processing in coordination with an accelerator mounted with a reconfigurable programmable device.SOLUTION: An information processing apparatus 110 is connected to a programmable device 150. The information processing apparatus 110 includes: configuration data storage means 120 storing a plurality of configuration data each defining a function implemented on the programmable device; program storage means 118 storing a plurality of software programs each using the function implemented on the programmable device 150 by corresponding configuration data; and configuration request means 112 for transferring the configuration data corresponding to a selected function of the plurality of configuration data to the programmable device 150 to request a configuration.

Description

  The present invention relates to an information processing apparatus using a reconfigurable programmable device, and more specifically, an information processing apparatus, a calculation method, and a program for executing processing in cooperation with an accelerator equipped with a reconfigurable programmable device About.

  Conventionally, there has been a technology for improving processing speed by linking a programmable device represented by an FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device) as an accelerator with a CPU (Central Processing Unit). Are known. Examples of techniques related to the programmable device include the following.

  Japanese Patent Laid-Open No. 10-285014 (Patent Document 1) discloses a technique for reducing the time required for reconfiguration. Patent Document 1 discloses a configuration in which a large-capacity memory is prepared in a device, a plurality of configuration data is stored in the memory, and configuration data is collectively written in a chip.

  Japanese Patent Application Laid-Open No. 2007-251329 (Patent Document 2) discloses a technique aiming at taking advantage of the feature that the function of the reconfigurable core can be switched in view of the prior art of Patent Document 1. Patent Document 2 discloses a configuration in which a dedicated bus is provided between a memory outside an LSI that stores configuration data and a configuration data storage memory inside the LSI.

  Japanese Patent No. 4165125 (Patent Document 3) discloses an image / audio processing apparatus provided with a reconfigurable processing unit for the purpose of efficiently realizing various functions using a small amount of general-purpose hardware in an image / audio processing apparatus. A processing apparatus is disclosed. The video / audio processing apparatus disclosed in Patent Document 3 has an internal function that can be changed, and at least one reconfigurable processor that processes a video signal and a reconfigurable processor based on functional data that determines the function of the reconfigurable processor. And a configuration unit for setting the functions of

  Japanese Patent Application Laid-Open No. 11-144661 (Patent Document 4) discloses a technique for reducing the circuit scale and flexibly responding to the addition of a new function for arithmetic processing. More specifically, Patent Document 4 uses a programmable logic device that can be reconfigured as a device for implementing a circuit, and a control computer selects one of a plurality of configuration data and selects a configuration. A configuration for starting is disclosed.

  Japanese Patent No. 3664962 (Patent Document 5) discloses a technique aiming to achieve both flexibility and low power consumption that can cope with various communication protocols. More specifically, Patent Document 5 uses a local configuration DB that stores a plurality of semiconductor IPs, and a semiconductor IP in the local configuration DB to create configuration data that is written to programmable logic elements, and is programmable. A configuration including a control unit that writes to a logic element is disclosed.

  Japanese Patent Laid-Open No. 2008-242850 (Patent Document 6) discloses an image processing suitable for image characteristics even when there are various characteristics of image data to be processed when image processing is performed using a reconfigurable circuit. Disclosed is a technique aimed at efficiently performing the above. An image processing apparatus disclosed in Patent Document 6 includes an image feature determination circuit that determines an image feature and a region having the image feature from image data to be image-processed, and circuit data corresponding to the image feature determined by the image feature determination circuit. Is provided in the reconfigurable circuit, and a control means for controlling the execution of the image processing.

  In the prior art, as exemplified in Patent Document 1 above, in order to realize a plurality of functions, an approach of increasing the capacity of a memory on a semiconductor chip and storing a plurality of configuration data on the memory is adopted. ing. However, an increase in the capacity of the memory on the semiconductor chip means an increase in the area of the semiconductor chip, and the number of chips that can be produced from one silicon wafer decreases, resulting in an increase in manufacturing cost. Further, the increase in the area of the semiconductor chip leads to an increase in the wiring length and increases the power consumption. In view of these points, it is not preferable to increase the capacity of the memory in the programmable device.

  As exemplified in Patent Documents 2 to 4, a memory device on which configuration data is stored externally or internally is provided, and the configuration of the memory on the semiconductor chip according to the switching of the hardware function unit on the host device side An approach to update data is also adopted. However, no consideration has been given to the addition or change of software, and the purpose of realizing various functions cannot be satisfied.

  The present invention has been made in view of the insufficiency in the above-described prior art, and the present invention provides a plurality of programmable device configurations in an information processing apparatus connected to a programmable device typified by an FPGA or the like. An information processing apparatus, an arithmetic method, and a program for accumulating data, selecting and setting appropriate configuration data to realize a desired function, reconfiguring a programmable device, and performing processing linked with the programmable device The purpose is to provide.

  In order to solve the above problems, the present invention provides an information processing apparatus connected to a programmable device having the following characteristics. The information processing apparatus includes configuration data storage means for storing a plurality of configuration data and program storage means for storing a plurality of software programs. Each of the configuration data defines functions to be realized on the programmable device. Each of the software programs uses functions realized on the programmable device by corresponding configuration data. The information processing apparatus includes configuration request means for transferring configuration data corresponding to a selected function selected from a plurality of configuration data to the programmable device and requesting the configuration.

  According to the above configuration, in an information processing apparatus using a programmable device, it is possible to configure the programmable device in various settings required by the information processing apparatus, and to realize operations in cooperation with the information processing apparatus. The effectiveness of the device can be significantly improved.

The block diagram which shows the outline of the arithmetic system by 1st Embodiment. The figure explaining the program and structure data which are managed by matching. The figure showing GUI for adding, changing, and deleting a set of programs and configuration data. The flowchart which shows the whole flow at the time of starting the arithmetic processing which made the host and accelerator by 1st Embodiment cooperate. 5 is a flowchart illustrating calculation processing in which a host and an accelerator according to the first embodiment are linked. The flowchart relevant to the function change by 1st Embodiment. The flowchart which shows the function switching process by 1st Embodiment. The figure explaining the utilization aspect which applied the cooperation calculation of a host and an accelerator to the video decoding process. The figure explaining another utilization aspect. The block diagram which shows the outline of the arithmetic system by 2nd Embodiment. The sequence diagram which shows the whole flow of the arithmetic processing which made the external device by 2nd Embodiment, a host, and an accelerator cooperate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the embodiments of the present invention are not limited to the embodiments described below. In the embodiment described below, an information processing apparatus constituting an arithmetic system that realizes arithmetic processing in cooperation with an accelerator equipped with a programmable device will be described as an example.

  FIG. 1 is a block diagram showing an outline of the arithmetic system according to the first embodiment. The arithmetic system 100 shown in FIG. 1 includes an information processing device 110 and an accelerator 150. The accelerator 150 includes a programmable device that is an integrated circuit on which the internal logic circuit can be rewritten on the user side. Programmable devices specifically include programmable PLDs (Programmable Logic Devices) such as PAL (Programmable Array Logic) and GAL (Generic Array Logic), CPDs (Complex Programmable Devices), and FPGAs (Field Programmable Gate Arrays). -It is a logic device. In the following description, it is assumed that the accelerator 150 includes an FPGA.

  The information processing apparatus 110 is a host apparatus that uses an accelerator 150 that implements various arithmetic processes such as image processing and video processing as hardware circuits. The information processing apparatus 110 is not particularly limited, but is a general-purpose computer such as a personal computer, a workstation, or a server, an image processing apparatus such as a multifunction peripheral, a copier, a printer, a facsimile, or a scanner, or a PDA (Personal Digital Assistance). ) And mobile information terminals such as smartphones.

  The information processing apparatus 110 includes a CPU 112, a control unit 114, a RAM 116, a program storage unit 118, a configuration data storage unit 120, and a transmission buffer 122. The CPU 112 is means for performing overall control of the information processing apparatus 110 including arithmetic processing in cooperation with an accelerator 150 described later. The control unit 114 is a means for controlling the data flow in the information processing apparatus 110. The RAM 116 is a storage device that provides a work space for calculation by the CPU 112.

  The program storage unit 118 is a storage area for storing software program codes executed by the information processing apparatus 110. The configuration data storage unit 120 is a storage area that stores configuration data that defines the functional configuration of the programmable device mounted on the accelerator 150. The program storage unit 118 and the configuration data storage unit 120 store a plurality of software program codes and configuration data, respectively. The program storage unit 118 and the configuration data storage unit 120 are not particularly limited, but can be provided by a secondary storage device such as a hard disk drive (HDD) or a solid state drive (SSD). The transmission buffer 122 is a buffer memory that temporarily stores data when the configuration data is transferred to the accelerator 150.

  The accelerator 150 includes a control unit 152, a configuration data storage unit 154, a local memory 156, a reconfigurable computing unit array 158, and an external interface 160. The control unit 152 is a unit that performs overall control including the data flow in the accelerator 150. The local memory 156 is a local memory used in the accelerator 150.

  The configuration data storage unit 154 is a storage area for storing configuration data of the programmable device included in the accelerator 150 described above. The configuration data storage unit 154 is configured by a nonvolatile or volatile memory device such as an EEPROM or an SRAM.

  The reconfigurable arithmetic unit array 158 includes a two-dimensional array of a plurality of logic elements. The logic function realized by the programmable device in the accelerator 150 is determined by designating the logic function of each logic element and the connection relationship between the logic elements. The configuration data refers to information specifying the logic function of the programmable device as described above, and is also called a configuration bitstream, and constitutes configuration data in the present embodiment. Hereinafter, the configuration data is referred to as configuration data. The external interface 160 is a communication unit that communicates with the information processing apparatus 110 and receives various commands and configuration data.

  The calculator array 158 in this embodiment can be reconfigured. Reconfiguration refers to changing the logic function of a programmable device to a different logic function by rewriting the configuration data in the configuration data storage unit 154 for the programmable device that can be rewritten many times. It means changing.

  In the arithmetic system 100, the information processing apparatus 110 reads the configuration data from the configuration data storage unit 120 by the CPU 112 and transmits it to the accelerator 150 at a suitable time such as when the power is turned on, idle, or when there is a user instruction. Requesting configuration processing of the programmable device. The accelerator 150 stores the configuration data received via the external interface 160 in the configuration data storage unit 154 by the control unit 152. In the accelerator 150, the control unit 152 performs circuit configuration processing of the arithmetic unit array 158 that can be reconfigured according to the configuration data stored in the configuration data storage unit 154. As a result, preparation for providing an arithmetic function to the information processing apparatus 110 is performed.

  The information processing apparatus 110 receives notification of the completion of preparation of the accelerator 150 from the CPU 112 and executes the software program code stored in the program storage unit 118. The software program code is a code that uses a function realized on the programmable device of the accelerator 150 by the configuration data. Hereinafter, the software program code is simply referred to as a program. Programs and configuration data are managed in association with each other as shown in FIG.

  FIG. 2 is a diagram for explaining programs and configuration data managed in association with each other. FIG. 2A shows the data structure of a management table that associates programs with configuration data. As shown in FIG. 2A, the program and configuration data are registered in a table in association with each function. As shown in FIG. 2B, a plurality of programs 200, 202, 204, 206 and a plurality of programs stored in the program storage unit 118 and the configuration data storage unit 120 are stored in the management table shown in FIG. Configuration data 210, 212, 214, and 216 are associated with each other.

  Note that the program and configuration data stored in the program storage unit 118 and the configuration data storage unit 120 are not fixed in this embodiment, and various functions are realized by adding, changing, and deleting. It is possible. FIG. 3 shows a graphical user interface (GUI) for adding, changing, and deleting a set of programs and configuration data stored in the program storage unit 118 and the configuration data storage unit 120.

  FIG. 3A shows a registration list display screen for displaying registered programs and configurations in association with each other. A registration list display screen 220 shown in FIG. 3A includes a list display table 222 for displaying a list of registered functions, a new addition button 226, an edit button 228, a delete button 230, a setting button 232, And a cancel button 234. The list display table 222 includes a column 222a in which the name of the function is displayed, a column 222b in which a program corresponding to the function is displayed, and a column 222c in which configuration data corresponding to the function is displayed.

  When the delete button 230 is clicked in a state where the function-program-configuration data set 224 is selected in the list display table 222, the set is deleted from the registration. The program and configuration data deleted from the registration are deleted from the program storage unit 118 and the configuration data storage unit 120, respectively, or deleted at a later date with a deletion flag set. When the new addition button 226 is clicked, a new registration screen shown in FIG. 3B is displayed. When the edit button 228 is clicked with the function-program-configuration data set 224 selected, an edit screen similar to FIG. 3B for editing the registered contents of the set is displayed.

  FIG. 3B shows a new registration screen for newly registering a set of programs and configuration data. The new registration screen 240 shown in FIG. 3B has a table 242 for inputting contents to be registered, an add button 248 for executing a new addition with the contents of the table 242, and for canceling the new addition. The cancel button 250 is included. The table 242 includes a text box 244 for inputting a name of a function, and text boxes 246a and 246b with reference buttons for specifying a program and configuration data to be registered in association with the function. When the text boxes with reference buttons 246a and 246b are clicked, a file selection dialog box is displayed.

  The operator inputs a function name in the text box 244, uses the reference buttons in the text boxes with reference buttons 246a and 246b as appropriate to select files, and clicks the add button 248 to add a new function. It can be performed. Then, the operator can confirm the registered content by clicking the setting button 232 shown in FIG. Alternatively, the operator can discard the registered content by clicking the cancel button 234. Note that an edit screen displayed in response to the edit button 228 can have the same configuration as that shown in FIG.

  The GUI illustrated in FIG. 3 is displayed on a display included in the information processing apparatus 110 or a display included in an external apparatus (not illustrated) that accesses a remote interface provided by the information processing apparatus 110. A program and configuration data are designated by an operation on the GUI by the information processing apparatus 110 or an input device included in the external apparatus. Then, in response to the designation, the information processing apparatus 110 receives a program and configuration data stored in the storage area in the information processing apparatus 110 or the storage area of the external apparatus in response to the designation, and the program storage unit 118 and the configuration data Accumulate in the accumulation unit 120.

  Regarding the operation of managing programs and configuration data, when functions are managed as in the management table shown in FIG. 2A, the standard function cannot be changed and the optional function can be changed. It is done. In this case, it is possible to avoid a shortage of recording capacity in a device having a small recording capacity by installing only necessary functions. In addition, subsequent updates such as improvements to installed functions and countermeasures against failures will be easier.

  Furthermore, it is desirable to add, change, and delete the above-described program and configuration data at a timing that does not cause inconvenience in function execution, such as when the information processing apparatus 110 is idle or after function execution is stopped according to a user instruction. . In addition, although it has been described that the program-configuration data pair is registered using the GUI shown in FIG. 3, the device that does not have a display or the like is appropriately updated with manual operation for firmware update. A state program and configuration data may be updated.

  In the arithmetic system 100 according to the present embodiment, as shown in FIG. 2, the program and the configuration data are managed in association with each other. Therefore, the information processing apparatus 110 receives the accelerator 150 from the information processing apparatus 110. The configuration data corresponding to the function required for 150 is transmitted. Therefore, no inconsistency occurs between the programs and configuration data of the information processing apparatus 110 and the accelerator 150. Since the program and the configuration data are managed as a set for each function, the software program code and the configuration data to be used are uniquely determined by designating the function.

  Hereinafter, with reference to FIG. 4 and FIG. 5, details of the arithmetic processing in which the information processing apparatus 110 and the accelerator 150 are linked in the arithmetic system 100 according to the first embodiment will be described. FIG. 4 is a flowchart illustrating an overall flow at the time of starting the arithmetic processing in which the information processing apparatus and the accelerator according to the first embodiment are linked. In FIG. 4 and FIG. 5, each processing step is described separately for the execution subject. Steps S100 to S104 shown in FIG. 4 and steps S300 to S307 shown in FIG. 5 are processes in which the information processing apparatus (host) 110 is the execution subject. Steps S200 to S206 shown in FIG. 4 and steps S400 to S407 shown in FIG. 5 are processes in which the accelerator 150 is the execution subject.

  The process shown in FIG. 4 is started from step S100 and step S200 in response to the information processing apparatus (host) 110 and the accelerator 150 being turned on and activated. In step S <b> 101, the information processing apparatus 110 causes the CPU 112 to read configuration data from the configuration data storage unit 120 and transmit the configuration data to the accelerator 150 to request configuration processing of the programmable device. Here, the transmitted configuration data is configuration data corresponding to a function selected in advance among the plurality of registered functions. The CPU 112 constitutes a configuration request unit in the present embodiment. In step S <b> 201, the accelerator 150 receives configuration data from the information processing apparatus 110.

  In step S202, the accelerator 150 stores the received configuration data in the configuration data storage unit 154. In step S203, the accelerator 150 performs configuration processing of the circuit configuration of the reconfigurable computing element array 158 according to the stored configuration data. When the accelerator 150 completes the configuration process, in step S204, the accelerator 150 outputs a preparation completion signal indicating that the preparation for providing the function is completed to the information processing apparatus 110. Corresponding to step S204, in step S102, the information processing apparatus 110 receives a preparation completion signal from the accelerator 150.

  When the preparation completion signal is received, in step S103, the information processing apparatus 110 starts execution of the program corresponding to the transmitted configuration data and performs arithmetic processing (hereinafter referred to as cooperative arithmetic and reference) in cooperation with an accelerator 150 described later. ). On the accelerator 150 side as well, in step S205 corresponding to step S103, cooperative calculation processing is performed.

  FIG. 5 is a flowchart illustrating a calculation process in which the information processing apparatus (host) and the accelerator according to the first embodiment are linked. The process shown in FIG. 5 starts from step S300 and step S400, respectively, in response to the cooperation calculation process being called in step S103 and step S205 shown in FIG. In step S <b> 301, the information processing apparatus 110 starts arithmetic processing of the program and instructs the initialization of the accelerator 150. Corresponding to step S301 on the host side, in step S401, the accelerator 150 executes arithmetic processing start processing and initializes the arithmetic circuit.

  In step S302, the information processing apparatus 110 determines whether or not to end the processing because the processing by the program has reached the end. If it is determined in step S302 that the program is not terminated (NO), the process proceeds to step S303. In step S303, the information processing apparatus 110 executes the instruction code on the information processing apparatus 110 side included in the program, and drives the accelerator 150 in response to the instruction code using the accelerator 150 to request calculation. .

  Corresponding to step S303 on the host side, in step S402, the accelerator 150 executes the operation requested by the information processing apparatus 110 by the logic function of the reconfigurable operation unit array 158 of the programmable device. In step S <b> 403, the accelerator 150 returns the requested calculation result to the information processing apparatus 110.

  Corresponding to step S403 on the accelerator side, in step S304, the information processing apparatus 110 receives the calculation result from the accelerator 150 and branches the process to step S302. On the accelerator side, after step S403, in step S404, the accelerator 150 branches the process depending on whether the next calculation is requested or a calculation end command is issued. In step S404, if the calculation end command is not issued and there is a request for the next calculation corresponding to step S303 on the host side (NO), the process loops to step S402 and the calculation requested in step S402 is executed. Run.

  If it is determined in step S302 that the process is terminated because the process by the program has reached the end (YES), the process proceeds to step S305. In step S305, the information processing apparatus 110 instructs the accelerator 150 to end the calculation. On the accelerator side, in step S404, the process branches depending on whether the next calculation is requested or a calculation end command is issued, and if a calculation end command is issued in response to step S305 (YES), Then, the process proceeds to step S405.

  In step S405, the accelerator 150 executes calculation end processing (following cleanup), reports completion of calculation end processing in step S406, ends this processing in step S407, and returns to the processing shown in FIG. Corresponding to step S406 on the accelerator side, in step S306, the information processing apparatus 110 executes calculation end processing (follow-up processing), ends this processing in step S307, and returns to the processing shown in FIG. . When the information processing apparatus 110 and the accelerator 150 return from step S307 and step S407 shown in FIG. 5 and complete the cooperative calculation process, the information processing apparatus 110 and the accelerator 150 end the process in step S104 and step S206, respectively.

  According to the processing shown in FIGS. 4 and 5, when the arithmetic system 100 is activated, configuration data corresponding to a preselected function is transferred from the information processing apparatus 110 to the accelerator 150 and is based on the configuration data. Thus, an arithmetic unit array 158 is configured. After the arithmetic unit array 158 completes the configuration, the information processing apparatus 110 can start a program corresponding to a preselected function and perform a desired cooperative arithmetic process while driving the accelerator 150. it can.

  By the way, as a programmable device mounted on the accelerator 150, a semiconductor device called a dynamic reconfigurable processor is known. This semiconductor device can be dynamically reconfigured, that is, the circuit can be rewritten in a very short time without shutting down the power supply. Especially in recent FPGAs, the dynamic reconfiguration is partially possible. The scope of application is also expanding. If a dynamic reconfigurable processor is used as the programmable device mounted on the accelerator 150, the configuration of the programmable device can be updated immediately without waiting for the power-off of the information processing apparatus (host) 110, The function provided by the accelerator 150 can be changed.

  The processing at the time of starting up the arithmetic system 100 has been described so far. Hereinafter, processing for changing functions in response to an instruction from the user after starting will be described with reference to FIGS. 6 and 7. By using the dynamic reconfiguration, the arithmetic system 100 can be programmed without restarting the arithmetic system 100 even when a function different from the function currently configured in the accelerator 150 is required. It is possible to change the logic function of the device to a different logic function and perform other different cooperative calculation processes.

  FIG. 6A is a flowchart illustrating processing for changing a function realized in cooperation with an accelerator, which is executed by the information processing apparatus (host) according to the first embodiment. The process shown in FIG. 6A starts from step S500 in response to the activation of the arithmetic system 100. In step S501, the information processing apparatus 110 determines whether or not there has been an instruction to change the function from the user, and loops step S501 until the instruction to change the function is received from the user (during NO). I wait.

  If it is determined in step S501 that there has been a function change instruction from the user (YES), the process proceeds to step S502. In step S <b> 502, the information processing apparatus 110 confirms the operating state of itself and the accelerator 150. In step S503, the information processing apparatus 110 determines whether the function change can be performed immediately. In the embodiment to be described, when both the information processing apparatus 110 and the accelerator 150 are in an idle state, it is determined that immediate execution is possible.

  If it is determined in step S503 that immediate execution is possible (YES), the function switching process is executed in step S504, and when the function switching process is completed, the process loops to step S501 and waits for the next instruction. . On the other hand, if it is determined in step S503 that immediate implementation is not possible (NO), the process proceeds to step S505. In step S505, the information processing apparatus 110 inputs a function change instruction to the queue in which the task is registered, loops to step S501, and waits for the next instruction.

  FIG. 6B is a flowchart illustrating a process of executing a function change command placed in a queue, which is executed by the information processing apparatus (host) according to the first embodiment. The process shown in FIG. 6B starts from step S600 in response to the activation of the arithmetic system 100. In step S601, the information processing apparatus 110 determines whether or not the information processing apparatus 110 is in an idle state, and loops step S601 and waits until the information processing apparatus 110 is in an idle state (during NO).

  Note that the idle state of the information processing apparatus 110 can be determined by monitoring a task scheduler provided in the OS (Operating System) of the information processing apparatus 110. Alternatively, a resource management function unique to the system by monitoring the input / output portion and the job management wait queue may be used.

  If it is determined in step S601 that the information processing apparatus 110 is in the idle state (YES), the process proceeds to step S602. In step S602, the information processing apparatus 110 determines whether there is a function change command in the queue. If it is determined in step S602 that there is no function change command in the queue (NO), the process loops to step S601 and waits for the function change command.

  On the other hand, if it is determined in step S602 that there is a function change instruction in the queue (YES), the process branches to step S603. In step S <b> 603, the information processing apparatus 110 makes an inquiry to the accelerator 150 and confirms the operation state of the accelerator 150. In step S604, the information processing apparatus 110 determines whether a function change can be performed. In the embodiment to be described, when both the information processing apparatus 110 and the accelerator 150 are in an idle state, it is determined that implementation is possible.

  If it is determined in step S604 that implementation is possible (YES), a function switching process is executed in step S605. After the function change instruction is deleted from the queue in step S606, the process is looped to step S601. Wait for the next instruction. On the other hand, if it is determined in step S604 that it cannot be performed (NO), the process loops to step S601 and waits until it can be performed.

  FIG. 7 is a flowchart showing a function switching process according to the first embodiment. In FIG. 7, as in FIGS. 4 and 5, steps S700 to S705 are processes in which the information processing apparatus (host) 110 is the execution subject, and steps S800 to S806 are the execution subjects of the accelerator 150. It is processing that becomes.

  The process shown in FIG. 7 is called in step S504 shown in FIG. 6A or step S605 shown in FIG. 6B, and is started from step S700 and step S800. In step S701, the information processing apparatus 110 prepares a program and configuration data corresponding to the selected function. Here, it is assumed that the program corresponding to the previously selected function has ended. In step S702, the information processing apparatus 110 requests the accelerator 150 to change the function and transmits configuration data corresponding to the changed function. In step S801, the accelerator 150 receives configuration data from the information processing apparatus 110 together with a function change request.

  In step S802, the accelerator 150 stores the received configuration data in the configuration data storage unit 154. In step S803, the accelerator 150 performs reconfiguration processing of the circuit configuration of the reconfigurable computing element array 158 according to the stored configuration data. . When the accelerator 150 completes the reconfiguration process, the accelerator 150 outputs a preparation completion signal to the information processing apparatus 110 in step S804. Corresponding to step S804, in step S703, the information processing apparatus 110 receives a preparation completion signal from the accelerator 150.

  In step S704, the information processing apparatus 110 starts execution of the program corresponding to the changed function and performs cooperative calculation processing with the accelerator. On the accelerator 150 side as well, corresponding to step S704, cooperative calculation processing is performed in step S805. When the cooperation calculation process ends, the process ends in steps S705 and S806. Note that the cooperation calculation called in step S805 of FIG. 7 is the same as that shown in FIG.

  As described above, by using a reconfigurable processor capable of dynamic reconfiguration as a programmable device mounted on the accelerator 150, the circuit configuration of the accelerator 150 can be changed for each function without shutting down the power. It becomes. That is, a certain task can be processed by hardware on the accelerator 150 in one aspect, and software processing can be performed by the CPU 112 in another aspect. Hereinafter, with reference to FIG. 8 and FIG. 9, a usage mode of the above-described cooperation calculation with the accelerator will be described.

  FIG. 8 is a diagram for explaining a usage mode in which the above-described cooperation calculation with the accelerator is applied to the video decoding process. The process shown in FIG. 8 starts from step S900 in response to an instruction for video playback. In step S901, the information processing apparatus 110 determines whether the quality of the video that is requested to be played is a high image quality setting. Here, for convenience of explanation, processing is branched depending on whether or not the image quality is high, but it can be determined according to the quality of the image file itself, such as the bit rate and codec type, and the quality allowed by the user It can be determined according to

  If it is determined in step S901 that the video quality is high (YES), the process proceeds to step S902. In step S902, the information processing apparatus 110 transmits configuration data corresponding to the video decoding function to the accelerator 150 and requests a change in the functional configuration. In step S903, the information processing apparatus 110 receives a preparation completion signal from the accelerator 150. In step S904, the information processing apparatus 110 executes a video decoding operation in cooperation with the accelerator 150. When the video decoding operation is completed, the video decoding process is ended in step S906.

  On the other hand, if it is determined in step S901 that the video quality is not high (NO), the process proceeds to step S905. In step S905, the information processing apparatus 110 executes video decoding processing by a software decoder, and ends the video decoding processing in step S906.

  According to the cooperative calculation processing described with reference to FIG. 8, when reproducing with high image quality, the video decoding function may be assigned to the hardware circuit on the accelerator 150 and may be reproduced with low image quality. The CPU 112 can be in charge of video decoding software. That is, by switching whether or not to use the accelerator 150 according to the size of the computation load, it is possible to reduce the possibility that the accelerator 150 will be occupied and reduce power consumption.

  FIG. 9 is a flowchart for explaining another usage mode. In the example illustrated in FIG. 9, the program corresponding to the function includes a code unit that is repeatedly executed, and the code unit executes function processing as software processing by the CPU 112 according to the preparation status of the accelerator 150. It includes a code that branches whether to execute the accelerator 150 as a linked operation. The preparation status of the accelerator 150 is represented by a preparation completion flag. The preparation completion flag is “false” while the preparation completion signal is not received from the accelerator 150. When the preparation completion signal is received, The value is “true”.

  The process illustrated in FIG. 9 starts from step S1000. In step S1001, the information processing apparatus 110 transmits corresponding configuration data to the accelerator 150. In step S1002, the information processing apparatus 110 starts function processing using a corresponding program. In step S1003, the information processing apparatus 110 determines whether an end condition of the program is satisfied. If it is determined in step S1003 that the end condition is not satisfied (NO), the process branches to step S1004.

  In step S1004, the information processing apparatus 110 determines whether the value of the preparation completion flag is “true”. If it is determined in step S1004 that the value of the ready flag is “false” (NO), the above-described code unit function process is executed as a software process in step S1005, and the process loops to step S1003. On the other hand, if it is determined in step S1004 that the value of the ready flag is “true” (YES), in step S1006, the information processing apparatus 110 performs the above-described code unit function as a cooperative operation with the accelerator 150. The process is executed, and the process loops to step S1003. If it is determined in step S1003 that the end condition is satisfied (YES), the process proceeds to step S1007 to end the process.

  According to the process shown in FIG. 9, a newly executed process in which the hardware of the accelerator 150 is not prepared is executed by the CPU 112 as a software process. On the other hand, as soon as the execution preparation by the accelerator 150 is completed, the processing is executed by switching to the operation linked with the accelerator 150. As a result, it is possible to make the operation of the entire system more efficient while reducing the CPU load.

  The first embodiment described above has the advantages described below. First, when using the function of the programmable device in the accelerator 150 from the information processing apparatus 110 side, the information processing apparatus 110 side needs to prepare a program based on the function provided by the configured device based on the configuration data. is there. That is, it is essential that the combination of the program on the information processing apparatus 110 side and the configuration data on the accelerator 150 side is appropriate. According to the first embodiment described above, the configuration data of the programmable device and the corresponding program are stored in association with each other on the information processing apparatus 110 side, and transferred from the information processing apparatus 110 to the accelerator 150 when used. Reconfigured. For this reason, a mismatch does not occur between the function that the information processing apparatus 110 expects from the accelerator 150 and the function that the accelerator 150 provides.

  In addition, the program storage unit 118 and the configuration data storage unit 120 do not need to be configured by a memory on a semiconductor chip, and are configured by using a secondary storage device that can be increased in capacity at a lower cost than such a memory. Can do. From this, it is possible to accumulate a large number of configuration data and programs in order to realize various functions, and there is no problem, and the semiconductor manufacturing cost does not increase.

  Furthermore, it takes a certain amount of time to transfer the configuration data from the host 110 to the accelerator 150 and complete the configuration setting in the accelerator 150. When a general FPGA is used as a programmable device, it takes time to stop the entire system, transmit an FPGA circuit rewrite command and configuration data, reboot the system after rewriting, and operate as a new system. Furthermore, a reboot time is required, and the user waits for this period. On the other hand, in the first embodiment, since the configuration data transfer and (re) configuration processing are executed at startup, the time required for the setting processing of the accelerator 150 is concealed in the startup time of the information processing apparatus 110. It is possible to remarkably improve the feeling of use.

  In addition, when the function change is instructed by the user, if any of the information processing apparatus 110 and the accelerator 150 is not in the idle state, the configuration of the programmable device cannot be changed unless the operation process is interrupted. According to the first embodiment, the idle state of the information processing device 110 and the accelerator 150 is detected, and the configuration data transfer and (re-) configuration processing are executed. Therefore, the result during the arithmetic processing is not lost. It becomes possible to accept a function execution request accompanied by a configuration change of the programmable device from the user.

  In addition, when a function change is instructed by the user, if any of the information processing apparatus 110 and the accelerator 150 is not in an idle state, a mode in which the process being executed is stopped or until it is stopped can be considered. In the above-described embodiment, the process is described as waiting until the process being executed stops. However, if the user permits, it does not prevent the execution of the function change after stopping the process being executed.

  The arithmetic system 100 according to the first embodiment described above is configured by an accelerator 150 and an information processing apparatus 110 that is a host of the accelerator 150. Hereinafter, an arithmetic system according to the second embodiment will be described with reference to FIGS. 10 and 11.

  FIG. 10 is a block diagram showing an outline of the arithmetic system according to the second embodiment. An arithmetic system 300 illustrated in FIG. 10 includes an accelerator 350, a first information processing device 310 that is a direct host of the accelerator 350, and a second information processing device 370. The first information processing device 310 is a direct host device that directly uses the accelerator 350 that implements various operations as a hardware circuit, and other information processing devices that cannot directly use the accelerator 350 for the processing resources of the accelerator 350 The function to provide for is provided. The second information processing device 370 is a request source that uses the computing resources of the accelerator 350 via the information processing device 310. Hereinafter, the first information processing apparatus may be referred to as the host 310, and the second information processing apparatus may be referred to as the request source 370.

  Similar to the information processing apparatus 110 according to the first embodiment, the first information processing apparatus 310 includes a CPU 312, a control unit 314, a RAM 316, a program storage unit 318, a configuration data storage unit 320, and a transmission buffer 322. The first information processing apparatus 310 according to the present embodiment further includes a network interface 324. The hardware components 312 to 322 that are the same as those described in the first embodiment function in the same manner as in the first embodiment, and thus the description thereof is omitted.

  The network interface 324 is an interface device that connects the first information processing apparatus 310 to a wired or wireless network according to a protocol such as TCP / IP or Ethernet (registered trademark). The network interface 324 of the present embodiment connects the first information processing apparatus 310 to the second information processing apparatus 370 via a network.

  On the other hand, the second information processing device 370 has a configuration similar to that of the first information processing device 310, and includes a CPU 372, a RAM 374, a data storage unit 376, and a network interface 378. The CPU 372 is means for performing overall control of the second information processing device 370 including processing that uses the accelerator 350 via the first information processing device 310 described later. The RAM 374 is a storage device that provides a work space for calculation by the CPU 372. The network interface 378 is an interface device that connects the second information processing device 370 to a wired or wireless network according to a protocol such as TCP / IP or Ethernet (registered trademark). The network interface 378 of the present embodiment connects the second information processing device 370 to the first information processing device 310 via the network.

  The data storage unit 376 is a storage area that stores software program code to be executed by the host 310 and configuration data to be transmitted to the programmable device of the accelerator 350 via the host 310 in association with each other. Software program codes to be executed by the second information processing device 370 may be stored in association with the program and configuration data. The data storage unit 376 is not particularly limited, but can be provided by a secondary storage device such as an HDD or an SSD. Since the accelerator 350 is the same as that of the first embodiment, the description thereof is omitted.

  When it becomes necessary, the second information processing device 370 requests the first information processing device 310 to perform calculation in order to receive the calculation function of the accelerator 350. In the arithmetic system 300 according to the second embodiment, the first information processing device 310 receives the configuration data corresponding to the requested arithmetic function when the second information processing device 370 requests the operation, and the configuration data storage unit The data is read from 320 and transmitted to the accelerator 350. The accelerator 350 stores the configuration data received via the external interface in the configuration data storage unit, and configures an arithmetic unit array that can be reconfigured according to the configuration data.

  The first information processing apparatus 310 receives the notification of the completion of preparation of the accelerator 350 and executes the program stored in the program storage unit 318. The program receives a request from the second information processing device 370, uses the function realized on the programmable device of the accelerator 350 by the configuration data, and returns the calculation result to the second information processing device 370. Contains code. The second information processing device 370 receives the requested calculation result transmitted from the first information processing device 310, incorporates it in its own processing, and obtains a final result.

  The program and the configuration data are managed in association with each other as in the first embodiment. The configuration data and the program may not necessarily be stored in the first information processing apparatus 310. Therefore, in the second embodiment, the request source receiving the calculation function of the accelerator 350 directly from the host 310 is used. The second information processing device 370 may provide these configuration data and programs.

  FIG. 11 is a sequence diagram illustrating an overall flow at the time of starting the arithmetic processing in which the second information processing apparatus (request source), the first information processing apparatus (host), and the accelerator according to the second embodiment are linked. The process illustrated in FIG. 11 is started from the request source 370 side, and in step S1101, the request source 370 issues a request for processing to the host 310. In response to this, the host 310 receives the processing request. In step S <b> 1102, the request source 370 designates the calculation (function) of the requested process to the host 310. In response to this, the host 310 accepts a calculation designation. In step S <b> 1103, the request source 370 transmits data and parameters used in the specified calculation to the host 310. In response to this, the host 310 receives data and parameters used in the specified calculation.

  In step S <b> 1104, the host 310 determines whether the program and configuration data corresponding to the calculation (function) designated by the request source 370 are accumulated in its own accumulation units 318 and 320. In the sequence diagram shown in FIG. 11, a case where necessary programs and configuration data are not stored in the storage units 318 and 320 will be described as an example. Step S1106 is omitted.

  In step S1105, the host 310 requests the request source 370 to transmit necessary programs and configuration data. In step S 1106, the request source 370 receives the transmission request, reads the corresponding program and configuration data from the data storage unit 376, and transmits the program and configuration data to the host 310. In step S1107, the host 310 transmits the configuration data received from the request source 370 to the accelerator 350, and requests a programmable device reconfiguration process.

  In step S1108, accelerator 350 stores the configuration data received from host 310 in the configuration data storage unit. In step S1109, the accelerator 350 performs a reconfiguration process of the circuit configuration of the reconfigurable computing element array according to the stored configuration data. After completing the configuration process, the accelerator 350 outputs a preparation completion signal to the host 310 in step S1110.

  In step S <b> 1111, the host 310 starts processing by the program received from the request source 370 together with the configuration data. In step S1112, the host 310 initializes the accelerator 350, and in step S1113, the host 310 executes an instruction code for driving the accelerator 350 using data and / or parameters, and makes an operation request. In step S <b> 1114, the host 310 receives the calculation result from the accelerator 350. Steps S1113 and S1114 are repeated as appropriate, and after the calculation requested by the request source 370 is completed, the host 310 notifies the accelerator 350 of the end in step S1115, and the request source 370 ends the calculation in step S1116. Report.

  In step S <b> 1117, the request source 370 transmits a result reception preparation completion notification to the host 310 that notifies that the calculation result is ready to be received. In step S1118, the host 310 receives the result reception preparation completion notification, executes a code for returning the processing result to the request source 370, and transmits the processing result. In step S1119, the request source 370 receives the processing result, transmits a processing result reception notification to the host 310, and receives a request end response in step S1120.

  According to the arithmetic system 300 of the second embodiment described above, even in the information processing device 370 that cannot directly use the accelerator 350, an equivalent arithmetic function can be used via the information processing device 310 that can directly use the accelerator 350. . Thereby, the effectiveness of the host 310 can be significantly improved. Further, in a configuration in which an accelerator is used only from a single host, there is usually an idle time for the accelerator, except when an operation that always requires an accelerator is performed. According to the second embodiment, the accelerator 350 can be used from the external information processing device 370, which contributes to an improvement in the utilization rate of the accelerator 350.

  Further, in the second embodiment, since the program and configuration data can be transmitted from the request source 370 even if the direct host 310 does not have the program and configuration data, the program and configuration stored in the direct host 310 can be transmitted. It is not limited to an arithmetic function that can be executed by data.

  As described above, according to the above-described embodiment, in an information processing apparatus connected to a programmable device (including an accelerator) represented by an FPGA or the like, a plurality of configuration data of the programmable device is accumulated. Providing an information processing apparatus, a calculation method, and a program for selecting and setting appropriate configuration data to realize a desired function, reconfiguring a programmable device, and performing processing linked with the programmable device it can.

  According to the above-described embodiment, in an information processing apparatus using a programmable device represented by an FPGA or the like as an accelerator, the accelerator can be configured in various settings required by the information processing apparatus and can be linked to the information processing apparatus. Thus, the effectiveness of the accelerator can be significantly improved. Furthermore, since the result of the operation in cooperation with the accelerator can be used in another information processing apparatus that does not include the accelerator via the information processing apparatus including the accelerator, the use range of the accelerator is expanded.

  The functional unit can be realized by a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark), an object-oriented programming language, or the like. EPROM, flash memory, flexible disk, CD-ROM, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, Blu-ray disc, SD card, MO, etc. Can be distributed through.

  Although the embodiments of the present invention have been described so far, the embodiments of the present invention are not limited to the above-described embodiments, and those skilled in the art may conceive other embodiments, additions, modifications, deletions, and the like. It can be changed within the range that can be done, and any embodiment is included in the scope of the present invention as long as the effects of the present invention are exhibited.

DESCRIPTION OF SYMBOLS 100,300 ... Arithmetic system, 110, 310 ... Information processing apparatus, 112, 312 ... CPU, 114, 314 ... Control unit, 116, 316 ... RAM, 118, 318 ... Program storage unit, 120, 320 ... Configuration data storage unit 122, 322 ... transmission buffer, 150, 350 ... accelerator, 152 ... control unit, 154 ... configuration data storage unit, 156 ... local memory, 158 ... reconfigurable arithmetic unit array, 160 ... external interface, 200 ... program, 210 ... Configuration data, 220 ... Registration list display screen, 222 ... List display table, 222 ... Column, 224 ... Function-program-configuration data set, 226 ... New addition button, 228 ... Edit button, 230 ... Delete button, 232 ... Setting button, 234 ... Cancel button, 240 ... New registration Surface 242 ... table 244 text box 246 text box with reference button 248 add button 250 cancel button 324 378 network interface 370 second information processing apparatus (request source) 372 ... CPU, 374 ... RAM, 376 ... Data storage unit

Japanese Patent Laid-Open No. 10-285014 JP 2007-251329 A Japanese Patent No. 4165125 JP-A-11-144661 Japanese Patent No. 3664962 JP 2008-242850 A

Claims (10)

An information processing apparatus connected to a programmable device,
Configuration data storage means for storing a plurality of configuration data defining functions to be realized on each of the programmable devices, and
Program storage means for storing a plurality of software programs that use functions realized on the programmable device by corresponding configuration data, and
An information processing apparatus comprising: configuration request means for transferring configuration data corresponding to a selected function selected from among a plurality of configuration data to the programmable device and requesting a configuration.   An operation that, after the programmable device completes the configuration, executes an instruction to use the function realized on the programmable device by the configuration data corresponding to the selection function according to the software program corresponding to the selection function The information processing apparatus according to claim 1, further comprising means. Means for receiving configuration data to be stored in the configuration data storage means, and a software program including a code that uses a function realized on the programmable device by the configuration data;
The information processing apparatus according to claim 1, further comprising: the configuration data storage unit and the program storage unit that stores the received configuration data and the software program in association with each other.   The said structure request | requirement means implements the transfer of the said configuration data, and requests | requires the structure of the said programmable device at the time of the said information processing apparatus starting, The Claim 1 characterized by the above-mentioned. Information processing device. Further comprising means for selecting the selection function;
5. The configuration request unit according to claim 1, wherein the configuration request unit is configured to transfer the configuration data in response to the designation of the selection function and request reconfiguration of the programmable device. The information processing apparatus according to item.   The configuration request unit is configured to transfer the configuration data and request reconfiguration of the programmable device when the information processing apparatus and the programmable device are in an idle state. The information processing apparatus according to any one of 1 to 5. A communication means for performing data communication between the information processing apparatus and an external apparatus;
Means for accepting calculation designation from the external device using the communication means;
Means for receiving data and / or parameters to be used in a specified operation, or one of these;
Means for using the data and parameters, or any one of these, to initiate computation in conjunction with the programmable device;
The information processing apparatus according to claim 1, further comprising: a unit that returns the result of the designated calculation to the external device using the communication unit. Using the communication means, the configuration data necessary for the designated calculation and the function realized on the programmable device by the configuration data are obtained from the external device and the function is used. Means for receiving a software program including a code for returning a calculation result to the external device;
The information processing apparatus according to claim 7, wherein the configuration request unit requests the reconfiguration by transferring the received configuration data necessary for the specified calculation to the programmable device. An arithmetic method executed by an information processing apparatus communicating with a programmable device, the information processing apparatus
Reading out configuration data corresponding to a selected function from among the plurality of configuration data from configuration data storage means in which a plurality of configuration data defining functions to be realized on each of the programmable devices is stored;
Reading a software program corresponding to the selected function from a program storage means in which a plurality of software programs that use functions realized on the programmable device by corresponding configuration data are stored;
Transferring configuration data corresponding to the selection function to the programmable device and requesting a configuration;
And a step of executing a process according to a software program corresponding to the selection function. A computer executable program that communicates with a programmable device comprising:
Configuration data storage means for storing a plurality of configuration data defining functions to be realized on each of the programmable devices,
Program storage means for storing a plurality of software programs using functions realized on the programmable device by corresponding configuration data, and a selection function selected from the plurality of configuration data in the programmable device A program that transfers configuration data corresponding to the, and functions as configuration request means for requesting configuration.