JP2013055533A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit with low power consumption.SOLUTION: A phase comparison circuit 11 compares a reference signal with a feedback signal with respect to a phase, and supplies to a charge pump 12 two kinds of phase difference signals (an UP signal and a DN signal) depending on the comparison results. A bias circuit 16 supplies a bias current to the charge pump 12. A control circuit 17 makes the bias circuit 16 operate when one or both of the two kinds of phase difference signals are in an activation state, and makes the bias circuit 16 stop when both the two kinds of phase difference signals are in a non-activation state.

Description

  The present invention relates to a PLL (Phase-locked loop) circuit.

  For the purpose of extending the battery life of portable devices, there is an increasing demand for lower power consumption of semiconductor integrated circuits. The PLL circuit is used as a frequency synthesizer, and is mounted on most SOC (System-On-a-Chip) products.

The PLL circuit includes a bias circuit that supplies a bias current to a charge pump or the like, and is required to reduce current consumption.
In order to reduce current consumption, a lock detection circuit that detects the synchronization of the feedback signal and the reference signal (lock detection) is provided, and after detecting the lock, the bias circuit is enabled at the timing of phase comparison, and the PLL is disabled otherwise. A circuit is known.

  As a method for speeding up startup when the bias circuit (reference voltage circuit / reference current circuit) is intermittently operated, a technique of holding a reference voltage in a capacitive element is known.

Special table 2003-529246 JP2011-8683A

  However, in the conventional PLL circuit, if the lock detection circuit cannot correctly detect the lock due to variations in manufacturing conditions, the bias circuit is enabled at unnecessary timing, and sufficient power consumption may not be achieved. there were.

  According to one aspect of the invention, a phase comparison circuit that compares phases of a reference signal and a feedback signal and supplies two kinds of phase difference signals according to the comparison result to a charge pump, and a bias current to the charge pump And the bias circuit is operated when one or both of the two kinds of phase difference signals are activated, and when both of the two kinds of phase difference signals are inactivated. And a control circuit for stopping the bias circuit.

  According to the disclosed PLL circuit, it is possible to suppress supply of a bias current at timings other than the timing at which the charge pump operates, and it is possible to efficiently reduce power consumption.

It is a figure which shows an example of the PLL circuit of 1st Embodiment. It is a figure which shows an example of a bias circuit and a control circuit. It is a figure which shows the other example of a bias circuit. 3 is a timing chart illustrating an operation example of the PLL circuit according to the first embodiment. It is a figure which shows a part of PLL circuit which considered the rising period of the bias current. 6 is a timing chart illustrating an operation example of the circuit of FIG. 5. It is a figure which shows a part of PLL circuit which considered the delay at the time of the fall of a charge pump current. 8 is a timing chart showing an operation example of the circuit of FIG. It is a figure which shows a part of PLL circuit which considered the rise period of the bias current, and the delay at the time of the fall of a charge pump current. 10 is a timing chart illustrating an operation example of the circuit of FIG. 9. It is a figure which shows an example of the PLL circuit of 2nd Embodiment. It is a figure which shows an example of a bias circuit. It is a figure which shows the other example of a bias circuit. It is a figure which shows an example of the PLL circuit of 3rd Embodiment. It is a figure which shows an example of the PLL circuit of 4th Embodiment. 14 is a timing chart illustrating an example of the operation of the PLL circuit according to the fourth embodiment. It is a figure which shows the other example of a bias circuit. It is a figure which shows the other example of a bias circuit. It is a figure which shows an example of the PLL circuit of 5th Embodiment. It is a timing chart which shows an example of operation | movement at the time of the operation | movement start of a PLL circuit. 6 is a timing chart showing an operation example when an abnormality occurs in the reference voltage during the operation of the PLL circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a PLL circuit according to the first embodiment.

  The PLL circuit 10 includes a phase comparison circuit 11, a charge pump 12, a filter 13, a voltage control oscillator 14, a feedback frequency divider 15, a bias circuit 16, and a control circuit 17.

  The phase comparison circuit 11 compares the phase of the reference signal input from the input terminal IN and the phase of the feedback signal output from the feedback frequency divider 15, and uses two types of phase difference signals (hereinafter referred to as an UP signal) according to the comparison result. (Referred to as a DN signal) is supplied to the charge pump 12. The phase comparison circuit 11 activates the UP signal when the transition of the reference signal occurs before the transition of the feedback signal, and the DN signal when the transition of the reference signal occurs after the transition of the feedback signal. Is activated.

The charge pump 12 generates a charge pump current according to the UP signal and the DN signal.
The filter 13 filters the charge pump current to generate a control voltage and supply it to the voltage controlled oscillator 14.

The voltage controlled oscillator 14 adjusts the oscillation frequency of the output signal according to the control voltage, outputs the adjusted output signal from the output terminal OUT, and supplies it to the feedback frequency divider 15.
The feedback frequency divider 15 divides the frequency of the output signal of the voltage controlled oscillator 14 by an arbitrary integer ratio. If frequency multiplication is not required, the feedback frequency divider 15 may not be provided.

The bias circuit 16 supplies a bias current for generating a charge pump current to the charge pump 12.
The control circuit 17 causes the bias circuit 16 to operate when one or both of the UP signal and the DN signal are in an activated state, and the bias circuit when both the UP signal and the DN signal are in an inactivated state. 16 is stopped. In the following example, the case where the signal level is “1” (or H (High) level) is described as an activated state, and the case where the signal level is “0” (or L (Low) level) is described as an inactivated state. However, “0” may be an activated state, and “1” may be an inactivated state.

FIG. 2 is a diagram illustrating an example of the bias circuit and the control circuit.
The bias circuit 16 includes a current source 20, switches 21 and 22, and n-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) (hereinafter abbreviated as nMOS) 23 and 24.

  The drain of the nMOS 23 is connected to the charge pump 12 via the switch 21, and the source is grounded. The gate of the nMOS 23 is connected to the gate of the nMOS 24. The gate of the nMOS 24 is further connected to the drain of the nMOS 24. The drain of the nMOS 24 is connected to the current source 20 via the switch 22, and the source is grounded. The switches 21 and 22 are turned on or off by a control signal from the control circuit 17.

  Such a bias circuit 16 has a function of a current mirror. When the switches 21 and 22 are turned on, the current generated by the current source 20 is supplied to the charge pump 12 as a bias current.

  The control circuit 17 has an OR circuit 25. When one or both of the UP signal and the DN signal output from the phase comparison circuit 11 are “1”, “1” is output, and when both the UP signal and the DN signal are “0”, “1” is output. 0 ”is output. That is, the OR circuit 25 outputs “1” when one or both of the UP signal and the DN signal are activated, and “0” when both the UP signal and the DN signal are deactivated. "Is output.

  In the example of the bias circuit 16 and the control circuit 17 in FIG. 2, the switches 21 and 22 are, for example, nMOS, and are turned on when “1” is supplied from the OR circuit 25 of the control circuit 17, and “0” is set to “0”. Turns off when supplied.

  Accordingly, the bias circuit 16 operates as a current mirror when one or both of the UP signal and the DN signal output from the phase comparison circuit 11 are in an activated state, and supplies a bias current to the charge pump 12. . The bias circuit 16 stops operating when both the UP signal and the DN signal are inactive. Thereby, the supply of the bias current to the charge pump 12 is cut off.

  In the bias circuit 16 of FIG. 2, the nMOSs 23 and 24 are used. However, the present invention is not limited to this, and a p-channel MOSFET (hereinafter abbreviated as pMOS) may be used.

FIG. 3 is a diagram illustrating another example of the bias circuit.
The bias circuit 16a shown in FIG. 3 includes pMOSs 26 and 27, switches 28 and 29, and a current source 30.

  The drain of the pMOS 26 is connected to the charge pump 12 via the switch 28, and the source is connected to the power source. The gate of the pMOS 26 is connected to the gate of the pMOS 27. The gate of the pMOS 27 is further connected to the drain of the pMOS 27. The drain of the pMOS 27 is connected to the current source 30 via the switch 29, and the source is connected to the power source. The switches 28 and 29 are turned on or off by a control signal from the control circuit 17.

  Such a bias circuit 16a also has a function of a current mirror like the bias circuit 16 of FIG. 2, and when the switches 28 and 29 are turned on, the current generated by the current source 30 is used as a bias current as the charge pump 12. To be supplied.

  Also in the example of the bias circuit 16a and the control circuit 17 in FIG. 3, the switches 28 and 29 are, for example, nMOS, and are turned on when “1” is supplied from the OR circuit 25 of the control circuit 17, and “0” is set to “0”. Turns off when supplied.

  Thus, the bias circuit 16a operates as a current mirror when one or both of the UP signal and the DN signal output from the phase comparison circuit 11 are in an activated state, and supplies a bias current to the charge pump 12. . The bias circuit 16a stops operating when both the UP signal and the DN signal are inactive. Thereby, the supply of the bias current to the charge pump 12 is cut off.

Hereinafter, an example of the operation of the PLL circuit 10 according to the first embodiment will be described using a timing chart.
FIG. 4 is a timing chart illustrating an operation example of the PLL circuit according to the first embodiment.

  In FIG. 4, an input clock (CK), a feedback signal (FB), an UP signal (UP), and a DN signal (DN), which are reference signals, are shown from the top. Further, a control signal (bias enable) output from the control circuit 17, a bias current (Ibias) supplied to the charge pump 12, and a charge pump current (Icp) are shown.

  At time t1 when CK rises to H level, FB remains at L level, and at time t2, FB rises to H level. That is, the phase of the FB is delayed compared to the phase of the reference signal CK.

  For this reason, the phase comparison circuit 11 raises UP to the H level and activates it at time t1. As a result, the bias enable also rises to the H level, Ibias flows, and the charge pump 12 starts to flow Icp.

  When FB rises to the H level at time t2, the phase comparison circuit 11 activates both UP and DN until time t3. This is to prevent a dead zone from occurring in the vicinity of the phase difference of 0 in the “UP / DN signal pulse width vs. phase difference” characteristic of the phase comparison circuit 11. Both UP and DN are active for a short time. It is supposed to be in a state of becoming. Between time t2 and time t3, the current generated by UP and DN cancels out inside the charge pump 12, so Icp at this time is 0 as shown in FIG.

Next, at time t4, FB rises, and then CK rises at time t5. That is, the phase of the FB is advanced compared to the phase of the reference signal CK.
Therefore, the phase comparison circuit 11 raises DN to the H level and activates at time t4. As a result, the bias enable also rises, Ibias flows, and the charge pump 12 starts to flow negative Icp.

From time t5 to time t6, UP and DN are both activated for the same reason as described above, and Icp is 0 at this time.
As described above, at the timing when UP or DN is activated, the charge pump 12 operates and Icp flows.

  In the PLL circuit 10 of the present embodiment, the bias circuit is operated when one or both of the UP signal and the DN signal are in the activated state, and is stopped otherwise, and the bias current is cut off. Thereby, supply of a bias current other than the timing at which the charge pump 12 operates can be suppressed, and power consumption can be efficiently reduced.

  By the way, if it takes time for the bias current to rise after the bias circuit 16 starts operating due to the control signal from the control circuit 17, or if noise occurs when the bias current rises, the charge pump 12 operates. May have an impact. In order to suppress this, for example, the following circuit may be further provided.

FIG. 5 is a diagram showing a part of the PLL circuit in consideration of the rising period of the bias current. Elements similar to those in FIG. 1 are denoted by the same reference numerals.
As shown in FIG. 5, a delay circuit 40 having delay elements (buffers) 41 and 42 is provided between the phase comparison circuit 11 and the charge pump 12. For example, the delay element 41 delays the UP signal output from the phase comparison circuit 11 and supplies it to the charge pump 12, and the delay element 42 delays the DN signal output from the phase comparison circuit 11 and supplies it to the charge pump 12. To do. The delay amount of the delay circuit 40 is set, for example, so as to delay the UP signal and the DN signal for a time until the bias current is stabilized at a constant current at the time of rising of the bias current.

  The OR circuit 25a of the control circuit 17a inputs the UP signal and DN signal before and after the delay, and outputs the logical sum of these signals to the bias circuit 16 as a control signal (bias enable).

FIG. 6 is a timing chart showing an operation example of the circuit of FIG.
In FIG. 6, from the top, the UP signal before delay (UP1), the UP signal after delay (UP2), the control signal (bias enable) output from the control circuit 17a, and the bias current (Ibias) supplied to the charge pump 12 ), The charge pump current (Icp) is shown. FIG. 6 shows a case where only the UP signal is activated for the sake of simplicity.

  When UP1 rises at time t1, the control circuit 17a sets the bias enable to the H level and starts the operation of the bias circuit 16. Thereby, Ibias starts to rise. At this time, since UP2 remains at the L level, the charge pump 12 does not flow Icp.

When Ibias rises to a constant current value and UP2 rises to H level at time t2, the charge pump 12 starts to flow Icp.
When UP1 falls to the L level at time t3, the control circuit 17a continues to supply the bias enable to the bias circuit 16 because the UP2 remains at the H level.

  When UP2 falls to the L level at time t4, the control circuit 17a falls the bias enable to the L level. Thereby, Ibias output from the bias circuit 16 decreases to zero. Further, the charge pump 12 causes Icp to fall.

  As described above, in the PLL circuit shown in FIG. 5, the delay circuit 40 is provided to delay the UP signal and the DN signal input to the charge pump 12, and the control circuit 17a causes the charge pump 12 to start flowing the charge pump current. Before, the operation of the bias circuit is started.

  Thereby, in addition to the effect that the power consumption can be efficiently reduced as described above, the PLL circuit has an effect that the malfunction of the charge pump 12 due to an unstable bias current at the time of rising can be suppressed. Also have.

  By the way, due to the delay in the charge pump 12, even if both the UP signal and the DN signal are inactivated, the charge pump current may not fall immediately. In order to maintain the accuracy of the charge pump current, the bias current is preferably supplied to the charge pump 12 while the charge pump current is flowing.

FIG. 7 is a diagram showing a part of the PLL circuit in consideration of the delay at the time of falling of the charge pump current. Elements similar to those in FIG. 1 are denoted by the same reference numerals.
The control circuit 17b has a delay circuit 43 that delays the UP signal and the DN signal, and the OR circuit 25b inputs the UP signal and the DN signal before and after the delay, and inputs the logical sum to the bias circuit 16 as a control signal (bias enable). ) Is output.

  The delay circuit 43 includes delay elements (buffers) 43a and 43b. For example, the delay element 43a delays an UP signal output from the phase comparison circuit 11, and the delay element 43b includes a DN output from the phase comparison circuit 11. Delay the signal. The delay amount of the delay circuit 43 is set so that, for example, the delay time of the UP signal and the DN signal is equal to or longer than the delay time inside the charge pump 12.

In the example of FIG. 7, the delay circuit 43 is included in the control circuit 17b, but may be a circuit block different from the control circuit 17b.
FIG. 8 is a timing chart showing an operation example of the circuit of FIG.

  In FIG. 8, from the top, the UP signal before delay (UP1), the UP signal after delay (UP2), the control signal (bias enable) output from the control circuit 17b, and the bias current (Ibias) supplied to the charge pump 12 ), The charge pump current (Icp) is shown. FIG. 8 shows a case where only the UP signal is activated for the sake of simplicity.

  When UP1 rises at time t1, the control circuit 17b sets the bias enable to the H level and starts the operation of the bias circuit 16. Thereby, Ibias starts to rise. However, the charge pump 12 does not start to flow Icp until time t2 due to an internal delay. In the case of the example of FIG. 8, the time from time t1 to time t2 is the delay time of the charge pump 12.

  At time t2, the charge pump 12 starts outputting Icp based on Ibias. UP2 rises to H level from time t1 at time t3 after the delay time by delay circuit 43 has elapsed.

  Even when UP1 becomes L level at time t4, UP2 remains at H level, so that the control circuit 17b continues to supply the bias circuit 16 with the H level bias enable. Even if UP1 falls to the L level, the charge pump 12 continues to output Icp until time t5 due to an internal delay. In the example of FIG. 8, the time from time t4 to time t5 is the delay time of the charge pump 12 when Icp is lowered.

When UP2 falls to L level at time t6, the bias enable falls to L level, and Ibias starts to fall.
As described above, according to the PLL circuit as shown in FIG. 7, the power consumption can be efficiently reduced as described above, and even if the charge pump current does not fall immediately due to the delay, the charge pump 12 The bias current can be continuously supplied for a certain period. Thereby, malfunction of the charge pump 12 can be suppressed.

Note that the PLL circuit shown in FIG. 5 and the PLL circuit shown in FIG. 7 can be combined as follows.
FIG. 9 is a diagram showing a part of the PLL circuit in consideration of the rising period of the bias current and the delay at the fall of the charge pump current. Elements similar to those shown in FIGS. 5 and 7 are given the same reference numerals.

  In the PLL circuit shown in FIG. 9, the delay circuit 40 shown in FIG. 5 and the control circuit 17b shown in FIG. 7 are combined. The UP signal and DN signal delayed by the delay circuit 40 are further delayed by the delay circuit 43 of the control circuit 17b and input to the OR circuit 25b.

FIG. 10 is a timing chart showing an operation example of the circuit of FIG.
In FIG. 10, the UP signal (UP1) before the delay, the UP signal (UP2) after the delay by the delay circuit 40, and the UP signal (UP3) after the delay by the delay circuit 43 are shown from the top. Further, a control signal (bias enable) output from the control circuit 17b, a bias current (Ibias) supplied to the charge pump 12, and a charge pump current (Icp) are shown. FIG. 10 shows a case where only the UP signal is activated for the sake of simplicity.

  When UP1 rises at time t1, the control circuit 17b sets the bias enable to the H level and starts the operation of the bias circuit 16. Thereby, Ibias starts to rise. At this time, since UP2 remains at the L level, the charge pump 12 does not flow Icp.

  When Ibias rises to a constant current value and UP2 rises to H level at time t2, the charge pump 12 starts to flow Icp at time t3 after the delay time in the charge pump 12 elapses.

UP3 rises to the H level at time t4 after the elapse of the delay time by the delay circuit 43 from time t2.
When UP1 falls to the L level at time t5, the control circuit 17b continues to supply the bias enable to the bias circuit 16 because the UP3 remains at the H level.

When UP2 falls to L level at time t6, charge pump 12 starts to cut off Icp at time t7 due to an internal delay.
When UP3 falls to the L level at time t8, the control circuit 17b falls the bias enable to the L level. Thereby, Ibias output from the bias circuit 16 decreases to zero.

  According to the PLL circuit shown in FIG. 9, the power consumption can be efficiently reduced as described above, and the unstable bias current at the rise time and the charge pump current does not fall immediately due to the delay. The malfunction of the charge pump 12 can be suppressed.

  6, 8, and 10, the case where only the UP signal is activated has been described. However, when only the DN signal is activated, or both the UP signal and the DN signal are activated. The same operation is performed also in this case.

(Second Embodiment)
FIG. 11 is a diagram illustrating an example of a PLL circuit according to the second embodiment. Elements that are the same as those of the PLL circuit 10 of the first embodiment shown in FIG.

The PLL circuit 10a of the second embodiment corresponds to the case where the voltage controlled oscillator 14 is a circuit block that uses a bias current generated by the bias circuit 50.
That is, unlike the PLL circuit 10 shown in FIG. 1, the PLL circuit 10 a includes a bias circuit 50 that supplies a bias current not only to the charge pump 12 but also to the voltage controlled oscillator 14.

The bias circuit 50 includes a reference voltage / bias current generator 51, a switch 52, a capacitive element 53, and a bias current generator 54.
The reference voltage / bias current generator 51 generates a reference voltage for generating a bias current and also generates a bias current to be supplied to the charge pump 12.

The switch 52 is controlled to be turned on / off by a control signal from the control circuit 17.
The capacitive element 53 holds the reference voltage generated by the reference voltage / bias current generator 51.

The bias current generator 54 generates a bias current based on the reference voltage held in the capacitive element 53 and supplies the bias current to the voltage controlled oscillator 14.
FIG. 12 is a diagram illustrating an example of the bias circuit.

In the bias circuit 50, the reference voltage / bias current generator 51 includes a current source 60, switches 61 and 62, and nMOSs 63 and 64.
The drain of the nMOS 63 is connected to the charge pump 12 via the switch 61, and the source is grounded. The gate of the nMOS 63 is connected to the gate of the nMOS 64. The gate of the nMOS 64 is further connected to the drain of the nMOS 64. The drain of the nMOS 64 is connected to the current source 60 via the switch 62, and the source is grounded. The switches 61 and 62 are turned on or off by a control signal from the control circuit 17.

  Such a reference voltage / bias current generator 51 has a current mirror function, and when the switches 61 and 62 are turned on, the current generated by the current source 60 is supplied to the charge pump 12 as a bias current.

  One terminal of the switch 52 is connected to the gates of the nMOSs 63 and 64. When the switch 52 is turned on, the gate voltage of the nMOSs 63 and 64 is held in the capacitive element 53 as a reference voltage.

  The bias current generation unit 54 includes an nMOS 65. The gate of the nMOS 65 is connected to the other terminal of the switch 52 and one terminal of the capacitor 53. The drain of the nMOS 65 is connected to the voltage controlled oscillator 14, and the source is grounded.

  The bias current generation unit 54 functions as a current mirror with the reference voltage / bias current generation unit 51 when the switch 52 is on, and supplies the same current as the bias current supplied to the charge pump 12 to the voltage controlled oscillator 14. Supply. When the switch 52 is off, the bias current generator 54 keeps the nMOS 65 on by the reference voltage held in the capacitive element 53 and continues to supply the bias current to the voltage controlled oscillator 14.

  In the example of the bias circuit 50 of FIG. 12, the switches 52, 61, 62 are, for example, nMOS, and are turned on when “1” is supplied from the OR circuit 25 of the control circuit 17, and supplied with “0”. Turn off if

  Accordingly, the bias circuit 50 operates as a current mirror when one or both of the UP signal and the DN signal output from the phase comparison circuit 11 are in an activated state, and causes the charge pump 12 and the voltage controlled oscillator 14 to operate. Supply bias current. The bias circuit 50 stops supplying the bias current to the charge pump 12 when both the UP signal and the DN signal are inactive. However, the bias circuit 50 can continue to supply a bias current to the voltage controlled oscillator 14.

Instead of the bias circuit 50 as described above, a bias circuit using pMOS as shown below may be applied.
FIG. 13 is a diagram illustrating another example of the bias circuit.

In the bias circuit 50 a shown in FIG. 13, the reference voltage / bias current generator 51 a includes pMOSs 70 and 71, switches 72 and 73, and a current source 74.
The drain of the pMOS 70 is connected to the charge pump 12 via the switch 72, and the source is connected to the power supply. The gate of the pMOS 70 is connected to the gate of the pMOS 71. The gate of the pMOS 71 is further connected to the drain of the pMOS 71. The drain of the pMOS 71 is connected to the current source 74 via the switch 73, and the source is connected to the power source. The switches 72 and 73 are turned on or off by a control signal from the control circuit 17.

  The reference voltage / bias current generator 51a has a current mirror function, and when the switches 72 and 73 are turned on, the current generated by the current source 74 is supplied to the charge pump 12 as a bias current.

  One terminal of the switch 52 is connected to the gates of the pMOSs 70 and 71. When the switch 52 is turned on, the gate voltage of the pMOSs 70 and 71 is held in the capacitor 53 as a reference voltage. In the capacitive element 53, one terminal is connected to a node between the switch 52 and the bias current generator 54a, and the other terminal is connected to a power source.

  The bias current generator 54a has a pMOS 75. The gate of the pMOS 75 is connected to the other terminal of the switch 52 and one terminal of the capacitive element 53. The drain of the pMOS 75 is connected to the voltage controlled oscillator 14, and the source is connected to the power source.

  When the switch 52 is on, the bias current generation unit 54a functions as a current mirror with the reference voltage / bias current generation unit 51a, and supplies the voltage control oscillator 14 with the same current as the bias current supplied to the charge pump 12. Supply. When the switch 52 is off, the bias current generator 54 a keeps the pMOS 75 on by the reference voltage held in the capacitive element 53 and continues to supply the bias current to the voltage controlled oscillator 14.

  Also in the example of the bias circuit 50a in FIG. 13, the switches 52, 72, and 73 are, for example, nMOS, and are turned on when “1” is supplied from the OR circuit 25 of the control circuit 17, and “0” is supplied. Turn off if

  Thus, the bias circuit 50a operates as a current mirror when one or both of the UP signal and the DN signal output from the phase comparison circuit 11 are in an activated state, and causes the charge pump 12 and the voltage controlled oscillator 14 to operate. Supply bias current. The bias circuit 50a stops supplying the bias current to the charge pump 12 when both the UP signal and the DN signal are inactive. However, the bias circuit 50 a can continue to supply a bias current to the voltage controlled oscillator 14.

  In the bias circuits 50 and 50a of FIGS. 12 and 13, the reference voltage held by the capacitive element 53 fluctuates due to leakage when the switch 52 is off. However, as described above, the phase comparison circuit 11 activates both the UP signal and the DN signal for a short period even if the phase difference between the input reference signal (input clock) and the feedback signal is zero. Therefore, the switch 52 is turned on in the cycle of the input clock. As a result, the reference voltage held by the capacitive element 53 is corrected at the cycle of the input clock.

However, it is desirable to design so that fluctuations in the reference voltage held by the capacitive element 53 can be corrected by the time of the pulse width of the UP signal or DN signal.
If the change in the reference voltage is ΔV, the gate potential of the nMOS 64 also changes by ΔV by closing the switch 52 (for simplicity, the gate capacitances of the nMOSs 63 to 65 and the ON resistance of the switch 52 are ignored). . At this time, if the transconductance of the nMOS 64 is gm, the drain current of the nMOS 64 decreases by gmΔV. Instead of decreasing the drain current of the nMOS 64, a current having a magnitude of gmΔV flows into the capacitive element 53. Based on the above principle, the capacitance value is set so that the time constant C / gm when charging the capacitive element 53 is sufficiently smaller (for example, 1/3 or less) than the minimum pulse width time of the UP signal or DN signal. It is desirable to determine C.

  It is assumed that the reference voltage fluctuates so as to be uncorrectable in the time of the pulse width of the UP signal or DN signal at a certain timing due to a disturbance or the like. In that case, the output clock fluctuates due to the fluctuation of the reference voltage, and the phase difference between the input clock and the feedback signal widens, so that the pulse difference between the UP signal and the DN signal widens, and the reference voltage held by the capacitor 53 is corrected. Is done. That is, even if the reference voltage fluctuates due to the influence of disturbance, the reference voltage is corrected by the feedback effect of the PLL circuit 10a.

  According to the PLL circuit 10a of the second embodiment as described above, the power consumption can be efficiently reduced as in the PLL circuit 10 of the first embodiment, and the circuit block always uses the bias current. Can continue to supply a bias current.

  In the above example, the voltage controlled oscillator 14 is used as the circuit block that always uses the bias current. However, the circuit block is not limited to this. Depending on the circuit configuration, if the circuit block that always uses the bias current is in the PLL circuit, the bias current based on the reference voltage held in the capacitor is supplied from the bias circuit to the circuit block. That's fine.

  As shown in FIGS. 5 to 10, delay circuits 40 and 43 are provided for the PLL circuit 10 a of the second embodiment to adjust the rising and falling timing of each signal. Also good.

(Third embodiment)
FIG. 14 is a diagram illustrating an example of a PLL circuit according to the third embodiment. Elements similar to those of the PLL circuit 10a of the second embodiment shown in FIG. 11 are denoted by the same reference numerals and description thereof is omitted.

In the PLL circuit 10b of the third embodiment, the bias circuit 80 is different from the PLL circuit 10a of the second embodiment.
The bias circuit 80 includes a reference voltage generation unit 81, a switch 82, a capacitive element 83, and a bias current generation unit 84.

  The reference voltage generator 81 includes, for example, the current source 60 and the switch 62 as shown in FIG. 12, and generates a bias current when one or both of the UP signal and the DN signal are activated. A reference voltage for output is output.

  The switch 82 is ON / OFF controlled by a control signal from the control circuit 17. The switch 82 is turned on when one or both of the UP signal and the DN signal are activated, and the switch 82 is turned off when both the UP signal and the DN signal are deactivated.

The capacitive element 83 holds the reference voltage generated by the reference voltage generation unit 81.
The bias current generation unit 84 generates a bias current based on the reference voltage held in the capacitive element 83 and supplies the bias current to the charge pump 12 and the voltage controlled oscillator 14. In addition, the bias current generation unit 84 includes a switch that switches whether to supply a bias current to the charge pump 12. The switch is controlled to be turned on / off by a control signal from the control circuit 17. When one or both of the UP signal and the DN signal are activated, the switch is turned on to supply a bias current to the charge pump 12. When both the UP signal and the DN signal are inactive, the switch is turned off and the supply of the bias current to the charge pump 12 is cut off.

Even with such a PLL circuit 10b, the same effect as the PLL circuit 10a of the second embodiment can be obtained.
As shown in FIGS. 5 to 10, delay circuits 40 and 43 are provided for the PLL circuit 10 b of the third embodiment to adjust the rising and falling timing of each signal. Also good.

  Furthermore, in order to supply a highly accurate bias current to the charge pump 12 and also to supply a bias current with less noise to the voltage controlled oscillator 14, the following PLL circuit can be applied.

(Fourth embodiment)
FIG. 15 is a diagram illustrating an example of a PLL circuit according to the fourth embodiment.
FIG. 15 shows a part of the PLL circuit 10c. The parts not shown are the same as those of the PLL circuits 10, 10a, 10b described above. In addition, the same code | symbol is attached | subjected about the element similar to PLL circuit 10, 10a, 10b, and description is abbreviate | omitted.

The PLL circuit 10 c according to the fourth embodiment includes a delay circuit 90 provided between the phase comparison circuit 11 and the charge pump 12.
The delay circuit 90 includes delay elements 91, 92, 93 that delay the UP signal output from the phase comparison circuit 11, and delay elements 94, 95, 96 that delay the DN signal.

  The control circuit 100 includes OR circuits 101, 102, 103 and a delay circuit 110. The delay circuit 110 further delays the UP signal delayed by the delay element 93 and inputs it to the OR circuit 103, and further delays the DN signal delayed by the delay element 96 and inputs it to the OR circuit 103. A delay element 112 is included.

In the example of FIG. 15, the delay circuit 110 is included in the control circuit 100, but a circuit block different from the control circuit 100 may be used.
The OR circuit 101 receives the UP signal and the DN signal before being delayed by the delay circuit 90 and the output signal of the OR circuit 102, and outputs a logical sum of these signals. The OR circuit 102 inputs the UP signal and DN signal delayed by the delay elements 91 and 94 and the output signal of the OR circuit 103, and outputs a logical sum of these signals. The OR circuit 103 inputs the UP signal and DN signal delayed by the delay elements 92 and 95, and the UP signal and DN signal delayed by the delay elements 111 and 112, and outputs a logical sum of these signals.

  The bias circuit 120 has a function of supplying a bias current to the charge pump 12 and the voltage controlled oscillator 14 in the same manner as the bias circuits 50 and 80 of the PLL circuits 10a and 10b of the second and third embodiments. Has the following elements.

That is, the bias circuit 120 includes a current source 121, switches 122, 123, 124, 125, nMOSs 126, 127, 128, and capacitive elements 129, 130.
The switches 122 and 123 are ON / OFF controlled by the output signal of the OR circuit 101 among the control signals output from the control circuit 100. The switch 124 is ON / OFF controlled by the output signal of the OR circuit 102 among the control signals output from the control circuit 100. The switch 125 is ON / OFF controlled by the output signal of the OR circuit 103 among the control signals output from the control circuit 100. The switches 122 to 125 are, for example, nMOS, and are turned on when “1” is input from the OR circuits 101 to 103 to the gates, and turned off when “0” is input.

  The switch 122 is provided between the current source 121 and the drain of the nMOS 126. The switch 123 is provided between the drain of the nMOS 127 and the charge pump 12. The switch 124 is connected between the drain and gate of the nMOS 126. The switch 125 is connected between the gates of the nMOS 126 and the nMOS 127.

  The gate of the nMOS 127 is connected to the gate of the nMOS 128, and the drain of the nMOS 128 is connected to the voltage controlled oscillator 14. The sources of the nMOSs 126 to 128 are grounded.

  One terminal of the capacitive element 129 is connected between the gate of the nMOS 126 and the switch 125. One terminal of the capacitive element 130 is connected between the gate of the nMOS 127 and the switch 125. The other terminals of the capacitive elements 129 and 130 are grounded.

  In such a bias circuit 120, the circuit unit that generates the reference voltage including the current source 121 and the capacitor 129 are connected via the switch 124. When the switch 122 is in the on state, the switch 124 is in the on state. Then, the capacitive element 129 is charged and the reference voltage is held. After that, when the switch 125 is turned on, the capacitor 130 is charged.

FIG. 16 is a timing chart illustrating an example of the operation of the PLL circuit according to the fourth embodiment.
UP signal before delay (UP1), UP signal after delay by delay element 91 (UP2), UP signal further delayed by delay element 92 (UP3), UP signal further delayed by delay element 93 (UP4), The UP signal (UP5) further delayed by the delay element 111 is shown. Further, an output signal of the OR circuit 101 (bias enable 1), an output signal of the OR circuit 102 (bias enable 2), and an output signal of the OR circuit 103 (bias enable 3) are shown. Further, the drain voltage (V1) of the nMOS 126, the source current (I1) of the nMOS 126, the gate voltage (V2) of the nMOS 126, and the gate voltage (V3) of the nMOS 127 are shown. Further, a bias current (Ibias1) supplied to the voltage controlled oscillator 14, a bias current (Ibias2) supplied to the charge pump 12, and a charge pump current (Icp) are shown.

FIG. 16 shows a case where only the UP signal is activated for the sake of simplicity.
At time t0, UP1 to UP5 and bias enables 1 to 3 are assumed to be at the L level. In addition, V2 and V3 indicate constant values (H level) of 0 or more depending on the voltage held in the capacitive elements 129 and 130.

  As a result, the switches 122 to 125 are all in the off state and the nMOS 126 is in the on state, so that V1 is also at the L level, and I1, Ibias2, and Icp are also 0. Further, when V3 is at the H level, the nMOS 128 is turned on, and Ibias1 is supplied to the voltage controlled oscillator 14.

  When UP1 rises at time t1, bias enable 1 rises to H level at time t2 after being delayed by OR circuit 101. As a result, the switch 122 is turned on, V1 and I1 start to rise, and then become a constant value. In addition, the switch 123 is turned on, and Ibias2 is also raised by the reference voltage held in the capacitor 130. By providing the capacitive element 130 that holds the reference voltage, Ibias2 rises quickly.

  When UP2 rises at time t3, bias enable 2 rises to H level at time t4 after the delay by OR circuit 102. As a result, the switch 124 is turned on, the amount of charge leakage held in the capacitor 129 is compensated by the current of the current source 121, and V2 is corrected.

  When UP3 rises at time t5, bias enable 3 rises to H level at time t6 after the delay by OR circuit 103. As a result, the switch 125 is turned on, the amount of charge leakage held in the capacitive element 130 is compensated by the current of the current source 121, and V3 is corrected. Thereby, Ibias1 which is a bias current supplied to the voltage controlled oscillator 14 and Ibias2 which is a bias current supplied to the charge pump 12 are also corrected.

At this time, since the reference voltage is held in the capacitor 129, voltage fluctuation can be suppressed.
When UP4 rises at time t7, the charge pump 12 starts to flow Icp. Thereafter, UP5 rises at time t8, but the bias enable 3 remains at the H level.

  Thereafter, UP1 to UP3 sequentially fall to the L level, and when UP4 falls to the L level at time t9, Icp falls, but UP5 remains at the H level, so that the bias that is the output signal of the OR circuit 103 Enable 3 remains at the H level. As a result, the bias enable 2 that is the output signal of the OR circuit 102 that receives the output signal of the OR circuit 103 also maintains the H level, and the bias enable 1 that is the output signal of the OR circuit 101 that receives the output signal of the OR circuit 102. Maintain the H level. Therefore, the switches 122 to 125 are also kept in the on state, and the bias current (Ibias2, Ibias1) continues to be supplied to the charge pump 12 and the voltage controlled oscillator 14.

  When UP5 falls at time t10, bias enable 3 falls to L level at time t11 after being delayed by OR circuit 103, and in response to this, bias enable 2 and bias enable 1 fall sequentially to L level. Thereby, the switch 125 and the switch 124 are sequentially turned off, and finally the switches 122 and 123 are turned off.

By turning off the switches 122 to 125 in this order, the reference voltage held in the capacitor 130 can be prevented from greatly fluctuating.
When the bias enable 1 falls to the L level at time t12, the switch 123 is turned off, so that Ibias2 falls. Ibias1 continues to be supplied to the voltage controlled oscillator 14 by the voltage held in the capacitor 130.

  As described above, the delay circuit 90 is provided to delay the UP signal and the DN signal input to the charge pump 12, and the control circuit 100 starts the operation of the bias circuit before the charge pump 12 starts flowing the charge pump current. I am letting.

  As a result, the PLL circuit 10c has an effect that the malfunction of the charge pump 12 due to an unstable bias current at the start-up can be suppressed in addition to the effect that the power consumption can be efficiently reduced.

  The delay circuit 110 can continue to supply a bias to the charge pump 12 even when the charge pump current does not fall immediately. Thereby, malfunction of the charge pump 12 can be suppressed.

Thus, by providing the delay circuits 90 and 110, a stable bias current can be supplied to the charge pump 12 while the charge pump 12 is flowing the charge pump current.
In addition, the PLL circuit 10 c includes switches 122 to 125 and capacitive elements 129 and 130 in the bias circuit 120, and compensates for leaks of the capacitive elements 129 and 130 by control using the bias enables 1 to 3. As a result, fluctuations in the bias current can be suppressed, and an accurate bias current can be supplied to the charge pump 12 and the voltage controlled oscillator 14.

  In FIG. 16, the case where only the UP signal is activated has been described, but the same operation is performed when only the DN signal is activated, or when both the UP signal and the DN signal are activated. Done.

The bias circuit 120 is not limited to the circuit as shown in FIG. 15, and may be the following circuit.
FIG. 17 is a diagram illustrating another example of the bias circuit.

  The bias circuit 120a uses pMOS instead of the nMOSs 126 to 128 of the bias circuit 120 shown in FIG. That is, the bias circuit 120 a includes a current source 131, switches 132, 133, 134, 135, pMOSs 136, 137, 138, and capacitive elements 139, 140.

  The switches 132 and 133 are on / off controlled by the output signal of the OR circuit 101. The switch 134 is on / off controlled by the output signal of the OR circuit 102. The switch 135 is ON / OFF controlled by the output signal of the OR circuit 103. The switches 132 to 135 are, for example, nMOS, and are turned on when “1” is input from the OR circuits 101 to 103 to the gates, and turned off when “0” is input.

  The switch 132 is provided between the current source 131 and the drain of the pMOS 136. The switch 133 is provided between the drain of the pMOS 137 and the charge pump 12. The switch 134 is connected between the drain and gate of the pMOS 136. The switch 135 is connected between the gates of the pMOS 136 and the pMOS 137.

  The gate of the pMOS 137 is connected to the gate of the pMOS 138, and the drain of the pMOS 138 is connected to the voltage controlled oscillator 14. The sources of the pMOSs 136 to 138 are connected to the power source.

  One terminal of the capacitive element 139 is connected between the gate of the pMOS 136 and the switch 135. One terminal of the capacitive element 140 is connected between the gate of the pMOS 137 and the switch 135. The other terminals of the capacitive elements 139 and 140 are connected to a power source.

The same effect can be obtained even when such a bias circuit 120a is used. Further, the same effect can be obtained by using a resistor instead of the current source as the circuit unit for generating the reference voltage.
FIG. 18 is a diagram illustrating another example of the bias circuit. Elements similar to those of the bias circuit 120 shown in FIG. 15 are denoted by the same reference numerals.

  The bias circuit 120b has a resistor 141 connected to a power source instead of the current source 121 of the bias circuit 120 shown in FIG. 15, and a reference voltage is generated by this resistor.

Similarly, a resistor may be used in place of the current source 131 in the bias circuit 120a as shown in FIG.
In the PLL circuit 10c of the fourth embodiment as described above, the current consumption of the control circuit 100 is smaller (for example, several μA) than the current consumption of the bias circuit 120 (for example, several tens to several hundred μA). . Therefore, even if the OR circuits 101 to 103 as shown in FIG. 15 are provided, the bias current to the charge pump 12 of the bias circuit 120 is controlled to be cut off when the UP signal and the DN signal are inactive. Power saving effect by doing is high.

  Further, the area of the OR circuits 101 to 103 can be reduced to about 1% of the entire PLL circuit 10c, so that the area increase is small. Further, even when the bias circuit 120b using the resistor 141 as shown in FIG. 18 is applied, the current consumption can be reduced without increasing the resistance value (increasing the area of the resistor).

  In a normal operation state of a PLL circuit that does not use the control circuit 100 as in this embodiment (the voltage-controlled oscillator has a circuit configuration that does not require a bias current), for example, the current consumption of the entire PLL circuit is 150 μA, and the bias circuit Current consumption is 80 μA. Although the current can be reduced by increasing the bias resistance, the area of the resistance increases in inverse proportion to the bias current. On the other hand, the control circuit 100 is applied, the time for supplying the bias current to the charge pump 12 is 1% with respect to the time for not supplying the current, and the current consumption of the control circuit 100 is 4 μA. Then, the current consumption of the entire PLL circuit can be reduced to about 75 μA, which is half that of the PLL circuit not using the control circuit 100, without increasing the area of the bias resistor.

(Fifth embodiment)
FIG. 19 is a diagram illustrating an example of a PLL circuit according to the fifth embodiment. Elements that are the same as those of the PLL circuit 10a shown in FIG.

The PLL circuit 10 d according to the fifth embodiment includes a voltage monitoring circuit 150 that monitors a reference voltage held in the capacitive element 53.
The voltage monitoring circuit 150 has, for example, a comparator. The voltage monitoring circuit 150 generates a signal indicating that an abnormality has occurred in the reference voltage (hereinafter referred to as an abnormality detection signal) when the fluctuation amount of the reference voltage held in the capacitive element 53 exceeds a certain threshold value. Notify the control circuit 160. For example, the voltage monitoring circuit 150 compares a certain threshold voltage with the voltage of the capacitive element 53 and notifies the control circuit 160 of an abnormality detection signal when the voltage of the capacitive element 53 is equal to or lower than the threshold voltage.

  The control circuit 160 has the same function as the control circuit 17 of the PLL circuit 10a shown in FIG. Further, when receiving the abnormality detection signal, the control circuit 160 has a function of activating the bias enable for a predetermined period, operating the bias circuit 50, and charging the capacitor 53.

  As a period for keeping the bias enable in the activated state, for example, while the voltage monitoring circuit 150 outputs an abnormality detection signal, or while the voltage monitoring circuit 150 outputs an abnormality detection signal, A predetermined period after outputting the abnormality detection signal. For example, the control circuit 160 includes a counter, and when an abnormality detection signal is notified, the control circuit 160 keeps the bias enable activated until a predetermined number of input clocks that are reference signals are input.

  In the following, a case where the bias enable is activated after the voltage monitoring circuit 150 finishes outputting the abnormality detection signal until the control circuit 160 counts the rising edge of the input clock twice will be described as an example. An operation of the PLL circuit 10d according to the embodiment will be described.

FIG. 20 is a timing chart showing an example of the operation at the start of the operation of the PLL circuit.
In FIG. 20, an input clock (CK), a feedback signal (FB), an UP signal (UP), and a DN signal (DN), which are reference signals, are shown from the top. Also, an abnormality detection signal (OVF) output from the voltage monitoring circuit 150, a control signal (bias enable) output from the control circuit 160, a reference voltage held in the capacitive element 53, and a charge pump current (Icp) are shown. ing.

  At time t0, which is the operation disclosure time of the PLL circuit 10d, the reference voltage held in the capacitive element 53 is low and is equal to or lower than the predetermined threshold voltage Vth, so that the OVF is in an activated state (H level). As a result, the bias enable also becomes H level, the switch 52 in the bias circuit 50 is turned on, and the capacitive element 53 is charged.

  When the reference voltage held in the capacitive element 53 exceeds the threshold voltage Vth at time t1, the voltage monitoring circuit 150 causes OVF to fall to an inactive state (L level). However, the control circuit 160 keeps the bias enable at the H level until the time t2 when the second rising edge of the input clock is detected after the OVF falls to the L level.

  However, in the example of FIG. 20, since UP rises to the H level at time t2, the bias enable remains at the H level until time t3 when both UP and DN fall to the L level.

  After time t3, while one or both of UP and DN are at the H level while the reference voltage exceeds Vth, a bias current is supplied to the charge pump 12, and when both UP and DN are at the L level, the bias is supplied. The operation described above is performed to cut off the supply of current.

  As described above, when the operation of the PLL circuit 10d is started, the bias enable is held in an activated state for a certain period and the capacitor element 53 is charged, so that the time for the reference voltage to reach a certain level can be advanced. It is possible to suppress the occurrence of problems in the operation of 10d.

FIG. 21 is a timing chart illustrating an operation example when an abnormality occurs in the reference voltage during the operation of the PLL circuit.
In FIG. 21, the input clock (CK), feedback signal (FB), UP signal (UP), and DN signal (DN), which are reference signals, are shown from the top. Further, a reference voltage held in the capacitive element 53, an abnormality detection signal (OVF) output from the voltage monitoring circuit 150, a control signal (bias enable) output from the control circuit 160, and a charge pump current (Icp) are shown. ing.

  At time t1, when the reference voltage held in the capacitive element 53 becomes equal to or lower than the threshold voltage Vth due to disturbance or the like, OVF rises to H level and the bias enable also rises to H level. Thereby, the switch 52 is turned on, and the capacitive element 53 is charged. When the reference voltage exceeds the threshold voltage Vth at time t2, OVF falls to the L level, but the control circuit 17 holds the bias enable at the H level until time t3 when the second rising of the input clock is detected. Keep it. However, in the example of FIG. 21, since UP and DN rise to H level at time t3, the bias enable remains at H level until time t4 when both UP and DN fall to L level.

  As described above, when the reference voltage largely fluctuates due to some factor such as a disturbance, the reference voltage becomes a constant level by holding the bias enable in an activated state for a certain period and charging the capacitive element 53. You can speed up the time. Thereby, it is possible to suppress the occurrence of problems in the operation of the PLL circuit 10d.

  In the example of the PLL circuit 10d of FIG. 19 described above, the voltage monitoring circuit 150 is applied to the PLL circuit 10a of the second embodiment, but the PLL of the third embodiment shown in FIG. The present invention can also be applied to the circuit 10b and the PLL circuit 10c of the fourth embodiment shown in FIG.

When applied to the PLL circuit 10 b shown in FIG. 14, the voltage monitoring circuit 150 may monitor the voltage of the capacitive element 83.
When applied to the PLL circuit 10c shown in FIG. 15, the voltage monitoring circuit 150 may monitor the voltage of the capacitive element 130, for example.

  As described above, one aspect of the PLL circuit of the present invention has been described based on the embodiment, but these are only examples, and the present invention is not limited to the above description.

DESCRIPTION OF SYMBOLS 10 PLL circuit 11 Phase comparison circuit 12 Charge pump 13 Filter 14 Voltage control oscillator 15 Feedback frequency divider 16 Bias circuit 17 Control circuit IN Input terminal OUT Output terminal

Claims (8)

A phase comparison circuit that compares the phase of the reference signal and the feedback signal and supplies two types of phase difference signals according to the comparison result to the charge pump;
A bias circuit for supplying a bias current to the charge pump;
The operation of the bias circuit is performed when one or both of the two kinds of phase difference signals are activated, and the bias circuit is activated when both of the two kinds of phase difference signals are inactivated. A control circuit to stop;
A PLL circuit comprising: A delay circuit that delays the two types of phase difference signals and supplies them to the charge pump;
2. The control circuit according to claim 1, wherein the control circuit starts the operation of the bias circuit before the charge pump starts flowing a charge pump current according to the two kinds of phase difference signals delayed. 3. PLL circuit.   The delay circuit delays the two kinds of phase difference signals, and the control circuit is configured to wait for a delay time from the other delay circuit to elapse after the two kinds of phase difference signals have transitioned to the inactive state. The PLL circuit according to claim 1, wherein the operation of the bias circuit is stopped.   2. The bias circuit includes a capacitive element that holds a reference voltage, and supplies the bias current based on the reference voltage held by the capacitive element to a circuit block in a PLL circuit. The PLL circuit as described in any one of thru | or 3. The bias circuit is connected to a circuit unit that generates the reference voltage via a first switch, and has another capacitive element connected to the capacitive element via a second switch,
The control circuit corrects the reference voltage held in the capacitive element by turning on the second switch and holding the reference voltage in the other capacitive element with the first switch turned on. The PLL circuit according to claim 4, wherein: The bias circuit is connected to a circuit unit that generates the reference voltage via a first switch, and has another capacitive element connected to the capacitive element via a second switch,
The control circuit generates the reference voltage by turning off the first switch after turning off the connection between the capacitive element and the other capacitive element by turning off the second switch. 6. The PLL circuit according to claim 4, wherein a connection between the first portion and the other capacitive element is interrupted. A voltage monitoring circuit that monitors the reference voltage held in the capacitive element and outputs an abnormality detection signal indicating that an abnormality has occurred in the reference voltage when a variation amount of the reference voltage exceeds a threshold value Have
7. The PLL circuit according to claim 4, wherein, when receiving the abnormality detection signal, the control circuit causes the bias circuit to charge the capacitive element for a predetermined period. 8.   The PLL circuit according to claim 7, wherein the voltage monitoring circuit outputs the abnormality detection signal when the operation of the PLL circuit is started.

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